From 73944a4bf4ab259b489af8128b4aec525484d642 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Sat, 13 Nov 2021 14:47:21 +1100 Subject: [PATCH 001/421] pseries: Update SLOF firmware image This has really just one fix from Stefan, the rest is housekeeping. The full changelog is: Alexey Kardashevskiy (3): Revert "make: Define default rule for .c when V=1 or V=2" js2x: Fix compile and cleanup version: update to 20211112 Stefan Berger (1): tcgbios: Disable platform hierarchy in case of failure Thomas Huth (8): Mention the CR vs. LF problem in the documentation slof/fs/accept: Replace TABs with spaces Fix the URL to the Linux kernel coding style lib/libc/README.txt: Fix "cannel" typo travis.yml: Fix keywords travis.yml: Update to Focal Fossa travis.yml: Compile-test the qemu build Silence some trivial compiler warning in the js2x code Signed-off-by: Alexey Kardashevskiy --- pc-bios/README | 2 +- pc-bios/slof.bin | Bin 991744 -> 991920 bytes roms/SLOF | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pc-bios/README b/pc-bios/README index db39d757b0..c51ae58824 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -14,7 +14,7 @@ - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20210711. + built from git tag qemu-slof-20211112. - VOF (Virtual Open Firmware) is a minimalistic firmware to work with -machine pseries,x-vof=on. When enabled, the firmware acts as a slim shim and diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin index 855521e650e8b33279dc3b9561952ae2ce7e9188..046ca63709aacf7f05c9b95a37535ac2c0b52df3 100644 GIT binary patch delta 125061 zcmbTf3tZJj`aeFO`5X{T4b~fY;~-uDQSpA@fE>IY1O;!2iiLoLT{hY-VuI(OmbhtQ zUIx<&G!0YpxY?f5qJ>>H-0U0e)<(NlSZR=5=(b^~=l_1@^Z6W*^tJo@(+lU!JePUq znP;AP=9xLiaDAO;ci&v!Z^Q z@@FMhY@Dumm4Ra83?)g4eeSIp%5}va^S_8KymsZH@{72bqU`Jb3oBmJzo_`>h$8Ef zU&QWNidm@@CuS+b13Za?*@3tyAui5Ra{d3*5dYbqV#R_~zSJonGa>t}8 z{rf7@g*{hU$JZz#dx;XI@>L7nt+`5DuyRRMu2Dinw+EG6Wtk{^P?@Am5Y9)H1QEGP z>A{l&Mdd~%RCHgZL@Pr@W2q9Z^6B^PdtgW}mz#j2bn z$s?4-R1D@bULvxAV){B|l(JgfzfM`DDB|mN%5BPWk+xpBU0F#*fAQ{m#jczekRb}IkJr}Y*Vfk`|j_6TLPQYy{}<)1L4eHBWvGE$g#DUT~p3D+*b z?iP)^lslDkBJD}#&d`O_S*q8&he~Us*K5fswb^-AqNslo!yGD_o>T_$EI$#jTbTuh z^LHx+%2sh=xAGurhMf)(!@QPf(+3hmq)D#lkT&nfqcvz5wj7)()>avvt->nce8o+#d{ z2-sGyeXt@6nC(+)sHbN^0iMsIc23;2U%7|q_bU$Ndy#bj1!@OC_>s8(Ij~6)rfL)~ zi|y5rFj;gvsJuuL9#kITWBi2ud6+-sejaK)A}XI(_VU<3G3}5tj>I{H)|W)ZA>}RQ z8oE3FfiIp|7OA+;oL07RWwyvZ z11C4zo&Aoo(WIa8$MJ%;cx-D|H2Y8i;e$+O3d!({-rGNQ;xYWf2!=` z-KD8p);-){=RJ?P4}Yd`m0ubtT<0+xTimt_%5xn0YifdZ?r?`R!%&pD?&7bM5voD@ zh{etW4!Vzjql{3rmE(Bx$0EzRM+)q`3s%mz$}g(&rn~6}Wf%{3N0J&YMZ06kOKuHx zi?E+T=XR(5tQ=M_Z>|4PmW*{rme>+w2s3V$JGR8UFjB{kN%dYiPWs87VocB@<#xrp zNo@E->=FFRm8>2^o>^Qj6@Z|}kz zl@-Dcxq{sZsou{v(a=)8m+Oy3yM;G^hrohE0{JVz{VN6M4tL89UG%#wx02x^1hYx_n+0$#~o>rW~8;7Bg?+KZ3&Ajpy>Ox{Jzg{J<#p6o}&@ zO2STF$GRn9Hmq^(v;>Ig-0x1XI2m(9yj^5h-dim0@6OjkH$Qggv5K-u47r(q>UWU( z7TE#3k9$xMx6yEJ3+Cm@Nq0*y7aZQHtQTL}tC`T6ZBL+kl zzN~7vJ9G6c2ych*Q4oH(+r6(hznNIS*oTkk=guZ8Xx-#4kmW&lp)60ki?$UO^b+0r z@_updLc8)-6|qjpVF#LW-9?s4Go#Ug-&YaCjpq&D^!h$ZI^R~hs#ch50h){QS z!a6i>a2Jvyn)bV$rBgA7UP#gxo)Ye*F@z8AEj=@J;&=m=p0f$eKZZSp@*Ib|FbNz8 zW_@i_kX?B*kv=!A=_tsXQPkF)=q|K0G8V^JUYyPAb-ey#(WL~pv%DEFl$K^@YQ5}s z?h0fks>cN~<T~WIcuPOIdDbiS2UCR(zIijwog#CU)i2blC|$7vIsph?tky z(qk^3a67Fh8E-=goN&USK@_h5&c2J7?>D}YZNLXyxrWE*ZAB$f^Li0~ti#^LYx}Q; z?ZiN%mBgR4DT@2?L71@J{rGrjtG*wf89afQ0J*5i!Jv^^?2`TY*r7C4uis6u-%i!* zQp3%Y-NMnI_jTw>8Kx`cg02+QrBeJgrNkw%5b_HpwzQaL4aP44CY3|=6zFD#+qvx^ z6pA{;34o!QF5$CXd37#{LP{*ohMvv>{tOGSe!_UMV|_$XYbh&iLn9F7>@}e-l_nMS z+RsEx3;_@HF@oZ0%!bnJ$}3X2ojM7Uom|t$D{o4EdLPqByLRO@xh-i*d}Y7vBn#4F zOL5T5be+|U%){|~$|&mKVihZsqodEI%qeV-slCM41Na?M^QZ152EWz(sl}3UqFbyP z$ont+-!w0^P38#gIvN+okR?#t#VT*p#Z%rET4TilDxzYkZEiPu(SoDDl{Bl~?EQ`n`Ua%x#KO3P`il{ekaie^kL)ti~pdLCwh zHA8in3BTkA;hfWB^twsbD+gZNfW;*lKvIql#LZ#6Fjg+%mk^1}}QMncuF!O^{Ez z_$mvz?-O>LT{$5Q<61Xy;v*V*(`5|(HSC0D=_(52Yzm{5+Ij)QPhzGfDu=^zp>OFj zP?s(P^^U8f;~bTYHGBpkVaPObyP-pg6a_zn_EhiBfi!5_I@YV%ij_E+JIH0}{`BH) zETs7CIM`*)%Oq##DMY*U!&t=9*OHI5M)1*C%>T2P*OAiUTo@^(43vwvo1=Dmj3(`m zFYD5d*L`?V+z{5q(U=xfJgC*S<~%beJJ~eLO&i!vGH_FB;>1r8{1GgNi=VO(yYiP5 z8b?!cM_2t9>Aaekxy3U>co>$$)@V)DhSsFTXx?B!E?@Vn`nzKpu{_ub< z>i{fO(Q_!z^>de5Kf$6K%ESEKWp?G|k)m=a-wC^!G>jua61l^8ol@$K8P0QPM|?bz zk3;c#B#)$UC6Y&@);Ef8l*?$`s=f1XwmAi%na~KLZ>#=!)@!lbsBkf6JUs*XYyzc zB|e(MbFogpOW}9P!KOk#$zpRV^zx3oF_l6$#6Yw8(%!QreI*MbEm?}aa93O7+}mgK zZL0FHh@8uphDQ-fs`sjgO8JWoib_k)qnUPPf8fqE9xmRT%V*F~=b@`IkuVR__Wib6 z#567Q_;BSVd^8Koe7;lx_xXIU(%roWwxqO?jV4U@7z2HAJW9Rz`ZK5dURpbfLXoGi8sjlM3u-9+@ zM$|6nhm_^+yK?yB3eKjNbNSmiCD-L)WKih}{vu9u4J)ANCJ~d*|DnwO^XnY#D{D6DirC(IOI+jWyO3je+ZHk^Lc3X7V`p9T?ro+2)PEc1Dm4ULX;pN-Y+88 z@?qWGl|E^QyT#JAJOZZXSj$s8K|Wl|7m)THJfHIiLfzX-v1=%o+{f4PE{gKK`^0+w zouY)h4?m2>g;U&sjeL#?65RPHuRv18v>DO<2cmT|7T^`PYYS!;9^mW8U|57)&bx3@ z^%F2FWK^Eu--6V-jsK%h>Oh(?+E^@=EI?h_T9D|~u)QM(H|+Tpf5i4_D7vu8JEjk@1Mi{>d2`!ugnPPxB+nj8?U zaUZ0c;I7!m=X2x;zTOYwl_Ku|zfEZtZybPgNp^33jxSP_X7?A>{9PV+iDX2$=@PCC z-dntP2pcQx_YnVtpRO(>p2|n!dad56HkNHjKq<^8Q`4x+^m~)_-24Su1;^bTS-Ol-FAvZMP+tvKUaUJ<5ku zoQDNB7m+TPWRc7)qkE7RcdewYx}fw{kk0a6Eso3}(oED%Tf`=M$&c zhONo0Fx49!M=GsKX5}&1*cPUkCzeEg)eCWsnfRWV0-H7 zPa@XEqxwQ87ojtX>@4A0R6-G-IJ1t2-UL4<6?@L>5%qVdVdAKZ_ee+16a)B(&PeO` zKwXPiSaFGLdvj3=n^>INm_e{&)o!x_Zga9U3Vgsmh&Js@R>trfKmq1g#5w2{W$1K_ zfZ~2ycBN6ChF_OsZc3R8bL7Ds)nXp&<5Ij{XrN*DIaXerC^eIj(8$!%0SF_)S^2gq zvGy3BaFg_zr3p~sGV#hWKBTLs5sE6d)WVax-r{2&k)he>ZnBf9R-D-$+P?k^Ya?RS zfy@*SK+bl?2eg&O=1)Y8conC}aFG8O*F&!tvye;F7!1(UkWR$P;oTZM-H+dRmdC=29W$S5A z(;O!=Lw4VfE};1IMeO<>(f2sck3WmF<9uScr=g;h)k%pXq^h#XuxR!SsrMa6yuD0( zaU4;QN8J39WHIw4KHguRqbkMR<9rPGxHLXji*LZ^A1{H=NP|z(pCzAFe+Hi&*^ty} z@F~~$T)q(>)eSyZ3_ka`C7ek8PUe5pEAp#jw?vv2(mBGGB(X4HkP|#twrW_hsz(?}@W7^E-et^DlfRipT$g zJ;fuA{zc05^_QD4zT_{ZYOjdZf=W_7~AAqR0-4_}(<{ie65IE8VXbDucH{T0ak`fJjwtFQAs zq>c+-$5?lW!>{vo{)GS4YBBx|;7@mFzJZR0dK%XLGb5udTnW(fTb_o8{*5)#ha}~D zXhSCbz4az{k)(gco*67+-{SG1o)(99dLZn2Z{M?Ciy zPw2jkl!iw1eBq>Mc?(+I;ts0gT}jgZr;#w4E;3K^ai-wX1Ze#<;&_j!L3=<7QBtG# zH1z5b!~ez;x_wNI#yYs?ZxSE~Ad@5p;8P9IM-;><@1v6~J3ru42W}!w#U ze1LURCC+>RCac9yA3$zM`cKSvl}P(17RY{4_fHJ!0ntj03q{C>=wOA&{16AF4@71I zALOX%MKfs0HnXjRSO9Hu6o+h0sR^>4tO-iJdU`)eVsWw{%IH|KgIHWj5WAFA6LKl5 z#titw1Sgv%ctSP{$j-%aGP))*^=e%+!J1yJ386k(SJuSF43)7>Y}4f$a}2Tr$?l&U z5TsFp{Ubi2n;dmQ4l)_JHDdI?;3H~8s#e_oFK&nLa{UVf`B>Ed3#s24k^XOqa;H{o z{5PhfMtuHnOiqos`7F;u6n58Hz7h8~Kb_^TVycgS%paUkV{12(4?ywn?F;r90Uzypme*v4u*x=i}P6n8`?GsFWjl1Wk=o0KlH}XeO)HL!m zs2S7QM+`d0r}57NMBX_*xnGUFWahkH&Cx7?bOU|Z=3r~FWaA2(&H>vF-x?s!p5ueN z*Vt39zWOpL%DSXR-1Hd?7_s?hd=$7Z`V6D35vxAqwG_X8jv5^{zd$Go=jAz%<3^3$ zvR{#cHoa0K`d@%y)QF@Dyl*HV7#0nO!UW6y$PgM1Vci2Tud$29&v|c-`ZE{!h~7Xa z)cp%gga*mJ`^6>wdfC~}(sdLw(_t+Gj{chY zQ84s2W2x5&>sK)M8sYwm4?zfj_A6w2Yed^uyoM&kbCJ)&gvfMcr%AE1AC8FuU-Lr) zU!u+}r<8if`L-hSdW97`aFMF zantuaAyh6WqP8mBY024DXg%eJQ>xz)k^Md5^M#`5dvL%t_4oW}_e+G>v|O#TvsQHV z1HTWu&-*`s>3-4r1H3|_F#m|!CNb?tJ`7#l`6IV?TTN70kuNkywTV}Mgqv#F%6^8Qc}LX$EC=}G&wPB43_OSjC5&2Eg28{VFSm(} z|G{owD$f3g=kW6bh3yykB%JJjfosGK^Dlhx;I=|L`*AUefE%T+t;^L0%(e%%$7K48 zVap0?<)gcOLnwxnsjZM}f+%R^gLo4JYQ@+}gsTuV~G__)R><|H$uyi2L zCAj!xan~h&CkPuZ;e`K@*zhZiWs9i&6_~ix{+0I+nM>W!Ad=Uq8>qWD8}lQ@^lZbv zguFqUWant(^;EkIGs9G0#-T^9S?s@M)>6Oh_;aRg$A-^~Xivs?g6!;b>CCiznqmgr z-U+_4z2~-{tfjn?=nNdtr*we7zxIooB07m_yw9D?X5tT5_=;}Q&smNMt%Cxgj@z}!)?O(t%1~0UKUUFYp+u?8Rco1{ zDZ&BQEjudJe*BZ*9VgUP6cH-wB%~7VQq;F$6Be#M$j{>Xn5$pXzOSllv}D~^rGCip z{o(`@i24J@`7cBdCN&JYNi(StS}cV`SvDZZESOX)mY~O^PUJrf6fGvT5C6eW1o)}* z@o*r^PaT1TRhgfPG{Z6RwZHmku$&(f+mf@V)y}@d{bLt(5#_JCsCQDXBS4Kn>`)k> z4(8v6itPdFHq8YzEmvHaDLG_(_TY1OVGC4KvA1syRMRPX4uqUYS5bj{W>>X8)~ux~ zWC<6WyQ(uobrZNM&v|&MvD=dKl-Tl!m$IWU|=xW*gfV{HH0=q2o(suT@<>KtkQ0GDs5TuR{9!gk5_+%Bs zdGc*My$Di&gwElJlgN<+{#KwE-xG>LM?KZi@PWsBLe~$7 zhMwwhL|MJmjgFUyt+qt3y2wn|zWyRQ|ExQ;W7b<_+th7nJF}}Dmu19EmKP8f3D4b4 za5)fJU%!v)a(T--GQDMLRrEJMkr|?n=)Q?iG{&!;6y+h9h9jarL`|LWy(C7U0|lnZ&pFRj+S$ia zG#u8;DF^~AR)>WEhQ349iT*V6Z&t|^b7iRdJFVWE^2}Wj6~17}Z4;k{s!6|Vb4tTQ zvVnpKr~yg5e(E52vh;rHkO5AahG2gUryjKFWednjR>7}7-cMZ+n5|*FiB;MUD*?Mk zf7r&o?wJ1SZAx#M)1d2T8XwHu-_BmcE@@Vu0?I63tARypFxFZhNBG4Jfv=+Au8A zg`y!$oi|jufBCF4?>O_7BFpDYDH)#8XJJ&+)qzp0Ye|$Pqd3rJ+d51U>1K5ro=9ys ztCPAdC+;NGw$oF^hi3Jez{D~`NJqGufD3>V;jo?wqBR`;?Ou1*U?@CLxj!j~y|8{w zqF5iH<|zfDDMB3)P?p4@oDe8vh-z=I-8lq;mWlEqpiC4;hrn+oig$;o*1?IJ(U)mg zm-BZbcVcp_JbxF`YquV=pD%!FO}nDc-yvd#s-pu7wniszwzHR43fnv$-gSz+-+RHC znYS50On8HMgq3X22m zl&7?y{}(m|OciS))kC3Z?kbz#&@-SXDC@U1QV~f}>LUNCn5>t!iak+qR4YVXl=`Xi zu)8{1^;e)gow0C_fRd}kqPGl%cb8mqnvmoZ?RT0<^voEqIP#pyUXtJj+S zIAu7oG_g3WUWU;5c?7uQ)zRHg(F|+O_rT90b39z*!=ie;Itq&Ua6I^=i)|C&h|MSKgteU8rwHQINLoe_T71om}@KOgp7OshEUq7t& z1E<89iE97Q{e-3atPpyfpe?)uTXs%T`_H|%9m=2W09{P&#cM+{78IE#(`TYWKh?-g z6@qyjwP{>=S_istan~d`qGRGPxObl}Ddl#uZ?$-T5;g%mxU{HuV2Jlv)Y1Ls?umMm zf``2;2orgpL7H@X@j%a_?)G!p*-6CeahRN^ge#7c#c`^?_#jRl*{>>)XpnPsO4>&9 z)Rl2kbaC%K0u$zE_cmUXljSt5oe0kPS)Wxeim3iVe ztNI)cGF=kXr0ywB>z;YI3ra7uE}1LlC#ZJJ{GJ4LCXNALB)~xcFA-+H*H1(ysz(zu zsSkPr{Lmg|woa*%62|YXa>dswik*4nu7~w@)PZaSWo6?VnSa~C`It7(F41eU+$^U} zMyP=uV>0X%(oIHhABmqPt3R%Ilh|vI*RGDI&kt>Y$>mg)#oKV($^I;-9NA?I_oLGU zCl5-AU^}Z^P4(hG^k0p1#^!_^cC;yXex+_6y(kv6RQh}D?CEnN&8CJ8tRnR0aAPN| z@=&7PvHag)^=D|#rhbS>Dmz(?7s^(G#ZNF>yE>x1*Fk?0#z{EFuV%QGN-dN7tvg* zd!z$}D|wxFyFr14rc;Sagkw-8%~Y3;S@6cD2;O^>%6n1t6E|yqwbi@eEpjNkx-9rB zIu40r6KlLB^kExio5VHO|{d>CWfHvia{5%zAQu^)CDTf5N*S-5Na~ z`L=hSBEe~@it~`?DPaf{pZG{?GlfWxf*cmwf%ZBrX zyTbW~UE#{T_!pXW~< zxGv0pUm6dl)C%{ws|%);V_NO=8?>Pn^0TO(r``fRd*`WV>0S4Hb$IwP@*z#nM~U0mx_+-J&{zjP*u2 zR@mth(Pfcp4w^vdH2p^Fq(z9)@G4-DIvbfh*x2Y)UkYHpf+>UGu0JP!l6v{_A!fH_eQZR^r!>AYJl|_3`d^m)`e3y`dT>- zSyWAyrDE!0b%;Z*L((+TJkQcSD4m5g_x`Xn0<`}`9ON(HmJ?7rhmXfdY;f5zTKl?EYTx}a^(iha#@T9xXkDz1#YjdhQTq>D zdZrC`!-Qjft*Q;Rx7@Ey(jMfDmZ*bxak+pcAyoMcIL&9I>R6yd+(3>SU4EG#P8KNAZIiPdh8VA~J4OM>(<@ zj!i-ucmuN)YY$PKfW1sKG6AV?gvU$?*xvU%Z;yWw6ms zKV7!Tffq|3A?e7wbRbNYNQh)QbSzT^ninb#C%7bpVmiXq95vN-bx- zY8SP^8Oekgu_<=Yt%Wn3+DY04xu(f+5nk`YDAQ!u9a-N-2KsGFE>*i3qoa{g*GNV# zyO_)haRH5yimrKT$jGd(4M%@0I_q2OuUHUpBQiGu3e3bN*~?(L>P32b+{+stUYthZg( z+q$9cir#hwZQ|y9q#?4z@O(8XahVK9?!%;TIBe*ikYf@~|}g@_ow!NSUoo z(#Q~{a7H-gZ!Qaxp;M*bcFVf`<(Ay6#%&j}>ZvX1Gj^0{t=^?|FqbB3v%a>MZ5_6( z8+}IGWvyIVN8N8t$!ekUm?I_YC;H$D%=%gaR$_ZVy}UU~#xlnOv%ZCkpFqs%7pn;# z_pycYvlDfh0sH$@qbzI58~*-?D8Cb?vqMzh zi7d@X(Re4$zTXfpjouM1V(!90=p9jb7jiv7ze^q0J*6FCZHcG{f&-#&+Cj}16~zgY z??tMUXcU3u>@BjI>7csl-VUUG^x1bl2ON0V!#2&<+v_E+MqjPdkCAQCDU`ga<5g!f z2L#p-TXe+04v2E|L`TkchWmmvys~p0@E*_^X13$)t<&*d?to_q80*99o3poEN8H*0 zaj1y=z3L73#F=CLl3t_8VOa=)X%*5YYFYOz%%pgNu-~IbOvr@ZP7v6#cV7WMyY$bb z&u8_|75H31pW|$?YTV#`^`i0~oKT(O1d6z9OQm<~)|qtbk(!lZ3^0S^20v>D?1>IA z`5YIpAi!cpP$9U~iWn*?guPH5HfULh<#j}Qd!G%FqB>bdtHR3Z`vrEkO8IaB-6h+5%czY!Q2}4u7__6P#SF zB8mYgdDiWhNo2`iqYrSNX5H*;^)YegUgUIaqUBz7B7E@hKdATd-y`Su2i1*N&_aex4@B!jY7T^6x(3=^CLC+jBD)-&=1dgVs6^?DY_yTu zS&m#L(w>v=-Q9(`3iej#>1w1*SJ z8auo7w8(R+t9s8Rlxtd9SOs~EP3Ec5_y@BOleJskzhLP}_z+P}B-b8t|x1~omr!p<_Kg=!m=(#wavZhxhnEqqzLzd^l& zFTz`dhvglW^I>(WAE*|+De4|pm+-}bV#p)vn&evRl>Htn-(PJ-o*A32jTp&jk#0ii zJBTb#T2y2b>p^J-1lOF}aelq_)EyDdP3p!83kgQ6q+(?r ze95xu9qPfTPoO&1WTA`~kedVE??mB$)DW@YkLtv+x%CwNEyowr5X14-Kjwu{UE07W z=gTfd=Qd!s>y8-DAMJF2#zoQ})qnQR3!*qVDTgv#3$9Qn)-}1}xku#{(V0ipdtiJC zo7MGnv$a{>h+7W(7Il^H(IK6g#M@hNhdEbV-hx1&Qp&k*f1~t=36J5}pC|5lOikj8 zy9?K2h#0Pj`p3W)%j$78qT6Z0$CxCedmaa)Bck$g+>_{x4nP_Cc**j(dQWe;F(c35 z4-@y-j!ScpcrI7x@I_!=jwo#8&aJq@p95pss*aoX05QiyQEhp{-N<7ve5akwmb07c zEt3nG7)qElu-Q*_6l(WY2!&TOU>GP5=~aUd+%E#2P@|PxG42Vqh!XQpsQElCRP@>g z*O(_(ZBxyZwc3U=7q*RUYBW#9h0=DY5$kQcI@LEi8ywBO;_L0|tbuuv^vE7&97EoU zJenmN-%sq47kg=Vo|wNwjR?$(B*%9tGEX>mz=H4%+8t{Dky0&K>2>=0_16Nmlqebn zIa_j1+L}&*6g!bv%M*)sVi(L4Hw$&qz&y(hdbUx|>jm{pH*&J)qe8Xo!J~{tSsJoQ z@~+FyX5i6Kh1#dzOh4)xe=Y$>B&}=Y4&YK|VA3m)fX)*eE7Y2P7|s+hjn0eJON(CG zw8wd87Y2ypUFxifd9#Qg{UV+%vaZRq$N!R-VdV#ktWyp+<7<&1*?XYe&XjJ1L+cxh zuT)&#g;b-|0>ohQ+?>t)Qm?qAc$7A=GyJ8LX-~qBB?{-02ng_+=}DE|7RBtw+-(ug z-Rjg(mv!&@2D&wXKbqFwLlTmiyVd((&>4Hw+(?hrn@3r;Q-op3IZ%twFX^A_@cAIE z+|sB#@$Wrq|G@`ZkOXsDUnR9H2_!TfY`4~84X%66EJB`Atx<~!RC*gWkIA?}o{U2| zu0oSby|vVCeeHmYc2YY_d`}cVg{T~_sz61H@hSBg+`#R5S{)pmH;a;N^hCZSy36sc zFrRmyRzr}LYkFFJu6sS4@M_`)?@})6UsZaGW6!A5!}F`PufVXgZAkLa%rwu+udqJC zx{)a~2jq*sm1+U`uS#`P_xx%~&^b1J)~oH0`J$#0X;9ozSE@6ErPm|=iOAx`O?fU> zWK^jm2FUF$(X8rQf4+x$*c$G?z}Yolh$_&RyWg);d+@G9Lv`sYg);?zU&i#T`n!I> zU&l;|Im{Hd`FuHOT(n~1?mS=Zj(t{rUJ1{c3e^d2y)ChQ*bM#bv7e z5@>r4;D%Vq7yF*W!Rx%c={c-UdaHC$eZ2P=>XBX`T1u5Rc$!D;Yyuv1J&yq3v>5-q zdZJrGwvFM5Z8zjW?iDT1BaF)zHy={_56v&1gUlqz=|^#P!MGvErs(|gdn1_>67*`i zBVQ~%q>dPs50llt;z+^PrlkCGx^$th>=fm8Xy-7s|E~yG}+z-1@ zV(Tu31oWdgP2yHeKkqXgFHweyBQL;@Ef-(Efb`Y}BIKx=JK^4J;FX3m$|;+1>dnCC z2ix!+q>`lmMKNJ?-d1AZ3VK0Id~N@8teeqy3)fNXMpuN{rS{L3Tf5GoD|F|?=hu)3 zs=r8FBEUtJE;@mHj6Q&y@M5i5|BP?b{P1!6zW$=~fH}Io6 zK5rKFE;YJOekCceb!C2qURI}izk|+?sS%4qJ9O8*LwE94ih=~{QrZ%1$I#_9W(g69 zZF5w9bwUp1r1L9^bL|L4eL342jjqqBGRqJiM;vV=L$sH zpWtim7Uh4!aVK1y{gXPQyU)HWo1^o^=oi&-{9ud7LkUMy@uE5-IKLdHv`RY*mfP~C zTl2+tFCvc37hR64sXlrogXnKNjvW-)kmK;lvxSR_TG4o1jsD$_-)k8bFV6UoXzz1% zV!%u4)Zjf-rD>7PpFLM83SWY0EEjuTQU`^T<=-r~^-Wn=DJ#1)(%Glz4y=|tMjhUj zl`sDNlDf(#1gn)o{8>#JnP1oRRDLZSwnFm<1dBCN_{MytjUwuq%BvWf~ zzIgl3a1j_7D1GDYF_bViEyD_P%keI9LokUHD)zY5B~ga%lo)hdzB(#QN{0nCM4zO( zq`gQLoXi(t9(58w*eWtTh@$;Og$EZNAB$QK!mNDpqX+KR&~i8FHH}^e(^|UvENr5Z z{0TnSlCGMbVzEsn%z|NriVZKT@lcfRrt&(8GEJVLzRVY&zO0Vm-?oTue^KK{l3s5L zmgBqaI(kJLMv-BV-uD-{^)%u7i@IoxhlrYT4%W(Y-9edrXxe+QK91eaikq#{;F?}L z*g){ADF+*crAD0}b+4XZvr{u>zfu27RIsZs=?N3L*BckGeVp?zMwV3^)nxBYrrkt{>|8^_-H4@4si$AB>9MdoT#!D=KJ9RtgcFC~c<{sQ-fE z{`w>WV0u#Us``6=ut^lZikLOredbklp8`8CJf+qQ4Whm`4Ss$wmCZTN2gs5?9|AwD z(C4Zt&znWYYlu(E#Ivudhq`AMzcNCmtxFeQC=^+*tHT|1L2hcEb)kT=ysKxO#mG6~bK6y^6%+jhu{Hbf)j`~SY}<6f2~C+uA=Z-@GPX5e*pPa) zkK7D&^%pfymK&RC+brOsuT5A^+rGN60hg3c+q$l7k0o1eO1<*0??tyaaBOgj?Qg*7 zGezwi(7+hc_y$%&rgnY_dQ-hwc|@4s1Z0D-y{V2HnQir6$k4MB^d&*u@?F>v6X^BQ zCPO-)U(32fjh39}3q>W76d*rfYTAE+{zi|l2p4ap$PWevS_d=ow zo_giWtzz?E)&72U5Wy}E|5cqgD8C-h5u}ZkM&;L2%!Rv&$b=lom3tvm40sFv)LFEG znIrvFZ~4IsW%$Bu8FVyM6uqU+m?cM3ekqB?+S#a6)C)w%@#TtK06SUM93z_5*Xm>E!7+zFoNlJF1 zOS#OkLCI@m0~eEkE}yTrvysv{UW7`4 zFdCBOFV(Xt{S(iXWAuY_`j7WZa>XrA$ zh%($4p%=^3g3|9)=rVrF% z>g1zMq>1L7qpegnz2=e=(e#-sfX*AVFq`<%7Ky`Ma%neDafQhGV3%1GG^pDWBV{#5 zK29MPHmZY#y`6hMY^0 z7b@g2s+;ckOsy-?;`|biG4kCXeyKJo$W7KZV;|YF^D8wTjn=Q!pJ-&U-{9^_DSOd; z_wx#$#$G)0`wH$p`vVS)ieuY=`zE{p{*(HSf(^OyKWc7bZR>L8x_FiGRPPr9rR1f| zC9hbKfJ(jc^h#=@UqoKqvd&dcchOC2fq&)c+4yP-^dBnT_yw0tC*9^&@{gC@woB@F z-IPWV>u>spvT0k)9kF737gMCEN0477-t3$DxOa9j-5ac!MN5dOFWy7SqD9p9Hud56 zI<@i-X1#Q2<$W1?*(hA0pwiJE2-2D#DAdbxt$eUjD<6s#wthfoTD7=QD@*ixiB7gw zFC7ej*9z!nt6ob~pxbr%fyGF4xN6oAok7WDf`H zLalIVt%dbk`G-cWyx*yn4`z!N!Ye+G(X)E}S(|7iB8{g~tqrBxsZkwtY31`RTKT7Py=)YfF`$ao3cdBX&hw=V4eL~p zh#d*6S}I2I*K{VYXS=gUnsUR$w`rz+Zok>4tiZ74Y$E>dTP*&~!M|hKc$SOLx%h86 zo4}U4owu00{;)^qGE*P@59RjgdB`Oymx1x2CQ(o2k%pbOn!+4rEIihuXP8qfM|iYy zF79GvyICt&QUN>zUeKV`!^~PaQl~TEx9jz=01f_vUh4I}DgIh}d{~C|!CbDD2E+dF zz|`UFI;}j?s+G7E#ZQl(8$F_dc| z>$SQeMyXCeCtGWG81f9w&>GA-AWZLA8!(Qi1cuxZ0a`goGREgftsYjPmrkwhSE!YP zTvX!6;AfPQ53_3R*JG@AbXYGp)Do8-J^$FCl`AquY_=&(Dcm}@m#Ih3ewm^G)ldSm z9$LYA?2=Vb4f2S}Y||uUR~iT_mibMeH+|-O4Lhi-lRot5IWR*6Er$&kh{)w&?G$z@ zDn$VmwW4gfX%HXSD5|N-L>(1o(L{w!1mvK|7Lh1Ioy>pAyyQ7k?UHR!_stsnL6ssq z2P_7(3MZ9=8boD|sZYN_t;~N~`ht|HsTzK_S`9xeNYv+;`i4d_Q~E8_=TRf143bGe zNE>F`nG0wpGfkV9E~k&6z4u70o?(R|mcV6x3+O zhSiJmT!-dWR7P zzoEgyp*(7Sw(K*H=*lltSc@ znAY^9Y3UN)BWQRYeZcCr?Y!O8H$0PdnU+2xE#0sx9cx&njs+2Khot2q6GfpTa?YS=?;I|~5K1awA9TAB_G*S*CM zOb5UStL+7*;Rm$_0)N^>5$d>R{t^GG}4_>H16~>uvz97S6jcwBfBcfHw#ikw;!192FoM32eyLsq-j{2)etY;yS|% zgiXS4(0f#cD7+i&LvGM}ov0+Rw}{scmCegH?By78v2Tcy-uB;mNtT# zVf$SVYw&2j6CWO|==U9mR<7as;7}~s`#SFohF+=nifgGx1ZchcwlTf;NPP?j_Ytu> z?*VmLC+bY*PqNRK!neyFW$%Os*+HJH+eEZ3n=e3cY3Sh@T4}(INW~{awWz+w6t?(A zY;=uKmoA@r5S_y58 z#reQkg9O&c^cyhNAi#0ux-11+IrP8O4eldDM9{sERUbl_LEfqELoW~+Ku1)8pY~AK z2Zrqc?C1nGB4Qs}15@XuWDpPhv`=?fg{=D`Xaj##5R5Brda|~&w&VK(#Ym0Lz;}$Y zF?C+Lz72Hjz!;X%QJvnQUN;zwDrBaSJ_hX_`UJcIAD!OObCiqujh(+JSsP;q20G!W zTD@ak0Hf{`poN*nUQYm{W4#deTH&=~1|W8@RuDH`vCN!>_J`?d1< z5w!+DR_wQ1;Uyo(47iP}f(!_V$CfJPiI4D=3@XW$zn z*Z9LVP6$E=z9C$vgYs)Tn1Ib>VfzSt0~k+ea21_LJfRTy*Wo{yrpj?W0=$S?l(N8{ zGDkA>b>Lf$x)^AK$;_i(e;V0g>1*;?J`Xc7}aYap*nYc{}Pjaogd6W<%M)yL&y zTfqG1OrM#&K%OVtCtnNE}ubW31I5%^T9LDCW1<^?G37iq#6*;V84UKDQ8oKe(W#i2>gtKVu4dd~F zA^TcvJ381{OOqNkbmQb?_%LJ17`+&_>SI@j3}5mT?UdJHN)0|n_nmF-ckz0M1|w^% zFgsxL6}lX*YvnQI^o`n(zfQxGz7%WzzsYMYVtkr*A_idxt?K4J`D!x?TuR5SztrZglyq- z!pt%>v{AKM>2qc_t!_A@2wkBGg<5+=fgZ;<>2yx5^s#Ti^LSGqhv8g|*vAmxC@mp6 zy{=EAo?!6R+izqjhF*<+6YY$TZr5jf_+WI{Nuf8?r?HO08Z`kY=oS!e*6Kce$7*$h zzu^=#yqFFq*Qg;HOT;impXBu-b{#A{fY9(`qknqz>^uR9javJSCcs#U2HVMH%zysu z(etLymUO;g!8bmAT!#D(t4-^`7`QPblPmQ0|1u+!8vhHPS%drVbiR7s;X8u)M$p3i zXUrZwJAIlYY#)I|??@j(XHzpw#u%C0_Q?liXmsOSbb5V2nupE$?NKzYT1V`p0b}hO zDvxNqmSN`&Gsz{)8!*Fq{|1?%SYy1lB4#p1dp(yBZ-}GIom8uJ>!Wuu#djL&;8JWl zo@11`6G031T}`_HwEG}~pz}DA&CD;_Ct*9jq3Fa+jlW^xodg`$6KM_}?Gv$`L2|Z6 z*jd2ja#8TGDJ)K(@L{?FjV;koIT_V7#2A^&3rnSL#w5N|P|fVVN3a(-7z^nld9z%l~yS7DIXZTo`%!G zEFJAP?5lBumwBDh=yaWA5Ec-OpVBJ&W1A{ zuD4HW)ZoSvHAXVS!;};P$)9#}GBg<0NPzZ&vCFxgj|YPw6sIA@O{>_qg)^LRTrA9oZW;7C>b9GP3-) zN6#DOHuN}Fd-{RtG@>p;8Fs{{U~ibR@8(BWif=S}-5^UrcsVv)_KkmhlhM9ou+2~3g=gA8ygg8;vOyW6IRj_rG>Ez2*OBS2UH= zrt70H^!LAxDlMCtd=D02%n_S4k<%KP-;}iEIpRRMDR^-JHR8ui|McjYrjN_8th82o zkCZ%LCb2rM2!oEuu0uB)f5l)c-Y66Z3l(^ow-w7#pC@A(&30zfFt_$cB zphAQD1{5jl{e4%N2BIO^96YsrqWvmiPPRtx1LIcr30xY4h(;Re4Mn{EZ=Z^MdozG+Hau|ys z+^O|ryr%S>mm99_e{QD8-eKw!ozZwL{@j3T>xNq9;x!(+4|U!EjO-o2ak?^n(&n0K~61&A)tz`pHB@70HnrvN}Vb}_@6Fy;8^5W`sXdZSi`S7_xB zqrFbAQvtep9^6P|OqI2ctH8I*$x#5jT*IHG@3#0ur&_~Ar&jusBq3VehiBI6opVizRL}{jDC_kkuTBe|8qA*8or^n`4z$=OkrJum??Go;w15kFog!j;;G)$sdz6a zY9Ru>Xsf`Hvyk~u&&-%URlW^qUpx!4HI56MT50U}Mh^?hMPUUdMmP2dvxer=hd#h` zm)5?ZQY($clHR1%4Yo$G6w#=)r|W!&#%gur^3BITNNXS4`D(|QfE8Rr=2MOA#VwubGBiHMxhbZTI0j#zk05mT1jnLUW}2TeQxE0aJ2290KHKZ8KA8>g z(Q{F~#>g<9Ofyp=By-vBI~Xji)bNZAWsx>uypeHgfLlCT`5T6Xj7R7<4IQl|Q>XLg z2hAG2Pv9WEZahuVHR2N#SLzXy#T$D}J>&GQZ=_U1nVtRGVq|2V!W>p;J^B2oORF0x zR%7{R>Z&qKAv0FPGxlIZvc))CE%fQIeM%NqYWRi<4byWN`^b${xVRpU->1WNhKn0D zhKArbRGlukA>a}-@iQ*lJ6z@)0oebmB9|00Q{=)?Q6x^sIbNh|c8RX3B~A(VC6SiY zGG!DK&pvJHnNp;I<`!tBu_gOt#`EL(+O;`UO=s?L0EV-i`WMz+DR4J9H#qAVmzh#h6W*_B;nRRT$b$)bi$ge4+C ztcFePFs(|#N3U;&YM4IiQl{0ko!ZkkLsi-V4@0TSbf||iRHYPL$`rNJ0Z(6B-v7Jj z`>yV}A#eKp`;o)<{lER3d+xdCF8U(_!ghU(yw!H51qlzE;56-rC%L?NzIpn?eihN513Yh0WBxT#A)*& zeke=NhCQDdO@=$Y5fPd7oj5f+T*?>JZ@&6MwEg3on*^$F%hcXtWaxxU; z!4l^n32M7?|G-{0U5>~vDiVM{?i1+}Sspo+z!&KrtKI!RZP{kWk0*F4WD5m}=~k{a zb{3ds{(f$q_=Ytu@ymMMOZN-lH7J)AqTt1sjA;i_Fj<<&i9`x0ccF#vTxX2f`t#dm z%*o@Le_+E>I4RhHXx+q1x9r@!a?Lh%^L@DA%RP2l<$|1f#%#R{TS?p*YDFzC6?R4n zFDhi=EAstLsnhI8XVmV=&`D4fPYXC?1}ce5dxpR<9dg7{YH6j^(jG`?2QpSq3xF#r z4yDVT1bte6K}ENEDC2Q8XK-dT;22<9B9|^q&oAoi-e1HKS z1F}i#HE=D?K%4$w0gP+Mvh#VGegdybX?>dPP7lDlA$OXA0(F6`txwmN%E?hF_cWZb z5Yz!)79;;CZC_Qla`?W_gHrnJTI}$}Hm%TGLau;i^&yLY=cwT>nAxfAF5)h{Bt|s; zqVx|Y#J-6BA30v-T;?@+852euKA12K9jY7nLgOU+$`A2gm{q|q;3}WXa|n0dH?7#t?*Y{M;ZRN+kzIU=>QF(Y zpOONHWN6Ed%{rf;*bxIn(z_4Lj{*zti3Jkfukz)MMR8;i@&H}M*AWr?Q1z+De56M zE(?Y}rjO*bH94YXZj<45h=+&RlR6z4!K;>QcCA^l$<}vf2)4J;S>qiRM+xmnUS)P1 z$28vwkkb@LNxVz`B+|nhZ`9z8H#Ge`CY_@tt&PY`ErWh?Mf1HuBukp_=yR6NeYO#e zUsBPn%;!Si02j=8yX+xqX`O0vS-ug&UCBB4wM_4?fTPL2drlmim z9x~+Rj3`Hr_r!J-d-<2HUB6{DnfZW8?r2%t-{y5Fc}o7$iUVgg>C*{7-ClzSuCbonQJ6#$?`fe7u0f274n)Ev)2bysEFb+ zTWasj*lb4TPnoFYY%lHvmoQ=(?M4<}PVG81e?E7b)CixeJ%a)ZisN-0XhMvG%aI50uXr#SjLKs4QC9%p587DX+x5!7?Mn!i6g-dGiEE9-k4E=ui}Wx zX;}Q-P}H=D-GuiGzS=mgA5ZqgwyxT^#y+3d&gLJEYVn&&x|MX~+QQjQ9@My`>6Mpk z1edakoegredD^iO(1vBm%CYGv~6;WT|yh4naJ$=h+vxGc70l_vAB$ju=$ z7#Gf55Ye=(_T-S1e&zn3*)E2iore*vD2YhGsr@ZjRU2he*W!tM!l6 zuWmX4E$xz~oNpcdTz&o3TAAdWRfUYMmC~`YY!*P4FLI0Tj1KUz>A%4g8m_Ou>I3{7 zvxwQ!9!=|3;yMz(4w)AS`3 z-8%0b^W8Y_O`c;VHS+bw$w!M?T>RdG4f#dHvj1vv-;^OnOZ$;g-A)eLtyAw?c=#O4 zY22}gHT$A1Teqy(yhg9tWmzc8%s<*tK^2CuVlEs0oxNT0pX9O}OL*cKS5>IXPOWr9 z-4rb*z0c9K&+62CF)K%nEOOU3*V6^0R?rTxmN zb!K6oJ}WLQCuntBP__R6Zd$1!(Q8o zjXUGvHlLQ46QazIGR=v7nN4{1Xm&dEHaxHUxBq=X#E%q2cDn!Af{482b9-lf!|V{n zPJbmpXQI&7t@+C6xzfZ4% zoOO;_c9iYTIn+Knz~k!6aFB!TcvQ>FZ1dq^O?$U>ZXdV#PH#Hbt;gf4K=FjNp4Y$7 zrww0EJZ#_DrgGwneQ-Py=cPf7*Wwvh*55T=)GrCjDn+U->oRA!CA9&maynms_KN5l zzP((V?vAsZ3@g1HYiXC>5`QwB9l$YMRn@;kp}cm=+W(pC2w%+H5v_0B5nXfI{nle_ zCtcL`(p+FiuTbB(X4CdH>i)mSqq;2o$0j2|NYTWJV|=u}ag{vmWM>E4B~HARwv_~^yJhn@!Y{lJ1fT02N&T)s=i_CTEghBCD1R&vQ$sDS>)K0 z0?8yccn>bTvEzm|5Vn0YhjyTI;shsCUPKKORPDaL=<`rj1auTA~FA7qWySYnbCU&Au0E+dE@?g6= z0O?=HAqOt{cjxR1wR=Y;R_bThKK;cNq$}Xl3}&@~|JGop{%m|l#`)rxcNTF19Q4@Z zfN3nzEs6FIE=}#EA{FT`*H2jPc&v?q(-IgtvqO)+$&kcH;W#46SR7_775@$n61FFs zAu<~|PjhmYJACc|p?73-JkG&W)UC38NuXRO7BVWcqaUIeg(e{ycnH&Bz0C zBJbpJCi$q2cZN5xkK*l%ts5`Ly@!UIt|J-yuciGIK7;oUm}5FsYM<{sRo1kmeyXBINQ^5a8Ffh=bDz&o#RI2f*L=S)~#HG$Wr)9uA`g|FR5rbnOtQl zE!V({PIDAsg^X^+z^Oq^JMoXG*a*h0kHtB@OM;qq;tpy09*$QI*i-Dr*=v*hxV1&u$P!2t)bne&xl;kC~No>_aefh%#(m^LguAqBg4 zQ04y-%VoJLlihEpQXJ@YtncuH+MeuMN-OJe=^&X{WS2(x;xC~Sy0*3*%7$g=IJ*`+ z1ZCGkO09=ZZOZgIltk~Vs{C{RuS7#SAsM2QkhI>!JPG`<@y~2`5-4hiQW@`|ct1Wj z{7)Fl+yUMxPqtrV1UVhU^2aP~UPg+8cWVCqKHWMalIaH=z8;Y)-_L15iBk%C0X_w` zW|zKqhl$L&GQ1$FsiXCkM+`ABfemC~Z?ZY*To;HQXX9*! z2>%Rvvf06_M?4S0f|FTM965r*_c|J>!(Z(wiI1h~>ZcLQ{;TzZ43Fz90%~6u(!*dr zctH((jJsEEsL1+O3MmErIL-_&;PN%5)#Qy9*;R`Ln9r>|OeQmX-7<~Kdl%b$n%*(0 zTW5H(eZi$;9w=+MmGaqVDd4>&F~BounrV4#H>znTj}aC99tHwFxJu24%6|{9lKcr? zCHWo>wqY$S2e+Iyr9EwvZ&1t2u{*iKbe`KHx6GF{zgJHD^~>J#^=!Z?3zth~BgtL@ zlY>qIk@4z0KoRFaM$Gn4I54ixS?v#EAyos&6n#_!DV;Waey}~w0&FNnN?&w|7q3;=$!UHthT?6SR*mlv?hssg7qZb<>RZddwTuCou)U z+?k^K(AP|JeJM?!W@bc{{~0sM8KP?On32M788^*)&F1hKW;`vmLO+vx`b_8@se4;K zXBzxC$9twu$>nfEb;q`y-j{x)Y%&sZm`i@pIJuSc6ZWUDweo|;Nqf(f_IYMBvairr z)Ot=w0`2I^*ivc;|AGVEle7bm*ZX2yx9^B;-J)9m z8Fv{o+N{h}vQ9j0WzFvYyVHuSCr{H4bNFmWdVi7hinIaOwXNiaoU)JSPCTAXxYFwVgmDOgy_w+0EaTI-8 zaY045mvAf3H3;nln5l2rv6W=$uXZ%ZAU|f=e0jubdu{z1(tuPzEz{MRhJr7gCM)=@R{Y67F82}ErAc;Yq#zBpsM@`hi(M$Zi{&M z1I&j)9$%Vx#Xhpn+P2BEL4q%Q&=zaYJT3Q{5Lds8J!xuj7|;qZ~hG${{tFC`qU^j;el82FFw*r4Zbf<4W9I( zrmPCDLg6#xYUEXIo4Bz3V^H|C{*OUrRh$}pS@y>e{hufdk@!$7H6b-lO-uzVXwoW* zMy;zfwyI3UP9a}`(x2hHLwKheqXzbWqU}?YRWWMt1SBfsR@S8n@L?SSf!LI}mg^Q}6qQQk8HF=e!rlfK|g~n&$ zgGl)JsrEq)e7vrGP=nV>slnUb)Zp#z*P&Rbs$n7nYV>vJhX;NJ0(g@dFP^|TLR1N!?~sXFHoJIVG|B#VW?8b zZ=gZQ)F5PP5b_%+6 ziOLX(A6}pa1Be>@@WL1x{O|%bP^1Qm)If0zil2ibkx--tiqt^y=V+iv4HT(?;?H%M zKS!AV3t+gER!YY`Xl zoG0zJ{R@~a2*#N?wyUN+=PrgZTl_oVWL@Kql`>sG`$C2>TM(SbJ5MWCvU*EkHcuvB zz-&SA2!+122G3$`{6@*YBlItfV~H5swk~Yh{J`bUYy1iPMhU6oi$?_O*joaZU(c{L z@Jpa^jm{J0a~Q=hg%F(8@D&WtdXi!Ma0_4@q3K_uZ*lbe5~B*gcr{EUjvh2!*sEE+ zW|gf;HJhH(x?e<5-ht_4-Gt4XS8db%-4d9|OYkqECyr$)EOho%f%q;`P5@_uRJ+ul@2lzaPrp^2UAlPFI^g?fVQSvo}BO zo73&Dh&i;>JA6KG8&=_mefW{Tq3FZDl|whGLKU1{&*sF!bhQzGv&ve))60IcMQ)_T$g{I=ZpAu>UgjZ}Z7k z(f`)t>fAx!59@!R-W>F$G2{|o@ZAn$Kl}oGH>{s9)cK@uS_4L=^(Ei_`sar}`z2q# zzVj8^mizviF?tUh5zOe zji#h3fZ<~NdEeTGxfNx77t;E`2~2zmA|xFq*}6KwDZrTKv)}ct!{l8i;W$Ap0pAm7 zT&Cwn23{c9q0Se4yQkyymU_=OyJ1>Y72X3IpSb|(pH|h%*A-N3+}ANQVceHk-*6zH zk}I0lq8%!(X!=qkX(iS+b%=QDS+A?=$|n4r2X1i?t$TkyC#D+?#rfKxs?v+#%eopb!*N-(Vs7D`KH-o%! zzlz-gFMXr$$PQH^)ovZk&2d#F@|4O^ zgCE5unQv%AH$O#&@cWikRU!6N{BQu887gob&019?YJ)a(EURU{qGi6WW!}<;j{Q-{Q0FkbwO_hmk9JmwzX6%0lm32QtyyGqvCMJgd;~-Cb zM{V6bzO8-Sb+roK1@h0Bd`-oOd`sm%3cGi`tujPj zs+-liDU!2}hP!{DNz|ESPfozs#v$w1oqF;dWr6H!L*lL@`#gQbx1Q|A$HXBWW@TJs z5ZSAHr+*PX77lVRlP5I!iVB|uH>jHwx$kJmWK@Efwr!~`{Y`W07f~4}sjV0R4X55#6~fQcuJ8Gr zCZE!kzUMV%Wq`h=lep(MEcII**}XUb3BE`V*LyJ|64}S-!GVt=>>EEg?0b)?Fkt+4 zwO#uAI#q(mQ`*yg4^i*YJZW?7-0UBdCFTTGr3NFOCY$@`so*J)*X!=T|8|XjhS5hg zI?Cv4sz}0bDC-_HepMl=MWu+sFRf9tO%iv6h z$l+;R8n)SIw6o{5v*%R|uDf3R;JRmDrcnzeT#S+O$8b>TNNFM)diB1h&^g_G0UgAj zzr{xQB+?fc3O>~Ii3tsTm_YK-24f`Ov~C8j;sW1pnp2+|vcBDP;4G{y3(p|$tQvl% z=>R|J*80PvrnQ6k(d1{F-fU3kej78`kDgHBZ#Q+Q-shTHaZZaq2Xnch^m7mZnfNZu z;X%9aHoe2Es@95(EDr7f6{T9cItag zpRd0~b(Wjvbls|b{KWLpc<>gLC?kXv!;cw88V}y8a&Fk{+s1>(R0(kXF*Qm)#K>zN zBdMX__nRg++Er6){{{2!a@22V|GzXfo!wQ?p8sREp;R{+yL~SsyFrGxc;G=*dAaEw z_1R~dCaRZygbpYUjs2+U%k}EOchNQf`LZg!fUf!azcqafYfS4^48R}14AK3sHcjW% zQtP|Vm^OnE?71|p?VeoKKHsBrkZUzHx%%}VH(`yLP}Wai@3XJM(Qo@yn26&)X$s(C z3x6%Gzdgo!`b1P0#An_}rvIl%`l+8ZeW6~u^mq509)dZQ`DxQPX#x2<%32zVzuxq0 zBX%x=KL?o}iu}B3;zZiWsM=(_+JqnQPOH+dY;yEhP47(TD%(M{b-e5`T~?LxrcdI^ zJ@sGc?~In3L?PDB6paTns^Erc`_P2TfMI0pztG=dHu4RYvgx|IOTt6p-!{Elua>>u zG_k$SISnuz98=csntrJs{R#S`=l4ym{$NEL>b_8Ae%~}{=*aJzo^7!4M|%9z8-kTb z68@KLy1nhg4W_eTMaAm<2XNpP>-{)>heqoCU#{n_XuIesmbS=4UE{&*Q0^@MgnBkM zSzrmRGE{8zzkfDn@uJ`Vc{K56|8X_v_cX|w{d*oc;Ga0udyc+gt zK#PB!1aRrQkfI7&_)iCrYVl8W0-QPlTmx6Rb8G5TKXDpdJ=brq%7X!a2d%Rs0sjH< zHcdvX1vT57DhB+M)c2bG6C0-Ws^B^P4)sRBzlX+9E6SA~insdv>!l~Bo3lgR6l~qJ z`RAa&gYA&cs7Ski9nLx#P)$*C(b6{kb!CB6L+$=RSCM(YMN3(6T`w-GO1pop|Kf3t z&zPdB=Rs%Pd47w3r?PFv22*EBrz)I>N|aee4k|HO9ylLpo>5QW7vnU1zW;bvNy9T` z-eTn`B~?A&zgEre^!wUoJ_jLJu$NR-tOH3WRHnl}sVl)IBqctmr=(O7u$prLN;_+U zN_9|aJN&KE7qi;ftSA&zU=r*Vw7ppud0?FHC;9PseOhE;^FiO#8x-eiOYNQK75j9R!owB+?)u~iBsH7SuDyhcMV2==gEp4-J zN8{>}DbbhtdQeNRkXmr>UW#)=$p1+Qr>5J&+3EfRsy~E|S~Wox z{OG6&GyJVhMXkQ7MdhApI$!n7@V802t7e!1Tv}3z8K|GAP!(M9O)lcc>;1=@%53pv zRSv<+)S3S2h$1%Ajv_hJKfC)5ea&f3I%YQB{LW;Bf$I*o5pwjq^(w8o`+W@?o>H+H{*IxJdHy@q zWvFrITz1z`p@)Kts^S7ziw=z}@T*45Er}(_FROA(z|E_{B?vjAs-R@d?>c70T6bA~ zD7e(W6`MUOwG6sA%`Wr5gOg`&IchU`seht+X1RZb^ywbY1asMl3R+MrtC$6sWtFu2 z`_&f9-_&}79Z@&qZ)!+YEX=l-jjM4B=bDg;ufXsdCak4xkIW2`;qXvlh5z09?#sBZ zukL`HYqVT8I#gWcKT^-@khXm z*CLss8d-}j&ns&k3YUj0BD~g|Ye**r7)z$?IzKj0GAa`V`EgaG<}p>F=BXhxKc;>v zZ3G!rqZ?7{S5#mVC|s08QIMn9VIUHl9YkJtp-K^%8F&jT?dzUY1)>7FS*^-M;qscA zvMOzW#tl9d-VE|Q-QXgVsHxie4Kq}N$a%VXRON_zOeI#6=HseFB-Y?I`6X2)@+$*2 z^)(gT0%}y-dtEnG-Mq`z|Dc1u5&HrZ{Ebsok#wfo7H*uODn!lJ=5Ksh1-62GMU}Ub z>|3h15tH?ezxMQ8N*DabaaHMr+)a(Du+`tK9^2|aA6pmDrIV=L;Chw3-t^o+49u5Q z@JfHjyp*g4c;JP`wY`+z^yBcCs068>QdMg1S2=1PRH^kaof^>Omvr-%mievD_T~xX zanjr=Y*nWXm`ot zOMLU}dGpgMwGHv#{Jib!7;3l;k+yk!4QgM6(nkdDiIY^iCqZumOf1$R6z_0 zwPlCDNln|~4`3>*zK&Ym@{qPMpp{=#8M5(`cJqoV67`0r{-DY`L0za7Z^ix;kuy|* znunA{&7)f836&xWTZYs;rA40BBG1?&bKf-!Hl6B)$>7#MFrTL@;os&{m0uy=+m@*C zF4)|mqqyxLrAdRz&gM1@Dk48a*+BSJRU+~=J*sXSQ&l2=t%AGJ_;nMq3#A5j`&-q4 z-F_c7Y;E|M%8=A4s!vD5?f0u9kwtxo-Tsz}fmF-m=rOFR*H2IkKje$KpLMMV_5f^^} z`Ue_Mt1!XOfO5l~48N!n1k<$chJy^hta1du$}sl>Kik}v#_k;8xyu04Nkfi~F|D0m z$$VCuD*R3Mcu((A!M!lP7k5cWQ;d@`B2QyeoZvoCas20n@3MWlw%kKC%Y`D&bp(xpeIaw%h z!qd1b?s$mhg&$)10fXOoFwgu)J^ZiO{43h-c+3Fmrb$4LoBWVCenR1U2_5}+$hhHR zIf0R3S0d9Su&*2ZT43Ms@O5BqcRXeAYjHho^V^+XasnGsrK{0BKhO<+JcuY9dT8dN z&nJ8AMmoh*+<=6)QKCkmD;{dV{kE@9{0brGB5{tdB1Nz0FuFDMJ)_MdzalGK$J{=?sNPUj>Y!mfjG z`V2x_+D^XAd@h&6f7K%&VENaWZxIdq!hZwAS#_!>=5L*M@-3UF1rY>I&VJ2&F3@xy zXD8nspz}}vg({dp$FDS{rscGD{|4rBs1ARV%0P{-sL)&^zO|1=e7z2TEp7d#??!$i zyRH9SwrY`Fox{&GfT|r6j-5=`4(f837j~?6m=pyD@XsP3b-v_ET(i;yY2ySWn z=waqtL_X zeX7l)z&&%S!^2O4Mk1%WnQswY8_B0+T9N{b9T~xP0!yI4k)DzvEDFMxitCK)_zQP! zrE!Vkf`BnRRws%DZCz!d9wf1?JOsiOHsT?-~{t6q7jeqPl9sys3d%f z`4(Dt!uNx6%O4~d_CId(SJf&lz$ZKkJd{p7#(WDcIS@YX)M3apoO(v(4q@hbPFY8Y zd{L7x5jkmY1615ma5nc$V7`UcmE}D?d)Ynj9&fjEw)dQ&d+!P9^Tj=3l{t(x&RQ6) zxviT~CNC{*_iRwr12{?DvxV_6@#|{%HV~x8{OK`5p|`{Cw1#^gQ~_j#1r<{6Xt?Kb zJIQ)nlG)@}bk0w)5$V|k8+n@f7SSkVf*KgdML3LJ^J`GGn4LP`E2R>1IjwfDpXDv0 zYyEPs92q)?#zP{1p$aGcllJU_aLtV~KJVRc@~7v?YD?R_hncU<)#S~Ywr+Y}b$-M@ zyGu%a@BJQo>cB_*lcqSZj5anq-EQG7r-G2XMh2Zux^5-~L(x2LTAkrz{u9h+bB_F% zOui$J-&=*7xi1*z8V~WYaPNzTT8%$SV}8<#w>)YI&=lQonQswY>*4#_Kp8bx#iN)j zrVo=?OWS=is+}6E3h;*M!)pAff6iQzBC%dHE;G|dnZJnnPV&mS&fnp8aBJW?|D^tH zrnZ#mKJS2tu~iumj#cLOncilI{AUdN&O~}2cV)kGuI8!tKIuz~45L~+!`^51W#b`{ z_jXo})KC_0XEFc&0APAp%TIE3>bq|?HTB=W4F6lJp>uTHzmoZ3l0`6LWG(aOF+Wdj zOWXY$m~RmcdEuK?ZakDB81lNBSp8eXfI@~E02x)h9s^#E2l2xr@&1P(Me#~p!XIG1 z$n&gxzZA~`PHu$%q`hM4Z@d3Fu-yd^0jaJIS21Mb3MpeE6mn_l&Iw5CDen1K>YGv)`fj;(Q5nYS-0X!*tBc|wA?CXjC z2i^i$3*RaG0}{SP+O_V;wt=e2JK<+LO#X}vXp|xAIdr8w*^6xX+SQ(;5Y(rVk5}{s z&&R7OcoX7{X!1|+fl4BIx9Lyv8XeUQo}&lY-)q~J#c$orh>qn!8QW5N;d@FuGs^NZ zwnbj}Dd5yyev+%JFJ)mnrY$DN?wm&_Ah6*S~ng2;L=q{}A z$;k)Fr*uI+i4E2i3Npgv@9Y!3T6?p=@?WPvfebNL+x@h3LbbDtHWJh)}v(wVSjKX6h~eK>zG=)55u>h- zfwqU=0O58JAQTSd(6ESxyztFKqs~d}w-9pM;hEs!KM-Gi?U=u<;gJTFLG|W6GJ$0+ zwD_A7q<>r59+BRb;6u#E9w1fyktGASqP&~z9#t>h>TkW62k|41LelL$%$kp>z%8Wt zxJsezenh(0A{?GA`WK$RqzX3v6_8}d!hiUi!-M{judA|+e*;W69wRB}<5?>ke~xj< zAkO#;DnX&YsKRLGN~cYwK|B4+U!tw0 z>hM3;a0dPq=6mdXZt5B2kAdG ze@&GjW#3&p{Ylcc!Lq6X_N?UU=A^W%FGxq&!v!6|{3lXWp^kYSyYSHP_p`$2AXk)`<5tm7@mJ=?NUCUwsj#DQ%rz-5lum7K`r@IT$6uhTm5E6zXxuqDmA!xd&<_0 zQ4>=cY7h=JcxH&2vI=|?O+{JM;PEwT5~@H=PL-)C43v=m@j4YQfx>+`YVa5UH3?Nh zqb7gL?^ExU{2{8qw;-LVQ?YLW$GvZA5~@fIcBrYros6f^6qQ9yS*3JScp8eIs#9ef z9QZb{3?2bR1E18u=eHq(SBXnR=2VrMvI>3&jiqALR8;0WkjZ245*bq!YOp8%4`@(y zYJw_74Ms9G6;-CDFz}4c3qJ$(M+5jS7)T4xuAsqEgqonLQiBwqMb7=tBIn)DB4h7Y6fF=x@^YOQsCMvve)HSAJcQ*y$cS171~u@A^C1y2m|uT$M<# zmr_D_7x+AQ2%kp+J~zgAr-@&Sfe*Xg-yxXvLngk+r((eUe_mods&d~)slNVQtd0lD z%#52#izCcWn0)D%3z80dM5P(CUz;zpb68MAoV{V1)t0hn>Y$rCR~a85feX{9QYpKMLt$1Gp=E?80RFy zdy|ZhnRt(-62KdJ0xE}g!@_`;yO8X;?9AuzF6=bxFTX?}V2y`A&FLC0E!_OF9&Wi~pGs(5SZhdf6YCQmAO^!Yo>s)SU_D z7gYF_<_^{IeF)zv8I?@oun3RZBe(m)iit}PT{xyn7}@hKtOBQ%lAgvg_&@yNx1+|< zxPq8p()@cQ8- z8n=9$`DuJe2;MRtIK^;YRR}J4U@9b8#TzI847lWh2N}k5uK$cd^5KdHA7LEt2a`Hc z?%2jOd=Z`sCOBxq^L-3Q@R=aMmIn?o93S`r(1Zt#GMZLlf-@dC$uOQNCb-~%vkc?T z8^OaKc#z>TKJbIQFB&!RD+or}E~?^7KR75aLjGm6lW}9?UvLTwsNjDQ8B{Tl>qDk? zPp8(N96{^qVtozxw`7{LF<`T@uQsO1#p7p?K zhVeKe!37U2K^9dC@cLm7JjmK3XkEdyRheJ*$d{OpwaZJW^yD!QKFav`zz-1&5$;sj zYA~R}1b3QnuTLun@h}s?VGkT+80#^DqaHZIFjk`kCp~bC;k2p(wm-e)3avNAa1O1j z5Ut!R!Mw*@mgNUkY!u##9=O183E$HJJmP_e8ODX_D9RYDcorFUzqEZA~9yrW!Oce-@d*CR;Nqj8_aLNNG z7|sm53^eOO(~Ra-nBam3&M{n634(_`@F2tZ(gDF`4_song74p;%omS&@KMIcRh86< za#yXY;VGCOegwGFgd;wNLn=ma*aHU{#;Y6z$2@R^;iM`8#^s)clhBkbzN`b`oJTm# z!h`s-4&b5(&NE!XmvsP-c;I1%NAYDHlwnH6gO?evs)CJ=dvGcnhQ}rN`~#T}nD9bE z2@VeY8_@v!<$)6nXVJQjgG&p{&!KhosPpwj zT;RhTU6x&hs$Vjqg0F(awcBDMEBHzf>U0U^?baUERxhnn8HmsIdEhF;LA0)5E-5k} z)7li6zcivMg4@c%BE#UaongUjOzvPyX1D8nfYXFPC{;hcsG9yrS| z))-{G2Yw1=p9igK8ug%IM&mY`^q?_D(>9v*peaW2`xIFF&zM#)@g)_;2Tgu&aR7(j6uESmHf+L6 zbF7Bb3e2`mD|>Kk$3cHlZ;|CHChpiBGx zm|&)-cMxL*PMku9(vWi-i?Lo-$CxwWr3HNDi(<^MSi!`d7(Ly$OyqGHL@|E;4T`bM zMn+5{y%|-8lUj_UCcdo5dSg1qst3l7=bNq=?ML}tDN2mfeIC7vHaopjmB$dHdJ{1& z3o|oh3M0l6oH#K~kC^!K0P96*;A7;{#)e zQI47ESyLD>7U858W8TDzHar@js{ za}2Gk5Qwn=C$$*IO?-J->&@`tvuoJ2q_Voyms$gFxk8)~G+_yGM#$t_ASuKd5!b^g2k!ev5J>3>I_%VVmf z$x$MEusQlmY<51ix!Jd2rYC3FoSf;&xo4QeteE~6#F>v;Y{sV5{lD}FoXyFZo?2kr zwMd?~{1R_?&e931j(7Y4e-DL$E|?Xv&Fr1!NmIg_6*1jAe9Po7$bu$&r;oGLJ6K*~ z1G0d&dqIHZlBRwSmVm&W@i;4O;wz~a$$nP%+N_+3W1}-%^>=KOox)jzUYzxdCSQi! ztYMSCGQ;wG?wwUO@t%Sz!QY~uILlQ`+_5`m@>iBXQy$p+`4xupv|r)HYqoJY<>(q} zJ#iKLm8&L~cbfRhsq)VgWvVaEGe2tb9r>8acjPHtcbF*^ z__aICq=~Nzf=0@hr*+E5e~qJe@h~&9XiZ}U7@Ozd6r_Q(UcuyJq?e)RUnR*7>zb5I zu^v1J^dHo1LX#9rvCt>nX5$#iLhd{+P*ka;}>E)x%nTPMs>gi=2oN>$c)fzR$Fi8gAqa#|}$4z{VkJS?2`5p}eiX89#!f#ldCi#~3aHk1N z7~!DFpU>fk$&bq%dNu)j{xwnVVycq(XI`tTe0Kd#OWS4|w9Z2@-%rg!gatp$15oy%*xxj~RF`&fw;px-Cunj7}u zT#vaC55EAK>{@8t_C!AFYUD z{-}pfDHFfq;SV#P^jvl@3lx7}n+4{Mn=mH(3c_$YexA?7*A=zddFc2*V3J<<2miVL zXn>hvRRYs{H7kesJj=AzJE97IaQljxcr?Ujafb(HTazZdI6d$_omwj_l{R5H&CJV~ z{3sV}9*%g*;K=*5N+M-cabCd`?j2V-IH{F`(sxxengvaIB^~032_wVm`?X7)d7~yA z9eyO(jOT(Li8bTW?U7{j+J@foM~XHv0%CDQ1?rnS7A>%#2QOE63M46BK`FVSS|4V4 z9`?7_HwU`cTg;?XUBVckh5F`6O$ml`D%j9`+79x1PV|bRhD)ZA^@FU9g9z7pGp_Jt z+EZY>g4X3cGNKX<&9(YoQ8n@PR8V9-A6xK&73mZbLho`eB#-v9*po&mmv{1y-Cho+T zG5H(fpedZ3j&V{WVvLM1vw+r&(Q0(ZSTyksS=Ph-Ns5uoxYV&sEkJ$Ih6syMDO|V{ zW5wie7-spZj&b7Ih;cCoPH&34jciEb>04Kf_OmH2CmY7Ju^!yCoPZcZraEHGL4A>Q zQxC=JQkNL*GrWtxv6IclY_sY;BgTYjWJ6vBC%9uwnfS&i8_VbzvnIR&>p7@9ech8c zaVN%t$={d;jlS-|4JxFr-kd;vU14Sktt%mn$G}8)jAawwILLYx9pjh@;{=d``UbmB z_d~*!BZku5dSsUF^$Yrc&?vngd5=`tQw|#$=<~UY@y)NHPUe zUi!Cp(ByBTVMNIf>yv+P$;6`(m1%0m$)A!Txw45z#+gsSyW)^#qkRr^@#VUum*RBs z;iuAs$(_uT8#3#HaViM-n>+lQiW*;lsjC@BVy7vF6;BFc8=^@T3wdzz3iAuX9)5uN zmdVFivJ89O3&;-X#Z0`XJkX4T%5j%4VJZ3o3dfbrW*=xWm$tJ|N1Aa^NoDM9G?#D` zr%E{K?vdE@rZH@*l?d-0VWU(cm;Qo~sseXbj|)mB9wmDe4C%Y{Q1ak8DEa0T}MBT{LQ1}VNQGq3R++|Tk>;AC4`P_cF=vY)Wm1P=UN?q4O&bB&h8VH1y)L8Ew!Exl5B<~&?QIf2AXVN|0EW6s>M zm@4T?AU39g=ewPyP5jCTXmXa-D}=>46Q_9q`p%Bz;(`aaK$HHUhflpm{G!R1m5sgq z?}`&Mf93qz3SsexsfH;s(BXndO&C#H9jJmF<%`EmoDMwT{wp)!BdR6X>YaoG(PxTb zfl-Fo(JQG4B-ZJ{%ghg&d`W6a$mGiqT@p6=SB`@w``86W80yF*98)ohnV2y&uF7ol zsoW%24=zb~@CazqOX-}_CQKWMQ16ogv?Ocda;jZIIlJ7-k+LLj@;8-0le+>Mw>Z57sw>to8kMenk| z3Xghpqe~W8EJuD^xRicr`V9Px$=?zLjp8izbS>>H!cVt@=S{tBRaNS)9aKvPO_-(@ zs8f#yFMt^tpi4(gIUHOu;Qs9~@F@%|XXpy&{tIZ{8fIqIRKoFIgwi}2e#=Pg18T6$ zXYx0dRONzN%*#4W7fO|Ka8)XJxpoVl$mLQZN?>@vy6N zbS$fy_>LTC7+a1xIQRi`Fs?YD?woLzcbe)lpq2+s{*}~YWHw~-rS!|gCVxv%Rp6(4 zM*)1&v(UI|hl3|D*)>3y$4p#C%JPKC-#n&LlWPOiep<<876(-UW}Wl(^6Y8qWl}GI zO;P2&@BnJIP|!gWmDzK7(d6$K2Tj&WcFEO|U~PG2KdR&k5F))tT)0eH z%g0PU5-TAzxy!elT)NbD;&uegIx9!ZXW|>iRq$fhp z-Gr$}!(j^2%QBoYVH~Lzp1Jn#9A=!CQ&!HD zqYY2UIoH!x!Ng@WT7xEEde(kW%2n1~8OTw%C4H)~Moc~QX801UXkt>XQ4d~b{ff!o zNp{HYn8|nIsG9s;ocD^lfy=OVo_Dd06#-LrHMT4elQTiA2%7k=anSI+B22bg zBOY`_#V(~wj4Vqe5i|L_LoA=LBOJOEhkyi~GDWv1R0S@aF|;CM;!>Oy6oRWW zFbD#dVG!(&gHH(*>;wi)sohDHg4Ckb5)egUSYhpw$={u4{-|xWVxm3Pz*KCUED_h9 z{*kM`72_VY0%(M~k{VYKi^o+M_PXs2KEgeHh*T56{kun4Kdj2rsN<*N;!BpAD=pLL zk~9lPO}+%T($i%<1(v6zT*2APatbP8@;O*_*|g?XXLPMhnL_a(Xi~-^4iUHJOqkXs z)2NUI7NgeX+lkfFt4^#%Q+^3{K4Gs`$dZZEm0|t9&Nkkq?-BK8Do4gqmCZ@iJM1(Xd|D^-gaN^v83|w9vXe z4Kv@<#gfUYm`7fW$4$N?pD_6n*(1{t*`6RkiY%ied)J7JBK)Ap@+Ln%#zqPz->I3W zqaFF8DKC-joI#PL*yxC!mRC`lu3&I@6=yVeTq(P{_LE^QT$ZP+C^#2iCbv~plfS0~ z8kJbBKKXtBq_)*Q6JFA(teKc{#GU={n9HoVTOBm@#2ser;4Iu7j_7PwTc+3^yy6b? z&XR3)%!`Aj=scY)C0?B{<@ZwfB%d_-I99^5u$%jdSjiHiY^PVn@kEt@u_w^LmOxiSKr$^>9Cf||In*6;MXp+yFd>Sfq zFs)t{XMB+3DVlP7eJTezXXvged2!YsG5Iod*OX1ZQ=U-laF|c@Z-N~jB!4+?dPjp!)q^Y$jo)s zXKl>1v)5w%xXG9LtWB7Fsn6P^$wxdX`0-yI2A|^P!+UMkl*8~WQ#@CZKFQ@x+^Ivs zg38B@r375JZbRB54KWhPh(&nPJZ@&4lygHl3bIl9W(iI&9Sy>@*O+l zCSNwA*MaR0iq{_MKj*pDH}<1uuE?)0kycClx}c7D*A=u2Q)XrutxLFPOl7X1m2QD? z%YzRyKWg%6_(0FUuaj{;+}BaJxb5SrX+8}f@lWM6aMsUw_*6kkBJ1H7n4k0Tac6jb z?W%bliMici_Xc5fJ82eA!^^;(HRHOHiSLVprf_%^^!7A6kMpgo0CM{(t3;3M;$dCY z#8;I-ldW-+PuJbhb7F}4Onl#n){AzkOb-@_@AcpkYh{_4AyarkTm^d(gp9ms#Kff# zQOo2nNU0d~YC*(Ie18Bmf{!K!79fV9-sW@t`?)yLv>n*=jHzOO34&Bk>q-?^fD_Gv z6r0SOdU8UE7EJzrkuT~x9AAJstS4o1QZj{cRbMcilug`mGHUYo4}vCpI6kP@6C<^& z#pt*xiz|k3ga#MaW<9m80f9$*62NKaA{W6J6|smZhPy%~h&iQSA2sp)70?K2eOy@! zssAIWyv_%##<0)~8JiJq5OqG5HuQv4w8WITJq+V?EqtAI^vE+n4TPAPd8wiu@+&PIgn?iaXqI!4yC>rrH6uS@S$rULE2)h>Q&^I+ACz-BlcY8VO?gRbW60!Rl~mSJS5g~2 zJtawPv`jrDm4aUVLiO3D&6Av*HYQB5#29Ggw2?b%!ZLSGSyR}_DR1(foC+pC(g~W3 z51Ra|vnsL7ozt+1N5ZUEGWkm_m4hC2R0(Y@sfsCgO%gQu<&K)V+?CWOpD8R!ZK7a5 zprbYgO}-?xDP;1m8dsU+uB0|aOk9%MWSM*@pXN{%tg$;H1m0-B8BQJ)>n9c`O)9vpYJ zS2i!eXKN{?{<4YocCz-U$(K#C%@vb>ZI3FZbzE#s?dH;!5fknWtBkEqQBo;JO&paj0(T~kEn_BrP)f+NVaHl5O622| zTYVm3oNm^-jBV}o;52>^#MY2Kn$_bl=06ls@$P0{_tt_3%z!43MSCgHw{_Tq#~3ep_$lUl$|;>|KepxyQjXuPqbjowdpu)0 z!FSg+2O17lR4|GF={v0bF;7XZ2x~{Npc%l567xeQ{}2akKYQj1;E>pfnDP>E%(D5- z&MbK-g9qVG%UPo=w3JQ8F$s^Pe4<%q>_ zQdOXBZ(O^yWs!Yl+EkOX=apHLFK5pyJ(XCHRn-kB^pP;TE0}ra)8E6XwG*b=!qmWK zSKYRG`YFi?Z_C4CA!1$BS2#CX`AU)#1vOgW?z*h%^ynuUFM9Y{<`0{EIm7HInSAM^9U~_HXdW~bV-yX2hVJ|R*47;r z5UwB(spZ?6Cv8|50-I#3COn^X!QV-ZTa98PzR%{-z~?OtfKTRQChnw>F!^}nDhEC14X&Lj6PLqn zXU60oOoApqS(A^+sS11kqh-bmw0=45BbV3Z86MF``%V&fRd-1Vzxv%g>B>PCtC+A1 zgq>q1Uk1X?s>#2OJ8KvAjdtP`^X3lhuE`S)y8<5JLHtIzYtwXB(8R^bu8_&UZX7g9 zvI|{7PLA({lf}Y}dW11d3@33Dcbp_l{`Fzdba-t|ew@n932w3bXUOvNRLZE(zwn)rI6$$Z7+%NX3{=^eVH-Hov= zVeR&rdcb4AojGrJ(8Q%yyFDFp{UGEJ$L@$8WV4|x<}*EvJ(j+wY!Hq!U>O-~te z#7~&=Jq6Ijr}DW5Gq!63ahhHQPkZpPvVc2RPP?-venS{E+0EN|sK?{Da=M<35R;O0 zJHwU-j5%BWyN6BODOSnk-;e`M_R88x?;f|4iYbiBCH7#pk!yn8RTGz+bi2n*{z@2! zo^y{V?lW;rf~7r}Eec>GmUyQL)8qnm{|zIIE50rn&2E7m)iAd{Pep!oPvqVaN9d*@-c74 zpx51-2cPT?n>dbw3~+xc%{XRss>Y}(c0)l`AhsYs_iOcowRUwlv{;mp}{F_1Ab}aT6_27YlKD>GA zV=3J71gRGEHBW0ujjBYSJCuy6>V%Rt`A#S~lYespG^M03E!wUcG;wTZR^hMzrVPt@ zdQ7I@t4gNcDiSBVBPKsWH1W$OUk3116_d{|Z>syQZEkgj%~e%XD2WBgwHQ`1xnAuv zal8XnAzb?J>P{2KunQc-u)8@AK7zYiUpuR{2XRlPr@%}Lt$WanGCykar6O0yOukg) z>bS|rOWXxGr(5o2w9ZQh_R~Bre|Y`o5a6T*b&4@-n!(4Y!iR9mCpN(a6F!1X5~w>9 z!PP|*KNbQ_dN{$*A#nAGiC;IUN~AAG_SKZVD>|o2c=z#e^Q7rxCVX=MG?}lOe3%VF zyep;Qebl(DqGMu*(J{w{8Sm85?F*W6FjItFpG3DWY~noy&~U#mV)C!|G2b%z67IgJ z$%mi75m&gLu0*)j5rlh7fX${j+_Y(?w^J1$=X_mcU)IDU!iHoPeQQSueDC;Q1Hf32XZ;Ih4PC=|I!0@mM zV_j7MJXhed7iP6llaCct8D8hf+_K-(1F}i7zv|H|3|t4bjUUro-+UrL{0owqA9+F?x?BP)4XdjGlkX_ zoNO>1NSk~o84AKJKgM=)CLeEKX0AtZWPA8P!Nlc)AZ?MlN@tD1aFNhvZbQ(pqGTW>4YtuWhFAbv}GB4EN$ zFB|GX6W>-HxDnQ6;3dK)jBhA}371Rxgk|EGdJ=?h^MOz9VdGoJyPgG3v9%E4K=PBU|YmWxd!r?9;3J>XzDG*jy=q- zx4$M1%$65Qr zCcY3i!*4-fWx+-meHI#b4+}r)<>QCRkzF2aQj41~RzGEU_1`XdN(FAi#ar4Gn^VQ_ zj^iy)*`@3wZ!Yh0d%MrmrLsBON9JAfa`x{lnEZ4SG=*8T!%)xOimQ9aNXZn&hFKLs z&6B6x`=|$9PSTVF85=eE$T@f$a!wC2Ue!5|n_|d01F@qE3R>)1pNTK2Fh5}O#qG77 zCSP*CHfZwGW1tb{wP95}j!VW#x4Uw_)-r_`;Ntpr%9(UXDQ4o1^SH@J&MD~m?+CFT zo_K<@59sGI#Pq!{GM_cgEDf@{r=K0Sc~joWxnT0|NV1)x&iTl3-1e4!zP4lvN7N?~ z>b#{E>ztvRuN^hjkaFobr98-bRh{yJ%ii24qU z5IH*^%$Rsj0W|4lP5z1?ejXlr@<7JHyooQ2v)-V|r)4hmx@Adrkn(cHvoADo0%qkX zIyhp&PMBqrkI!m_NpD3EdxSPv;ouIm^~VB<9jP!D$@o9JmVy+j}SQ z7OV`sLm^XEE;|l|O};!ma42H(R|G*L)ykRy_Foo~TFuzEKJ4wpzHqWT~ zGCh}aJ6V#W`B2#-JIJy)Md8^p^^)7|;gm;sR0|)@QjDj)9)0Jy3WMF0W~rjSx;T7y zbHM)flkUSMAg(|qsKa;?^|*_2H{I8=Acnp;Ts6gInA#6Dxy(qP9w9Xse+7jP zJ4dJ+T>Ps?Rq&*1oE_;j@w=!-q!&`#ELloUDoR zo-ndsVk;&LB4s5?pg}Ql^8AtsA~8jALZii+nZCv9kA^lxcI;So{3HMBI{taGV?WD( z?W^k?<%#GV&=bVXmQY#Xu4K;!Qn&Uv_wcSzSs%yLj3 zfr_MU;bm-%L2v11Q;*4ZkJ=J{r@(7M<1p zt}g50&tL381TNo$yK>}AK^vpZjy>q4Z zot6dd>XgH`P)F;*VIj-wo9E5##X6Q6BX$yn#YzZQXEna7Xfn8DmhJ8UC%wGpBQFXX zrbE+z1m61%~(zBLvylcbvAr6l&lznei*`)d+f z4&Q5L!H-G5*QA24s1~hBYdH+f64}|^2TpdJG~(E|4?fr+Cpmd~S~IQftW3`xKvrcd zVog!g@-Vfgq;X^|1HCA#YdpQ|QKoHWU3T{F^pJ6pzsUi8`BU3j+^+$d(o7s_AYxGSl3=G}}_IFh^e@$!dAki(rp_-qd1zC<}A9jrdkkA*|6 zx~F5>Q2mIk*VmG?b!Ds?5wKt)c&%XJlKQm?Ex)J7@@dnD3+~JQ9W9eTWL-dO@tO-K zQLkK^(`IC3taSp7bIcy}m+t9sGX<@O-+^lqzuafOK$*p1?1;vt=y`pt} zjjySi655G2zt;^lf5*`HvskTAIN|QyRM=+grc3HK6Ha_W^Y~5mqvMOOzSn0urD;j^ z-5HIqG=Fq-JSp3?cV{(=r_ma$MyK@d&TAg`nf6imOlss)QPb$s5b9HZm}0)HdAV5c z_B6h?!Sc26Dd<1f@G?yDbGNUB5m&EK$qX1y>MUpbCHuduJqU`-o~ z`a--F%e^g@_cbm9U_B+=lHXrq`F8MRJ%4?7?z;%Z`hMU;WxbPv_vKl9=$Pp+KGL`h zm7o=?Sve$FN@)3Oo1vXjGQiD`PvB=dC9kEF7T(`6iIdiNC}lJ+c`Qw89IvOcq$lIG zl+%3V+_c8&)d=*0adPtPMtN{7$?BWj=}Mkf-`|-#h4jnm>QYV9lA#h_2A{wyWgK2O zg$2l+r?6<+Pier=D7CZ>X4D#NE|aVWN0uyCq8@e~Jv@^@Z>j8=mHL{`m(7rPSv8l2 zn#Yq_Y7XswFa{ic1xJ^xcIBoXyqmXhe3ausFFI4OA*Jo&N^OE)B{RT=jKlk=Q+rNE z<&L(&&1BUijCILva58#8>=naR_J$J7TmJ6H%mMw6$R)kO)4Z%cHdHk(x!h3G_)GzH z^4||HuMG{&%gEc{eTHn3Q63?o+Feq-A`cADv8@T(7dcnHjXqd>%@Bi+fGWS?n!7o zcu@dn?n!E#oi}$pfZq?ScE}opCQbH1JQifNEOy`84_JA=C$IT~Y1B!*5U87O874(DnOWzQ?xLRl1R9gI$sX%M&;55^CgO0lS!Gq&( zos!MRdpcT2cJ}X~#8|c>S9*bwEBcx~m_?nsH_&*sZn6*AVHs)uU?bGqgtPh&!MD>7 z;a7cnj3u?~ay${k)-oAWo6?#WA2ww)zI%G^Va(ChBAd->nx2%wj~yZ!UDz}oxU#T- zniYU*&(t6mea5n>ta+ILHhCJCz-_8({HBx{!rrpT>$>LUR=3I5IJRk1k3dh}I&Erd zUT#&J+8Y0ZwDF)9y>;5;B$(c^J%S0S1T~7nK&xZ-w-5DbvA1cY`9t|oZ*wfX^K4FN zzM3;xAK{a0d2>qhaxHJpX#7wCb@;P+QsWp5KI|Rpa@Ps`nxF!@j7$@FHCbFz7@M+EeTD6HtnQg8D}2A-{zR zOCGOIn`kF`MA(whJpAp0AG@zZiqKDo{%*-=IT{_0S)*f1R`W7Cw&XQ_AGJqzr!`Ka z1NN2$FMWtFYFAtMRB8PL^dN+|t+bha0F<`;0G>!jun4^W4PTXQD!B!>I6rjKNq4wtc4ZY^nE zRv}x<8pj@c_DQ5&9+b9LH6Q8KG>#*=CFs$EkdHDtV!XAf<#6($OZJcCfs^}f&0j}; z65i4H``UA-VfF)UrhA%(+01FY!6lZo2f?s0A3trq>)blhI!6kja2bdC8+f;v(De0_ zOeZyt3vCEjmdP`J*-4y4sGQMyh-|76MktRmicpy%VGW=o^Na^R+NvuT9G>LS$KcqK zrAIIB$gYH_T-JIBQJ?ttwOQZE>{Qw$p0Wm9xvuqRNsZdYF)4&=VN266??Zh|p3};m za1XlN)pFO8Su)epI5vg5(2su9BsigDbq}9EJw3kof>}RQ-xj_f+!oVTj^GU~#6BiV zhHXjB%O>r%l*Z*M42~*Ut;$+%o0CkO?`xx-rIB7%+oQV-__5g$aP)TDbU15oD`+|R zn}5dkx1@QQwYQZu9<}RfJo48`F8pnxowNSdwI1DNz>gi}!L==%cNcAIX*n$6vS;uh zI7>M7tE2hZ1mj(e%RIZSr}3i=mJcu3Mcam&M|)kg7v*z1iCg)Rd~SEffy8G!`D4jT ze6}Ywj`(Drwc@iqt$B>j0`b!C?UR~E{A%FGj`o2gF5C0Qe-0PPv=&3UhY*Wi{RM|{ zEcYZ#+e=!nmSeNk&}>c9h?4glEv(6FYTeho>{V=UXgrEiQ{#A%+Jrrt%=;*#KTEQ` ztK|@t#HYX?Z2_lt`vYvMkc1xig(L@ldW?qr&9Ro>R@nASWV6br;3EdVF|qUNDr zBlA_JsYjN1sJBU7Ru4N!&f;ml06%st#`@uI(4rj;Er(3!KaI1JvN#S-X;^lS4q3mg z^`dq=8kYgL!^!NiI@{svatGP9+QDp}_){Dv`uvB-V>j(2S&Nh@ekXOt!ezMaOlTaP z&%)T)u^t&(FtHQ4_)}aw87+p3$A{RIT*EuFnwP%p%xV013UxAzYaC|H`OjnDKt|Wj zq86rc@H|GBOe{NpEs<=@(|X77@*jH9P~Tb8JWUYb$ByS&zY+Gasl|}rA;hBjZf9Hb zazEJVwt_40UtfOjKJ%PuRmoOY;^}eg2`I~C2-qbj~EQVh6k=U+|=CN3- zk=^A!>-RJ-V|-U%<9G$$CcAQp?HW2fzQPUsEdfWbcT-{YM~3z8gvN0_=U=w$?oMeQ z^OpyH*$J_m(Y!3%cTZ{@!@dcWHSyMtg(K2XvP4id=_{2wk_?pK7z%KY`3ukvz^CxqtQ#WzO4&5}@y@C;a zgq$X@i^6gqW2^9rHMW9dO%@+@VxaX_VC+EeY$ryVM=smMOK>VN&7<8R@shJjQu7Ex z>NA%8N?P;CX&(I8$rf<*tC9`ZwiW8Uh8Y?7b znZ?wV_^g$Kil_Nglc5y!HHhTc-co_~qu0c8#CE=-$2~i#M%blApWX3(k(q_0%Bz-AfKw z@sc?1O=!H{V|k|ovQXQba^xvaWS`oRE!UU6gaa?KrM@?(HKLaD8jo6@)_Bx%LF4zQ zQKy#6;TZm%FXJ2E$VgQS%L;sNUE^}0?Dc;G-q83xW#fPO>}RmS#mK77 zjTdXC{b!i&W#4^YR`YjK%HaOKoW^k=Y6!h(b9A4RLONyg6%1qgg*ue0BDc%hj$|n~ zKxO$WJ0bgOS{`pLny@!jZvrR3e9ghCRyaP`Ooe^m``t7nq-} zS~(uOa(_dUawps0)HsG>9!jesr`npAA+f)s@yJ;xW%uLg;$I*(d59x3!D~#bFStPa zXm0Eiwbi)M&&sl1}ACbb;a%&ETt zFVU)IH2)y(I^gLGACKf7N`Oau)x4Gi-vmD;XYqn_GnPLRmugAtT|LS6yf7}o5id*c z>byyG&%QJd4lP;q!(~=)2I^)@7jHk8`wX^GTEbBuyC$`AeDOzv4N;4i7+3pRPZki> zp~hw8RNdHD=l&a}L+SECTu@zv@L)3R;=z~@@&BVLZV97;I)zA613?ttUgghu)Z9WW8SC?83el!(7;e*rnHs*iiFw zChyS5)MoL`*L`Hoip8}_0v1f%7t=U?b1m`paOTgVjQ)njeQ7O+6>N$4HGSY@XHxSB zk57Ct!F*ox*!by!U-nRs`GV&ExXU>8&+;2T=l?ox0iWnFUDmWrU-wlVyv6c$jU(DM z*cNXWwe`fB&FpL!8UmFTyH$K>_|qFa`QMc zsqs&e5jb-sAKt`{OluzB2;{$sWf7^7SW(lF*^Gc4&DF}Sl7aG zr#a%A%p2oNKH%i&pxA2u2DO&Pca%)x4a9+7=q@_qs=iRRTZu zSef}D$7Q7D5SK3GrXH(>aFF3#pPPA?x=G8fkv_w8?^xB5*XO`Nx~6BLYX0rr*b{_w=`|Tkp}d7RDj{E{sKo^p8%OJe1rI z0}f{A`j$(<870eQxRe2Z)}?}O<%tC9GXf2or!H7@q~>W{@=~j69C<0g z-q@2F;M5(TyVKBeG<+cUF-b|SrTM5kZQxc);*XU%hO7xkmB z`KTWQjYnx3YW&GM>S+JiJX82SF4UL5hYM8(@v(#!Mlkx{!_(4;buxj@!bvTK&5i8$ z5i)7=SkC0WKYnAh@;+A7^0@qcl9v!2Ll^%6SD2^8a0PWC7JUPJtfu*LYwjOF%ah76 zU(+-_fRCn!V@=JU&ZAC&=!Bi>Y8va;Hq@h!R*v;GFZnp;#67}?S{|Vs!rs_v8YgJ> zcw%mV@c-Tq@Iy;}nXwc~EB9jScv|BU=;IlUH&6|1=g9U#>Y!zf?hrq~h`m{)3YwQK z$>UDCW<|}MJ_=q>(-Gd+I1-+LUUUZxPAOTlLwm(86MP`BMff@|Q% z8k0mUm^hI%g&!gdDJ?dGx9<>}I^AWljOHb`C&-M|{8I^*&jn`9@BI_5TNyYfrnNBo z;{6k1AR#*8q*P)Mygj!XK_8pYi>{dyp0@i`7Io@dEp%eZ58;HoYdGP9vy5Q_KKnxi zOvcrTrsk2y67egmz{#kaN8B*LM?cYe!b#+EpY{4Et#+|h-i02<$=r`%{=?9SI z7+(Ekz%RR{#XJRA@r)-mPB#eXjXlL~pTxqEwu(GjkY!&Mq9^lO zPcEyI1&t%8sUM?1^7iv&N%P2E9{i<}+moK=WefRaH8`Me4*VGBV`R7QWL*oRlT8>K zdpZpqxjESiI%yXFFaBw~RVSTnMcwJTme@j1<4-pjAB2{-!1CDj1eO;THH|w?`zO}bbE>TQXY#C$H&bwIA+>I`x(gdhLkt*+sc}j8 zsg}l(!#wPbJ>#)nH*B`2#c*3_LTu_TYK}TL(0t_1P~)<@aB5@<{|P%PbEIy$do?z# z|2M{~JgLtmG>;z^&k`>~a4w~JxL*Q4_Dlyj{F>u+eOCW!X+)I3cQ#Gk1HhkcVkVJ&puevL`I ziBHgjJHtQ@;>8Tl;^w)|92Sy^X9#c1gU2|6t+U!6n=^;Fv*Vw z)V|{T1T2^cUiw=OBrjw8wv z+6^Qa@1V3BXffW?@)z?EtoI%HF3FpfKO3K@tfhZ0n7BWN!ZtZzJc-hB;bIyeB%eZI z$$yGnyMGe6C7&#!PV!k4wtPCo&DVc6zVPB%{-9O&3u|*`1pY1 z`$asyAHWylKOetb&H+E*c=>5D>%ofE^^4MM7TcshAHQtr#E9!nlvXc4T{GRE<5zRO zYz9Av&mX$bB>xrV?{rM=U*Y>nQ>LO|8dO|jdPIJ3U}C>O^#wCYMa>kcSZnH3my;$nKfbtfL!J3)ho5A; zgwo394SB}Pj(maf8cJK9uZ%~j9V;L&dx5-paejQ^)QuMgm5JbGrY+<%?nLcB@NE6) zaPC|Tsdt4^pG=~(wMUF+QQ9uO$~d+w&W&HTbVZx%)KyErg%4)WjW5A{rgd)os`=Ny zY6j=V>1LEX57jB$qRvD05>rOCvVzCyV+C#Gl`QHQp}~77%ZbUaG47$X8hxe6IK|7B z=YjQ@@5omJ`O3s&Ek}U|%42Oup%ExdJl1pMZ(zKS(sroBI7QQTC?4WLD$cE-!b{0l z223Qi!gVw<5Q)cAD69rP6JvZ5rPaW7zt4CUr7fRkd>W<5Q~TE?m?)sM6>^N1QHlco zdF_`O_fXpMMaJtWZFw3W)BzubEnlStCJ`+VwgQLr@wTJTK%L}!C@lHqzhJzN(r%!` z_z0yf|7wUo5wveB446nd3X_bdP+IbzjWJHV)qw2xJdt(e(=0zN@)Upk@0yeJ{|hFb zD4?(#$T40w1L|S4U><>@yio$ z04KeH!*`4q!?pjQsmJ11O)Yyf6nm1|x6HhnWW0dVYIa$Z@#5SCn4pM7BTv>)*xKCt zCmX;kg6j0da@{E^I+VULZ zM%j@svV7H%zlQNzC?BmPKJPK%qqG{hiYJ2x#ld!{&hjlsUi#N|cD#rGu}aI%eUx;MWOCF3a_$4AEm9(WqgRz zZs0wPj~w|yh(8^31hsE9&?X!XJ)J^fHSq4QGM+|h%O@G1bmV`*cowBCpJ6^LhQQ8hY$au+-FEH+*wB_TBS5aE_EA289bw}X_#(k8QLc7Lz z6Q$L_m1h`lIr0t0JC6Jt0bZGSy6Y&k17hOo0ZO}p+ZZ3Bv>ob&_%ks_ekbDzM}EY3 zn&c_}oPsNU#6$+A)xZ~%jOS3=4qd`{-jSbVynxb@zr4nH5vACt_P;pIL>Z;6&}Q62 zDGK=K7fXzjK}-IM7Z|UjwB@UeHyn8{Sgo@PEX6k7qrHFQQI*wIElOXDP0> zewle+$8xBr#WUs05`PVP z)X2!RQ8!;%9A9`rA;6a0f^Vz{`{%{+#M1E+gDI3&uf{!-T7otHIQ4ekf+e?P9Nsti zCGjN}w3x>4i7dvB$SpZXtjB!b!3T^_JNSt4!f(Kf8jr_Vp1OhHT(l&<=$5i0lV%z3 zH{ex`kCU&|<(es>i@^u`^MUY;`<4{bzVShut;zUX$KFDIkxtWe2|OKulMJ@!lE7XM zFfoo#9smX(Oju!G;Iqom6hJSea9C|Gz}csZk-CSI@z~N;)OVYt7{G^B`1URtU%Y5l z(&2H?g_M68C{s{uWvY{M&ZI7eU*x7mC&&?^@kh#trlxF~d%CJ@Jfb~^=1#A|D{0V` znnRN~8E>Pog0U#Uc;CTOA$}_rw!Gj}+Bo;^)@+DhDXCmU02;ovfWlIUWl<;GGo_{I zj*pr}FDjr;bldnu_ffOyYDnKU&vcjKnz)VfVDT5Vn9n$Pm+_o~_Zcr}d@;drMc zrx>pVxVhtP@kNz}BU50Rwu5_&_Z*yTQCmX?_e1={F$Zrlo(l2kiEVM4iOGoemh#z-por2?VBvoO|6|Sv3ARpi0(LanQ8no1<`$n_Lv@+F6fHW zm2@?vZ+E(qt}&iQX>~E}GoE#DavEK{y^G>J{1?uT&#WIZP9^Y{KmPCI7o3B)k)?OU zKXlF;ruB~abr@9Dqb5HltH`<0*Z=AYBhqEniZWa#~hr&OX5ij z(%hJus3{nhc(jI2T4*=z@{7)?6P<2YX`pq&Q=Kp`^M2QUo@YSR_ji8pA1{4y&)$2j zwbxpE?X}lldk)PSW){VFO^dEGkANp!fVo*z@QMtoL9WJsR;g-pdEHMuoZXO;xe3&^lHa>QE z{P0m7+nXoOGG{IL)5D7%e84=$+W z6WRWkH;Tlxhz{L1#VU^tO04S?oa=jwHMtqnKL>01bC`U!jc;ywv zEY?j>d`d^LZlaQ?n9JUssQiCtTlnnCdF2OjK1JEn@dxHw(aY(2F2ZS@{e##xSurd1 z;^<^$U|`*tzHDDy)H-o~vXa~8FpK~8FWDk9Re8Uo(*em`=d4a@^2Veoy?QA9g*{hU z#UDE@9J7@ul`k9RZOT!E<6N0sj4#4=?XIzS~{Y@Da`5V4Ob zCXwM(+A1$o>u7HINfbGuqm9iJ#$DO6T$!ZoZEhJgif9IlqUA~#<#THH9$T(FW>VHt zdvCEJUx^a=E0yWWSAOmSMY>xF<;nRX$gRv#lDtdY%I#cPFP<+@tjdSPd4#fvioSf} z+k_S>CahA10AlGXWtq}h{J2WFTX{&Ntyb<;mQ&G7e6(7zE5C`NHA+8`utw__xwaO4atevJ4^IGLLK6G!3%8(=}fwyX{GO%su44SB>T}qy1 zm8Z$h7o~d}Hz+T)y=}@BIfD=Na&B186g!{tlecoS(pOOyi@!gkWMUp7w=Pu=8B}x3a3!EPkuHA}&ZFSuPE4m%T z_9(B>NY4WUG@nQ9xLC4Rd64k;DsJUtF?Syd)b;`KRk5@TWTJ$r9K}|#xf~pZiw^sh z!^Gi!<#8T+M%Z6~`GfBlpw^9|^aW)%AKDKItLS zIQ?33*2JPdPsAKlrot3m2bCH9k5LciWsN)c3#Xk=d{M72r4kq(v~3l?9)z>_&|6oj zl&MO}E@Q^AeXd2loN<%a1&-nD@wmWs-q(&OKXl-s4V#W;g{r)F!=^8@Hh0ho z)!6ySsKc&V`2i~Lv47L$xgjd={^FLCkbZE(;iGp(D&7xHDVw-5SU5g_n;YzPe5kB5 zDHFW)A1m7elqm0-&y=sZ5+ri}iA5G9*8LMo3G$ZxQ^^caioKV=QTFhT(%3Dl*4Em2 zmtyaMZxyccrYoZI4Cdp0ukEZ-#-YLbdf4Y9-rxq9iZaaWI;RX$4b;aib{@Fid*ml& zkfN;}_uIcXEvp`1XyRw?~lfqY-ldu85l{!kJWES27um6g2ABC1V1SRA>m3dHAc=n!np-OZeK4T@VxbR`{O5|d$fvw%QsP9WiGKl?7aPEz zRLaB~0en(uS;D0xR%)%o%C#}&(k@nY={T!S+|Bk`kCk~N+VErrp!c@rb;<-`2Vb4b z5>kENt|!q_eV1zvMVAR*APvLYf_nQc~sl)c11ECH<>AiCY6avxA0$pVeP9|h(ImU;Jd#EKioF%AA|>7IqaKdhnicWqEex z-2x(=ki+)X=axAwrDjIbpnVawTf&*AArZLa(66wd^QV1Hut#xs4?ZZQ%#pAP&1=f? zND=jW%RB|im_r{p>A_(%*sy~6z;4nv6EXK&u=JeuApRBXDTL>^%kmOIf%>c`)(6>@ zw?pZ3{fd^1yxor48pf36S?U;zV{Cq$&F6E!`HS;nLYb$i0evVf4b0SZxy-Y*9Wzlq zt{qb@_Ac`rN@0qur!anTZkZ?Fb~&aPpJkgnikXOrT{+%g4ua3F#l4(FJl{4o=KRqz zkM$Vimrw#mAs7 zQld}V6t14U4<>9|Pd*abs_Drmb?!z)0PL)HGian5`(!UZygyCVo9Wbd{ZzdvHQX?^ zOt^dT9&TMJ19YXF)s=#}R7x97DRGG`nEXP%EiI-&>*E*ECzV6>6zFDRnP<~}C=_+D z69_{yUBqX*^2RV?g_P)WKu=$yeNAR#raS^14feAhmUm2@mli{Ux)S6 zcUvQ@B}DQQudT>98y0XKdmxS}>|%d8wX6Z9&p?a z%h$FNpRK15?a~ip5ldf7KGqt+hhj1R*KFQ^OSflcq~x-lT)Z9J)e~YgZhv`I=XRv- z!<}*cSX*~pT8yhtlWoNrW=`_3@s?ZGuv=v4ro0v+evROdV>z7vh6US|zebT9^{$q# z`mfS?HQZSycJ||8SPsR}nyL-0NsH68sE`(=#c6f99Q@vy+M+aPlj{5TBRa3Wu~bEu z{yaCJtkC*37F~ZH)~2k`uDse&l=kOaU^ll9;0TaJ?f`yLndgle$a82%d@7QUK=EcI zkEC!Vl1HP~BZ_b0ADk8kqPQDJjhJY@Q#tPaAetvCN`dGQ!+lDDx5Hrmph@ZMbq(XI zRh;-n@uA9B-q=z6T}64>+cX+Wv)eqfj|EFOt!5CY*Ai4-;!`Uw{sQlXa@y>+P+x*-Ni=X1IZmiVPCh_qyJ`QWaKL%f^Q`6g9a zAR?#nIpOUHB-MAdic0y54T?%j&J)>o<@ts!X*^uKJ&jK!QKw@li%6J`Y5N#whOVM< zIv=P!L&pbUnZf7a#Jzb2->q~k+YVb&V&L71qszR>GvQMB&ePrlS$q;#UiJQ(%}4Nn z1vHNE%z>&W%;DWhiF0@_RK5JrH= zdm$gkH^Q#mvHZfGCoUDPIo(#^SUPS!2$j!h?DptY^GeydJ#O93-KaEFBk8=$p7X>B+?Y_Q)qe$qRMNr ze8@CT(z)=D0#=G6TTP;ksh1R1eW`%eSrt~aV)p9qFP&yhR*%n@_$}M_$1Ya>2hL7^ zoMu%kx-qlWS6+K5oSnQhkJVbu2wLW`ye35n!jZ2&cQ)hJQbY%JOqsRaG@wm|{YA995Lh=Zd!5k_uQ1uvQ-A11S!~ zf}0k17vmDm&df6Y1FEZCDQ(qDbkwV^NQpWZbyIN?bAii3NVs&9!aPqOXKRYXSzf9y zI*wGjD~T1wU}Kw^Vji6zb*}63G1x3uF>}G)h^EK3J>qI_x5c&h`8v3d*=)7~7HHdX zwNb=W@~A|}c^>+q=*|+3$OIfx#5ctQ-Be2#@FNDGAH~xF#{kmxaUb;OtGblrs}YXB zsXfHOO5SOfs~5@kIUSN$A1kl5&SGJ%M`hdFvr^b-S8ja<^|@5L&5C}Thowd*cZ(F2M+0f%)^WpU`BCBk4y3S zF#9#oRjtdKVcT|^6+!(O33W^@2t~jV&Wbk86OSI^qi)G}fM~%O%+nn4$|2qlM)t)a zo-ngBwU2c$)rvFSV-K(X-dYE<=*3L&HpX%uW<0)t6~&h_#fk}-HQO}6&R7~TN3>j5 zn_i-MFTue21V*AgP^7)Xd%6eiBHC6TQ&#w3FY-_jxt`kcv;XMo?)ScPIT=J^u+5$P zcW08vw|(WChn?0-OiA_qG0YHt#W`j!na7G+*q0QLPUi)I<#m>7#x|X1F6R%czbAnm zKQNBCTWJy<5A(?66)fnF%Pf#ozG4M4Uve>a4r)9HHJ*bS&q0mnp~CY};d!W;rl<9k zh}ix-d}1ekLj?QA+!QS;|B~1&T3;^n=tcX>YpLFJs=S^o3ZVWUT^#YzVT1|gqU{kJ zIM0ZLBYbptd2LAnJ1OOhkc+@UW=E5#%P2M-;Wp%3KRJT13EumNBys!8d}N!K9T=fh zBpuYw#oyCS%u_b*aDqls2a9n)wDqjqc+yBZZp>Y2dn^3vf`B%x;XMg4P&In6S-lIb=D%{1 zwlO5}* z<4zjJ==ezM_?ZbBb<%-5c~ThV&R7pdc%i^@?IA8AM!^7 z_6J&5ydZM_2TOK>DES}A`MG%Oe-Jc0;*I=>LY1{5y9TzFE{bX>q7Z=}gT^!w^D!n9 z1AmN2@t83G4T!}e?QbAFN|gT%;vnPnH-wL`ihh5`M0XPl|IWig9wDh++yB{>j(x5Y zbB1e8+as8JBt!p>Q1_IW{|Qj1i4C9N{1PgvKfxe7wtUKyL$?xUTp|t(i7b5kGN$0r z@I9qPQ+;3O3&*Em>JG8yQ>>9g;)72?WWD(HQ}7K=|ADzZB+~wY#qhE?`40%SRy0xL z0ulTf2ACkSKf@{NWszOW`?xE*lJYGMGb`@H0x5$?TU~KVMUeGaMNsP1Q!*c9@vtD; z?k$cW7MBvlE+$q4Uz}TEM!$47WS`WZ;9!A{T%0wdDffjcrZJipRm8^h zmw``g{pAXC3{nS4-rs5w!BO`8b3UlUB7#rIL7F4CLJa*U{6U3C)rx!n$&u<5mH&hw z$3)FPkr%EIQ@@ZP_i4qtFEAYy;=3;}IThm8FZo%5dGh6m%vhj@dz1Qbq=o5E;jj6Bj zcKHTFg8a}r{sfBG>UbLTi|Onx`kdzD`L|VK{%Jn8XN5g~()6wk(JYX31AW+N8?iWi zK6yyk^x|D@#h0gf-;Ndb)T?j2N`hNwSBP7_g#jaQ|CSE{^;zFS+6uAkTV74U?RTir zN%VWfsklz6I)k%Fh264Ok&M>AULks&g<({P#Iw9d2znqEi9`FUWp89Ki9=8iqMKLP zMcsG28%KTTSw5&6zzKA3ris9Snn0l6XkB_!`_!x63B)ROh5f(>w$lc&evP^Kfv>=r zQgt^V^xY3&x{tqMko7_%~@TE4~}>y@d_}x!PgCmEW_g zo&9z{4eMg216q0<<2CSuAn0qrQm+u!b1?S`;XQ|NXqfo&98$p*;?g<(8cj&mc|I8v zB6F3kCdJPFT`YS4$SXphp#dz%l^XY%OHT7@g}L0gXJ3iI>D2xGk5DXb7k}b^=7ASQ zLT9y~sQQV2%iCTM+y8|%hK=iA*lEs-pZ~=dwi`vn>`HfB3;qmO)uur_|1<0miIGMa z=O~fg2y(dAqvC#1+K4Uhytw58PY78+nDlE^xW|&SHP3oH07uw>jlyvO!TTuTyZ{Qg z#lFA~cKn*uK_?W_qy{hL1w2lUCmK@>~=-|z~d!u$(ri^TX}_y7!X-!I(W;SR#W zihQXd>b!X47r43e;`U$Rfzbae%n#R=zakGXQ$+s8@8aiv6NSIQ&%7vVev<Ca^M%J}2FkkD4Xby%`zXWtGM8CT)P;2p0b{c~O% zzRDeNl3jf~IbcPF+tlT zO5r~=B+T*G#Y8C8cgf}c{u1$RvdrTpX#ZSm|7||CxlM0Mx$LZN*fVKruQ*95)z?%Q zf0~yNgdsUtxJa1VTs0LMnj#obz5kg~wI~1T!ZSzJWy*3fQc-V5o?(fiz7LzQaP?9C z1@4x)`U9+?L{(R4nY?oa0Z9M-?g0_7`ftejPeczUH4M5*GpP|B$7sx6b)W}n2a{^W z609<*qxpp^qS2&w=NHb1zyNgycHX%G>L6sZ3IkN+Ad1D0ZPX_^%lRQ1mYnTPcJ?!( z#J1`zN^Z4P@1sOWpcff0$%G4 zyhRF0 z+tk)g)}S#614tt2z0Q!8nj+L1eL zlx@kI(DuRdW>}UHGnP@x!y@~0w^6?oMAldDp}Jh&vW_$`Xl~VMZeMX~$n*JexH3B> z+H_Mp!ybdXsmb&_rJH&f9y_SJI%wu0f~H?f&Q1>&hdh7RuT*UM{5X&}D6+G+P7#c2 zX)otW$;Df*Qhnv-o?RnHDhwxw^7`i#o2JsY?i5AcVZY%bqX#k{-*s1Gk@S+E2lY_< z!3yztS%`d=K~xYm{BGG@T4Y&O3U~JPouaM>R?(?5B0E?e)Nv7kXoOGf5Jkb5hK-^o zSWO-Eu|!6o0|lnZ&pA6w?d&Vb8V>436a=9!R__Z&AI1(*N4LQ(FnhZ|=ATPL)Z1kJ zt=}jK-4;>dOP1X8;+qgP@wW3GX?RFOP!It%Aj8*F?E_CXwWr#zcezYZuy^E1QJY?t zNltPX{Q6Tp)y#H58pPXJr9H6{uxs>!ZA|mV^iuCux)l&-bT>`%!IazB*$M2@z16!y zFL*lFku%1Z@NgT=Z&>h_Q-*PA1pG-eY{wRUz~nvS(^X{AUAQ~N3x#NA zKssd_m1E3I8M}(Tv}*HUu?@Z0&Z@((NJoj**$%!r|YhdFS?p!rNU~nwZ00TD@YhSRJ9x#}mE!2z5|kWg>@if}xOps=c{( zUq3KfDT?|5bFetr4}NQ~_^6+1?K^k_#xiYfd!`riB&NzmXL=*ScGn^MnP8~av^Dxn zPZ85!9ojCqIC}5~J9{-n*rxOF_T%Jf;U!P*VDVIcN$nsCK6tYz>MzImS+;s_9iVnm zFjmAs>@h{Py$R+|x+td}1W+oRy9CWwNm;)Z+W!ZMuGBl!ooWUN-hwW2dSc6m3-*H z4xbj=W2CpPicx=tV=W(yJ)z^4A=pkTe-pt&px|QR8lv8Vx&Lm6I+tu}sQRRG!TZrr zbpwa*pF3QA11_WY2=z5`X(QC=o^c-cvB_Om?8Pa=1M|h=K)w#4^9u-YN2)_R?xGpi zobNuoMH>m%xImPTREIz@pN#~aM6qcU98se9Y?L~%O(NFf{&oVle*HGpEi{Rk(duNy zCYFs>&035g$zc@uhidDwIC!aj$3*35wMPKL(S5tb2cy+qA!`Xr_gTU8azR^o`|jUz zyV`4-G-a)qKi{G^j<8%SgEKOnrm^&yurN*yvQT*-9ztz8URn!0MJ%};j;L510QHXj zC8pd?_S_*pxgDE8oG@9`#Srm9i#oJt()OrlDR|gDfgq97>7#MC8}Iil>b8JdJ3EG0 zJx-k^K8jP@h?nEko(MZ@;?&_iOB)F1+;QfSxOL>IOB?O%D0bp_H6kDzA5+Bmcy(Z? zR6Ie#>D4zw?+OA4;sHP-Ha-xK@MX^#aWY=rqKp%FTh%gz2W=D7#Ex+u>-KTDC`v4} z&Q20D5>z~m65A8hNjL_4p8y8|xG^yMU1vn(81>*7$q~H}er!8Z;p29d)0pwQch$yM zD~g>}$z2cY?Vuak2+G&S*ReL2_9w$hS1lJ^$I8ue{8)q<*fGY!PQl$+jP|Pdb*%c! zg1tmed)an%Bz=Bt4NNX)S7p2nSE1|`Ips(#L)_0#Q9pT5N)g*x=^a#e{i)Y-q%$@o z%&{Eo_%FdoUF4AmjSZD!(H-sBI;jX%iR@lNkynbY_Kyx6w7vor!&DB^7O`b-0v+-Qt?{xb1`x}tYfQp>3H=P9urC^Gm7u^>e*m^^#>LP@n6IWm6(gocUv`UTVln78MiK`LP>YU{ofp@@+OSu+VfY@j1a5 zSc#L=Im5=kwLXG(Td(r26#c|aPA<3l#=lDrWoz5Tg69XQ_m z{v;L8+HiPDf$}k_DOi=qwHm_96ikc~=lx_dX5O7#MaNXR*gZ74Ps`bX6FZ1=OdFcy zf~b^o2cQ zbt0mT@6yy|(OXXwUEBp47Vq=u|Ovidr&XibqC)=#DM|puW_j`c1BdF0Kf=U~F^nF-k8**#@a0f+Kj%iEsQ=luuW)pl9E7^-CNT zzMP>B43Bd##db~uv@uwP$#073sP-8k)(0 zW^z*wr278nPQs^peQv6llcn}XM#GtrRLxPjssk8b)6$N5G4!@scW%?@;@>q);2)a1_Ztd?tKLL7V3+`E3!W6-4R%BO!?m zE;~kRUp0@~w|zxpinDj%Y&AhN-JuSLB!gzFy#}OyaOpT}BpB<7U5#`J-=ru(kZObb z`>dtfByES=ovrp6kb07y4nitU7tF=>)DIw?sW|#f@=!QiihFiU zV}Vov5e2coK|oW|D!v3|n}i&)th8EWRc*Fayxz|8UnT~u3d@sa-`&i5ml7;@6ZK74 zYyLCT9zXCZiY#hi*q2cn!0;v{$Mg^lc>^^7@uN zc*7uxf6k1#j2o4%j z@Px{Bw|dt!C>664f0gyt6uTlxjzjytWO#-2J+6Gzr8ium@##C)6-wSZ4sMBy^!@5;Z)5pU@m-4tq=_eT)QZu&vD)y?0Yb>%ahQ8L)_Z6bK6;AUbhmvJ z>Q(giLt;s;8s^?b-Ex~JQ;|mr*H_dAtx^nIs^zSgEvGg(Bbg8*GA=jWT6h#{CvG!y zO=IICe7>1crm>Za)BY9NE?`qqf!e{4jwGX@k&L|aJk~NUn<1%aKVJ`yQH^W(%Z~vyR5fe*4sLu?TX%Z1#RNidys}m69ey26UU@8 z8JU#giOHn2%LS3xvhdvyS{cQt7o(2+unp2FR=^a;E8|h8+z9zEvF9F$kS2WhsFT{I zcc9jyMQLK{z3L43g@hb-kc@~tEQw#VCq0mq*;Fr$3{eVa1XJ{OdJvh2r8Ho(W!2s) zOKw`-rn6}^)P}3&gM@4KrJjVj)Ki=F#O}!A0qGs+Gukd|W$H;9zBnbVk;+5vl(b*z zLuI?PA7#fPY!9dxHKfT{=1{w|f5F9fBjWUn)f9vXW|aKwL0x9RF1!pJ)201qVpFeL zLZ~nG>g}DWY)D9}tzV=}Pxbve4aS>5ZL|e8B;rX6+C}L?IAc!;dVFba9dlz84Sky;dQuiB=}+1x2-<+2^&v+mkNQi} zMeK5QQs~RF+r#2zWCNAyxlos#Io6BK%hjP#a{D8!Z3S$poz1(WB}MnwJ>~lsJG&3* z_T}ocQRxeH64H4#M9uJAYG9T)n-&k_~{6rp6%k@#SMM1-t=%Ow9q) zb5=mR>B7B2b=swLnln)4iy8D^=vTr2R;(<$O+D(o#78 zb-GA&sUz+j>~ZdG`wkAbls!=rPWXIHdu9~Twz9t8j6%yhk2-0~A(V>~W|YJQrY|I> zo8HCy)u=WrX+G3=E9~s9{bIgHUDj zOf69J@cgE_03P~NdN2_z8Vg`+kBG=s@afX!gBcv)SPi*E>n?^ZVlGBNcek~2gzYUE zn~R*#Dz#TP>F1<4giT*#V{?$)qhLH96DBjLy{w5;V;3DExF@KFZ zHN4u+vZaM;8;HWHHc z*bMP|p_+lKd;5A!-A3VAudW+4iu!1klq|}GE#29_MZGiX-KdT=nJ41~BQ1 zefMn_flsT^$_z2$Y1K)I`KQ%;c;CFGb8B*KFm0VycKygivwR?Y?~Q-abTvH@r)YLE;EuG-^IvG z;eG}dgvXB0sJ#YDwP2;6)YoqtEf`8^M^ccpCCRllZ3h=ykXXwUv$kLt%oMi@byjGm zWcl6PHpHW818O4RN>C!V39@z)e^MAC*v?f@1s z5tCkm40NVgSE9bw6XL)|FGgp^>ZL_5ZS**=_olj;CgIwuP9B{(nds54YdKz+uE?~< z|DKs)<@-vlL#9fg(SXz|l>tObOL5rn zcO;&L9}5+pXAuzKHPf>yy)BB_hPk_6c($p@A+^@st83}j0RCt^p=u)}BAK~OeHaFv zv0crLth4$uDa)o=Y0kcSe3mZJlCuv-zRUY*PO7m8*YFE$i3>CwvD{gLf$sHE-Z< z`Or>vLU>kr%ou5pUtU6zhi0Z>a#o4;an^xMp&>9!^e9yqlK(1Ihjh#;rv#mQ{kL5& z{W(j#R*Ezz?x;)ENuBQ}+VndHS-iM$W!WNQmpZ7o-0sGhRekHvs-h8!!`ozf+Gh!| z3-~tgC%e>6ynVlmgbnUWg(n3U5vJ$W+j;_i6*G;=VWzkZXKcW!q!kl)-sbA{M!SX|jyT&B_=0JeP}ZitmEv8N0NueZJRWmuiK!&|an zeX3h$8j)TgS_+g)@H9`@*+@L-dI15zelhX|^{BY~g4%~?72(SzT}5n#+NMob(G+AP zMfJBz$ZZ&SeRNjQLy^pbA-mQu&JuGf)ImeCitJ4L!Xrgj>l3qz=$eJTp6|?UTem!A z^pfQ%Lk^H4x1vu}#`3P>WQE#yW>(Si6idw3NJ(G;F-OSG#ck`Hi$*VTE*f&+p@Gap zNVqVGiL>FsGQp#c0p-@x8XkQj@c^7is3V`V=(U zS+5U8(2EFY?-zM5sOrvf@2x1YKNn(D`cXV4ZFSN2H4yU$;pVw#TeiE^jYOl;)4vec)Xb;qwXPernDWl?YH#Ywq| znt%U9qO}l7R8*=1dI8>`0};y!pX&I$T{Kpz(cQC3No7rovP$$4$GXOjBKD9P5f#^h z{9qzadp`{!Ed~~1XisEJ=OH~nn`ksdWtAu7P>wmP#FcB$5VoJN438gDr{L9O&|lO^ z-M+V;#`h=o4RVs$77y~^yUU8ilE1)rY!sD$!SN+YT>gtXv7_I7OBwE_ zSc4L;TB{DL6FX-WVTMZWtn(v8YyDkW;?^UGOS8nlBWkK2U&$bR_Yv%f<)ZWmeC++A zhKl+vFRRhF{n}Yem_R?o(C)HEk?^vb+*zJ_NoBJ6+p?3Q=w(cMfjIiI+9#as`qmxP zwSF$v!J@Wxbd+%}##&fBn>m>M}nMtXlH$ikdh$>ty|otZHIB^~z6jna7!V zpv8gb#AC9mQ?H!6LR5*TCKpWj6|8v3+3muy-hO;K57fnW6 zeBbim_;KZt@j2yo>#;L7tMAP0xNr9d$DP<8DH4uB`%z;4F?DtSx<5`U+4!!zgZ?~J z{OVCF@~ z)z|tXrHi_+YAq2YM6XBn3A^3C!glaBk`@I$P88-cNT7sA^nRK5Mr+`>-!qtSKOX8XFCv6 z^AN#6otKwKt^S@qUyMGBoNd=(!u*cfw_{cfBC1l#3Ru5}!+J-J9UKgf?;zrYE!Xto zv$$wf=GVW0L%WA|HT^x`l^+g?1MjH40vf?Xp7`J$b$Xwy8oVx$HdYXoRYM^Zt{Nf} za==*b*+7x-F5GFXa{)6)2B^NG{bw!sVr*gRm4D(JP4B7`CrfdvE+(>AI~#JGxFA!& zbB9{`Ouv>@6*OE1`gh4X{y~2geU|lA2h5h7ibxT8QjKtTus9T?raMaqMe9JnjxZ5f z+7+}vWOO!=JOafc1{uSP>Lf|awHQ(^b8JTPR@i{WEMUkN5EBl*KyBxtQowld(EYuW zYKJzGp*->BNu1tCTeqKOqTea38jDCfr9K#H(UpU{1P>>jAKu0Oge*tirRcM`ojs+F z2&F$XrA=f3%kxiU98F}zpad=qa!WMdR`eUVYqxu z!Wza^+GM?NrCk)(s+-2hlPgF#B5)JpuLTLoPXn)XO4M~i!D7c>l2n&RtjW0;dDbq!vUH2)_e@QT(135=Whq(S-+xf+6$CVO4cJCr z6y|ekJX+_RQ-3ANGJe8Ulu~)veE$oIl6?662exwW<$vS&r<85#{qR`tzkgLfRFphX z{U0@VOkUGGR(bv^BAt|a<+=6LM!yKExMfvk6WuJ=uLS&+=k6Dd z-=Y3E@%`_(GWyDEYa;jfrPpy${keluBr@8V{;urb6tg&1WVSU$;!k^;O`U=QO7RNc z)ZM$Kt?8l8nEb|IQxC-u*t*s17%ESMC#Ugro0%s25fKfZqIo*8E_G*8E_RC>n?%Dz)mLsdLn|M( zY2`AViqoUjopr(-Y3iZTa+hk21v+qnRu@|$O|g8fL+dQmJO8W?yn$)$8;Z2@Nu7ft zy?nY(Yu~K*Kcmr6wrFE+Db>2SG;WCo`+4$T9ks-)^_5g><<>@7D%&*FZ92v6L86*) znO5k?&*?}zJsR>(y?tk+$QT4@vsPqiy}N--+TEjLJ+IZpJA+KYysT2x5lWo~Q|{2p z{Y6^&LXB4bB~LG_MQIGcgS0|#J)%)W_FGP8HB4qOfJ(KZQY&;yZ`!<$!KU0W+t7s% z-oIezyhZm7%^OO8Yj^O&OCG#u=${_E|KXuC(xy%vx@1uf{XVc@>Cimqf+dR{c*Hp* zH^z()3(Wl&MYZ>Sk!HH9UD$j!pT*)gm(9a}!%z-G-NHu6PouoqStehb@JL*oOqf0a zD-%DRf;!>5f+$baP{BHNsi+msJ559Qfgn*%7`!pVgHNP9v|k^KA5Yt(jeF?PphXlYUN92 zt?Z{WvaU{4-Ua^k?*7?Yw=w=ygPcQapIW4q;d+^=%WKsAczGI}!N$5Kt!}VUpyN*| z)Y{z!KmDCrgIVtgb7*xSY&K;aI( zlysO?YrhfUKn?JKKH!>qt^NcRfM4JdfeurcQc^svtEp3$p7{H4sD^0l1UG6>C3@MV zPn~c&Ot<6Zc_krbiyDWiM~IWPNluwQVbTmqGN^r~Mmn@;%RB&;3o{ibg^h}O;h1OY z!}|mZ4^<;YDHV47NgxypMI9A|TXOI(@N%%WP6|s75JJr&8)eTh#?-VFIRfz?)IqWa zh2U=-13bjS)bTSjB-^sPNaH0eLsV1uLT1WHNlw-JfgPiFdqg93moU?eSxGv2r=V^N z_3lbx&PDf0#-}4f)_yt#bv4GW6B*Rq!~&-KsdozM^1Oy^4iX;fj%01dPsqr$;{`Rb z)>T)N8OlUAlzB22n$Kg(AZ-8%)kSB)T(o6AXp}Q0x<&78ItS)z5lh{*tj+Wp_LPYl z>7d)31ly^LxluUgo4WT54`gc66zLKq@!KS+PF=#GJVJ-^vZqd$jl^N+Li&hqD37`q zGDY&PVFh*8jHF9Alt1*z!Ir&ibg6*M9@7bszmHPK&@qbW`g7y|8xq9JfNdODfd7r z5rKGhY;;qRyOhotidvsx%sO2kYHX3h@9| z?$ubKqE=+wi>YoB3-5(Z_X`q*Xbp*Fru3;fIQD zx=UD_*~wF9PSNMw?9jWR_JyW_P`k;VG{a7fBz@RYS$63M=@){B{#b}q_GEa*0uHef zslZC4qHxP1{EL-H1y(Q>Siy^cFaU^D#R{eZcvJw7ioz|6P4xFEA{V1lBkWW(iiL}T zHxNQoHCB|P2*_Z3=oE2av8h+vJZ4Iskd`K1T5Jk&7cq5cvSI3-g4*koHc%6zi@8P@ zBT_2|Rsw$34dBgM|8?+nfKR&tyiJ35w?>Ez0z&o;5F9riAkqf-DK~)k+yp+4smV#k z%J1ZEmbh9+DAh`1r->|O>a1pjW_ZITw1%&NR z*5Tc>R{TcixG_SsnVF{CXaLVm;4@f2vOQ_KCUP_Vs8S8ynA&I$6Uqao?ruk`_Hqq> zFg3U2Ppfw^f+s(n8o*;kT?g-x_}9UMFUgz#g?%DF7smG$cR;}gaXfyqe))+iYH|Xdp4c;I6)N1u`r&b#MMl9#& zsz!JoYz`3(Fh3cGPDbBR466%^)&KVwO?rQ>E`$O1EbrqT=PBX(p==GSXN0cFuL8Vcrrq}({ zN<{3R0B(TY1kDd#EAj|j2OCnaQ`M;(bpw28u&4xhoIzDDhelqDW-J?{-H)EVHx-Qej{ z)6$53OB->>dY9`4v}^6g^7ISPYL4`NcNc?`>li7$$pE@$42g`B+D+-`nlS{5bue}K zSR=T0H!mB5pr2!1<;DPpL`G>49ESaNxc@kEJw1c2QC>rz_E%#7KS2)>w2}Duxj8{| zpzQBrI2wboYX-OxeJtZd{e0Ak1~6~e2n~-FrH{x+md5R3uGg9kzJ}XHO^a^r6wtgl zhdZ}C+Ke0?+zPo|#G*T{HBB4}#FXt8XhAM%0VE7Tpm91@#$f z8yPH0sk=#QjU9a%sf!;z=q7MgI-brpAJru4mm@4G(b|o$W3*1!P{!yY zBs7L!e~uWQt>GDqFd|r|qmN@ONGJk0hpt5)gixt=-R5t8wE0>w$FX`~%@OVFf}-ryR%c(F~vN z2Wvv!W1JS&Uc-+=!!wlUpF~}Li(VRZEXe(@Fm;a~Y}WAl)@x;JJj1iL4oECcVRp5^ zH*EC3#y=_YTH+fk=fA~|3l`Nb*nW-1wjoyBLdK1ASWETzx3v4i)HVo?btE zt67SxW_-AI=#lVlzqix@4deGS)Chzd4Pd~x8Xz7Au?bldrVyJg8Hy{F^)7y|tU0?| z{5~>1L)7J)dQ5X_a0Va7{2Bbj7czCm*yg;M!N1`=4EyoJKOs_s_xESxK|RFRwP>(wsKH=+bltVX z^l73xeuC&9gcZ7aTC?LH29rE9{d!Mpr1afJ4C{ARHjS_W5aH132_;$?QKZMn^;*5P zH$c*n`^Rgsj12E$#1OiGbGjIkT5LK&-ENHf7+q3hehdxyHDPE#FAd4ZX zt;bO8D1CyA-N8R>tj@09Z@38q&S2MV5HjrF=#9>+`4Wk zCNWsVu5NY^2A{1B$>7K6PmI+0)#V%&tk-qE!u5%3J&|!WI-JgyF;9z)m2Ef%BSWe8X&Y^V=&{c1!+K_mFJ{7Ic zBT4n5q$PTZM&>$ni{4H}i!;GEn`mr_UafUshn}ssQ_&K=MA#oUg^kj?4Lib96bWXi z#HbtkAJ@p*X3r97kDGdptkgkkwQ`(6N}oETZlEUHfGScSH}ziB3NtzI+Ch!FAG3(H z88>V4)D#&NGzTe$W{p#(;f4Hobs}#aLQ0E9{$^m~gF!y+dh*G-Ack)Ib-jIjq(;{m zZhVGlTxaS&+t8U|00y2P4%a+svnHl#>8xgP422nZ*U`uSTA|R?;|^WVHxp+r8E z6*fU%|AqpLdTRkDmI%wA;SW68n1*XLJn2Ba-SGUzO6{kc(Zo7Y^k;ZNoi$@eGDbB- zFu*5SL=C|2(7}xbYm_%bZ%wXs-A~>rY)@bxx(RvX41FC}^^6bFJRP*qY}+w99V5eU zD8(4Qb*A4QiyNh>=^5f5PnbH#Ihi_j;zUv_ewv9I2l$&3DH7%lkfBPV`Hz&>jdhZ# z3A1bjgr8>e;kB~f`hf=XP%{?5&GHL+45LUez|A)63>dmiL9{sBrggU*&G8<8(*iD#_)a3T795RD{neXp>RC;ze{5b zV=UtT>oBR1=D!)nqH#O1mD2iV=+Zd;-=#@~G*A5((ip=8YvlaW{FlR|L7M-=FcWmL z|L0*KO%akM>47X@Tw2nURN}V9O7lnkX4&2)T^FZcq+U1UyP&2Xn#ZIj`ss8%ShlDy z!efOZ5mam%h-Dv;oRpbt*P#7J4708?W4Wa3Q{-Q5wHkHvLVXmYzeub1lLV1-Z@h88 z(caUDK8+CAFHN1ODTZ6B)bRT>QHdW1{R63t@tj)S|NiWM8PD(%hFr$Ym%)a?m%+yH zDNYuUG;XSv_iiy8MvBFF5oaJw4H6|!Bb99vRa7`cEfpTo^fYu{D$JWqJqF}yJWnms zN<*i95^%L+Q>KW}Vp9muV8Xe{6n00320N%u$2Dl^?FJ1$O`W!(RzF^qhHs3OVHS-b zPtSHXqreLyD)4NFiYAe_*))Jp3l=4)wzV;yjQbq%+-AI2ao`g7j*JOJt)-F1m&ke- zzn_fM>XUSP2-oM$cxdTAqSk6~24B-WEC3hzG#-AMx0`8!8l2l8FfCSVFzS8+bu3^; zMpClIVKae@Rty;M)A1E?2`{sz&G3c-{Q?Ec@!Vae>jV2GsMi?r6U@NMGM*{5kifrx z=`&}3>k9O*NKGMKTDzy#`#GLuscFf{LZ|gsq64b!lz}mKDqbrY2`5r4h9jGdm#o|DAjm zlF?gD-J^Tz!WhhJG2!*^p|T2v`B~f`IW)2cIBTcXue%)3hxfzDw{*>9{q54go7)ZP zvrgh2qCZ>HJn3%3VvPl8tJE24)XQqUtkue~MqTeW2AGAnfC&)8}| z>N2ZIYd7S`wu?rv6K7bF&c-Z<24>teX4Pr+>(EPtZ9CRrxz_DZ;@P#jpPL}PZoI_M zhx2oRLsi5LZn%v@*mYXf*)+7|f1zOzyu-%S$RT(YD1Vx#XI3>e!2de*vQ{fCHmx)k zdA6=5Bc#aA*7}XD+&>O(mu5yVF>{CMw$?iIn^v`kdovy0fxmvW15-FVP=hmgyQ%VO zG&qBY*_gr|m_mIH{x@B<_U*GVh0noJ=v>a$C7rF4^N&)`6ueQ=f0{LVM=3RR>N2fJ zD~+wyz?*}}7UWZ;9X6lr=HR|(rk`Fjx!JnnZ%WQ1f_B2-sKD_>kTCXr=oWE&jCKq3MpiW3sW5J!2RgglfG5|NO^d61lhJVbaY2?XIPadKe1#x6WSc`0NvM zZ@>Be`MzXlt>1d@efHUBpDn3+23{+u_B?_Z)IrE1QYMUz70utqg+JL1U^@<%=zU*D z-hGI0gG=fn{UK*C+>svDhGj2bRwomNh>t(Mdb_I-?$;gZz}Q7=H(s_>ADL8N zx(l0?HYtuCPjP((HDCHnuC8;rFWsThspWQX>*^0^zT`5|i4j*{k@-w_3E($4mko-7 zAD5SmQoLxM4Oet4#gwj_;fKR4z?sUZ*@+FSM@N@AC#)@_rkYGM z(n)S1r4TmDGcAR6M+@K8Wr-=Hv&*fp6o?b{CFbTOiYEjd`}lzWAAxtd4>(d`X{Ex_ z?(EhMWVoIXK*AS5QPXaMK~2k^vmVYD<3_`PMCxzdl5>XkfGU5&g!*+mJ76+*#P-+Vaa^6;ydco_kO>BTtY|s;a|TgLt`;1PILM8_dl&_@MLOMUhPRSEXH z}N#XW%oBDfk_I@pY^a_)yd!rTmXBX5+U(LkYA+5F-`%PcL?TMq2EpCzC zi<5z0!NcIt=gzIV9iN5VJEAIIshJSk$7SBvt0IrrOpLI)sO>8TPF=g?vgM1^%%Pfb zyZyy-bIIu-R*aZA?5kjBXVuzE^-_H_hkZj@Za*~`%;Ijpr3Mj&T0B%UwsF0$$M%ftg)a`}>F`mQr-c@O6!!)`BolI6~B@jReC%Vp>vc6%+2i#<2O3hfST zTCSe|YE8rCVx&_GyJ>M(?k{WpexIBh6qikmr_(C-1X9F@%BaDI%FuM#+K4-Yu`{{H z$ps)=K>i@o!#@3prsY{lW>$9stY};+*6Ln?84b(`>(;*#xEkLr@HKSa*B`GL>n=ki z%6+UP=V;t)avV)mw~~eH-B-G+NemH~Uw!-4JZr!}%nwH*>D@R7WtUzSi@!wt!lvUx$n&#coy9Y)--oB(I z=}Ig1++|!)>-#(Hnht!)7+*=rL$1q^iNN~O>1Bq{tU(mz<`Idpx~O136+6eCny$s%_IG%O7}E0VGP-ql z5IZ$3iMuy^TeT4%6;m!wIOkwv@|XKdfi~p zQ%Hx?@P{j2L|aDF34432Fa7J6m*`|1NWV+}u6Of{>F^{iF(hHTQ-H1Iq@Sdfw65<{ z!%yL2;qr>V>xRti@r5U`zt@-6-;Y+|2Dv7<(`0GxZiJS!70JpkFTo2gRTMk&yyhRo zT>?lpa+$dfa=!3K@QKuQ>-k{t=p8l_sF4ixYv0? z^JN7mmz(sf^uMgk+{iz3a#mrQc3kpVXW*PzprfE=089_4_Wrdy<2-z1LY z5|L+{6P`(&Lg2%sD|N-1WMqnhJLI|WQYqYL;iCbOPQ zUSdz?1i7T8AU6$HRnPcu6yzrMyIQ(ZHg*ql;Qz0Jh`a=XueXYRYxH{c&nYK}6ru$;JF|L#PXbofnwXpbOG_kO#kR)UzD*Gh5?xD^{JlIeGD_HF^w>UP5Bf?S`V`&|L%I8x!+IoV4RY-=5X53>_)JCzEQZh(#L? zf1#1YEtp}OZ+@prvQ!bxNDfAV6W_H4NpMiY(f=iaw*&$W(#37TPtIyRF zzU$A&m;1Y%trB@RkCVw~bo`C}z&?fD{O{r0&0?zed$`PT;`4iWw6|3m&8gjiGm@Lt zjz82it4Yt-oQbbEO*{{@tnBBpP0*oDN=U~>G%YFLffqL<#+5m#7~a=FY!z!ya9UW3 zX=@U%v{&{rzhbto*KU>kKDNoZJK}*P29A|9-;KY5Z;ZxxjkCC|+Y?>~a(V8^vz)}w`AirhKK@94 zHWBsihpJBqPyDf+u45fq!Cwg1a7yE&1>nyFe5m;+IN(4o<9uaU`0aCnr|}IH#)8`5 zonhTdPe{S;EUC=@!V2KRsK!s&Q073dWqr5jSza~=rFB=z?Dw#(?Yg@o%ol%l$-%GU zJ2r@@R*<3N?m6%flsyNT#r4n`z0;rIFsAJtkEqNG|F=Y0PKKx?B&|O&Ujlz={L`A; z1e`I3XV|h1Q05}(nY$w@@dFIyP7V8~x*Pgf&DO2kF)2--^qDB4@#AsUbHc#?xnu5j z`FcdQe3a9I5~sv>R)?zmpk`b{M#IAH#v8*QBJ84OyJ2y8-2u#2-R|Xq?^cJ?bIlg3 z#yDs2^`46R$arH``;p<$%~fqYY->Oad^)ZMe~8&PqbfhFncU^>M6kT*f4ZCPvHH0j z$K1T;%QmJg$z;dE<)2KC^;z#y_voM~iX+*|aQQ{;SRDC>$)|f&`A2wE<2bKLYw;6i zyr|}XdO)}GQbO{Ox=Fe2=?>IfzEQq(c641VYpf{Oi8sfZx>5;kILhs|xTa-l4>&J- zalkL7`EtN-BaxU|-GSo6rDN_M(Q@*2#4>Z&ukNS7I!s*TKErmoI;S*!25XoSzMz#8`wZ(z z_5R9Ml~T=w^=UGPZsYC=*FUG}!?wY1+MCm~JXs1Zo2#zfUSJ6==_k$GXSY?Z`E^mpK-0+r z&!trOr+9sFl6dPMHP!Focu#6>KxJUAp;N2LX!tCqhM$g(2A6FGPF=BT`5LFw{*o-u zFr$%&_}xRAFB8ANnxD;7jm5WrFIVk9s~JBvsfACr>T!d^ci#UDSFtZ+f$zs@YQWOb zGW*El@4tKVkVWDN`f-k0qUW|tdO}+1c%h~BuRZSXs2a14UgBNp7X~|Anu`iRgfBJkNsiH$T z=P{twW!9DAJTMqIb&ZwLy$1s-hht>&;@lNuHCHU52I1X* zc|Mp?BVbSU1tqrvH#e@qgL!5B^XPiXf7Dm*r*iJye_wUwb2=9{IJ{9xf6NDYWX^N- zInped>Znp4VwCUyBoW1G}wJy>HNJB5RYZudZGRODzqA^rCa1!`L^Gfg)L?Js zmskxx6ja?r;ya(I=}<$|WP4u2zxalCYH%`&ni19c8WjF#ROMgOwuuYdMCDZQSD^44 zDbx(9j$c9a^C%RNG1W&+N|mVTR3m8A%5qJEikEA~oiZ3WQ&pXE`k88Hxh71j)G~Dc z2DhRzq%BpX25!pQ&Fg3iDn<=X2~vYog0G`LAI4YDzYbAkLR=gkpa!3Oqz0dSd;=JA zrv|yd0gW%l`KG3v(?~Urmzo|L1o`#Uc_s=iF z`EP3QBZ?~X86zaYVc*G)C?>8Ul8u2s0@)9;?!UqQIl3>YPx%d@h|kK zfgUx`8;0JOphqP1sDU0e(4(fi=ePJ5delJgw>48v84fh7${*^RRra?v_0^9dPU0p4 z5%s}!^%3>bZ?TzZt6?x{_`VHAl=p26pS$0#saJd7t~s~*%K_E>HmVd?1BBx`296Q@ zulN@um>P`Wf5q>bjHqs+(0TugYpWx0YI4=GxJC6t(Pw?$X`A{os!VXV1JAOEOYp@` z+tim=;okwqHwi%dVvD$d<9ucIm6S#BumjI_;cFeSrmqB4=6Coqyst#?qYxX`^Q-}N zo;1FK3zyWB_&E2n^|LfyAD;Ott7A?fxRZY8WW6>H=QGzZoa^~Fp!lZsE0%6_(HXyE z6mtr}Ls+sdS<1fa!!w>?7<0q6n(KK7XkXye)Mb~r-8n6*Eq@h7c?Ul#)e=?7 zcVG*1$vYTJDbug$1X8QO zG6p;~xKJv%BEN=dmq`3h2Ac8o>G}2YJ0A66{k4wuO<%)UB&qJ6Kh%s{(rY?Cx2S1% z+o4L+Ut_tXrD?fuf35HCjz84&cl_bhb55_SRi6!xnegD}$DC1JTl>x8n8C4{^L;~h@T+?CztcivT7fJGjhUnwU7<0nq1pe_(3t(F;6G|<{g_x)?cLYa zkHO!u{nyn8#~tm@ekQ0+#g&9V^^L#j3)EFd>HqYnzNs;%;`aw>ND$fhRy6R5phf?u zKY;VfCfK?AJG?2;sMBh=pmGEkg%y~ZwdDWMF5#H}WVQLc)54#%$EXkP53aBJj#~G* zAl=h%_*`)O8RNb=|FX4xmv8vTBa82^IsAp*AH4kGPu1r?7kmhvKj(qq%$B;Km_tjo zb!eC_tLy{8aaDc&y$=KzS68L_hkAmiS5-aHKdgd(stRMGI3*ko1nNk=exTC-&R+)$ zHTa3X{KLVXnyTme=lpH(`&DQ^dNerml&Ywj*%xeXiBw2D5XjO$bw?XS|GPbEXJ7E= zRnMt8UkP^7-1U{2XJ=6crlfmAq$TMU`{|Vpf z+KN1tinnRqgA12Nsk{wsIRF!W+vqDADj9(4EHTbJb z{>ASO`?_GAJRfk zt1?mF(uQsvQQ=!aPSUB}G+AYCshy%0Q~7V2p)6qPqpsR<)i*6tc@jL{lSMc;-Q!T> z=>|iqtq@gQ{?s=diT2zI*=5eZw)5``+QE?*oqSquu7o!bro*DUR8+vhR*Ef=T!7IkZ0g~uF>RlGoW(E5#lYMQCZ>^@Ub?KxBgTWh@7m- z)XdOLn+o3!s$Dlro!o9)p)6v4pq<=)ExuM7S@&J?fX!3U|OWe3_vgE$GI-A2cB!l||lTWEKkx%O|vI8oN4j%vQj}IgJys`jS zy{g0b)D`&lVvs*{GE^^i)y_io@?g<0392cFYEQ2|wi<;TSGAVLNOSeE4^*7U^Hq_W zZ)oa8r`C78t8&DAU#D?rjSlh7kdEz6T!4VpJGkbn?@X)cryzTXu^aKdyomeg$H#r= zF_k6h2Xx$b#Z-YvzJ%|3gt`wmATadTw{y%

XVFYhMQS>fP0emqp=O^JxkroKt3_~VldzYx$je#; zwISw*s&FTogi29^pzcDmLS>0Mpo8hYUd!Mh331WSXvROy1>#%G8EHMfy3y}2aYDc6 z7)HO7hmx*e_siPhE85|!Do?s^e0=S@-=?A4T>a^QR{r$Tp5soiG?n$wI9?k&tz}nH z`}v!<*#_TKb`|?G_t)M#rg~Sg=dWP{bmXsVSGKDAepWkH?fa+NsjBOR+OhpT|5Ur> z6gBZxFyDK=wn6>Mxz&BYcI)_vHvIDgrr|x2{_OW_|D{?ldFmT}@wkBpCKgrp1w=WZ zdS9rWsXqE8oV@r#?d#Rx6n;eG8yxlGk7|EAKB_&GuQx2z?1`$X;wbE^&EpYu-K&?{z%Fk=*k?uKi-wc`9A1ojG1_L^Qnqkk7+;s!&4RquRskkNDv8 zRoM$a$*{gJ*6f+2!aqTVlT_>{@F7N|6S)KSMEf&8shwDZg#ceA9fPas-Q#n<7vpbfo$NM-(9d#3u2*J~Re z{Ca3i|0mw4eY{G&LqU9S+~;IKm403O9jx+lZ(^w2_d)HL{;$1BODX)$_HU7TtiSuW zwPVME%vBt+uTqO2oQ|pRyABz9xAvVe<8{uB&A!4!M^yYjQJJ_Z{wI3hseFCoI0}38 z#!<5;t}0%5(+P0&efWy2#QW&|4kyXRao;i%Ij^HX`+n_vRW0X+wZM28MBLx!Vvpg2 z+TW`Qr-g#*_@A*bJBt7HKm6y~a<#*J@OUWZ@E&|RRB|}g=TxiAX`yEISXF3CRidXl zglVilQXRrjNN6t;XYw10k*=S8MLO(gpo0p-NEX~SUNOO`r*(L@jFFEsRaX$-=2mLZK~i; zedCmNG@dbhZik9Dgmz+EH3zAxe1Bgb;SnIVg(-Nsg5u;*f}bY|#g{`&F8X};k$X;@j!2ct27lCnOCRopbjngNX@Oc51 z8y9kaRi|sONYLV6>(27&W$vv_QyK$rezU zy@-mbB2n11J_}S%CD5pk;Gl8F5%$ir#iUGs_N>slPrz9zhS4{uhGU_bwIv(1^kwi$<(8_uNk}at60t~ocEym^f;eyZ- z@U4aDp@KHH=}?aqYVJR>Ftn-)uN8`mpn?aTMWJ_aD=jYuHLSuGCY*|v-{PBaF2L&! z3sU$-GYif~)PNP*(K0#8(zl|e-sVeXa!SRQgqo`-W4Ce%rqh(_TY@eqv-JBcEs2%; zD@#JS6;37`{k^@}6qp=%dRb_H)p%ROSHA3nZIxXfx(^pvcm-lhs@RIqeb}1DpZZ4o zF&5UL)$FlVNlOi{Kt8zaR-)UJDz_4qXPv9eX@_)*fU*BGv@(QkmZQpE1+quQsd>t2 z`gg7h4OXj<)?x4;c*qxEMp#ANRz2@ozZ>ZuLD85aK*sVEDRfx=})Z18xU-Nkt zy$obPHy5iEQIG1TsF@?GK+GE5gjAWRdKF%arrBwnr?t_?{;%GUM@T5gb;p!NQpZ(p z9eiJRkIE2vuPQGi@_v;EIsO62R^xAolmdYXJPTZh1v+_pPB$-Tzb|ROZ>ab>VAaZ| zW{gUa!Rtfhhhob*hAA`kF$KEv5s~%RBZ3y(>BdV~S+9w!((}Bmo>$6^B>+h-JdWd5~ z&9QbUsw!k{o+@uZvs7iNS*D9{Xstu4t_`6`)r(pJ52+;amI_~iWnz#yYhNHuHnkI6YDsLiky%xf*-*52f@!}PsS~Yef?wCh3A6FJxd|F>8ho7N9 z##KGf24$sG}-J4R&pa`H&WQSc^QOMIO^4FRQ$brNxb} znH8TJ)3v%0+sp5w!)`j8VyAs5in;oxWt16>6is5J5P2&l02J$KBA?Zv-h|s5kuNd% zwki=B)Wtcnw5J2q3e8-v;zaF6O`EHa>{B*TIp?~mKJtPi`J$FAsUl&oIF$Nw2fF7y zt@XZ&ZUJ(!zS?fS#~cN*VV&8{a-Xq?#^)4-f4|B?eS8miWAWF*U-}cIf9e}=en=Gv zei)P&4l|66AA)K6^}-Q`pHktixL>I)p>S=KdEZhNc+N%%sqmNCL)RvEyv%*i=0 zg&lTIf|zH;;qs^J!QF}NVzNFDFG=WLAlAt^(&=2(vkmA{5FPmIN4Gn^tB&cprSrJ5 zN%{#$mhqS8N&F9gVCxMQdrNopEdf=8c$e=Yk7cy@Epn0TTU205l=%nHdNOk5uV=o< zJHggB-g3ytPq7_dD^B9ubIqP414j*onmxN!iPDNPeB6Kov3L(Amo7Iv88=+3DH6v0 ztR{R3g9g%QI-^mTcS}UU?rCI=$_HXmhksV%EsyvBag67%D>2@`p&NXlmnd9wXm+97 z9b;0nVaHhGt&2>4jK}A#t9^Wn<<~M_k`p^yReVQiTx5p{$3#s{+!-2IeQQ?Pkirei zX{PHYrJI~867~&EeW=PiF&*7r%?2GqfxuLb@Aj06!Xg$f&b;$U?9meWj0z89R{A6k zb$}fIM<~z6U*GsVdWQ3yTz#}#Wg*t}B>UjnOm%$KHy(Y8`3?==!hf3iBEKFqhW*iR zF`sKQRrufb$tPI;Su!sQ%0z40bdR`pxcs=?8^DVUa!$&V0kG`br{g@_?Vk6gS z@vZ^w~z{TSUW8lp63Sqxm>Hr2lbzeMNLh zm237U*wAX9g79VNOF#=)em%gAt?48+iO6@MvsW>aJKkk2CCW9|-( zn=66b>Vrl9nAfn!ZcbTOg_?I~fA7;{d!K4yzJ-=5D*UCOsB)56nBe-xPpx3SMKt7v zzenW`V1oSA5pX|F?Kcvon2cdj;0%sQ#dT!^)3}1iCa?qM zPtAiyK*uIAU)vd#H^+Rykw29bVk)&4Gn))SZO^?{j%{Uo7FtR$N)6O@pz&6g6F;__ z`4(DFL5}SM<&~#bv}EUi<}Y7Jzj@4!lxZZCI)ReV40 zsZxFJt=19pQr~z-t6?@UwUhZXn9sfF%9B2Y!F*T#Vtt#s<62dOJ1o9X19-<9dLr>O z=8*S0qq|-L(^~>A{2fv{F=vrBa(kQQ9eT8*?vP7K z=TNiP!6E;FDyLDZc2?8o+yQ*&B9qUD!5Z&e!F(=>Tp)L@HuNrX0bH~%_|(FnDcDz-ZxKD(lXt!gYP1VSYb#yC#h6+qHQ15S z?XT^J+D@ZXLlo}9t~0$>c=BQ{~Whx#CNG;(W>6b*tgUozd?)=Hv5BeAjX2TWG09JmKDDc2vz?Eq_ttUH(3D z6zd!B^7oPOD|*#(T=LV!b;tYhNpL%QEsydiGhgJBpwSt}TbXYWjevzua-*GEvzJHQ zaecuw$>ZoKU@QANTxi$(^mxo2Kg4|9AMThte#9rw*Z*-Tm<62T68>kLHA+|G@yEgT z1}FkjP>b|DiZ6j0l@Cm_2u1;3Hu z)Tq3h?%nU1{MJ5FgS`Kuw3z=P+EW7PZ;6`~x&tbI1LC8j=eQ-^Q&J@&Bbxjl$({@- zy|GmNKRPvtcgG}ycT51gnjOosx(iIRwa3rM$YzHw-&fda8J3rkE%L%o0k6j25Xl7s z=jQ0&`o_=LXch(n>b*>;VV54xqe0xLh5l+QS}LCyW&XWyFrRyOn(*KLc=`KMx*qpo zZ}cEi$4ddK)_pjKLpSpKc<(HCnkoZU-#>`WqqOsXd{}@)+CID6^fI70GD*|F^^FhSi^dyqhWYn1 z-y$0F!tVj$mG2}Jb{=BBMKt7v{}>3!cLgkB1F-2|C_IkFYbeWnb7l<86uxw|l%|{I zpGHe|ETUmw_|o-SUVY-0P;JYD((jfd8kRt!KO{~Iy;(6e7Ze6ET{dif+Kk)+dwI7%NB!2t#7UYPxytjm=s4v_S3Rdk=*;CO= zU&s3;f}YV^zJ=+kLgY78^j0*dInDTHm<{4@8-F>$N7~)rwWt(HVW~@RR{rizl?AD0 zc46P{sbN(h4ClITLxZEOM6J=x9+j=FaSAPR1wL#9J(dMbp-@mFu{-#upD8Wq1CRuZ~-KsWf@3^9X5HCGQj zpmIbORAnNOKUGB{{F@) z(izu>Q3I|XRf9(6vjaWoExZ2-JGw&Wo`>|Zk2r6A3yKZ2GyE8sh>M!6%21QRF>5*n@)(YV{rs^| ztjc=&%b^>nz?pA5!g*>kszgno=Q|EBP7U^%smZAvH3*xUqN-41t7s98rBc*nRF)b< zQ$(4LlvSBXyu|x1n!K{8u~bG=d1{KP^j(N{m3y8AW#h}_91)wEl*&yb8*ah0P6JL=SgRfQV7P=6jxL8YiEsw_1~Q8UZWLm#tz`1{~Sl|>DfGSpzDNexnT zsGdP8|MyY;IfE#FLD_>){Zd)w03h@tHOP{hl8XK>G#Qnm20p35^`V(%YOoFb0vdGk z3o!F-BuQjm<*7lEXw;8ifVZ(fpw3qDAA}~fw9x3Gc|{MSzTB4@dcgvvhnWYv>6@GwuB?;=&_{&xZbl?;kkM(CG%+EM#v^4x7uEMM-^&CyA zWE?*`_fn|2u_bTfv++dnLj*Ouz;e`jyez>9lpg`#-@$m%#G!8y-X*z~OdR?d2bVa? zCJy~P;g<}9PjOaE9Qq~TlRnA#StRC(Z+3zh^-X65@yR0CIV*e;Jc5rFA^)?YJ{;4= zi+JX5FM>~Y;yygZeDdS*JFAoVmdU?rg!xI6|6GjuWY1$~9{CH@tM9!SY6$&}B$;tK zOHKYU_BMLNV%F50kCSgdM#f7-DQDt)F|Y}rod%yW%lq(NRUmv$FXIIhKY+ta23|CA z8W|<%@0CiFOq@mr;SYoD_%EaJWPTM+mjQ26;=f|zdng}@oAUSQ&5Nr%>CMk-{Oq8K zx3k{aVUs^Qtx6@ji}m~jQSobwrnBQdsep?A1Q+2T8&CS+0`pTQKc2_e^1$rHWyY!K zo}l482fTVVe&!Bsm+QXUCr9c?`fMtSNB`Lb^YbSEp$hZ+O#T;x%%^xgc5Wkof%;RL z&K^|dSL>SF&Mx@`@{T~$*~2D3t`(ck2{=Qu7202V4i6^Cj$Hx{MEBq z7XQPa`lfTDXgqoslON*8Rs2#+lINsU=_O2K9j4etNfyiW{BLZhbox-6Q3`VOJ{|~W znV&=Jae9&P(Q7d0d`i>{_p(}1

`1X;V!pmye)wWPV(g;7)zvi*@6wCnkGd z#zmY`VVavJ+7R)W3ULAx(<=2YF1LxD$|muwD*Zc&6YLeA&K@uouE5}%*r$plUQn6$ zNE^#AB5``RLgbK&{v2dkMc*M~71LNF(dhSyBg#4l#-jK(gP%h#8V1{wRy&D7E*ez@ zG8a?%G>Kyk4$?W+>XnYOG%_9n?7J@7lMG{1jo=JOueQx_x5^Nl^TBi-Q7Bm00LJrC z{C$de09;R*8n{eR)Z;fOM6}fN&yXHc`HzUg87v~P%A0~b&J8I0pTRyi_+XC6h{`!+ zR8<@pPxU07P?_ljoa~Lu2gL z5FJ<9UqU>gQVyBK_rSoouQ%sf+W2{Rf*?2z(o>|l9Smay`x@Y^56&>0Qx@PZU*2=O z87`pp4BGSa%=Z;yuJB7f`DhoEWB7&}q!9PP5r%01cv3j8!2Fa?KEZq&tw(;61)ALW3Ouia`JHGXub%%EQpkev zq%beTLU>3*jQ-&@kIQ^MzJa9-m_qYv=UKa`Qh=2z;{@RV^U5kqDixnfNy8TeRH2O9 zh4aAyugMX{qi8)@PT<+-f*AN7`T1d%w^aCbxT9iv;CPVX4rLLXHsSdxhC4Of?SnH6 z_iDJ$2j>_b(D0xSE-*Z#;b9+KVt54KEQHX4KDeUc$q^05On5<;@bY9l3|RDt2LhATdJNW)VCs{Ct281}*3(Nm%tj+^kp z2y0s!PWj*j!?uPqKDdM7tcG(wxRc?$1FLbr37sBV*vm|8F1#5UH+9gb6J)q#^4o{- zO-p!Gofl`kY~l+Cm|tMiPIy@HNzz=RhLsshwo+WS~+(8Lj48F*-s;AI`%uqn21gw-o1 zza1~=hCR_uB{5HJ7Y%8>sbQ5H4vlMw_+YH?pzcQJ?=nPJ0v=i%WHVSLz>IT_((9#z z;go3}(Zzr3jm|dl#R=BS=;%64cu_aLHOm`aw}~UVBJj}SG@Hrm==w~tg%W(hj)RO?>ePXoS}q*V|{U2@}V4k%7J&Uu)9D5nmp7$cnKYo8wEHa&lp`W=wv2 zU(fF_W5!uKYoZoD82dZyPcH6LHpH-9+4;NBifRiN>+iftm3(RiHdp4PhE057P(}ZZ zk}9$s6~R+XB$WalvZ%9AoM~a5)U=2xCrM3nD*W4MR?{dukNG7*RsJ_*g{wOJ zdnc>d@A2tBJi=(I`}fFk5snRLa+t`)o%kj$Ps-DLDKFuar|Fbc&pX&zn@xF9{1r0* ztEh@F)+IY<&Vs`e;Ow&2n;tav=46>4Hu+YO`M&zd&fD~;DbF_$bwLGtf=jr_(=DgS z>Ubp-Zj;ETr%X-PQ-{gN_EQ0muosgS|fBt7QV6-s#g%fJUXJcbohs2Z2Wwg0?#*edJr^%m>?O@sincd5{uPbRL1s=L2$#~ug zW=o&XOqt<=$#=~TnEd%7Uo`o%v5@|wwbZp4I< zObOOQmkeoqMp%X4Lx)97F?s1RBkJd?_&f>&t@R!~2Y+ww^M@W)Cvl z;o}!n5$f)6n2|Q|WftqY|k1tUdef$y7)9;DU7rehEgNAo?YjirZA?;B4V9Iv64==50)5me!i+8hL+``mp5^gB>JBy z$#NTfvOAz-+5DfOu=DIoJYQEX9Z*^5w9to>9Gx;6Z=JCE2HxhTLUr@t^Yfs|F2(HO z<9=U;UiHOg6~_MJ>ZJo(E*>%E#BV(2<8uw-l&i-s`XNL1#Bba(@%AEU#1r@RpS+}r zcbM|1Sqb(+%L}ZR(YM?&|3!<1G&8fN5{ef8FRW6q?fG9+yE2RAO|fMKl>_eHx#Q%+ zlZ#vtajK1%kKqBm(Hwn!=H^&3_1qlGCLiHOKk)Q%oNDX!H=^XvIn3t@az#)fw7kMuvTiL##5h>sk{l#i$9pJYYru|3=ing zil&qs+Mvmw6YZ(0b06E0+KDLN6$n>eCN0S~Rtf=})-i&O22pghqfDhv;rd_-4(`e<}R zCce7Bdc!(8GUG9e6=!%1qFZfiG3P$*!4aJWJhZyZctn-QBDyF@kC+_Tm>o0ut8*$3 zbvL@%2@}6G3>rz#PC8~AQYJh<+cTDeBO#Kq(RjQfxH$08r55;vck1A>pgdx3aNQ<< zHO>G)eKfdU6TdVAn#}g;;0h+Z8vCLYopkK%qKPBAXpo}IgHL9LbaZ7zY@uE`m>X;wCODwsy

_HBR*b-|gDXnE0wPXwvI6`L4aJ$zN3jP4d28#a=pI zXNJ}gN-#Efv1_=ry#Ufv9+}?T2TXo@AL|uO{u*om!>-#M?Ij=H%X)n4elJwlFy3Zf z#gv_mJ98aMF*mC5In;P!YcDcCX!2!QF(+*DlQzpoOg>f!S@>~do)a_iHAAeI&_igB zW#U)~l%d~}%&}a`#M|-ceHvaBbOryzM&nN0|=r7E0(S)5Dh+-+3d^dKgiKj2z*vlqgmWs|P z0*`#M2ss@3d+-x=4Wor0F_katb%dG{I8uLl-MA$btH*{+Sc!(Cd+AR2l<0TkMseTTp<6Wo2 zrqW#X5oBDSb4k@xcUnkb+36mbol6OOaQL)=ht`%zvA$_;OqIj%sluK_=Ta3sN|^VG zj#1JfrId-oX~l4An>gJ@8nBv+f=%kU$C1y?4e%-N6P<$+9-q+3Hq_4TM?zAQu49lFjL2@k%G`jO%&Ic6J%O!fJ=L>p1U_9BbYGBf1jQ-RR~;O}%v^pb;J1kl6-bUtps&-sFjHUeZ*DnhiXZ zim@46N0&Cm*7Y%*G5J`S7s=_h%4t&B(j&T{!@Np0BV!))0xJE-ybdcC1moQX+zRhpR* zQ;8nS&qO6;%9tPX;c1lz-X?3O`3WCB!gehme^8akt_&~dXon{`-29uV1frhSH;ne? zy6|dAe14~Cb8Zwg5_e`@k1biK%%^&K_?KfP04MGkbgm>XZnHgXX<+4{-fPB6K#Es1 zZJ|!lamdGwt#ksOB3xD_&X&8!7fs#3-HnU+6;odpm-DG0UOg_*0>MJ2xh01kvi-ImzkMB>v4Yh0P`)APs@RbC)oul6URu*0}ri_ zf=|xUjgLbM9`ztwYur3!|nIHeL&k(F7||>oJN4#xn5LbJL6`O?-Wx`6-h>x0m_0$)Am@ z}J0xZsHhzS>WzI^&-o}<-X$_^zl>`%lrb_y|fH@lxNas1#*1<$UxxppULU^*n!?GW@%VA=^qKs5R1U1n zzcit)A#?@(pOlOG(PxprOA|d4k&9d4(!>a66?=@klhtG8ek##Ozq7vMIDJG9V zi;E^7)-zC-`|RS93Dd0uW~95`!0#8IN@{B1k^WK z6r~485;k!6&SynUd}ACm>BUSwHUx5H_tGfi2_HV9iey(7mX@ze<<4Psn0o7mRP?;j zs#p}ZCtS>1sq?UUkky6N>B9#>Q@B}^@2tv+-)-{c%CmAlenA!B#~s~P-o!VSL6beb zVp?kXI$f?p=Ln29euV|P zd_i8>G2DLK2s=&OjWBES7g(Sv!fum~_ft98b4T0KUK8&~vYx&`8=bfOo_J8n=v1oY zAj?tf!QD80J?q9fWXdnF*-qKyyOkU^`BKTdrlOJ^d4NdrlAx~STT|=8T^%+vBWOL5 z$q>IJYVtdREFUxZGQ=J3-5L#qX<8)W<`^~B@CL344Qm5GGFg+39I5X zekZ0c?41x@xUPEboP88LCW-jYcUvXhwSUowtu6BIJ6qKQ`tW)KuV^+`l zV5$q*!M^K-c)t7cg>|R9m-4b+Q+R6!3+tY4b4~$xiX;Ph*?_4hm+G>j6N8#F!|TM? zvs?4*r0itYwu~z4bz(DKG5M|&JWyST{mbWP)P>zlmIqDYtwY+#@`&y(=V+G4iA*BP zW2T;T*Ydc@r{OWvGdz}CCcZ5U8f9LdVt-Ugk3YFwoMTxYz9h9gZOU(psPG#YHOOA8B2fJ&#QfmM@-z+i<*2q657yncjH&a zO&p8h9PrTgVerW>c6kuYmXs+b)n7@~^n@jk&ns<{F9lnf_VMvlKHD>dR(6{Bl@@3U zqg&VH?%8!=dDdRpYs%u;qc9scf)Q4s${3-kGQook5126a2g2?2lqxv29(5U?D}7yy zH&qr2B)gj{%cdIYnSt5Rm09p9kr7p%gLg1Qd9CBQ$??v?C&PZ66zZFj5tDz(aL*j{ zrUaLanJ~P^frqZFu)3waCrz=XBPs{6wmDfA>o9Q{WX>yfZ`61+f!;j%Tt_lv>hbVy zN_Lw39SQc+tqLfHnv%dVsU2Bn=A9V*ujb?=M6zJoLjAJ|8qmG0UNmu(pa49yL+~MO zzHExg!HMLs$%pyyTy(E!kC-s5TXV^J34HX=D(ni*Lq<2x#a92EGBcxSy=6-?-`86> zF_4F`HaUE<%JS)v8aYY%_=%o*s6cy>VKVP=M}q)(XlIb|tP`XEldpJO$w92m*-s!Z zl(NT+431TKlaC4&$-RpgOdRejj{8pV$u2&-h!QoFOfk4m&BxP{3}vUkz3#aORt@{~ zs7J_b#pJtb5dJZCoa0j-zD&j6oR6t^XAw#;x;pCI&>L6#dMcGy;RQJ3F*mC$v~5?W zSU!o?V{}fL`GkA;TMH@!z1^;!ZQ^q{snuzdzmVdfxH2Yx?f~<%CLgsg!B5BzGoI&s z`b;_G6JMzFvC)p^Gib^s#7@cNZyi=S=#A!6Ht~eSJ#6w9CP7m^6_YRdTuQK~ZZwwQ zCuHXcsBgNI`{z=!?~y}3sYN=UEZSL8=S#_-M^5s&G-dL)sjn}p8|S8TscpiN&ZTLS zFX=dEJ(u>Ga!4lwIT~(xv~KrYI%vuzEYM`9Wb(Hc zR0(>c`IJpO(E*zDhE4uL%8&RJlP~$KA=r~A@`+oNPmX~4rZwC>YhtDx^2tGt@+qQq z^I4NLm{YH=i}OiAz3fD1J|TlFyoq$#?U~ntbGwT7rCbhry?OxPR94 znR3Xd06EI1jCM4iK~v7nr)2WCb*S)C%zZLU*OX1%&1cx;yZKa1zT|Tm*xvl*etcQb zl<_ga>ZV;P(t&-M9(P z=~ZC_(K3%}MUE{K$776GV}Ua3D+i zwPh2=(xU=h_btWRiix*VdC2F8$;a#U=t{&S^U6(NVGCtQ?CVy`PH2Fz61GHtG?ZcCdXXtx18`ouha9V|vsQ-+O*l}2w z_krD@$@T#0j$b$EgZmg(i}5XVUF*s|xRc>wAHSFRzKY8t&^dDEsgz`%A~g?xZ%Nxp zh0)?&`6pJ@)jD~o_EmM^(7qtU34NvZfZ1|U2Q!msJ+|=ujKx*xRr!9#6v=t;y&bAT zxWt%B`|w^BT}|%~IJZ=%iO4=yr1?7$5pKDew#R@co4?I$S&cX_<$QW&v7ctY481x;v*zKl@+ zsI(VOGMv$H7Ni$WGn`X7XsfYnuwjwPGm~16Fz$`;{r`BCo zH!ie)nC!tUmOpFj#>En*)IQE^y=C(EtFJ@bO<;Y>gwrw5WYu=8cBM^NM&tU7$)B4A zO={G7a!gZH#P2rwb9x`0D7|x?m{X!O{gMsK|h+B(LVytHr;p8`rvi z&<7JuF_cXHoI=k!Pgkxln{c`hG^te_r)vK?Yyzb{w(juNxQSz^+h>>o5;I29*O6*A)@Jinf16%;d`+(-r;#6OE*=@D=##LFQwF@=|p8 z6&eeO95C?%Bdj+_U4O!z_nIQZ`thM< zBZ+%@-Z_y9x0?bg{4PrU-bR#K78RSqrZAS8(M?!tUQ^aaH^o$$e8x>NdCR&fp=}=D z#(k+VkErdK256F>T={ zmfC{rpXWPLb3!Uo)ZSFxGuK znK{{>ZMcK48)7(W!b?Y(@9WUnlm(LNh@0{fZAZe#AH=U~dpguP?&FE_x(eIlJ2-+0 zx6O?*lVbM>%M8}h>EkC<1x{M7Cp8K#XW}$HY)8qiPch!-l&rb~pHro|<@k2IQk4gq zj-si2ofMEV_XOjdZXjnRlYi|nXyOl<{Obd%j3C^VY6r=A>|LJ+O?o&vxdX$6C@);l z@Rp#-$GK7KN{nJT`n)A#;!?9MF_VvP*vLcA4QGpG;@4L|Bb+Tbx`1%h*d25@o^#t` zo5I&(=X(cTN@-Tgn7Gt-i?8GG%FKpdOM8*^x=lTFTn>2Xh9u+Ikw!51#_1^fTfMgf zTTbF~z*NQ6AKeMla^!f+po!z|oZ4A8ZWbA)G=04#7x$JjU~f0z3lhle4IQjUW%A&N zxBxtKL$AiS235sI#P~QXjkIRlGt!(xIv(9klmcSe8Z&LmHMccx@@1rLO_+R)w2bZP z+O1SQk00tB#}6Lm5!+N7lot*&OqKQU@ouREv+i1XYu3asE`z440W^!ci?XwHt|dzH2Kl< zYW22&GuT?U1$}b1mfIHg@e3-u+hc!Q)Q4ACPwxUR-RA4P8~PZxOuhZR%uky9G!`>g z@mdFAZ|gAOgP0$#s+&=L5Dytwp%-KcvJGzypoSl}p}WV@ZDifk*$2rPnaiW`@ZBgV zN)JDs=-J~>rTuQq=Y4Q&iL6bjy zk89m-gY?8Lb=aOZ`3G^wpm^j?v%S;AG4+S{0Z;IV+TLyAv+ zkb(N@G`S_bVB&5WiY8yS!M6{Z{QbSE1bgmj z#I!`a-TP5!Da@5Y6TgP!Vd=`S$v>E2e#Dt=8?TI-IBkT(t{dT%aT7mO22FM?9pU7( zMCk0dd1{9UQ)zF6HWWShwPcwrQEfeZH$wfi(0FC1i6g=S?2bm*ZQ_R|!(J!C#w+tC z-fpSz)ff_TBfhd=;`kJa<=|jD@%j1?Lp(#cJPckrWa{ItnFmhq=t^kYoNw@;JV#79 z*`M4&Zan$77kdt1$jPd6hpz)?_mX^l(~gL#CS}_ZHTl@Sv|-OJ*N%jVAI^a$dr4I| zfYTBw6GkrEXYHb}}k?kn@z-F!?g&?6gh3 z9B0~@Hu<#VxQ;q513tyqtuL3IIa7{K>p;%^toY8n4+rV!7fk-Vu&O|B((EkbMH828 z_?K7mv-km>yuWdUl}au%~XmZbMn)hv`C*x)x0* zsH;u5Ti23_<3h0sLyVC$HUcAC5DcH#+k~fyA6+6y%1?dBR_Xc>rR&!tBL1VX4|~e}5KO zK64UzUl*gw)=i#U@9u6>??{pD>6MCl>?W-E!b34(*ryx9h`WZ(!X>s+6 zCXNq69;s`t?aYBq>dx!;t-H&nl&d{#@@3Czcg5r{q*Tb9uY)^r;0o^C)y7ppQ?Ik6 z^{&Fqdo#97{&d8%i|d@y@uViN!mf&&M(A7gZ$`?Uc{XO5IBsnz;GtW>jCVNB{5vv| z^Hph6eGcV>+^))){Dm>*`??u9m*H+SXR3`SjayQz*Q;}0+3C%>&lFCGlY+@#n8a^b z;|;N!bJ4`-sV{Wm4e>2GuqpN-opRZfa#J2Q`H2qDq*gKca_;M@6T3NniznqhK~wLR zlD4-eq8Al=q9z{4ZJC`Uc`B!GUQs8B-!48 z=?~}l!nf&X1PiVEEV5_Fl*6wFWPneSXN5h!eskl%8zNd0Ja!w_1oQLS>0W9)!AmfE zeVrwT`1VFjd6@?HMom6u6s(Uzw`Rdct@c`~a62yL{kLQHQwG@Hl&OP#g&dUH&4EwOI!#>m6ZU3J{%v?Hp+(%cZ?CIu=ru8PcJ!0LUi)NSuzIg^ zTB&hw(UfV!X*|e;ZtDY|{0=!u`tO6cks86iezAmK0qp4lH{21Ee_IJO?Cc9W?|@tP z`MRR5%(yR=+XMJLaimgz6lo4X#^dYuD1KWU*uzKbW>w+$mhgXfirVLk>-Irye}6z_ zyU>?&y6R4MmMx9@!=_a{4%l7j5LrU)kD9o2@cx*|UxHIK&}+F8Y|3^ zM;K2zkyLf4LU&zr>weo5|37to4YXUub?!AGiF~i>$iBpuFC-E46$GS-Fkr3?4`d)k z7+%qOYjsu4YG2Qy0c7JJ+4x5`wsrik>tFfrj?9mJ0D}eCL94oAmL%ea_7B-oqnnk?r}uz4z?dGiT16IdgP3$Fy2e;?%b;+-%Ni zz8bp079OsTS;4jx%TckVT&PERxvwGJZ7yp!Emd-nmzUg;#Pp`d@OFT(Ia~2f$!6Vw zMeKxb!&5Yc$LiULzSxS^o6Dn^l>CG6MZ9?i36A72`*K%xh~Mmobr-GdU00vn#+GA6 zYCSXGkkV#(i9d)V4X_*AXn05R$fg5+c=G@_I;~g^Tjxr(&A#%{=;;KLRxRi=^^0wI zR@z+Cpa;o9+T2sA?U=!%7Ex9iA7!E?@dvvoQzbqG*T*04fWN3Gi_{^E-%>)E?69-8 z9Si5aMNftF61>B`0~uM8uy~z;C28gEq)y*~?Tw7rmcd(vUpu zE`lF6_sb=C4#OYTm=&CbVNqZqU4vef^(9l%PbG;mvc3dAL4mYQ!v}}Rz^tW&GB=o1 zQoAUeE)g?Ems;81lvH`}^X@Qw3ToUQ#lS8jak^cToyqLdtmMrgTWa+b{!CGq;)!^x zrz$a(*bTqI4>3@@Md{a!fTd-L%xH7RCG01ii4OAkc{W%hG7;km{0C)0y|bzf%%>z?;sz-;?&}>@4`jQBWVy zDZwcp7OdH{xStx!a5SQXpr<>4DO`NmjbgBw#I&|fh4iw7%I-t9u_g6W+&_a8I!w(h ztd~*a8IJFqGJ9E%FSB}J8+k|V%g{KupIMORxR3dJ5tOU7iju~4)ra?Jxx36tIr=fR z4`buGpN_FN6?`?{ltFOzCJv#Q2qc}*-!HgRR!0}Nig0lnwG~Tj@5CA?93~PMb~R!@@EnJUGU|a5TpuyWkB4HOJ~MGxC?a zvRaJ%8tkIWak+Kn;O^stUu;eUFSmNeJa{a(u9ygK$@*{?N*x@TeX&_xFKmcr{=2o-3Cw1?^`wRGrP9!cLNFH~_?m>(I3K=d}#3a2G$7O0TH+PN|Ny*=f z2V(G7MSNQF^L>=bZ${#`sFk&mq}e%Mk(KPWw(_V}(~&C*l1GPhY6!Xrn4FVj{d~PQ zc?jKMM(v8Sq|M!9MOETvw63U09Bp*qZ|r~MfKzpzi;l*DN@ahP@Cik{@@#U%K7ivb7m4J2=}xH4wpu44x?YbU*PuPjI&`7VLK+vIy?QSzq$ zR+c4hE~l052jEqSqu)BHXLv^wIK|lr`mM5($}HX;zUEsJH?!DE;+g*TF3RMuEpc-> zueADoXI<;}An_^BZ~V^4%(0aNX}ohPR4T=kGl?5jLef`bY#l{TclNbfO7a*Zsbk^W z#QZT_ImTO7s-bILsLhMq|$I$>5REvzSZB_xm-Jy@P%R~q_!I=I_H)=;08cmX zK4kbhW>r=ynH{!OIf>Jfq>i34uQ69yJsAb-NIP?HTV?kkjy}O(v?^KUO1oWcl&KN5 z;NtrHs=DNNHZ|`_-1PXWhQ!UJvx@9kQqZG`}bM3P_dAARJ)VDeo)Tci35N^h1MqQnh&TtiG9>Rb!Z!=e?B~N!6@X?2K ztH&iDY%)=0S&5tASLY;-;A`*~1;4r=`5;&1uc+LIuw?wVhp_cib)ZCGHO%1Znq^ed zd|l$f=?1d%B#xfRKYVUCWp#LWym_@R)lA2%wmPh8s+*GfI5yLLn77U9xM~yn6b`PY zN8W$7*0_BjX1R4$_K|SrDM3bWY9B~TJrnK&Ru|zD2@iHr${)x{yJ{b0g!Op37n>P(%|P?uB~uO@M<3cSb9tqRt9lE$uShpOF0=^^u`#TO@^prPBv@R)m zvrJo;lK8c4txuJ)#+XIOx{So>bj>Li^t!C%_x4dnPS;`If_`mdT|x3RgkT>Hp>;*c zn<2EWEb*w_uEc2wJ&C?Fr-RqkBu_)=$#ds2)_IaP_mFi>iJOUFT}$FoHNM1YHH$E& z@5=$F=7(n@)^(*?R2^lBWjm^FAaPUOdca&C)n%T-B)qRf#EjAPsc?u)K7~&+$OmB= z2v!Gn%6!;Fe>G)&R`TYeUQbP6c4lr{pO-kUqCWgZ!*{(S`TYr$DUOorK1KJY(^%Q; zr|u>&T#H_@zK$ZR%&ZC4dlJX8t$7;VY#vzGHzki@)dfG#Jg~0!C2xk+`i{i0Z|-@>n@UO= z@5i4;cki!iEj)fe>+*4_b-knMti+KV2jT}|gCZ7$vod5N3UZYW6H+$J_S62~;^pq_Iv zmn45Mg)+sAwL7ML^~M<dxvZwBi|Yd{?6PJWTMsVL2A zF_e*`jpd+Cm%EZSqjqCe;&=<_2)A{~*GedpTdX#as>@rFj*{j}oCX%$MrTwvQpQypL}4_vn%!4;>rcFSwtCQ!_IUT>5pS-e2PvB@Or)tpym@)^pey-_ z;^dbxv<_0IQ7dbbj;gI&cvI_p5|6^5=I}7^87k_Du9pW}l0TF|nd)x`SyJEr^2o;) zo34LwN-CShdT^M7RZ>f8Cp}Alp!%Znf#eVQq1`4d5HO*AeiQj&e$92aDJ5}plh~A& z_^GK!}tc?`KM_~FAj?I)a| zXKkuVJ&ZXIdeQUxrn=}%t!)27otP|cx z?)?hxBc{(cb)_=KaShI*Ph&UrB_G8$koe)G@?jTUroq_&79(=j2S0qc4Lbz0Ii;Fk z!7P-PZcJF4tu8%SRrwd;-b|^Rv(gUkUGT$4bc#0PKpNaHa->@1z9{j-Rg@{JlEe>o zRTplf%W1PK`6GFh$*!h4FXG|YvuNYC6-1-fzl6Kfk-D~NOJ%IwyqA!9Gm&ndlDxUI zZ|+%mak7QXT;~F&P^^x@8P^Q>=)iigo5niEtjx9~q+5Jw<&a;K@hvIIW5rbikC)cU zhm3BTTe4DbzK=5E+LDvF8Aw|wg)APEo-GB5qrTKvSyyZ+O8!U#WvZvFGGD_=VE0#% zYjdyMQni%pstIRN(zZ~aupqE(?GkUM}9n5TWz6J1@Eg5-~OQAQRj*l(Z(@TD)aiK|kU z%9yzFFQZG$K3&D?@~E*jX?Fx?=3p01Toq69=#nP*;bRVP3P!&MulOjkoMW<2e4S19 zm5$`i@$Jf##G|;n5@atbU(@k%a^zr|8862 zQT-i>FU+8fzqR<|Z{R1!Crd$L)a{4;cAJ0hFB@zniUo!v7bPFJn{H^bHDS?p_ zIwfh^swLXjG)2Lji&rs2n7!ex9yn%+7tpEK(6T7PrsQ#l$rB&h`;y0@ zA(wd5&09N?hyNz{xn}ESYgh93s2{yHf}b%O0H&Dx7L8Ts>$Hno5BcB>p9o*$F==P2 z+m?_x21%CunFMc3NnR&%bX!{D%0(IRZOcNi`s=tiy*@JM;v8V2s}^0lzWleSzC3WM&kO3CwY?$r zjt{Bkw}R8QU8qMF)%LbjGkqAG#bV(GuSCiHl%+pFnegrh;5~`!v2fw&_P!*J*HDI| z9f=_Rn|CB7e=X&Y_>_f@Ydj-yoPg=P5xj?<{5GZ_ot+&dS+nX5mH9UAE9M>64oC84 z3x5aI&g||hD~If^Z33sL%91zV(e7|1j-zNbgfnei`7rAjQDrCD^RP|0C5hK@ z02cl#roVT(k~jUmvnugxx+qig>k>Dka;InEI-SAk92S>uhq~uGBQx>IwyJ#xgXoW@ zU`)_~Kdl)a~DDkec z)T2Z6#4pqxysIjCywxaykDixy)g^B}jM?Q$9CjY;&b6m0`E{o8Es00%X-oXR`sAPL zqY02>!FQvSj-FJ*vxEbFv3a$)Yan^EpxX_Yr#Hf55~l-8@E5JwcPAzPND5`du{)!j zKSv+_+n-|1Zu)R{7M$oqmHM-=Px6q_#_VoK>Y-0u@X=Q+yRD1P^wsXNv_sCDu#0jY z96e+8o1E{iNjsDC-JZnpV@e4$3X^O0&*9eOe77&v%q?!W)n#UA?Cx0l166{*b2;rw z{?Qc5l+!^lpI%X=B5Q`Z(^sv&x;Hu5K~~KwtZH=?4kcxXH&aYCE#2Zuallv1OV?^v z@@Dp^<|J;iS1m~Vk#UsKjNteh3*Ss5K|KtAG}OOxv|5&qA_GbUGr-tP{RNhF8C_3Z z(pNbeZ|F2OEuN~O_*xRj0?7Rfyu3f*X+C@(RP9PNv%6I7SvXmd+kwRCgZaP2C^FqM z5tF>RVkeRkH=}MMC2`EkCHRX*(FCP|W#>d2WyCR&4e!ct{U!c7pgDRIoL^(g<~ekt zU^(e(CyvC;bP-7AN3X_4CrVQPx?|A(4 zzkhD+H8CaWlQq@LYKVt9CXuNR48ZZ7r$HTbNAD zGH*{y@@CT5)0X&2A7!efBXRSM+nyTd)o=~E(3?v!Q$$u< zQAv}`%?z>6x6JW41^%jt??~Q^=6zEVzeRoQZ?OMjPMhzewzD>GYpd+vgzKsjWVCMD zACr1!W(m$>F?)pV!EWrTGW5}`{VB^1T>}1YGjZKlHdsQIRz2mTgMyTRKg zGV-O7xt{jpJ@ngnTW@tCHlE$TWt-{yyVCr@I?Cj>Cvo$pcz<8w6DGES#J9Mri+ZBD z?LbWOPk1P!o&!mh`8&L=OrgY5Vp4S=E%7H>D*Jcb?YQJmB~T`}`M~YWf~2vL*n#<& zY0UwOo>jZqpZpO9s98!LC|fkSBk!)naab_}ySZlVbinRN^@l&gZxfx$!i>zZ34=B- zYDzDr=MJ0 zspfZwXJ2uUGRt_=@duMOu9{t>c#8|1{8~MTLEQyEd}>PbSylUcM3+O6xkq$az)^IR z14c*DIg`*@WOZW{TS;0)cv<2Ytlrg|RlIIX$`j1I*1Od9Wq< zC|G>`jc6-vNk>sx{b%m<2d6$jzbo-5<2{L+JK4d0h^s&Q2mF1ZCu=C7O|_VwRQ{1I zmugArVoOZr|B=lawKVu?`0rBuhyRVdK>rVC83>j*)3h2Tkl|$yWzx?=FdQAxL_N`v zuH_~FLFMOK(vtjB1(eAj?v3;YcK(lfOQxhUTH^c|*Hjc7^)O3+{FJJJk2Zm7 z18MJhD5J7NBv@l<1|h#@Ah%VihN~*^&+Mu?RF}L-#vxC2$h;wGw5 zT@v9*sc*tMoCCD{Rybrq)$5$WupJKRe1ss@L*WLo`tAVFI(I(_P^RRWeDgE5;Yx|bO=||_t zzkawH4NgR{xUlD%_@D5*Ag}GGEPH~fSv?ESs}k&@%kS_&@<^8lKAKaGSbb^w{>TUP z<&mWA4`sx0BqeeD3HtxVdgVw)(hUb?GRvyOJMX`v?yf5b=3}QRdQvMuuPQ|vnEBsmq}fP4T9Q1@AvoZJ*EOVPdh}>b>d{{T1z#~edeoDAgf}D}HJajNjWdh# zqb-S>RrOI{;(E$czwxg)ukcJBBxMZm*Kj|bb=2x{EYaP6MPtm;{^-DVrkdb~pXr2t zjwL4hnAxbGS%}yBnoUW35w4X!yqlZHv5e#~xU=AgpN(nz9C=?vG5`O(7bL!@q^%r@ z;~=32uhA{(80j&8&t_3ZPL5TnwwX1_ZgD674>$HC{cIU!GH#La@A;D5Ol4x*5;y5R z){*#TY7*&BNu2I9A_}Y9o^5EmfnKHl3>z-y{xXSQA^RC#>iq7{Fh!V}CzG-UY#z8j z!#7U%4?<6qX~~;Sg~^P>&E~-5cu>jAtfXz z1-}00JaAWfpk0rjBk*Mu7+ig5(vLihXVX{f5?`vh-sb??OfuKp%bl3rye_l79q1aS6Vs z@f0MhKY2>yX-MYpIbBaZYw2I0^>dbfII=6F^@23GaECTNgL-05?l+%OI?06cIxtqI8<2Z>1^WZsw z)Bi=&IY{R2i+HSnx;e~pylByR)g53Vk?gC%VC1vYx+?we5KUDeQBu`^$KRZqlU6M% zzN>m9e3kqUh%czze}J4FQ)Mc?s~Qjs{4k7%Q?i~f5scn>I19nTzJS6dJf{-B9Jy?P z9<~o#VSXvE)vD6`<0XyPROy!^myUfrt;j;w+b&S) zUm^CkDv&s;sw5oM`W49Ex=8h?*i*^>gm^*aNYqprVu9|AN3A%Y&xQ3rYQ_0EgV$8| zKe4^kfEvrf=k(S0s1^3}dh9;hmio7Lbu}GG*39Q=j3b+m_8^%5ThC~`4+;H+=3;uD z#xe{}#2~mqS>p*vUco>$|1aX#m%@pRq+dvCvpghsM{cN^0t9pS!nnpukWBxUw>3^- zaD6AluQ*Y|Kez!Ulq#r0a0C2k;d>bUYc$=mXis_XVf5pvxAor0C&x~b8gpyDMmdSU z{`Ve6r%U{d(UWNiR?Am(^G@b~bMtGoe*RcKe%ai2b%`3wtqaF$ar`aBV~zM{&RbMG zHWmNO!mQElS-S1ehZlonH7!bN94~mM#V@NoqKg?wR@I9}EicWp<66I9=^LCvX4PfS z*ZO5k-wE-GSHnM;!A%qhGUwGHctEbkn~+?;qwy9b*Y`9|Jk!5X=gXT4^v^8}Ui7s= zUmDzGGBgMbqPxqB-BACrgw(&00zm^FOG2=KULu(A3`7*rMMFb3=^5g&aS+@fHTj|V z?1eXO(sl)l&T7028TlI;x}mOdeBu6~_?*kB$mzVMJxE?#Rn@4v8`fyvxA=y}yO7M^ zjTdOVr@9}CN7M4-Nxn$A|5tr8dOWML=f^J{yWwT6SAt~rt(uQ?FL2`qP#vRCW21D2VzQ&7?TtBaI z7n19nimR4>iS#QoMo)Q=%wYaEi2&Y!;1$#~?n83@z!CJ@mVQ&~cP)LB(H`&$ub>ke zJV}C8aP6-&9)slieT}Cex&F%o3#s*K2|HxAlAp|>zzs6Q&KP~tfnXI} zGo|q&B-hVt+=b-&M>SrB|PzuYN=|rpG@uw*W2Xecrn$!~0W?>Q2YB)6_)@hE?`* zQRBpOb4TNN13etSv@$QP%alcK?`wPj$?UJ{hxlm{T)(Sv^2hYA{({CckWByUu>ikv z^t9E!t3Ry`9LoS37$fmHbHAr)*P@Fm3wl~r6-F>0-in_vkAHIPG)2pzxk}Fmrw7U( z!5W|zI%`R=lsOWz6gD-9R_;0BL`M57AH zD=2HcZt3gnHatt;G^}aqUxP9=tQF{=TLZk(&_o-O1@swxwKqC}L9_;V#n<{>NUm>M z+yl-VFs1beTp#s+Mz{EB;<-UTG_21Tbnd;{TMNL#KgH0N*L2`Xp;~pfh z;7*MqYrJRa@6&kS((eZK&lr7% zcwWKFp}{jT%V41Kq^199ji(@41N?->GmzZ>?`ym=ZW*LCk&^~jeoy0hOFye|2a;8A z<*zhegyaDgG+qw%qxH^}%QWFaa)Xk_YmmHxM>Jly^s5?gSo(2|H-&y>$oDkiL-Go4 z(0Ch?2h`H|l+?fCjK;f=T)(67J|y#h#oL5qz4Ocfk{k4hm@)cn0)iXdsqrKv(|?s< z($7F}{Y@GlhvfPxjprdN%;55OG*N)$23d`lAesIZ7iqi<$@LwLQ&%wk%W4`Ysr7^L z|EjAA50V@B8mGSG71TA}f@J!azo2m+lIu4$-ht%$?$B*Okh&?$fcl(p>I!a<)p#G0 zRgg)m)M$M6C6^~c{tQXRzdF!(Cj6T`XR?yd6g2MyN3_m6gCh^4ar_~N(RgBdPII;3 z#YyE%UE01@)VwEg^BUz$L*iza{Y+Ehua!|on}gkU*5U!ZZaW1aB&c!2-W z=-Hw)_()qDlq`dS#$8Aj(B%YE1F8_b0-eFL_!*Ah!8^oY7oYPrZHI*?z1ckLTlStx z&Bp53^xWBwoZ!N)Ba+E)2KT^`X75|8<@hMBcuJNvgdm6XeIYRLa&6tx5+j(w8j!+;( z3?O(wR3Y%&NpQTU+}XIyPR@zPrX^Hu4qbAy;~yK2$FxC8`2_wmz_EB*gBj^1j>A+? znx5BmR;7|yrRPvQ5C7?db-$L;qKz{s0!j+bXU>h!R+GtiVt7VLgT5*e_(lL`HHZrs;LW#Bq0EAt zVG=U{&Z?b7W~gB?38tUGZ%&Z&8DsJ3GgB6a7ZJqW2ySl1;&dw)k1J;^KIf{eMY||d zb<_qPMndB?<&VW@pSKua-$RZq?pS)d8H@X>5BIl|8FLfMhHmc2NPJda<0P5>EJx!d zmA^1PXHm_ftD0_FxTo>9#6R9r&V@+KD;LINl{>6Vf4mzS-IvY9QHqs&o-%g*#goPYor$W8uEWdlpW5(5IJb zqMj}Rz>^l<*LWttuZ*s|IfRozE+Ed~35`1{^9g-TvG&X%KV()@4(Q-z45!H((LMyn zDRqQTS$I+76eia%hxl(>(WPq|&qGcQ4XIyzB0h7jg90;7*R>LkWPS4eO-Os1#&$5# zzYQ0d2Q1-PE*inYA=-wJ_b*c;C_|J!IrA7vg;U7tV;!t|UFeJqX}0&Hhw; z`m|{&l}g2L!|rY|6~AtJm2`%tJ>O7`RDAukj7nV`-*w(SZ>z?|@#~=5y*NI9_^vkt zt&iUIrb=Ccay}>yQQ5g9eiQz%ibn!3F)xYVc-{{OyHmd&$A7=}QtH=d?0fJ0nX|^O F{C~^ZQZ)bo diff --git a/roms/SLOF b/roms/SLOF index dd0dcaa1c1..a6906b024c 160000 --- a/roms/SLOF +++ b/roms/SLOF @@ -1 +1 @@ -Subproject commit dd0dcaa1c1085c159ddab709c7f274b3917be8bd +Subproject commit a6906b024c6cca5a86496f51eb4bfee3a0c36148 From 6a23f8190fe953546ce50142d037588fb972f8ce Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 16 Nov 2021 08:28:29 +0100 Subject: [PATCH 002/421] meson: fix botched compile check conversions Fix a bunch of incorrect conversions from configure to Meson, which result in different outcomes with --extra-cflags=-Werror. pthread_setname_np needs "#define _GNU_SOURCE" on Linux (which I am using also for the non-Linux check, so that it correctly fails with an error about having too few parameters). Fix struct checks to use has_type instead of has_symbol, and "#define _GNU_SOURCE" too in the case of struct mmsghdr. Remove an apostrophe that ended up at the end of a #include line. Reported-by: Peter Maydell Signed-off-by: Paolo Bonzini --- meson.build | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/meson.build b/meson.build index 2ece4fe088..93a5e50a16 100644 --- a/meson.build +++ b/meson.build @@ -1547,8 +1547,6 @@ config_host_data.set('CONFIG_INOTIFY', cc.has_header_symbol('sys/inotify.h', 'inotify_init')) config_host_data.set('CONFIG_INOTIFY1', cc.has_header_symbol('sys/inotify.h', 'inotify_init1')) -config_host_data.set('CONFIG_IOVEC', - cc.has_header_symbol('sys/uio.h', 'struct iovec')) config_host_data.set('CONFIG_MACHINE_BSWAP_H', cc.has_header_symbol('machine/bswap.h', 'bswap32', prefix: '''#include @@ -1561,8 +1559,6 @@ config_host_data.set('CONFIG_SYSMACROS', cc.has_header_symbol('sys/sysmacros.h', 'makedev')) config_host_data.set('HAVE_OPTRESET', cc.has_header_symbol('getopt.h', 'optreset')) -config_host_data.set('HAVE_UTMPX', - cc.has_header_symbol('utmpx.h', 'struct utmpx')) config_host_data.set('HAVE_IPPROTO_MPTCP', cc.has_header_symbol('netinet/in.h', 'IPPROTO_MPTCP')) @@ -1574,6 +1570,14 @@ config_host_data.set('HAVE_STRUCT_STAT_ST_ATIM', cc.has_member('struct stat', 'st_atim', prefix: '#include ')) +# has_type +config_host_data.set('CONFIG_IOVEC', + cc.has_type('struct iovec', + prefix: '#include ')) +config_host_data.set('HAVE_UTMPX', + cc.has_type('struct utmpx', + prefix: '#include ')) + config_host_data.set('CONFIG_EVENTFD', cc.links(''' #include int main(void) { return eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC); }''')) @@ -1615,7 +1619,7 @@ config_host_data.set('CONFIG_POSIX_MADVISE', cc.links(gnu_source_prefix + ''' #include int main(void) { return posix_madvise(NULL, 0, POSIX_MADV_DONTNEED); }''')) -config_host_data.set('CONFIG_PTHREAD_SETNAME_NP_W_TID', cc.links(''' +config_host_data.set('CONFIG_PTHREAD_SETNAME_NP_W_TID', cc.links(gnu_source_prefix + ''' #include static void *f(void *p) { return NULL; } @@ -1626,7 +1630,7 @@ config_host_data.set('CONFIG_PTHREAD_SETNAME_NP_W_TID', cc.links(''' pthread_setname_np(thread, "QEMU"); return 0; }''', dependencies: threads)) -config_host_data.set('CONFIG_PTHREAD_SETNAME_NP_WO_TID', cc.links(''' +config_host_data.set('CONFIG_PTHREAD_SETNAME_NP_WO_TID', cc.links(gnu_source_prefix + ''' #include static void *f(void *p) { pthread_setname_np("QEMU"); return NULL; } @@ -1662,8 +1666,10 @@ config_host_data.set('HAVE_MLOCKALL', cc.links(gnu_source_prefix + ''' have_l2tpv3 = false if not get_option('l2tpv3').disabled() and have_system - have_l2tpv3 = (cc.has_header_symbol('sys/socket.h', 'struct mmsghdr') - and cc.has_header('linux/ip.h')) + have_l2tpv3 = cc.has_type('struct mmsghdr', + prefix: gnu_source_prefix + ''' + #include + #include ''') endif config_host_data.set('CONFIG_L2TPV3', have_l2tpv3) @@ -1689,7 +1695,7 @@ config_host_data.set('CONFIG_NETMAP', have_netmap) # xfs headers will not try to redefine structs from linux headers # if this macro is set. config_host_data.set('HAVE_FSXATTR', cc.links(''' - #include ' + #include struct fsxattr foo; int main(void) { return 0; From 14554b3dccae18ddc58d39654443c8e4551252c9 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Tue, 16 Nov 2021 16:08:37 +0100 Subject: [PATCH 003/421] pmu: fix pmu vmstate subsection list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The subsection is not closed by a NULL marker so this can trigger a segfault when the pmu vmstate is saved. This can be easily shown with: $ ./qemu-system-ppc64 -dump-vmstate vmstate.json Segmentation fault (core dumped) Fixes: d811d61fbc6c ("mac_newworld: add PMU device") Cc: mark.cave-ayland@ilande.co.uk Signed-off-by: Laurent Vivier Reviewed-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Signed-off-by: Cédric Le Goater --- hw/misc/macio/pmu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 4ad4f50e08..eb39c64694 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -718,6 +718,7 @@ static const VMStateDescription vmstate_pmu = { }, .subsections = (const VMStateDescription * []) { &vmstate_pmu_adb, + NULL } }; From a443d55c3f7cafa3d5dfb7fe2b5c3cd9d671b61d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 18:33:53 +0100 Subject: [PATCH 004/421] tests/tcg/ppc64le: Fix compile flags for byte_reverse MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With a host compiler new enough to recognize power10 insns, CROSS_CC_HAS_POWER10 is true, but we do not supply the -cpu option to the compiler, resulting in /tmp/ccAVdYJd.s: Assembler messages: /tmp/ccAVdYJd.s:49: Error: unrecognized opcode: `brh' /tmp/ccAVdYJd.s:78: Error: unrecognized opcode: `brw' /tmp/ccAVdYJd.s:107: Error: unrecognized opcode: `brd' make[2]: *** [byte_reverse] Error 1 Signed-off-by: Richard Henderson Signed-off-by: Cédric Le Goater --- tests/tcg/ppc64le/Makefile.target | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target index 5e65b1590d..ba2fde5ff1 100644 --- a/tests/tcg/ppc64le/Makefile.target +++ b/tests/tcg/ppc64le/Makefile.target @@ -9,18 +9,12 @@ PPC64LE_TESTS=bcdsub endif bcdsub: CFLAGS += -mpower8-vector -PPC64LE_TESTS += byte_reverse ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),) +PPC64LE_TESTS += byte_reverse +endif +byte_reverse: CFLAGS += -mcpu=power10 run-byte_reverse: QEMU_OPTS+=-cpu POWER10 run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10 -else -byte_reverse: - $(call skip-test, "BUILD of $@", "missing compiler support") -run-byte_reverse: - $(call skip-test, "RUN of byte_reverse", "not built") -run-plugin-byte_reverse-with-%: - $(call skip-test, "RUN of byte_reverse ($*)", "not built") -endif PPC64LE_TESTS += signal_save_restore_xer From 0cc4965049d9792ffede8fc371b58193d6ecbb02 Mon Sep 17 00:00:00 2001 From: nia Date: Wed, 13 Oct 2021 13:54:17 +0000 Subject: [PATCH 005/421] nvmm: Fix support for stable version NVMM user version 1 is the version being shipped with netbsd-9, which is the most recent stable branch of NetBSD. This makes it possible to use the NVMM accelerator on the most recent NetBSD release, 9.2, which lacks nvmm_cpu_stop. (CC'ing maintainers) Signed-off-by: Nia Alarie Reviewed-by: Kamil Rytarowski Message-Id: Signed-off-by: Paolo Bonzini --- meson.build | 4 +--- target/i386/nvmm/nvmm-all.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/meson.build b/meson.build index 93a5e50a16..582f356209 100644 --- a/meson.build +++ b/meson.build @@ -323,9 +323,7 @@ if not get_option('hax').disabled() endif endif if targetos == 'netbsd' - if cc.has_header_symbol('nvmm.h', 'nvmm_cpu_stop', required: get_option('nvmm')) - nvmm = cc.find_library('nvmm', required: get_option('nvmm')) - endif + nvmm = cc.find_library('nvmm', required: get_option('nvmm')) if nvmm.found() accelerators += 'CONFIG_NVMM' endif diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 14c996f968..9af261eea3 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -750,7 +750,11 @@ nvmm_vcpu_loop(CPUState *cpu) nvmm_vcpu_pre_run(cpu); if (qatomic_read(&cpu->exit_request)) { +#if NVMM_USER_VERSION >= 2 nvmm_vcpu_stop(vcpu); +#else + qemu_cpu_kick_self(); +#endif } /* Read exit_request before the kernel reads the immediate exit flag */ @@ -767,6 +771,7 @@ nvmm_vcpu_loop(CPUState *cpu) switch (exit->reason) { case NVMM_VCPU_EXIT_NONE: break; +#if NVMM_USER_VERSION >= 2 case NVMM_VCPU_EXIT_STOPPED: /* * The kernel cleared the immediate exit flag; cpu->exit_request @@ -775,6 +780,7 @@ nvmm_vcpu_loop(CPUState *cpu) smp_wmb(); qcpu->stop = true; break; +#endif case NVMM_VCPU_EXIT_MEMORY: ret = nvmm_handle_mem(mach, vcpu); break; @@ -888,8 +894,12 @@ nvmm_ipi_signal(int sigcpu) { if (current_cpu) { struct qemu_vcpu *qcpu = get_qemu_vcpu(current_cpu); +#if NVMM_USER_VERSION >= 2 struct nvmm_vcpu *vcpu = &qcpu->vcpu; nvmm_vcpu_stop(vcpu); +#else + qcpu->stop = true; +#endif } } From 3f26c9757726918015d351fafc436b2888689985 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 18 Nov 2021 10:03:26 +0000 Subject: [PATCH 006/421] esp: ensure that async_len is reset to 0 during esp_hard_reset() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If a reset command is sent after data has been transferred into the SCSI buffer ensure that async_len is reset to 0. Otherwise a subsequent TI command assumes the SCSI buffer contains data to be transferred to the device causing it to dereference the stale async_buf pointer. Signed-off-by: Mark Cave-Ayland Fixes: https://gitlab.com/qemu-project/qemu/-/issues/724 Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211118100327.29061-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Paolo Bonzini --- hw/scsi/esp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 84f935b549..58d0edbd56 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -894,6 +894,7 @@ void esp_hard_reset(ESPState *s) memset(s->wregs, 0, ESP_REGS); s->tchi_written = 0; s->ti_size = 0; + s->async_len = 0; fifo8_reset(&s->fifo); fifo8_reset(&s->cmdfifo); s->dma = 0; From 283191640c875e0b3e79c75ba2c6bc6b96588666 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 18 Nov 2021 10:03:27 +0000 Subject: [PATCH 007/421] qtest/am53c974-test: add test for reset before transfer Based upon the qtest reproducer posted to Gitlab issue #724 at https://gitlab.com/qemu-project/qemu/-/issues/724. Signed-off-by: Mark Cave-Ayland Acked-by: Thomas Huth Message-Id: <20211118100327.29061-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Paolo Bonzini --- tests/qtest/am53c974-test.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tests/qtest/am53c974-test.c b/tests/qtest/am53c974-test.c index 9b1e4211bd..d214a912b3 100644 --- a/tests/qtest/am53c974-test.c +++ b/tests/qtest/am53c974-test.c @@ -223,6 +223,34 @@ static void test_inflight_cancel_ok(void) qtest_quit(s); } +static void test_reset_before_transfer_ok(void) +{ + QTestState *s = qtest_init( + "-device am53c974,id=scsi " + "-device scsi-hd,drive=disk0 -drive " + "id=disk0,if=none,file=null-co://,format=raw -nodefaults"); + + qtest_outl(s, 0xcf8, 0x80001010); + qtest_outl(s, 0xcfc, 0xc000); + qtest_outl(s, 0xcf8, 0x80001004); + qtest_outw(s, 0xcfc, 0x01); + qtest_outl(s, 0xc007, 0x2500); + qtest_outl(s, 0xc00a, 0x410000); + qtest_outl(s, 0xc00a, 0x410000); + qtest_outw(s, 0xc00b, 0x0200); + qtest_outw(s, 0xc040, 0x03); + qtest_outw(s, 0xc009, 0x00); + qtest_outw(s, 0xc00b, 0x00); + qtest_outw(s, 0xc009, 0x00); + qtest_outw(s, 0xc00b, 0x00); + qtest_outw(s, 0xc009, 0x00); + qtest_outw(s, 0xc003, 0x1000); + qtest_outw(s, 0xc00b, 0x1000); + qtest_outl(s, 0xc00b, 0x9000); + qtest_outw(s, 0xc00b, 0x1000); + qtest_quit(s); +} + int main(int argc, char **argv) { const char *arch = qtest_get_arch(); @@ -248,6 +276,8 @@ int main(int argc, char **argv) test_cancelled_request_ok); qtest_add_func("am53c974/test_inflight_cancel_ok", test_inflight_cancel_ok); + qtest_add_func("am53c974/test_reset_before_transfer_ok", + test_reset_before_transfer_ok); } return g_test_run(); From 5135fe71101db08cf65090963247f9b1b8138b73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 18 Nov 2021 15:34:01 +0100 Subject: [PATCH 008/421] docs: Spell QEMU all caps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace Qemu -> QEMU. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Darren Kenny Reviewed-by: Markus Armbruster Message-Id: <20211118143401.4101497-1-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- docs/devel/modules.rst | 2 +- docs/devel/multi-thread-tcg.rst | 2 +- docs/devel/style.rst | 2 +- docs/devel/ui.rst | 4 ++-- docs/interop/nbd.txt | 6 +++--- docs/interop/qcow2.txt | 8 ++++---- docs/multiseat.txt | 2 +- docs/system/device-url-syntax.rst.inc | 2 +- docs/system/i386/sgx.rst | 26 +++++++++++++------------- docs/u2f.txt | 2 +- 10 files changed, 28 insertions(+), 28 deletions(-) diff --git a/docs/devel/modules.rst b/docs/devel/modules.rst index 066f347b89..8e999c4fa4 100644 --- a/docs/devel/modules.rst +++ b/docs/devel/modules.rst @@ -1,5 +1,5 @@ ============ -Qemu modules +QEMU modules ============ .. kernel-doc:: include/qemu/module.h diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index 5b446ee08b..c9541a7b20 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -228,7 +228,7 @@ Emulated hardware state Currently thanks to KVM work any access to IO memory is automatically protected by the global iothread mutex, also known as the BQL (Big -Qemu Lock). Any IO region that doesn't use global mutex is expected to +QEMU Lock). Any IO region that doesn't use global mutex is expected to do its own locking. However IO memory isn't the only way emulated hardware state can be diff --git a/docs/devel/style.rst b/docs/devel/style.rst index 260e3263fa..e00af62e76 100644 --- a/docs/devel/style.rst +++ b/docs/devel/style.rst @@ -686,7 +686,7 @@ Rationale: hex numbers are hard to read in logs when there is no 0x prefix, especially when (occasionally) the representation doesn't contain any letters and especially in one line with other decimal numbers. Number groups are allowed to not use '0x' because for some things notations like %x.%x.%x are used not -only in Qemu. Also dumping raw data bytes with '0x' is less readable. +only in QEMU. Also dumping raw data bytes with '0x' is less readable. '#' printf flag --------------- diff --git a/docs/devel/ui.rst b/docs/devel/ui.rst index 06c7d622ce..17fb667dec 100644 --- a/docs/devel/ui.rst +++ b/docs/devel/ui.rst @@ -1,8 +1,8 @@ ================= -Qemu UI subsystem +QEMU UI subsystem ================= -Qemu Clipboard +QEMU Clipboard -------------- .. kernel-doc:: include/ui/clipboard.h diff --git a/docs/interop/nbd.txt b/docs/interop/nbd.txt index 10ce098a29..bdb0f2a41a 100644 --- a/docs/interop/nbd.txt +++ b/docs/interop/nbd.txt @@ -1,4 +1,4 @@ -Qemu supports the NBD protocol, and has an internal NBD client (see +QEMU supports the NBD protocol, and has an internal NBD client (see block/nbd.c), an internal NBD server (see blockdev-nbd.c), and an external NBD server tool (see qemu-nbd.c). The common code is placed in nbd/*. @@ -7,11 +7,11 @@ The NBD protocol is specified here: https://github.com/NetworkBlockDevice/nbd/blob/master/doc/proto.md The following paragraphs describe some specific properties of NBD -protocol realization in Qemu. +protocol realization in QEMU. = Metadata namespaces = -Qemu supports the "base:allocation" metadata context as defined in the +QEMU supports the "base:allocation" metadata context as defined in the NBD protocol specification, and also defines an additional metadata namespace "qemu". diff --git a/docs/interop/qcow2.txt b/docs/interop/qcow2.txt index 0463f761ef..f7dc304ff6 100644 --- a/docs/interop/qcow2.txt +++ b/docs/interop/qcow2.txt @@ -313,7 +313,7 @@ The fields of the bitmaps extension are: The number of bitmaps contained in the image. Must be greater than or equal to 1. - Note: Qemu currently only supports up to 65535 bitmaps per + Note: QEMU currently only supports up to 65535 bitmaps per image. 4 - 7: Reserved, must be zero. @@ -775,7 +775,7 @@ Structure of a bitmap directory entry: 2: extra_data_compatible This flags is meaningful when the extra data is unknown to the software (currently any extra data is - unknown to Qemu). + unknown to QEMU). If it is set, the bitmap may be used as expected, extra data must be left as is. If it is not set, the bitmap must not be used, but @@ -793,7 +793,7 @@ Structure of a bitmap directory entry: 17: granularity_bits Granularity bits. Valid values: 0 - 63. - Note: Qemu currently supports only values 9 - 31. + Note: QEMU currently supports only values 9 - 31. Granularity is calculated as granularity = 1 << granularity_bits @@ -804,7 +804,7 @@ Structure of a bitmap directory entry: 18 - 19: name_size Size of the bitmap name. Must be non-zero. - Note: Qemu currently doesn't support values greater than + Note: QEMU currently doesn't support values greater than 1023. 20 - 23: extra_data_size diff --git a/docs/multiseat.txt b/docs/multiseat.txt index 11850c96ff..2b297e979d 100644 --- a/docs/multiseat.txt +++ b/docs/multiseat.txt @@ -123,7 +123,7 @@ Background info is here: guest side with pci-bridge-seat ------------------------------- -Qemu version 2.4 and newer has a new pci-bridge-seat device which +QEMU version 2.4 and newer has a new pci-bridge-seat device which can be used instead of pci-bridge. Just swap the device name in the qemu command line above. The only difference between the two devices is the pci id. We can match the pci id instead of the device path diff --git a/docs/system/device-url-syntax.rst.inc b/docs/system/device-url-syntax.rst.inc index d15a021508..7dbc525fa8 100644 --- a/docs/system/device-url-syntax.rst.inc +++ b/docs/system/device-url-syntax.rst.inc @@ -15,7 +15,7 @@ These are specified using a special URL syntax. 'iqn.2008-11.org.linux-kvm[:]' but this can also be set from the command line or a configuration file. - Since version Qemu 2.4 it is possible to specify a iSCSI request + Since version QEMU 2.4 it is possible to specify a iSCSI request timeout to detect stalled requests and force a reestablishment of the session. The timeout is specified in seconds. The default is 0 which means no timeout. Libiscsi 1.15.0 or greater is required for this diff --git a/docs/system/i386/sgx.rst b/docs/system/i386/sgx.rst index 9aa161af1a..f8fade5ac2 100644 --- a/docs/system/i386/sgx.rst +++ b/docs/system/i386/sgx.rst @@ -20,13 +20,13 @@ report the same CPUID info to guest as on host for most of SGX CPUID. With reporting the same CPUID guest is able to use full capacity of SGX, and KVM doesn't need to emulate those info. -The guest's EPC base and size are determined by Qemu, and KVM needs Qemu to +The guest's EPC base and size are determined by QEMU, and KVM needs QEMU to notify such info to it before it can initialize SGX for guest. Virtual EPC ~~~~~~~~~~~ -By default, Qemu does not assign EPC to a VM, i.e. fully enabling SGX in a VM +By default, QEMU does not assign EPC to a VM, i.e. fully enabling SGX in a VM requires explicit allocation of EPC to the VM. Similar to other specialized memory types, e.g. hugetlbfs, EPC is exposed as a memory backend. @@ -35,12 +35,12 @@ prior to realizing the vCPUs themselves, which occurs long before generic devices are parsed and realized. This limitation means that EPC does not require -maxmem as EPC is not treated as {cold,hot}plugged memory. -Qemu does not artificially restrict the number of EPC sections exposed to a -guest, e.g. Qemu will happily allow you to create 64 1M EPC sections. Be aware +QEMU does not artificially restrict the number of EPC sections exposed to a +guest, e.g. QEMU will happily allow you to create 64 1M EPC sections. Be aware that some kernels may not recognize all EPC sections, e.g. the Linux SGX driver is hardwired to support only 8 EPC sections. -The following Qemu snippet creates two EPC sections, with 64M pre-allocated +The following QEMU snippet creates two EPC sections, with 64M pre-allocated to the VM and an additional 28M mapped but not allocated:: -object memory-backend-epc,id=mem1,size=64M,prealloc=on \ @@ -54,7 +54,7 @@ to physical EPC. Because physical EPC is protected via range registers, the size of the physical EPC must be a power of two (though software sees a subset of the full EPC, e.g. 92M or 128M) and the EPC must be naturally aligned. KVM SGX's virtual EPC is purely a software construct and only -requires the size and location to be page aligned. Qemu enforces the EPC +requires the size and location to be page aligned. QEMU enforces the EPC size is a multiple of 4k and will ensure the base of the EPC is 4k aligned. To simplify the implementation, EPC is always located above 4g in the guest physical address space. @@ -62,7 +62,7 @@ physical address space. Migration ~~~~~~~~~ -Qemu/KVM doesn't prevent live migrating SGX VMs, although from hardware's +QEMU/KVM doesn't prevent live migrating SGX VMs, although from hardware's perspective, SGX doesn't support live migration, since both EPC and the SGX key hierarchy are bound to the physical platform. However live migration can be supported in the sense if guest software stack can support recreating @@ -76,7 +76,7 @@ CPUID ~~~~~ Due to its myriad dependencies, SGX is currently not listed as supported -in any of Qemu's built-in CPU configuration. To expose SGX (and SGX Launch +in any of QEMU's built-in CPU configuration. To expose SGX (and SGX Launch Control) to a guest, you must either use ``-cpu host`` to pass-through the host CPU model, or explicitly enable SGX when using a built-in CPU model, e.g. via ``-cpu ,+sgx`` or ``-cpu ,+sgx,+sgxlc``. @@ -101,7 +101,7 @@ controlled via -cpu are prefixed with "sgx", e.g.:: sgx2 sgxlc -The following Qemu snippet passes through the host CPU but restricts access to +The following QEMU snippet passes through the host CPU but restricts access to the provision and EINIT token keys:: -cpu host,-sgx-provisionkey,-sgx-tokenkey @@ -112,11 +112,11 @@ in hardware cannot be forced on via '-cpu'. Virtualize SGX Launch Control ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Qemu SGX support for Launch Control (LC) is passive, in the sense that it -does not actively change the LC configuration. Qemu SGX provides the user +QEMU SGX support for Launch Control (LC) is passive, in the sense that it +does not actively change the LC configuration. QEMU SGX provides the user the ability to set/clear the CPUID flag (and by extension the associated IA32_FEATURE_CONTROL MSR bit in fw_cfg) and saves/restores the LE Hash MSRs -when getting/putting guest state, but Qemu does not add new controls to +when getting/putting guest state, but QEMU does not add new controls to directly modify the LC configuration. Similar to hardware behavior, locking the LC configuration to a non-Intel value is left to guest firmware. Unlike host bios setting for SGX launch control(LC), there is no special bios setting @@ -126,7 +126,7 @@ creating VM with SGX. Feature Control ~~~~~~~~~~~~~~~ -Qemu SGX updates the ``etc/msr_feature_control`` fw_cfg entry to set the SGX +QEMU SGX updates the ``etc/msr_feature_control`` fw_cfg entry to set the SGX (bit 18) and SGX LC (bit 17) flags based on their respective CPUID support, i.e. existing guest firmware will automatically set SGX and SGX LC accordingly, assuming said firmware supports fw_cfg.msr_feature_control. diff --git a/docs/u2f.txt b/docs/u2f.txt index 8f44994818..7f5813a0b7 100644 --- a/docs/u2f.txt +++ b/docs/u2f.txt @@ -21,7 +21,7 @@ The second factor is materialized by a device implementing the U2F protocol. In case of a USB U2F security key, it is a USB HID device that implements the U2F protocol. -In Qemu, the USB U2F key device offers a dedicated support of U2F, allowing +In QEMU, the USB U2F key device offers a dedicated support of U2F, allowing guest USB FIDO/U2F security keys operating in two possible modes: pass-through and emulated. From fbab8cc24ded54f371ab9db2c9998be23c158e62 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Wed, 17 Nov 2021 21:53:55 +0100 Subject: [PATCH 009/421] meson.build: Support ncurses on MacOS and OpenBSD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MacOS provides header files for curses 5.7 with support for wide characters, but requires _XOPEN_SOURCE_EXTENDED=1 to activate that. By default those old header files are used even if there is a newer Homebrew installation of ncurses 6.2 available. Change also the old macro definition of NCURSES_WIDECHAR and set it to 1 like it is done in newer versions of curses.h when _XOPEN_SOURCE_EXTENDED=1 is defined. OpenBSD has the same version of ncurses and needs the same fix. Suggested-by: Daniel P. Berrangé Signed-off-by: Stefan Weil Reviewed-by: Daniel P. Berrangé Tested-by: Brad Smith Message-Id: <20211117205355.1392292-1-sw@weilnetz.de> Signed-off-by: Paolo Bonzini --- meson.build | 5 ++++- ui/curses.c | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 582f356209..fbdd415376 100644 --- a/meson.build +++ b/meson.build @@ -679,6 +679,9 @@ iconv = not_found curses = not_found if have_system and not get_option('curses').disabled() curses_test = ''' + #if defined(__APPLE__) || defined(__OpenBSD__) + #define _XOPEN_SOURCE_EXTENDED 1 + #endif #include #include #include @@ -702,7 +705,7 @@ if have_system and not get_option('curses').disabled() endif endforeach msg = get_option('curses').enabled() ? 'curses library not found' : '' - curses_compile_args = ['-DNCURSES_WIDECHAR'] + curses_compile_args = ['-DNCURSES_WIDECHAR=1'] if curses.found() if cc.links(curses_test, args: curses_compile_args, dependencies: [curses]) curses = declare_dependency(compile_args: curses_compile_args, dependencies: [curses]) diff --git a/ui/curses.c b/ui/curses.c index e4f9588c3e..861d63244c 100644 --- a/ui/curses.c +++ b/ui/curses.c @@ -38,6 +38,10 @@ #include "ui/input.h" #include "sysemu/sysemu.h" +#if defined(__APPLE__) || defined(__OpenBSD__) +#define _XOPEN_SOURCE_EXTENDED 1 +#endif + /* KEY_EVENT is defined in wincon.h and in curses.h. Avoid redefinition. */ #undef KEY_EVENT #include From fdc6e168181d06391711171b7c409b34f2981ced Mon Sep 17 00:00:00 2001 From: Daniil Tatianin Date: Wed, 17 Nov 2021 17:23:49 +0300 Subject: [PATCH 010/421] chardev/wctable: don't free the instance in wctablet_chr_finalize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Object is supposed to be freed by invoking obj->free, and not obj->instance_finalize. This would lead to use-after-free followed by double free in object_unref/object_finalize. Signed-off-by: Daniil Tatianin Reviewed-by: Marc-André Lureau Message-Id: <20211117142349.836279-1-d-tatianin@yandex-team.ru> Signed-off-by: Paolo Bonzini --- chardev/wctablet.c | 1 - 1 file changed, 1 deletion(-) diff --git a/chardev/wctablet.c b/chardev/wctablet.c index 95e005f5a5..e8b292c43c 100644 --- a/chardev/wctablet.c +++ b/chardev/wctablet.c @@ -320,7 +320,6 @@ static void wctablet_chr_finalize(Object *obj) TabletChardev *tablet = WCTABLET_CHARDEV(obj); qemu_input_handler_unregister(tablet->hs); - g_free(tablet); } static void wctablet_chr_open(Chardev *chr, From c29cd47e82df0bc7385cdd49a158d838314daa9e Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 18 Nov 2021 18:18:34 +0000 Subject: [PATCH 011/421] escc: always set STATUS_TXEMPTY in R_STATUS on device reset The "Transmit Interrupts and Transmit Buffer Empty Bit" section of the ESCC datasheet states the following about the STATUS_TXEMPTY bit: "After a hardware reset (including a hardware reset by software), or a channel reset, this bit is set to 1". Update escc_reset() to set the STATUS_TXEMPTY bit in the R_STATUS register on device reset as described which fixes a regression whereby the Sun PROM checks this bit early on startup and gets stuck in an infinite loop if it is not set. Signed-off-by: Mark Cave-Ayland Message-Id: <20211118181835.18497-2-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell --- hw/char/escc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/char/escc.c b/hw/char/escc.c index 0fce4f6324..a7d9050c83 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -354,6 +354,17 @@ static void escc_reset(DeviceState *d) cs->rregs[j] = 0; cs->wregs[j] = 0; } + + /* + * ...but there is an exception. The "Transmit Interrupts and Transmit + * Buffer Empty Bit" section on page 50 of the ESCC datasheet says of + * the STATUS_TXEMPTY bit in R_STATUS: "After a hardware reset + * (including a hardware reset by software), or a channel reset, this + * bit is set to 1". The Sun PROM checks this bit early on startup and + * gets stuck in an infinite loop if it is not set. + */ + cs->rregs[R_STATUS] |= STATUS_TXEMPTY; + escc_reset_chn(cs); } } From 319e89cdc32096432b578152a47d0d156033b711 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 18 Nov 2021 18:18:35 +0000 Subject: [PATCH 012/421] escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ESCC datasheet states that SPEC_ALLSENT is always set in sync mode and set in async mode once all characters have cleared the transmitter. Since writes to SERIAL_DATA use a synchronous chardev API, the guest can never see the state when transmission is in progress so it is possible to set SPEC_ALLSENT in the R_SPEC register unconditionally. This fixes a hang when using the Sun PROM as it attempts to enumerate the onboard serial devices, and a similar hang in OpenBSD SPARC32 where in both cases the boot process will not proceed until SPEC_ALLSENT has been set after writing to W_TXCTRL1. Signed-off-by: Mark Cave-Ayland Message-Id: <20211118181835.18497-3-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/char/escc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/char/escc.c b/hw/char/escc.c index a7d9050c83..8755d8d34f 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -586,6 +586,20 @@ static void escc_mem_write(void *opaque, hwaddr addr, s->wregs[s->reg] = val; break; case W_TXCTRL1: + s->wregs[s->reg] = val; + /* + * The ESCC datasheet states that SPEC_ALLSENT is always set in + * sync mode, and set in async mode when all characters have + * cleared the transmitter. Since writes to SERIAL_DATA use the + * blocking qemu_chr_fe_write_all() function to write each + * character, the guest can never see the state when async data + * is in the process of being transmitted so we can set this bit + * unconditionally regardless of the state of the W_TXCTRL1 mode + * bits. + */ + s->rregs[R_SPEC] |= SPEC_ALLSENT; + escc_update_parameters(s); + break; case W_TXCTRL2: s->wregs[s->reg] = val; escc_update_parameters(s); From fd08ddb9cb050182c0f7c9d74b11038e9c479f4f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 14 Nov 2021 11:35:36 +0100 Subject: [PATCH 013/421] linux-user: Split out do_getdents, do_getdents64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Retain all 3 implementations of getdents for now. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211114103539.298686-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/syscall.c | 325 +++++++++++++++++++++++-------------------- 1 file changed, 172 insertions(+), 153 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 544f5b662f..a2f605dec4 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8137,6 +8137,176 @@ static int host_to_target_cpu_mask(const unsigned long *host_mask, return 0; } +#ifdef TARGET_NR_getdents +static int do_getdents(abi_long arg1, abi_long arg2, abi_long arg3) +{ + int ret; + +#ifdef EMULATE_GETDENTS_WITH_GETDENTS +# if TARGET_ABI_BITS == 32 && HOST_LONG_BITS == 64 + struct target_dirent *target_dirp; + struct linux_dirent *dirp; + abi_long count = arg3; + + dirp = g_try_malloc(count); + if (!dirp) { + return -TARGET_ENOMEM; + } + + ret = get_errno(sys_getdents(arg1, dirp, count)); + if (!is_error(ret)) { + struct linux_dirent *de; + struct target_dirent *tde; + int len = ret; + int reclen, treclen; + int count1, tnamelen; + + count1 = 0; + de = dirp; + target_dirp = lock_user(VERIFY_WRITE, arg2, count, 0); + if (!target_dirp) { + return -TARGET_EFAULT; + } + tde = target_dirp; + while (len > 0) { + reclen = de->d_reclen; + tnamelen = reclen - offsetof(struct linux_dirent, d_name); + assert(tnamelen >= 0); + treclen = tnamelen + offsetof(struct target_dirent, d_name); + assert(count1 + treclen <= count); + tde->d_reclen = tswap16(treclen); + tde->d_ino = tswapal(de->d_ino); + tde->d_off = tswapal(de->d_off); + memcpy(tde->d_name, de->d_name, tnamelen); + de = (struct linux_dirent *)((char *)de + reclen); + len -= reclen; + tde = (struct target_dirent *)((char *)tde + treclen); + count1 += treclen; + } + ret = count1; + unlock_user(target_dirp, arg2, ret); + } + g_free(dirp); +# else + struct linux_dirent *dirp; + abi_long count = arg3; + + dirp = lock_user(VERIFY_WRITE, arg2, count, 0); + if (!dirp) { + return -TARGET_EFAULT; + } + ret = get_errno(sys_getdents(arg1, dirp, count)); + if (!is_error(ret)) { + struct linux_dirent *de; + int len = ret; + int reclen; + de = dirp; + while (len > 0) { + reclen = de->d_reclen; + if (reclen > len) { + break; + } + de->d_reclen = tswap16(reclen); + tswapls(&de->d_ino); + tswapls(&de->d_off); + de = (struct linux_dirent *)((char *)de + reclen); + len -= reclen; + } + } + unlock_user(dirp, arg2, ret); +# endif +#else + /* Implement getdents in terms of getdents64 */ + struct linux_dirent64 *dirp; + abi_long count = arg3; + + dirp = lock_user(VERIFY_WRITE, arg2, count, 0); + if (!dirp) { + return -TARGET_EFAULT; + } + ret = get_errno(sys_getdents64(arg1, dirp, count)); + if (!is_error(ret)) { + /* + * Convert the dirent64 structs to target dirent. We do this + * in-place, since we can guarantee that a target_dirent is no + * larger than a dirent64; however this means we have to be + * careful to read everything before writing in the new format. + */ + struct linux_dirent64 *de; + struct target_dirent *tde; + int len = ret; + int tlen = 0; + + de = dirp; + tde = (struct target_dirent *)dirp; + while (len > 0) { + int namelen, treclen; + int reclen = de->d_reclen; + uint64_t ino = de->d_ino; + int64_t off = de->d_off; + uint8_t type = de->d_type; + + namelen = strlen(de->d_name); + treclen = offsetof(struct target_dirent, d_name) + namelen + 2; + treclen = QEMU_ALIGN_UP(treclen, sizeof(abi_long)); + + memmove(tde->d_name, de->d_name, namelen + 1); + tde->d_ino = tswapal(ino); + tde->d_off = tswapal(off); + tde->d_reclen = tswap16(treclen); + /* + * The target_dirent type is in what was formerly a padding + * byte at the end of the structure: + */ + *(((char *)tde) + treclen - 1) = type; + + de = (struct linux_dirent64 *)((char *)de + reclen); + tde = (struct target_dirent *)((char *)tde + treclen); + len -= reclen; + tlen += treclen; + } + ret = tlen; + } + unlock_user(dirp, arg2, ret); +#endif + return ret; +} +#endif /* TARGET_NR_getdents */ + +#if defined(TARGET_NR_getdents64) && defined(__NR_getdents64) +static int do_getdents64(abi_long arg1, abi_long arg2, abi_long arg3) +{ + struct linux_dirent64 *dirp; + abi_long count = arg3; + int ret; + + dirp = lock_user(VERIFY_WRITE, arg2, count, 0); + if (!dirp) { + return -TARGET_EFAULT; + } + ret = get_errno(sys_getdents64(arg1, dirp, count)); + if (!is_error(ret)) { + struct linux_dirent64 *de; + int len = ret; + int reclen; + de = dirp; + while (len > 0) { + reclen = de->d_reclen; + if (reclen > len) { + break; + } + de->d_reclen = tswap16(reclen); + tswap64s((uint64_t *)&de->d_ino); + tswap64s((uint64_t *)&de->d_off); + de = (struct linux_dirent64 *)((char *)de + reclen); + len -= reclen; + } + } + unlock_user(dirp, arg2, ret); + return ret; +} +#endif /* TARGET_NR_getdents64 */ + #if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root) _syscall2(int, pivot_root, const char *, new_root, const char *, put_old) #endif @@ -10227,162 +10397,11 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, #endif #ifdef TARGET_NR_getdents case TARGET_NR_getdents: -#ifdef EMULATE_GETDENTS_WITH_GETDENTS -#if TARGET_ABI_BITS == 32 && HOST_LONG_BITS == 64 - { - struct target_dirent *target_dirp; - struct linux_dirent *dirp; - abi_long count = arg3; - - dirp = g_try_malloc(count); - if (!dirp) { - return -TARGET_ENOMEM; - } - - ret = get_errno(sys_getdents(arg1, dirp, count)); - if (!is_error(ret)) { - struct linux_dirent *de; - struct target_dirent *tde; - int len = ret; - int reclen, treclen; - int count1, tnamelen; - - count1 = 0; - de = dirp; - if (!(target_dirp = lock_user(VERIFY_WRITE, arg2, count, 0))) - return -TARGET_EFAULT; - tde = target_dirp; - while (len > 0) { - reclen = de->d_reclen; - tnamelen = reclen - offsetof(struct linux_dirent, d_name); - assert(tnamelen >= 0); - treclen = tnamelen + offsetof(struct target_dirent, d_name); - assert(count1 + treclen <= count); - tde->d_reclen = tswap16(treclen); - tde->d_ino = tswapal(de->d_ino); - tde->d_off = tswapal(de->d_off); - memcpy(tde->d_name, de->d_name, tnamelen); - de = (struct linux_dirent *)((char *)de + reclen); - len -= reclen; - tde = (struct target_dirent *)((char *)tde + treclen); - count1 += treclen; - } - ret = count1; - unlock_user(target_dirp, arg2, ret); - } - g_free(dirp); - } -#else - { - struct linux_dirent *dirp; - abi_long count = arg3; - - if (!(dirp = lock_user(VERIFY_WRITE, arg2, count, 0))) - return -TARGET_EFAULT; - ret = get_errno(sys_getdents(arg1, dirp, count)); - if (!is_error(ret)) { - struct linux_dirent *de; - int len = ret; - int reclen; - de = dirp; - while (len > 0) { - reclen = de->d_reclen; - if (reclen > len) - break; - de->d_reclen = tswap16(reclen); - tswapls(&de->d_ino); - tswapls(&de->d_off); - de = (struct linux_dirent *)((char *)de + reclen); - len -= reclen; - } - } - unlock_user(dirp, arg2, ret); - } -#endif -#else - /* Implement getdents in terms of getdents64 */ - { - struct linux_dirent64 *dirp; - abi_long count = arg3; - - dirp = lock_user(VERIFY_WRITE, arg2, count, 0); - if (!dirp) { - return -TARGET_EFAULT; - } - ret = get_errno(sys_getdents64(arg1, dirp, count)); - if (!is_error(ret)) { - /* Convert the dirent64 structs to target dirent. We do this - * in-place, since we can guarantee that a target_dirent is no - * larger than a dirent64; however this means we have to be - * careful to read everything before writing in the new format. - */ - struct linux_dirent64 *de; - struct target_dirent *tde; - int len = ret; - int tlen = 0; - - de = dirp; - tde = (struct target_dirent *)dirp; - while (len > 0) { - int namelen, treclen; - int reclen = de->d_reclen; - uint64_t ino = de->d_ino; - int64_t off = de->d_off; - uint8_t type = de->d_type; - - namelen = strlen(de->d_name); - treclen = offsetof(struct target_dirent, d_name) - + namelen + 2; - treclen = QEMU_ALIGN_UP(treclen, sizeof(abi_long)); - - memmove(tde->d_name, de->d_name, namelen + 1); - tde->d_ino = tswapal(ino); - tde->d_off = tswapal(off); - tde->d_reclen = tswap16(treclen); - /* The target_dirent type is in what was formerly a padding - * byte at the end of the structure: - */ - *(((char *)tde) + treclen - 1) = type; - - de = (struct linux_dirent64 *)((char *)de + reclen); - tde = (struct target_dirent *)((char *)tde + treclen); - len -= reclen; - tlen += treclen; - } - ret = tlen; - } - unlock_user(dirp, arg2, ret); - } -#endif - return ret; + return do_getdents(arg1, arg2, arg3); #endif /* TARGET_NR_getdents */ #if defined(TARGET_NR_getdents64) && defined(__NR_getdents64) case TARGET_NR_getdents64: - { - struct linux_dirent64 *dirp; - abi_long count = arg3; - if (!(dirp = lock_user(VERIFY_WRITE, arg2, count, 0))) - return -TARGET_EFAULT; - ret = get_errno(sys_getdents64(arg1, dirp, count)); - if (!is_error(ret)) { - struct linux_dirent64 *de; - int len = ret; - int reclen; - de = dirp; - while (len > 0) { - reclen = de->d_reclen; - if (reclen > len) - break; - de->d_reclen = tswap16(reclen); - tswap64s((uint64_t *)&de->d_ino); - tswap64s((uint64_t *)&de->d_off); - de = (struct linux_dirent64 *)((char *)de + reclen); - len -= reclen; - } - } - unlock_user(dirp, arg2, ret); - } - return ret; + return do_getdents64(arg1, arg2, arg3); #endif /* TARGET_NR_getdents64 */ #if defined(TARGET_NR__newselect) case TARGET_NR__newselect: From 540a736f54a5dffb0851f2adf455f50869b409a1 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 14 Nov 2021 11:35:37 +0100 Subject: [PATCH 014/421] linux-user: Always use flexible arrays for dirent d_name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We currently use a flexible array member for target_dirent, but use incorrectly fixed length arrays for target_dirent64, linux_dirent and linux_dirent64. This requires that we adjust the definition of the VFAT READDIR ioctls which hard-code the 256 namelen size into the ioctl constant. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211114103539.298686-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/syscall.c | 6 ++++-- linux-user/syscall_defs.h | 6 +++--- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index a2f605dec4..499415ad81 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -197,8 +197,10 @@ //#define DEBUG_ERESTARTSYS //#include -#define VFAT_IOCTL_READDIR_BOTH _IOR('r', 1, struct linux_dirent [2]) -#define VFAT_IOCTL_READDIR_SHORT _IOR('r', 2, struct linux_dirent [2]) +#define VFAT_IOCTL_READDIR_BOTH \ + _IOC(_IOC_READ, 'r', 1, (sizeof(struct linux_dirent) + 256) * 2) +#define VFAT_IOCTL_READDIR_SHORT \ + _IOC(_IOC_READ, 'r', 2, (sizeof(struct linux_dirent) + 256) * 2) #undef _syscall0 #undef _syscall1 diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index a5ce487dcc..98b09ee6d6 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -441,7 +441,7 @@ struct target_dirent64 { int64_t d_off; unsigned short d_reclen; unsigned char d_type; - char d_name[256]; + char d_name[]; }; @@ -2714,7 +2714,7 @@ struct linux_dirent { long d_ino; unsigned long d_off; unsigned short d_reclen; - char d_name[256]; /* We must not include limits.h! */ + char d_name[]; }; struct linux_dirent64 { @@ -2722,7 +2722,7 @@ struct linux_dirent64 { int64_t d_off; unsigned short d_reclen; unsigned char d_type; - char d_name[256]; + char d_name[]; }; struct target_mq_attr { From 1962cb0029197bc0cd4bb0461171cda677e64966 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 14 Nov 2021 11:35:38 +0100 Subject: [PATCH 015/421] linux-user: Fix member types of target_dirent64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The host uint64_t (etc) does not have the correct alignment constraint as the guest: use abi_* types. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211114103539.298686-4-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/syscall_defs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 98b09ee6d6..41aaafbac1 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -437,9 +437,9 @@ struct target_dirent { }; struct target_dirent64 { - uint64_t d_ino; - int64_t d_off; - unsigned short d_reclen; + abi_ullong d_ino; + abi_llong d_off; + abi_ushort d_reclen; unsigned char d_type; char d_name[]; }; From aee14c77f42533f2480dfa8552f531efde6c19ee Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 14 Nov 2021 11:35:39 +0100 Subject: [PATCH 016/421] linux-user: Rewrite do_getdents, do_getdents64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Always allocate host storage; this ensures that the struct is sufficiently aligned for the host. Merge the three host implementations of getdents via a few ifdefs. Utilize the same method for do_getdents64. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/704 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211114103539.298686-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier --- linux-user/syscall.c | 259 ++++++++++++++++++++----------------------- 1 file changed, 121 insertions(+), 138 deletions(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 499415ad81..f1cfcc8104 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8140,172 +8140,155 @@ static int host_to_target_cpu_mask(const unsigned long *host_mask, } #ifdef TARGET_NR_getdents -static int do_getdents(abi_long arg1, abi_long arg2, abi_long arg3) +static int do_getdents(abi_long dirfd, abi_long arg2, abi_long count) { - int ret; + g_autofree void *hdirp = NULL; + void *tdirp; + int hlen, hoff, toff; + int hreclen, treclen; + off64_t prev_diroff = 0; -#ifdef EMULATE_GETDENTS_WITH_GETDENTS -# if TARGET_ABI_BITS == 32 && HOST_LONG_BITS == 64 - struct target_dirent *target_dirp; - struct linux_dirent *dirp; - abi_long count = arg3; - - dirp = g_try_malloc(count); - if (!dirp) { + hdirp = g_try_malloc(count); + if (!hdirp) { return -TARGET_ENOMEM; } - ret = get_errno(sys_getdents(arg1, dirp, count)); - if (!is_error(ret)) { - struct linux_dirent *de; - struct target_dirent *tde; - int len = ret; - int reclen, treclen; - int count1, tnamelen; +#ifdef EMULATE_GETDENTS_WITH_GETDENTS + hlen = sys_getdents(dirfd, hdirp, count); +#else + hlen = sys_getdents64(dirfd, hdirp, count); +#endif - count1 = 0; - de = dirp; - target_dirp = lock_user(VERIFY_WRITE, arg2, count, 0); - if (!target_dirp) { - return -TARGET_EFAULT; - } - tde = target_dirp; - while (len > 0) { - reclen = de->d_reclen; - tnamelen = reclen - offsetof(struct linux_dirent, d_name); - assert(tnamelen >= 0); - treclen = tnamelen + offsetof(struct target_dirent, d_name); - assert(count1 + treclen <= count); - tde->d_reclen = tswap16(treclen); - tde->d_ino = tswapal(de->d_ino); - tde->d_off = tswapal(de->d_off); - memcpy(tde->d_name, de->d_name, tnamelen); - de = (struct linux_dirent *)((char *)de + reclen); - len -= reclen; - tde = (struct target_dirent *)((char *)tde + treclen); - count1 += treclen; - } - ret = count1; - unlock_user(target_dirp, arg2, ret); + hlen = get_errno(hlen); + if (is_error(hlen)) { + return hlen; } - g_free(dirp); -# else - struct linux_dirent *dirp; - abi_long count = arg3; - dirp = lock_user(VERIFY_WRITE, arg2, count, 0); - if (!dirp) { + tdirp = lock_user(VERIFY_WRITE, arg2, count, 0); + if (!tdirp) { return -TARGET_EFAULT; } - ret = get_errno(sys_getdents(arg1, dirp, count)); - if (!is_error(ret)) { - struct linux_dirent *de; - int len = ret; - int reclen; - de = dirp; - while (len > 0) { - reclen = de->d_reclen; - if (reclen > len) { + + for (hoff = toff = 0; hoff < hlen; hoff += hreclen, toff += treclen) { +#ifdef EMULATE_GETDENTS_WITH_GETDENTS + struct linux_dirent *hde = hdirp + hoff; +#else + struct linux_dirent64 *hde = hdirp + hoff; +#endif + struct target_dirent *tde = tdirp + toff; + int namelen; + uint8_t type; + + namelen = strlen(hde->d_name); + hreclen = hde->d_reclen; + treclen = offsetof(struct target_dirent, d_name) + namelen + 2; + treclen = QEMU_ALIGN_UP(treclen, __alignof(struct target_dirent)); + + if (toff + treclen > count) { + /* + * If the host struct is smaller than the target struct, or + * requires less alignment and thus packs into less space, + * then the host can return more entries than we can pass + * on to the guest. + */ + if (toff == 0) { + toff = -TARGET_EINVAL; /* result buffer is too small */ break; } - de->d_reclen = tswap16(reclen); - tswapls(&de->d_ino); - tswapls(&de->d_off); - de = (struct linux_dirent *)((char *)de + reclen); - len -= reclen; - } - } - unlock_user(dirp, arg2, ret); -# endif -#else - /* Implement getdents in terms of getdents64 */ - struct linux_dirent64 *dirp; - abi_long count = arg3; - - dirp = lock_user(VERIFY_WRITE, arg2, count, 0); - if (!dirp) { - return -TARGET_EFAULT; - } - ret = get_errno(sys_getdents64(arg1, dirp, count)); - if (!is_error(ret)) { - /* - * Convert the dirent64 structs to target dirent. We do this - * in-place, since we can guarantee that a target_dirent is no - * larger than a dirent64; however this means we have to be - * careful to read everything before writing in the new format. - */ - struct linux_dirent64 *de; - struct target_dirent *tde; - int len = ret; - int tlen = 0; - - de = dirp; - tde = (struct target_dirent *)dirp; - while (len > 0) { - int namelen, treclen; - int reclen = de->d_reclen; - uint64_t ino = de->d_ino; - int64_t off = de->d_off; - uint8_t type = de->d_type; - - namelen = strlen(de->d_name); - treclen = offsetof(struct target_dirent, d_name) + namelen + 2; - treclen = QEMU_ALIGN_UP(treclen, sizeof(abi_long)); - - memmove(tde->d_name, de->d_name, namelen + 1); - tde->d_ino = tswapal(ino); - tde->d_off = tswapal(off); - tde->d_reclen = tswap16(treclen); /* - * The target_dirent type is in what was formerly a padding - * byte at the end of the structure: + * Return what we have, resetting the file pointer to the + * location of the first record not returned. */ - *(((char *)tde) + treclen - 1) = type; - - de = (struct linux_dirent64 *)((char *)de + reclen); - tde = (struct target_dirent *)((char *)tde + treclen); - len -= reclen; - tlen += treclen; + lseek64(dirfd, prev_diroff, SEEK_SET); + break; } - ret = tlen; - } - unlock_user(dirp, arg2, ret); + + prev_diroff = hde->d_off; + tde->d_ino = tswapal(hde->d_ino); + tde->d_off = tswapal(hde->d_off); + tde->d_reclen = tswap16(treclen); + memcpy(tde->d_name, hde->d_name, namelen + 1); + + /* + * The getdents type is in what was formerly a padding byte at the + * end of the structure. + */ +#ifdef EMULATE_GETDENTS_WITH_GETDENTS + type = *((uint8_t *)hde + hreclen - 1); +#else + type = hde->d_type; #endif - return ret; + *((uint8_t *)tde + treclen - 1) = type; + } + + unlock_user(tdirp, arg2, toff); + return toff; } #endif /* TARGET_NR_getdents */ #if defined(TARGET_NR_getdents64) && defined(__NR_getdents64) -static int do_getdents64(abi_long arg1, abi_long arg2, abi_long arg3) +static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count) { - struct linux_dirent64 *dirp; - abi_long count = arg3; - int ret; + g_autofree void *hdirp = NULL; + void *tdirp; + int hlen, hoff, toff; + int hreclen, treclen; + off64_t prev_diroff = 0; - dirp = lock_user(VERIFY_WRITE, arg2, count, 0); - if (!dirp) { + hdirp = g_try_malloc(count); + if (!hdirp) { + return -TARGET_ENOMEM; + } + + hlen = get_errno(sys_getdents64(dirfd, hdirp, count)); + if (is_error(hlen)) { + return hlen; + } + + tdirp = lock_user(VERIFY_WRITE, arg2, count, 0); + if (!tdirp) { return -TARGET_EFAULT; } - ret = get_errno(sys_getdents64(arg1, dirp, count)); - if (!is_error(ret)) { - struct linux_dirent64 *de; - int len = ret; - int reclen; - de = dirp; - while (len > 0) { - reclen = de->d_reclen; - if (reclen > len) { + + for (hoff = toff = 0; hoff < hlen; hoff += hreclen, toff += treclen) { + struct linux_dirent64 *hde = hdirp + hoff; + struct target_dirent64 *tde = tdirp + toff; + int namelen; + + namelen = strlen(hde->d_name) + 1; + hreclen = hde->d_reclen; + treclen = offsetof(struct target_dirent64, d_name) + namelen; + treclen = QEMU_ALIGN_UP(treclen, __alignof(struct target_dirent64)); + + if (toff + treclen > count) { + /* + * If the host struct is smaller than the target struct, or + * requires less alignment and thus packs into less space, + * then the host can return more entries than we can pass + * on to the guest. + */ + if (toff == 0) { + toff = -TARGET_EINVAL; /* result buffer is too small */ break; } - de->d_reclen = tswap16(reclen); - tswap64s((uint64_t *)&de->d_ino); - tswap64s((uint64_t *)&de->d_off); - de = (struct linux_dirent64 *)((char *)de + reclen); - len -= reclen; + /* + * Return what we have, resetting the file pointer to the + * location of the first record not returned. + */ + lseek64(dirfd, prev_diroff, SEEK_SET); + break; } + + prev_diroff = hde->d_off; + tde->d_ino = tswap64(hde->d_ino); + tde->d_off = tswap64(hde->d_off); + tde->d_reclen = tswap16(treclen); + tde->d_type = hde->d_type; + memcpy(tde->d_name, hde->d_name, namelen); } - unlock_user(dirp, arg2, ret); - return ret; + + unlock_user(tdirp, arg2, toff); + return toff; } #endif /* TARGET_NR_getdents64 */ From 6b717a8d4482fa88fb2a40b5afd5a55e7a0ba412 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 19 Nov 2021 11:25:49 +0100 Subject: [PATCH 017/421] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configuring a drive with "if=none" is meant for creation of a backend only, it should not get automatically assigned to a device frontend. Use "if=pflash" for the One-Time-Programmable device instead (like it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c). Since the old way of configuring the device has already been published with the previous QEMU versions, we cannot remove this immediately, but have to deprecate it and support it for at least two more releases. Signed-off-by: Thomas Huth Acked-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster Reviewed-by: Alistair Francis Message-id: 20211119102549.217755-1-thuth@redhat.com Signed-off-by: Alistair Francis --- docs/about/deprecated.rst | 6 ++++++ hw/misc/sifive_u_otp.c | 9 ++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index c03fcf951f..ff7488cb63 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -192,6 +192,12 @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. However, short-form booleans are deprecated and full explicit ``arg_name=on`` form is preferred. +``-drive if=none`` for the sifive_u OTP device (since 6.2) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +Using ``-drive if=none`` to configure the OTP device of the sifive_u +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. + QEMU Machine Protocol (QMP) commands ------------------------------------ diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 18aa0bd55d..cf6098ff2c 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -209,7 +209,14 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); - dinfo = drive_get_next(IF_NONE); + dinfo = drive_get_next(IF_PFLASH); + if (!dinfo) { + dinfo = drive_get_next(IF_NONE); + if (dinfo) { + warn_report("using \"-drive if=none\" for the OTP is deprecated, " + "use \"-drive if=pflash\" instead."); + } + } if (dinfo) { int ret; uint64_t perm; From 526e7443027c71fe7b04c29df529e1f9f425f9e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 19 Nov 2021 11:47:57 +0100 Subject: [PATCH 018/421] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Once a "One Time Programmable" is programmed, it shouldn't be reset. Do not re-initialize the OTP content in the DeviceReset handler, initialize it once in the DeviceRealize one. Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-Id: <20211119104757.331579-1-f4bug@amsat.org> Signed-off-by: Alistair Francis --- hw/misc/sifive_u_otp.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index cf6098ff2c..52fdb750c0 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -242,14 +242,10 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) { error_setg(errp, "failed to read the initial flash content"); + return; } } } -} - -static void sifive_u_otp_reset(DeviceState *dev) -{ - SiFiveUOTPState *s = SIFIVE_U_OTP(dev); /* Initialize all fuses' initial value to 0xFFs */ memset(s->fuse, 0xff, sizeof(s->fuse)); @@ -266,13 +262,15 @@ static void sifive_u_otp_reset(DeviceState *dev) serial_data = s->serial; if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD, &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { - error_report("write error index<%d>", index); + error_setg(errp, "failed to write index<%d>", index); + return; } serial_data = ~(s->serial); if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD, &serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) { - error_report("write error index<%d>", index + 1); + error_setg(errp, "failed to write index<%d>", index + 1); + return; } } @@ -286,7 +284,6 @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data) device_class_set_props(dc, sifive_u_otp_properties); dc->realize = sifive_u_otp_realize; - dc->reset = sifive_u_otp_reset; } static const TypeInfo sifive_u_otp_info = { From 802ae45e94151a6d3ee20eadcb865cf6c875df34 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Sun, 21 Nov 2021 16:17:11 +0100 Subject: [PATCH 019/421] linux-user: fix Coverity CID 1464101 target_mmap() can fail and return -1, but we don't check for that and instead assume it's always valid. Fixes: db2af69d6ba8 ("linux-user: Add infrastructure for a signal trampoline page") Cc: richard.henderson@linaro.org Reported-by: Peter Maydell Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <20211121151711.331653-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier --- linux-user/elfload.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5da8c02d08..767f54c76d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3254,9 +3254,13 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) * Otherwise, allocate a private page to hold them. */ if (TARGET_ARCH_HAS_SIGTRAMP_PAGE) { - abi_ulong tramp_page = target_mmap(0, TARGET_PAGE_SIZE, - PROT_READ | PROT_WRITE, - MAP_PRIVATE | MAP_ANON, -1, 0); + abi_long tramp_page = target_mmap(0, TARGET_PAGE_SIZE, + PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANON, -1, 0); + if (tramp_page == -1) { + return -errno; + } + setup_sigtramp(tramp_page); target_mprotect(tramp_page, TARGET_PAGE_SIZE, PROT_READ | PROT_EXEC); } From 4323118cadc5a316f73b5b0a60b5789ed9201369 Mon Sep 17 00:00:00 2001 From: Alexander Orzechowski Date: Sun, 21 Nov 2021 01:55:03 -0500 Subject: [PATCH 020/421] ui: fix incorrect scaling on highdpi with gtk/opengl Signed-off-by: Alexander Orzechowski Message-Id: <20211121065504.29101-2-orzechowski.alexander@gmail.com> [ kraxel: codestyle fix ] Signed-off-by: Gerd Hoffmann --- ui/gtk-gl-area.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/ui/gtk-gl-area.c b/ui/gtk-gl-area.c index 461da7712f..01e4e74ee3 100644 --- a/ui/gtk-gl-area.c +++ b/ui/gtk-gl-area.c @@ -41,15 +41,16 @@ void gd_gl_area_draw(VirtualConsole *vc) #ifdef CONFIG_GBM QemuDmaBuf *dmabuf = vc->gfx.guest_fb.dmabuf; #endif - int ww, wh, y1, y2; + int ww, wh, ws, y1, y2; if (!vc->gfx.gls) { return; } gtk_gl_area_make_current(GTK_GL_AREA(vc->gfx.drawing_area)); - ww = gtk_widget_get_allocated_width(vc->gfx.drawing_area); - wh = gtk_widget_get_allocated_height(vc->gfx.drawing_area); + ws = gdk_window_get_scale_factor(gtk_widget_get_window(vc->gfx.drawing_area)); + ww = gtk_widget_get_allocated_width(vc->gfx.drawing_area) * ws; + wh = gtk_widget_get_allocated_height(vc->gfx.drawing_area) * ws; if (vc->gfx.scanout_mode) { if (!vc->gfx.guest_fb.framebuffer) { From f14aab420c58b57e07189d6d9e6d3fbfab4761a6 Mon Sep 17 00:00:00 2001 From: Alexander Orzechowski Date: Sun, 21 Nov 2021 01:55:04 -0500 Subject: [PATCH 021/421] ui: fix incorrect pointer position on highdpi with gtk Signed-off-by: Alexander Orzechowski Message-Id: <20211121065504.29101-3-orzechowski.alexander@gmail.com> [ kraxel: codestyle fix ] Signed-off-by: Gerd Hoffmann --- ui/gtk.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/ui/gtk.c b/ui/gtk.c index d2892ea6b4..dc4a1491f0 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -838,10 +838,11 @@ static gboolean gd_motion_event(GtkWidget *widget, GdkEventMotion *motion, { VirtualConsole *vc = opaque; GtkDisplayState *s = vc->s; + GdkWindow *window; int x, y; int mx, my; int fbh, fbw; - int ww, wh; + int ww, wh, ws; if (!vc->gfx.ds) { return TRUE; @@ -850,8 +851,10 @@ static gboolean gd_motion_event(GtkWidget *widget, GdkEventMotion *motion, fbw = surface_width(vc->gfx.ds) * vc->gfx.scale_x; fbh = surface_height(vc->gfx.ds) * vc->gfx.scale_y; - ww = gdk_window_get_width(gtk_widget_get_window(vc->gfx.drawing_area)); - wh = gdk_window_get_height(gtk_widget_get_window(vc->gfx.drawing_area)); + window = gtk_widget_get_window(vc->gfx.drawing_area); + ww = gdk_window_get_width(window); + wh = gdk_window_get_height(window); + ws = gdk_window_get_scale_factor(window); mx = my = 0; if (ww > fbw) { @@ -861,8 +864,8 @@ static gboolean gd_motion_event(GtkWidget *widget, GdkEventMotion *motion, my = (wh - fbh) / 2; } - x = (motion->x - mx) / vc->gfx.scale_x; - y = (motion->y - my) / vc->gfx.scale_y; + x = (motion->x - mx) / vc->gfx.scale_x * ws; + y = (motion->y - my) / vc->gfx.scale_y * ws; if (qemu_input_is_absolute()) { if (x < 0 || y < 0 || From c3abdb2faff62e3ded21bf8c3ef493ed70785623 Mon Sep 17 00:00:00 2001 From: Dongwon Kim Date: Sun, 21 Nov 2021 09:22:37 -0800 Subject: [PATCH 022/421] ui/gtk: graphic_hw_gl_flushed after closing dmabuf->fence_fd The dmabuf often becomes invalid right after unblocking pipeline and graphic_hw_gl_flushed in case a new scanout blob is submitted because the dmabuf associated with the current guest scanout is freed after swapping. So both graphic_hw_gl_block and graphic_hw_gl_flushed should be executed after closing fence_fd for the current dmabuf. Cc: Gerd Hoffmann Cc: Vivek Kasireddy Signed-off-by: Dongwon Kim Message-Id: <20211121172237.14937-1-dongwon.kim@intel.com> Signed-off-by: Gerd Hoffmann --- ui/gtk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ui/gtk.c b/ui/gtk.c index dc4a1491f0..428f02f2df 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -589,11 +589,11 @@ void gd_hw_gl_flushed(void *vcon) VirtualConsole *vc = vcon; QemuDmaBuf *dmabuf = vc->gfx.guest_fb.dmabuf; - graphic_hw_gl_block(vc->gfx.dcl.con, false); - graphic_hw_gl_flushed(vc->gfx.dcl.con); qemu_set_fd_handler(dmabuf->fence_fd, NULL, NULL, NULL); close(dmabuf->fence_fd); dmabuf->fence_fd = -1; + graphic_hw_gl_block(vc->gfx.dcl.con, false); + graphic_hw_gl_flushed(vc->gfx.dcl.con); } /** DisplayState Callbacks (opengl version) **/ From 2e572baf659f5a457c876c6b2d02a217afb401c5 Mon Sep 17 00:00:00 2001 From: Vladimir Sementsov-Ogievskiy Date: Wed, 10 Nov 2021 11:38:00 +0100 Subject: [PATCH 023/421] ui/vnc-clipboard: fix adding notifier twice vnc_server_cut_text_caps() is not guaranteed to be called only once. If it called twice, we finally call notifier_list_add() twice with same element. Which leads to loopback QLIST. So, on next notifier_list_notify() we'll loop forever and QEMU stuck. So, let's only register new notifier if it's not yet registered. Note, that similar check is used in vdagent_chr_recv_caps() (before call qemu_clipboard_peer_register()), and also before qemu_clipboard_peer_unregister() call in vdagent_disconnect() and in vnc_disconnect_finish(). Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20211110103800.2266729-1-vsementsov@virtuozzo.com> Signed-off-by: Gerd Hoffmann --- ui/vnc-clipboard.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/ui/vnc-clipboard.c b/ui/vnc-clipboard.c index 9f077965d0..67284b556c 100644 --- a/ui/vnc-clipboard.c +++ b/ui/vnc-clipboard.c @@ -316,8 +316,10 @@ void vnc_server_cut_text_caps(VncState *vs) caps[1] = 0; vnc_clipboard_send(vs, 2, caps); - vs->cbpeer.name = "vnc"; - vs->cbpeer.update.notify = vnc_clipboard_notify; - vs->cbpeer.request = vnc_clipboard_request; - qemu_clipboard_peer_register(&vs->cbpeer); + if (!vs->cbpeer.update.notify) { + vs->cbpeer.name = "vnc"; + vs->cbpeer.update.notify = vnc_clipboard_notify; + vs->cbpeer.request = vnc_clipboard_request; + qemu_clipboard_peer_register(&vs->cbpeer); + } } From 4067691a2fed9a7639b1264b07c131d8e11f2b4f Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Tue, 16 Nov 2021 08:28:40 +0100 Subject: [PATCH 024/421] migration: fix dump-vmstate with modules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To work correctly -dump-vmstate and vmstate-static-checker.py need to dump all the supported vmstates. But as some devices can be modules, they are not loaded at startup and not dumped. Fix that by loading all available modules before dumping the machine vmstate. Fixes: 7ab6e7fcce97 ("qdev: device module support") Cc: kraxel@redhat.com Signed-off-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211116072840.132731-1-lvivier@redhat.com> Signed-off-by: Gerd Hoffmann --- softmmu/vl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/softmmu/vl.c b/softmmu/vl.c index 1159a64bce..620a1f1367 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -3766,6 +3766,7 @@ void qemu_init(int argc, char **argv, char **envp) if (vmstate_dump_file) { /* dump and exit */ + module_load_qom_all(); dump_vmstate_json_to_file(vmstate_dump_file); exit(0); } From d612405ed2a1163a142f94552a9874ad4b02de30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 17 Nov 2021 18:43:31 +0100 Subject: [PATCH 025/421] hw/i386/microvm: Reduce annoying debug message in dt_setup_microvm() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: f5918a99283 ("microvm: add device tree support.") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Sergio Lopez Reviewed-by: Darren Kenny Message-Id: <20211117174331.1715144-1-philmd@redhat.com> Signed-off-by: Gerd Hoffmann --- hw/i386/microvm-dt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c index 875ba91963..6ee6c42904 100644 --- a/hw/i386/microvm-dt.c +++ b/hw/i386/microvm-dt.c @@ -327,7 +327,9 @@ void dt_setup_microvm(MicrovmMachineState *mms) dt_setup_sys_bus(mms); /* add to fw_cfg */ - fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__); + if (debug) { + fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__); + } fw_cfg_add_file(x86ms->fw_cfg, "etc/fdt", mms->fdt, size); if (debug) { From 1b38ccc9a1fa865a8838c89216dc36df87e9c9d5 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 8 Nov 2021 14:07:17 +0100 Subject: [PATCH 026/421] microvm: add missing g_free() call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes: CID 1465240 Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211108130718.840216-2-kraxel@redhat.com> --- hw/i386/microvm-dt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c index 6ee6c42904..a6a59a6e12 100644 --- a/hw/i386/microvm-dt.c +++ b/hw/i386/microvm-dt.c @@ -143,6 +143,8 @@ static void dt_add_pcie(MicrovmMachineState *mms) nr_pcie_buses = PCIE_ECAM_SIZE / PCIE_MMCFG_SIZE_MIN; qemu_fdt_setprop_cells(mms->fdt, nodename, "bus-range", 0, nr_pcie_buses - 1); + + g_free(nodename); } static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev) From b9e5628ca5d42994cc6f82752d9bf0bc98f51f64 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 8 Nov 2021 14:07:18 +0100 Subject: [PATCH 027/421] microvm: check g_file_set_contents() return value Fixes: CID 1465239 Signed-off-by: Gerd Hoffmann Message-Id: <20211108130718.840216-3-kraxel@redhat.com> --- hw/i386/microvm-dt.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/i386/microvm-dt.c b/hw/i386/microvm-dt.c index a6a59a6e12..9c3c4995b4 100644 --- a/hw/i386/microvm-dt.c +++ b/hw/i386/microvm-dt.c @@ -336,7 +336,10 @@ void dt_setup_microvm(MicrovmMachineState *mms) if (debug) { fprintf(stderr, "%s: writing microvm.fdt\n", __func__); - g_file_set_contents("microvm.fdt", mms->fdt, size, NULL); + if (!g_file_set_contents("microvm.fdt", mms->fdt, size, NULL)) { + fprintf(stderr, "%s: writing microvm.fdt failed\n", __func__); + return; + } int ret = system("dtc -I dtb -O dts microvm.fdt"); if (ret != 0) { fprintf(stderr, "%s: oops, dtc not installed?\n", __func__); From 1644cccea5c71b02b9cf8f78b780e7069a29b189 Mon Sep 17 00:00:00 2001 From: Eric Blake Date: Wed, 17 Nov 2021 11:02:29 -0600 Subject: [PATCH 028/421] nbd/server: Don't complain on certain client disconnects When a client disconnects abruptly, but did not have any pending requests (for example, when using nbdsh without calling h.shutdown), we used to output the following message: $ qemu-nbd -f raw file $ nbdsh -u 'nbd://localhost:10809' -c 'h.trim(1,0)' qemu-nbd: Disconnect client, due to: Failed to read request: Unexpected end-of-file before all bytes were read Then in commit f148ae7, we refactored nbd_receive_request() to use nbd_read_eof(); when this returns 0, we regressed into tracing uninitialized memory (if tracing is enabled) and reporting a less-specific: qemu-nbd: Disconnect client, due to: Request handling failed in intermediate state Note that with Unix sockets, we have yet another error message, unchanged by the 6.0 regression: $ qemu-nbd -k /tmp/sock -f raw file $ nbdsh -u 'nbd+unix:///?socket=/tmp/sock' -c 'h.trim(1,0)' qemu-nbd: Disconnect client, due to: Failed to send reply: Unable to write to socket: Broken pipe But in all cases, the error message goes away if the client performs a soft shutdown by using NBD_CMD_DISC, rather than a hard shutdown by abrupt disconnect: $ nbdsh -u 'nbd://localhost:10809' -c 'h.trim(1,0)' -c 'h.shutdown()' This patch fixes things to avoid uninitialized memory, and in general avoids warning about a client that does a hard shutdown when not in the middle of a packet. A client that aborts mid-request, or which does not read the full server's reply, can still result in warnings, but those are indeed much more unusual situations. CC: qemu-stable@nongnu.org Fixes: f148ae7d36 ("nbd/server: Quiesce coroutines on context switch", v6.0.0) Signed-off-by: Eric Blake Reviewed-by: Vladimir Sementsov-Ogievskiy [eblake: defer unrelated typo fixes to later patch] Message-Id: <20211117170230.1128262-2-eblake@redhat.com> Signed-off-by: Eric Blake --- nbd/server.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nbd/server.c b/nbd/server.c index d9164ee6d0..74ba487094 100644 --- a/nbd/server.c +++ b/nbd/server.c @@ -1418,6 +1418,9 @@ static int nbd_receive_request(NBDClient *client, NBDRequest *request, if (ret < 0) { return ret; } + if (ret == 0) { + return -EIO; + } /* Request [ 0 .. 3] magic (NBD_REQUEST_MAGIC) From e35574226a63f29e32eda8da5cc14832f19850e2 Mon Sep 17 00:00:00 2001 From: Eric Blake Date: Wed, 17 Nov 2021 11:02:30 -0600 Subject: [PATCH 029/421] nbd/server: Simplify zero and trim Now that the block layer supports 64-bit operations (see commit 2800637a and friends, new to v6.2), we no longer have to self-fragment requests larger than 2G, reverting the workaround added in 890cbccb08 ("nbd: Fix large trim/zero requests", v5.1.0). Signed-off-by: Eric Blake Message-Id: <20211117170230.1128262-3-eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy --- nbd/server.c | 23 +++-------------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/nbd/server.c b/nbd/server.c index 74ba487094..4630dd7322 100644 --- a/nbd/server.c +++ b/nbd/server.c @@ -2509,16 +2509,8 @@ static coroutine_fn int nbd_handle_request(NBDClient *client, if (request->flags & NBD_CMD_FLAG_FAST_ZERO) { flags |= BDRV_REQ_NO_FALLBACK; } - ret = 0; - /* FIXME simplify this when blk_pwrite_zeroes switches to 64-bit */ - while (ret >= 0 && request->len) { - int align = client->check_align ?: 1; - int len = MIN(request->len, QEMU_ALIGN_DOWN(BDRV_REQUEST_MAX_BYTES, - align)); - ret = blk_pwrite_zeroes(exp->common.blk, request->from, len, flags); - request->len -= len; - request->from += len; - } + ret = blk_pwrite_zeroes(exp->common.blk, request->from, request->len, + flags); return nbd_send_generic_reply(client, request->handle, ret, "writing to file failed", errp); @@ -2532,16 +2524,7 @@ static coroutine_fn int nbd_handle_request(NBDClient *client, "flush failed", errp); case NBD_CMD_TRIM: - ret = 0; - /* FIXME simplify this when blk_co_pdiscard switches to 64-bit */ - while (ret >= 0 && request->len) { - int align = client->check_align ?: 1; - int len = MIN(request->len, QEMU_ALIGN_DOWN(BDRV_REQUEST_MAX_BYTES, - align)); - ret = blk_co_pdiscard(exp->common.blk, request->from, len); - request->len -= len; - request->from += len; - } + ret = blk_co_pdiscard(exp->common.blk, request->from, request->len); if (ret >= 0 && request->flags & NBD_CMD_FLAG_FUA) { ret = blk_co_flush(exp->common.blk); } From 4825eaae4fdd56fba0febdfbdd7bf9684ae3ee0d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 22 Nov 2021 13:41:48 +0000 Subject: [PATCH 030/421] Revert "arm: tcg: Adhere to SMCCC 1.3 section 5.2" This reverts commit 9fcd15b9193e819b6cc2fd0a45e3506148812bb4. This change turns out to cause regressions, for instance on the imx6ul boards as described here: https://lore.kernel.org/qemu-devel/c8b89685-7490-328b-51a3-48711c140a84@tribudubois.net/ The primary cause of that regression is that the guest code running at EL3 expects SMCs (not related to PSCI) to do what they would if our PSCI emulation was not present at all, but after this change they instead set a value in R0/X0 and continue. We could fix that by a refactoring that allowed us to only turn on the PSCI emulation if we weren't booting the guest at EL3, but there is a more tangled problem with the highbank board, which: (1) wants to enable PSCI emulation (2) has a bit of guest code that it wants to run at EL3 and to perform SMC calls that trap to the monitor vector table: this is the boot stub code that is written to memory by arm_write_secure_board_setup_dummy_smc() and which the highbank board enables by setting bootinfo->secure_board_setup We can't satisfy both of those and also have the PSCI emulation handle all SMC instruction executions regardless of function identifier value. This is too tricky to try to sort out before 6.2 is released; revert this commit so we can take the time to get it right in the 7.0 release. Signed-off-by: Peter Maydell Message-id: 20211119163419.557623-1-peter.maydell@linaro.org --- target/arm/psci.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/target/arm/psci.c b/target/arm/psci.c index b279c0b9a4..6709e28013 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -27,13 +27,15 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { - /* - * Return true if the exception type matches the configured PSCI conduit. - * This is called before the SMC/HVC instruction is executed, to decide - * whether we should treat it as a PSCI call or with the architecturally + /* Return true if the r0/x0 value indicates a PSCI call and + * the exception type matches the configured PSCI conduit. This is + * called before the SMC/HVC instruction is executed, to decide whether + * we should treat it as a PSCI call or with the architecturally * defined behaviour for an SMC or HVC (which might be UNDEF or trap * to EL2 or to EL3). */ + CPUARMState *env = &cpu->env; + uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0]; switch (excp_type) { case EXCP_HVC: @@ -50,7 +52,27 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type) return false; } - return true; + switch (param) { + case QEMU_PSCI_0_2_FN_PSCI_VERSION: + case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case QEMU_PSCI_0_2_FN_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN64_AFFINITY_INFO: + case QEMU_PSCI_0_2_FN_SYSTEM_RESET: + case QEMU_PSCI_0_2_FN_SYSTEM_OFF: + case QEMU_PSCI_0_1_FN_CPU_ON: + case QEMU_PSCI_0_2_FN_CPU_ON: + case QEMU_PSCI_0_2_FN64_CPU_ON: + case QEMU_PSCI_0_1_FN_CPU_OFF: + case QEMU_PSCI_0_2_FN_CPU_OFF: + case QEMU_PSCI_0_1_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN_CPU_SUSPEND: + case QEMU_PSCI_0_2_FN64_CPU_SUSPEND: + case QEMU_PSCI_0_1_FN_MIGRATE: + case QEMU_PSCI_0_2_FN_MIGRATE: + return true; + default: + return false; + } } void arm_handle_psci_call(ARMCPU *cpu) @@ -172,9 +194,10 @@ void arm_handle_psci_call(ARMCPU *cpu) break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: - default: ret = QEMU_PSCI_RET_NOT_SUPPORTED; break; + default: + g_assert_not_reached(); } err: From cd6b1674d61120a77823b99516d27486c4f4f883 Mon Sep 17 00:00:00 2001 From: Kashyap Chamarthy Date: Fri, 19 Nov 2021 20:31:17 +0100 Subject: [PATCH 031/421] docs: Fix botched rST conversion of 'submitting-a-patch.rst' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I completely botched up the merged[0] rST conversion of this document by accidentally dropping entire hunks (!) of text. :-( I made it very hard for reviewers to spot it, as the omitted text was buried deep in the document. To fix my hatchet job, I reconverted the "SubmitAPatch" wiki[1] page from scratch and replaced the existing rST with it, while making sure I incorporated previous feedback. In summary, in this reconverted edition: - I did a careful (to the extent my eyes allowed) para-by-para comparison of the wiki and the rST to make sure I didn't omit anything accidentally. - I made sure to work in the cosmetic feedback[2] that Thomas Huth pointed out in the merged (and botched) edition: - fix the hyperlinks in "Split up long patches" - replace ".". with "does not end with a dot" (in "Write a meaningful commit message" section) - replace "---" with ``---`` so that it doesn't render as an em-dash (there were two other occurrences; I fixed those too) - Use "QEMU" spelling consistently in prose usage - Add a consistent "refer to git-config" link where appropriate Thanks to Thomas Huth and Alex Bennée for noticing it on IRC. And sorry for my sloppiness. Fixes: 9f73de8df033 ("docs: rSTify the "SubmitAPatch" wiki") [0] https://gitlab.com/qemu-project/qemu/-/commit/9f73de8df033 [1] https://wiki.qemu.org/index.php?title=Contribute/SubmitAPatch&oldid=10387 [2] https://lists.nongnu.org/archive/html/qemu-devel/2021-11/msg03600.html Signed-off-by: Kashyap Chamarthy Message-Id: <20211119193118.949698-2-kchamart@redhat.com> Reviewed-by: Eric Blake [thuth: Some more cosmetical changes, fixed links from external to internal] Signed-off-by: Thomas Huth --- docs/devel/stable-process.rst | 2 + docs/devel/style.rst | 2 + docs/devel/submitting-a-patch.rst | 198 +++++++++++++++++------ docs/devel/submitting-a-pull-request.rst | 9 +- docs/devel/trivial-patches.rst | 2 + 5 files changed, 161 insertions(+), 52 deletions(-) diff --git a/docs/devel/stable-process.rst b/docs/devel/stable-process.rst index e541b983fa..c21fb86645 100644 --- a/docs/devel/stable-process.rst +++ b/docs/devel/stable-process.rst @@ -1,3 +1,5 @@ +.. _stable-process: + QEMU and the stable process =========================== diff --git a/docs/devel/style.rst b/docs/devel/style.rst index e00af62e76..9c5c0fffd9 100644 --- a/docs/devel/style.rst +++ b/docs/devel/style.rst @@ -1,3 +1,5 @@ +.. _coding-style: + ================= QEMU Coding Style ================= diff --git a/docs/devel/submitting-a-patch.rst b/docs/devel/submitting-a-patch.rst index 6fefc67d52..6acded5c93 100644 --- a/docs/devel/submitting-a-patch.rst +++ b/docs/devel/submitting-a-patch.rst @@ -1,3 +1,5 @@ +.. _submitting-a-patch: + Submitting a Patch ================== @@ -20,11 +22,11 @@ one-shot fix, the bare minimum we ask is that: should not be posted on the bug tracker, posted on forums, or externally hosted and linked to. (We have other mailing lists too, but all patches must go to qemu-devel, possibly with a Cc: to another - list.) ``git send-email`` works best for delivering the patch without - mangling it (`hints for setting it - up `__), - but attachments can be used as a last resort on a first-time - submission. + list.) ``git send-email`` (`step-by-step setup + guide `__ and `hints and + tips `__) + works best for delivering the patch without mangling it, but + attachments can be used as a last resort on a first-time submission. - You must read replies to your message, and be willing to act on them. Note, however, that maintainers are often willing to manually fix up first-time contributions, since there is a learning curve involved in @@ -45,6 +47,8 @@ Reading the table of contents below should already give you an idea of the basic requirements. Use the table of contents as a reference, and read the parts that you have doubts about. +.. contents:: Table of Contents + .. _writing_your_patches: Writing your Patches @@ -60,11 +64,9 @@ check that you are in compliance with our coding standards. Be aware that ``checkpatch.pl`` is not infallible, though, especially where C preprocessor macros are involved; use some common sense too. See also: -- `QEMU Coding Style - `__ - +- :ref:`coding-style` - `Automate a checkpatch run on - commit `__ + commit `__ .. _base_patches_against_current_git_master: @@ -76,6 +78,13 @@ of QEMU because development will have moved on from then and it probably won't even apply to master. We only apply selected bugfixes to release branches and then only as backports once the code has gone into master. +It is also okay to base patches on top of other on-going work that is +not yet part of the git master branch. To aid continuous integration +tools, such as `patchew `__, you should `add a +tag `__ +line ``Based-on: $MESSAGE_ID`` to your cover letter to make the series +dependency obvious. + .. _split_up_long_patches: Split up long patches @@ -104,18 +113,17 @@ Make code motion patches easy to review If a series requires large blocks of code motion, there are tricks for making the refactoring easier to review. Split up the series so that semantic changes (or even function renames) are done in a separate patch -from the raw code motion. Use a one-time setup of -``git config diff.renames true; git config diff.algorithm patience`` -(Refer to `git-config `__.) The -``diff.renames`` property ensures file rename patches will be given in a -more compact representation that focuses only on the differences across -the file rename, instead of showing the entire old file as a deletion -and the new file as an insertion. Meanwhile, the 'diff.algorithm' -property ensures that extracting a non-contiguous subset of one file -into a new file, but where all extracted parts occur in the same order -both before and after the patch, will reduce churn in trying to treat -unrelated ``}`` lines in the original file as separating hunks of -changes. +from the raw code motion. Use a one-time setup of ``git config +diff.renames true;`` ``git config diff.algorithm patience`` (refer to +`git-config `__). The 'diff.renames' +property ensures file rename patches will be given in a more compact +representation that focuses only on the differences across the file +rename, instead of showing the entire old file as a deletion and the new +file as an insertion. Meanwhile, the 'diff.algorithm' property ensures +that extracting a non-contiguous subset of one file into a new file, but +where all extracted parts occur in the same order both before and after +the patch, will reduce churn in trying to treat unrelated ``}`` lines in +the original file as separating hunks of changes. Ideally, a code motion patch can be reviewed by doing:: @@ -138,8 +146,7 @@ as a separate patch which makes no semantic changes; don't put it in the same patch as your bug fix. For smaller patches in less frequently changed areas of QEMU, consider -using the `trivial patches process -`__. +using the :ref:`trivial-patches` process. .. _write_a_meaningful_commit_message: @@ -154,7 +161,7 @@ QEMU follows the usual standard for git commit messages: the first line (which becomes the email subject line) is "subsystem: single line summary of change". Whether the "single line summary of change" starts with a capital is a matter of taste, but we prefer that the summary does -not end in ".". Look at ``git shortlog -30`` for an idea of sample +not end in a dot. Look at ``git shortlog -30`` for an idea of sample subject lines. Then there is a blank line and a more detailed description of the patch, another blank and your Signed-off-by: line. Please do not use lines that are longer than 76 characters in your @@ -170,11 +177,75 @@ displays the subject line some distance apart (that is, a body that starts with "... so that" as a continuation of the subject line is harder to follow). +If your patch fixes a commit that is already in the repository, please +add an additional line with "Fixes: +("Fixed commit subject")" below the patch description / before your +"Signed-off-by:" line in the commit message. + +If your patch fixes a bug in the gitlab bug tracker, please add a line +with "Resolves: " to the commit message, too. Gitlab can +close bugs automatically once commits with the "Resolved:" keyword get +merged into the master branch of the project. And if your patch addresses +a bug in another public bug tracker, you can also use a line with +"Buglink: " for reference here, too. + +Example:: + + Fixes: 14055ce53c2d ("s390x/tcg: avoid overflows in time2tod/tod2time") + Resolves: https://gitlab.com/qemu-project/qemu/-/issues/42 + Buglink: https://bugs.launchpad.net/qemu/+bug/1804323`` + +.. _test_your_patches: + +Test your patches +~~~~~~~~~~~~~~~~~ + +Although QEMU has `continuous integration +services `__ that attempt to test +patches submitted to the list, it still saves everyone time if you have +already tested that your patch compiles and works. Because QEMU is such +a large project, it's okay to use configure arguments to limit what is +built for faster turnaround during your development time; but it is +still wise to also check that your patches work with a full build before +submitting a series, especially if your changes might have an unintended +effect on other areas of the code you don't normally experiment with. +See `Testing `__ for more details on what tests are available. +Also, it is a wise idea to include a testsuite addition as part of your +patches - either to ensure that future changes won't regress your new +feature, or to add a test which exposes the bug that the rest of your +series fixes. Keeping separate commits for the test and the fix allows +reviewers to rebase the test to occur first to prove it catches the +problem, then again to place it last in the series so that bisection +doesn't land on a known-broken state. + .. _submitting_your_patches: Submitting your Patches ----------------------- +.. _if_you_cannot_send_patch_emails: + +If you cannot send patch emails +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +In rare cases it may not be possible to send properly formatted patch +emails. You can use `sourcehut `__ to send your +patches to the QEMU mailing list by following these steps: + +#. Register or sign in to your account +#. Add your SSH public key in `meta \| + keys `__. +#. Publish your git branch using **git push git@git.sr.ht:~USERNAME/qemu + HEAD** +#. Send your patches to the QEMU mailing list using the web-based + ``git-send-email`` UI at https://git.sr.ht/~USERNAME/qemu/send-email + +`This video +`__ +shows the web-based ``git-send-email`` workflow. Documentation is +available `here +`__. + .. _cc_the_relevant_maintainer: CC the relevant maintainer @@ -219,17 +290,26 @@ such as 'git-email' on Fedora-based systems.) Patch series need a cover letter, with shallow threading (all patches in the series are in-reply-to the cover letter, but not to each other); single unrelated patches do not need a cover letter (but if you do send a cover letter, -use --numbered so the cover and the patch have distinct subject lines). +use ``--numbered`` so the cover and the patch have distinct subject lines). Patches are easier to find if they start a new top-level thread, rather than being buried in-reply-to another existing thread. +.. _avoid_posting_large_binary_blob: + +Avoid posting large binary blob +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If you added binaries to the repository, consider producing the patch +emails using ``git format-patch --no-binary`` and include a link to a +git repository to fetch the original commit. + .. _patch_emails_must_include_a_signed_off_by_line: Patch emails must include a ``Signed-off-by:`` line ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -For more information see `1.12) Sign your work -`__. +For more information see `SubmittingPatches 1.12 +`__. This is vital or we will not be able to apply your patch! Please use your real name to sign a patch (not an alias or acronym). @@ -246,8 +326,13 @@ that author's Signed-off-by: line is mandatory, with the same spelling. Include a meaningful cover letter ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -This usually applies only to a series that includes multiple patches; -the cover letter explains the overall goal of such a series. +This is a requirement for any series with multiple patches (as it aids +continuous integration), but optional for an isolated patch. The cover +letter explains the overall goal of such a series, and also provides a +convenient 0/N email for others to reply to the series as a whole. A +one-time setup of ``git config format.coverletter auto`` (refer to +`git-config `__) will generate the +cover letter as needed. When reviewers don't know your goal at the start of their review, they may object to early changes that don't make sense until the end of the @@ -288,6 +373,18 @@ it's best to: of the patchset you're looking for review on, and why reviewers should care +.. _consider_whether_your_patch_is_applicable_for_stable: + +Consider whether your patch is applicable for stable +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If your patch fixes a severe issue or a regression, it may be applicable +for stable. In that case, consider adding ``Cc: qemu-stable@nongnu.org`` +to your patch to notify the stable maintainers. + +For more details on how QEMU's stable process works, refer to the +:ref:`stable-process` page. + .. _participating_in_code_review: Participating in Code Review @@ -367,19 +464,19 @@ Include version history in patchset revisions For later versions of patches, include a summary of changes from previous versions, but not in the commit message itself. In an email -formatted as a git patch, the commit message is the part above the "---" +formatted as a git patch, the commit message is the part above the ``---`` line, and this will go into the git changelog when the patch is committed. This part should be a self-contained description of what this version of the patch does, written to make sense to anybody who comes back to look at this commit in git in six months' time. The part below -the "---" line and above the patch proper (git format-patch puts the +the ``---`` line and above the patch proper (git format-patch puts the diffstat here) is a good place to put remarks for people reading the patch email, and this is where the "changes since previous version" -summary belongs. The -`git-publish `__ script can -help with tracking a good summary across versions. Also, the -`git-backport-diff `__ script -can help focus reviewers on what changed between revisions. +summary belongs. The `git-publish +`__ script can help with +tracking a good summary across versions. Also, the `git-backport-diff +`__ script can help focus +reviewers on what changed between revisions. .. _tips_and_tricks: @@ -411,27 +508,32 @@ If your patch seems to have been ignored If your patchset has received no replies you should "ping" it after a week or two, by sending an email as a reply-to-all to the patch mail, including the word "ping" and ideally also a link to the page for the -patch on -`patchwork `__ or -GMANE. It's worth double-checking for reasons why your patch might have -been ignored (forgot to CC the maintainer? annoyed people by failing to -respond to review comments on an earlier version?), but often for -less-maintained areas of QEMU patches do just slip through the cracks. -If your ping is also ignored, ping again after another week or so. As -the submitter, you are the person with the most motivation to get your -patch applied, so you have to be persistent. +patch on `patchew `__ or +`lore.kernel.org `__. It's worth +double-checking for reasons why your patch might have been ignored +(forgot to CC the maintainer? annoyed people by failing to respond to +review comments on an earlier version?), but often for less-maintained +areas of QEMU patches do just slip through the cracks. If your ping is +also ignored, ping again after another week or so. As the submitter, you +are the person with the most motivation to get your patch applied, so +you have to be persistent. .. _is_my_patch_in: Is my patch in? ~~~~~~~~~~~~~~~ +QEMU has some Continuous Integration machines that try to catch patch +submission problems as soon as possible. `patchew +`__ includes a web interface for tracking the +status of various threads that have been posted to the list, and may +send you an automated mail if it detected a problem with your patch. + Once your patch has had enough review on list, the maintainer for that area of code will send notification to the list that they are including your patch in a particular staging branch. Periodically, the maintainer -then sends a `pull request -`__ -for aggregating topic branches into mainline qemu. Generally, you do not +then takes care of :ref:`submitting-a-pull-request` +for aggregating topic branches into mainline QEMU. Generally, you do not need to send a pull request unless you have contributed enough patches to become a maintainer over a particular section of code. Maintainers may further modify your commit, by resolving simple merge conflicts or diff --git a/docs/devel/submitting-a-pull-request.rst b/docs/devel/submitting-a-pull-request.rst index 8729d29036..c9d1e8afd9 100644 --- a/docs/devel/submitting-a-pull-request.rst +++ b/docs/devel/submitting-a-pull-request.rst @@ -1,10 +1,11 @@ -Submit a Pull Request -===================== +.. _submitting-a-pull-request: + +Submitting a Pull Request +========================= QEMU welcomes contributions of code, but we generally expect these to be sent as simple patch emails to the mailing list (see our page on -`submitting a patch -`__ +:ref:`submitting-a-patch` for more details). Generally only existing submaintainers of a tree will need to submit pull requests, although occasionally for a large patch series we might ask a submitter to send a pull request. This page diff --git a/docs/devel/trivial-patches.rst b/docs/devel/trivial-patches.rst index db3f2001da..9380c730f7 100644 --- a/docs/devel/trivial-patches.rst +++ b/docs/devel/trivial-patches.rst @@ -1,3 +1,5 @@ +.. _trivial-patches: + Trivial Patches =============== From 93e86b1664951f02fceed9ac312576f60232d503 Mon Sep 17 00:00:00 2001 From: Kashyap Chamarthy Date: Fri, 19 Nov 2021 20:31:18 +0100 Subject: [PATCH 032/421] docs: List more commit-message tags in "submitting-a-patch" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add some more examples of commonly used commit-message tags. (Thanks: Alex Bennée) Signed-off-by: Kashyap Chamarthy Message-Id: <20211119193118.949698-3-kchamart@redhat.com> Reviewed-by: Eric Blake Signed-off-by: Thomas Huth --- docs/devel/submitting-a-patch.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/devel/submitting-a-patch.rst b/docs/devel/submitting-a-patch.rst index 6acded5c93..e51259eb9c 100644 --- a/docs/devel/submitting-a-patch.rst +++ b/docs/devel/submitting-a-patch.rst @@ -195,6 +195,10 @@ Example:: Resolves: https://gitlab.com/qemu-project/qemu/-/issues/42 Buglink: https://bugs.launchpad.net/qemu/+bug/1804323`` +Some other tags that are used in commit messages include "Message-Id:" +"Tested-by:", "Acked-by:", "Reported-by:", "Suggested-by:". See ``git +log`` for these keywords for example usage. + .. _test_your_patches: Test your patches From b980c1aec63908074040e5cab135728e3b5db117 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Wed, 17 Nov 2021 22:07:02 +0100 Subject: [PATCH 033/421] Fix some typos in documentation (found by codespell) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Stefan Weil Message-Id: <20211117210702.1393570-1-sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé [thuth: "what's" --> "what is" as suggested by philmd] Signed-off-by: Thomas Huth --- docs/devel/multi-process.rst | 2 +- docs/devel/qgraph.rst | 2 +- docs/devel/writing-monitor-commands.rst | 2 +- docs/hyperv.txt | 2 +- docs/system/cpu-models-x86.rst.inc | 2 +- docs/system/devices/nvme.rst | 2 +- docs/system/gdb.rst | 2 +- docs/system/ppc/ppce500.rst | 2 +- docs/system/riscv/shakti-c.rst | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/devel/multi-process.rst b/docs/devel/multi-process.rst index e5758a79ab..5c857ff3b9 100644 --- a/docs/devel/multi-process.rst +++ b/docs/devel/multi-process.rst @@ -641,7 +641,7 @@ the CPU that issued the MMIO. +==========+========================+ | rid | range MMIO is within | +----------+------------------------+ -| offset | offset withing *rid* | +| offset | offset within *rid* | +----------+------------------------+ | type | e.g., load or store | +----------+------------------------+ diff --git a/docs/devel/qgraph.rst b/docs/devel/qgraph.rst index db44d71002..43342d9d65 100644 --- a/docs/devel/qgraph.rst +++ b/docs/devel/qgraph.rst @@ -14,7 +14,7 @@ support that device. Using only libqos APIs, the test has to manually take care of covering all the setups, and build the correct command line. -This also introduces backward compability issues: if a device/driver command +This also introduces backward compatibility issues: if a device/driver command line name is changed, all tests that use that will not work properly anymore and need to be adjusted. diff --git a/docs/devel/writing-monitor-commands.rst b/docs/devel/writing-monitor-commands.rst index b3e2c8481d..1693822f8f 100644 --- a/docs/devel/writing-monitor-commands.rst +++ b/docs/devel/writing-monitor-commands.rst @@ -677,7 +677,7 @@ return a single text string:: The ``HumanReadableText`` struct is intended to be used for all commands, under the ``x-`` name prefix that are returning unstructured -text targetted at humans. It should never be used for commands outside +text targeted at humans. It should never be used for commands outside the ``x-`` name prefix, as those should be using structured QAPI types. Implementing the QMP command diff --git a/docs/hyperv.txt b/docs/hyperv.txt index 5d99fd9a72..0417c183a3 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -195,7 +195,7 @@ The enlightenment allows to use Hyper-V SynIC with hardware APICv/AVIC enabled. Normally, Hyper-V SynIC disables these hardware feature and suggests the guest to use paravirtualized AutoEOI feature. Note: enabling this feature on old hardware (without APICv/AVIC support) may -have negative effect on guest's performace. +have negative effect on guest's performance. 3.19. hv-no-nonarch-coresharing=on/off/auto =========================================== diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc index 6e8be7d79b..7f6368f999 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -49,7 +49,7 @@ future OS and toolchains are likely to target newer ABIs. The table that follows illustrates which ABI compatibility levels can be satisfied by the QEMU CPU models. Note that the table only lists the long term stable CPU model versions (eg Haswell-v4). -In addition to whats listed, there are also many CPU model +In addition to what is listed, there are also many CPU model aliases which resolve to a different CPU model version, depending on the machine type is in use. diff --git a/docs/system/devices/nvme.rst b/docs/system/devices/nvme.rst index a1c0db01f6..b5acb2a9c1 100644 --- a/docs/system/devices/nvme.rst +++ b/docs/system/devices/nvme.rst @@ -70,7 +70,7 @@ namespaces and additional features, the ``nvme-ns`` device must be used. The namespaces defined by the ``nvme-ns`` device will attach to the most recently defined ``nvme-bus`` that is created by the ``nvme`` device. Namespace -identifers are allocated automatically, starting from ``1``. +identifiers are allocated automatically, starting from ``1``. There are a number of parameters available: diff --git a/docs/system/gdb.rst b/docs/system/gdb.rst index bdb42dae2f..453eb73f6c 100644 --- a/docs/system/gdb.rst +++ b/docs/system/gdb.rst @@ -56,7 +56,7 @@ machine has more than one CPU, QEMU exposes each CPU cluster as a separate "inferior", where each CPU within the cluster is a separate "thread". Most QEMU machine types have identical CPUs, so there is a single cluster which has all the CPUs in it. A few machine types are -heterogenous and have multiple clusters: for example the ``sifive_u`` +heterogeneous and have multiple clusters: for example the ``sifive_u`` machine has a cluster with one E51 core and a second cluster with four U54 cores. Here the E51 is the only thread in the first inferior, and the U54 cores are all threads in the second inferior. diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst index afc58f60f5..9beef39171 100644 --- a/docs/system/ppc/ppce500.rst +++ b/docs/system/ppc/ppce500.rst @@ -75,7 +75,7 @@ as the BIOS. QEMU follows below truth table to select which payload to execute: When both -bios and -kernel are present, QEMU loads U-Boot and U-Boot in turns automatically loads the kernel image specified by the -kernel parameter via U-Boot's built-in "bootm" command, hence a legacy uImage format is required in -such senario. +such scenario. Running Linux kernel -------------------- diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst index a6035d42b0..fea57f7b6b 100644 --- a/docs/system/riscv/shakti-c.rst +++ b/docs/system/riscv/shakti-c.rst @@ -45,7 +45,7 @@ Shakti SDK can be used to generate the baremetal example UART applications. Binary would be generated in: software/examples/uart_applns/loopback/output/loopback.shakti -You could also download the precompiled example applicatons using below +You could also download the precompiled example applications using below commands. .. code-block:: bash From 8f75cae2dda8a55eb3a6c712bd22b18a90c0a5ac Mon Sep 17 00:00:00 2001 From: "Rao, Lei" Date: Mon, 22 Nov 2021 15:49:46 +0800 Subject: [PATCH 034/421] docs: Drop deprecated 'props' from object-add In commit 5024340745 "qapi/qom: Drop deprecated 'props' from object-add" (v6.0.0), we also should update documents. Signed-off-by: Lei Rao Message-Id: <1637567387-28250-1-git-send-email-lei.rao@intel.com> Reviewed-by: Markus Armbruster Signed-off-by: Thomas Huth --- docs/COLO-FT.txt | 16 ++++++++-------- docs/system/authz.rst | 26 ++++++++++---------------- docs/throttle.txt | 8 +++----- docs/tools/qemu-nbd.rst | 2 +- 4 files changed, 22 insertions(+), 30 deletions(-) diff --git a/docs/COLO-FT.txt b/docs/COLO-FT.txt index 8d6d53a5a2..fd5ffcc6e5 100644 --- a/docs/COLO-FT.txt +++ b/docs/COLO-FT.txt @@ -289,11 +289,11 @@ Wait until disk is synced, then: {'execute': 'human-monitor-command', 'arguments':{ 'command-line': 'drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.2,file.port=9999,file.export=parent0,node-name=replication0'}} {'execute': 'x-blockdev-change', 'arguments':{ 'parent': 'colo-disk0', 'node': 'replication0' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-mirror', 'id': 'm0', 'props': { 'netdev': 'hn0', 'queue': 'tx', 'outdev': 'mirror0' } } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire0', 'props': { 'netdev': 'hn0', 'queue': 'rx', 'indev': 'compare_out' } } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire1', 'props': { 'netdev': 'hn0', 'queue': 'rx', 'outdev': 'compare0' } } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-mirror', 'id': 'm0', 'netdev': 'hn0', 'queue': 'tx', 'outdev': 'mirror0' } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire0', 'netdev': 'hn0', 'queue': 'rx', 'indev': 'compare_out' } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire1', 'netdev': 'hn0', 'queue': 'rx', 'outdev': 'compare0' } } {'execute': 'object-add', 'arguments':{ 'qom-type': 'iothread', 'id': 'iothread1' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'colo-compare', 'id': 'comp0', 'props': { 'primary_in': 'compare0-0', 'secondary_in': 'compare1', 'outdev': 'compare_out0', 'iothread': 'iothread1' } } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'colo-compare', 'id': 'comp0', 'primary_in': 'compare0-0', 'secondary_in': 'compare1', 'outdev': 'compare_out0', 'iothread': 'iothread1' } } {'execute': 'migrate-set-capabilities', 'arguments':{ 'capabilities': [ {'capability': 'x-colo', 'state': true } ] } } {'execute': 'migrate', 'arguments':{ 'uri': 'tcp:127.0.0.2:9998' } } @@ -318,11 +318,11 @@ Wait until disk is synced, then: {'execute': 'human-monitor-command', 'arguments':{ 'command-line': 'drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.1,file.port=9999,file.export=parent0,node-name=replication0'}} {'execute': 'x-blockdev-change', 'arguments':{ 'parent': 'colo-disk0', 'node': 'replication0' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-mirror', 'id': 'm0', 'props': { 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'tx', 'outdev': 'mirror0' } } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire0', 'props': { 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'rx', 'indev': 'compare_out' } } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire1', 'props': { 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'rx', 'outdev': 'compare0' } } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-mirror', 'id': 'm0', 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'tx', 'outdev': 'mirror0' } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire0', 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'rx', 'indev': 'compare_out' } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire1', 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'rx', 'outdev': 'compare0' } } {'execute': 'object-add', 'arguments':{ 'qom-type': 'iothread', 'id': 'iothread1' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'colo-compare', 'id': 'comp0', 'props': { 'primary_in': 'compare0-0', 'secondary_in': 'compare1', 'outdev': 'compare_out0', 'iothread': 'iothread1' } } } +{'execute': 'object-add', 'arguments':{ 'qom-type': 'colo-compare', 'id': 'comp0', 'primary_in': 'compare0-0', 'secondary_in': 'compare1', 'outdev': 'compare_out0', 'iothread': 'iothread1' } } {'execute': 'migrate-set-capabilities', 'arguments':{ 'capabilities': [ {'capability': 'x-colo', 'state': true } ] } } {'execute': 'migrate', 'arguments':{ 'uri': 'tcp:127.0.0.1:9998' } } diff --git a/docs/system/authz.rst b/docs/system/authz.rst index 942af39602..55b7315e49 100644 --- a/docs/system/authz.rst +++ b/docs/system/authz.rst @@ -77,9 +77,7 @@ To create an instance of this driver via QMP: "arguments": { "qom-type": "authz-simple", "id": "authz0", - "props": { - "identity": "fred" - } + "identity": "fred" } } @@ -110,15 +108,13 @@ To create an instance of this class via QMP: "arguments": { "qom-type": "authz-list", "id": "authz0", - "props": { - "rules": [ - { "match": "fred", "policy": "allow", "format": "exact" }, - { "match": "bob", "policy": "allow", "format": "exact" }, - { "match": "danb", "policy": "deny", "format": "exact" }, - { "match": "dan*", "policy": "allow", "format": "glob" } - ], - "policy": "deny" - } + "rules": [ + { "match": "fred", "policy": "allow", "format": "exact" }, + { "match": "bob", "policy": "allow", "format": "exact" }, + { "match": "danb", "policy": "deny", "format": "exact" }, + { "match": "dan*", "policy": "allow", "format": "glob" } + ], + "policy": "deny" } } @@ -143,10 +139,8 @@ To create an instance of this class via QMP: "arguments": { "qom-type": "authz-list-file", "id": "authz0", - "props": { - "filename": "/etc/qemu/myvm-vnc.acl", - "refresh": true - } + "filename": "/etc/qemu/myvm-vnc.acl", + "refresh": true } } diff --git a/docs/throttle.txt b/docs/throttle.txt index b5b78b7326..0a0453a5ee 100644 --- a/docs/throttle.txt +++ b/docs/throttle.txt @@ -273,11 +273,9 @@ A group can be created using the object-add QMP function: "arguments": { "qom-type": "throttle-group", "id": "group0", - "props": { - "limits" : { - "iops-total": 1000 - "bps-write": 2097152 - } + "limits" : { + "iops-total": 1000, + "bps-write": 2097152 } } } diff --git a/docs/tools/qemu-nbd.rst b/docs/tools/qemu-nbd.rst index 56e54cd441..726cd18960 100644 --- a/docs/tools/qemu-nbd.rst +++ b/docs/tools/qemu-nbd.rst @@ -31,7 +31,7 @@ driver options if ``--image-opts`` is specified. *dev* is an NBD device. -.. option:: --object type,id=ID,...props... +.. option:: --object type,id=ID,... Define a new instance of the *type* object class identified by *ID*. See the :manpage:`qemu(1)` manual page for full details of the properties From eff708a876b40fe71bedb792d084972d7a52166a Mon Sep 17 00:00:00 2001 From: "Rao, Lei" Date: Mon, 22 Nov 2021 15:49:47 +0800 Subject: [PATCH 035/421] docs: Use double quotes instead of single quotes for COLO Signed-off-by: Lei Rao Message-Id: <1637567387-28250-2-git-send-email-lei.rao@intel.com> Reviewed-by: Markus Armbruster Signed-off-by: Thomas Huth --- docs/COLO-FT.txt | 106 ++++++++++++++++++------------------- docs/block-replication.txt | 52 +++++++++--------- 2 files changed, 79 insertions(+), 79 deletions(-) diff --git a/docs/COLO-FT.txt b/docs/COLO-FT.txt index fd5ffcc6e5..8ec653f81c 100644 --- a/docs/COLO-FT.txt +++ b/docs/COLO-FT.txt @@ -209,9 +209,9 @@ children.0=childs0 \ 3. On Secondary VM's QEMU monitor, issue command -{'execute':'qmp_capabilities'} -{'execute': 'nbd-server-start', 'arguments': {'addr': {'type': 'inet', 'data': {'host': '0.0.0.0', 'port': '9999'} } } } -{'execute': 'nbd-server-add', 'arguments': {'device': 'parent0', 'writable': true } } +{"execute":"qmp_capabilities"} +{"execute": "nbd-server-start", "arguments": {"addr": {"type": "inet", "data": {"host": "0.0.0.0", "port": "9999"} } } } +{"execute": "nbd-server-add", "arguments": {"device": "parent0", "writable": true } } Note: a. The qmp command nbd-server-start and nbd-server-add must be run @@ -222,11 +222,11 @@ Note: will be merged into the parent disk on failover. 4. On Primary VM's QEMU monitor, issue command: -{'execute':'qmp_capabilities'} -{'execute': 'human-monitor-command', 'arguments': {'command-line': 'drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.2,file.port=9999,file.export=parent0,node-name=replication0'}} -{'execute': 'x-blockdev-change', 'arguments':{'parent': 'colo-disk0', 'node': 'replication0' } } -{'execute': 'migrate-set-capabilities', 'arguments': {'capabilities': [ {'capability': 'x-colo', 'state': true } ] } } -{'execute': 'migrate', 'arguments': {'uri': 'tcp:127.0.0.2:9998' } } +{"execute":"qmp_capabilities"} +{"execute": "human-monitor-command", "arguments": {"command-line": "drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.2,file.port=9999,file.export=parent0,node-name=replication0"}} +{"execute": "x-blockdev-change", "arguments":{"parent": "colo-disk0", "node": "replication0" } } +{"execute": "migrate-set-capabilities", "arguments": {"capabilities": [ {"capability": "x-colo", "state": true } ] } } +{"execute": "migrate", "arguments": {"uri": "tcp:127.0.0.2:9998" } } Note: a. There should be only one NBD Client for each primary disk. @@ -249,59 +249,59 @@ if you want to resume the replication, follow "Secondary resume replication" == Primary Failover == The Secondary died, resume on the Primary -{'execute': 'x-blockdev-change', 'arguments':{ 'parent': 'colo-disk0', 'child': 'children.1'} } -{'execute': 'human-monitor-command', 'arguments':{ 'command-line': 'drive_del replication0' } } -{'execute': 'object-del', 'arguments':{ 'id': 'comp0' } } -{'execute': 'object-del', 'arguments':{ 'id': 'iothread1' } } -{'execute': 'object-del', 'arguments':{ 'id': 'm0' } } -{'execute': 'object-del', 'arguments':{ 'id': 'redire0' } } -{'execute': 'object-del', 'arguments':{ 'id': 'redire1' } } -{'execute': 'x-colo-lost-heartbeat' } +{"execute": "x-blockdev-change", "arguments":{ "parent": "colo-disk0", "child": "children.1"} } +{"execute": "human-monitor-command", "arguments":{ "command-line": "drive_del replication0" } } +{"execute": "object-del", "arguments":{ "id": "comp0" } } +{"execute": "object-del", "arguments":{ "id": "iothread1" } } +{"execute": "object-del", "arguments":{ "id": "m0" } } +{"execute": "object-del", "arguments":{ "id": "redire0" } } +{"execute": "object-del", "arguments":{ "id": "redire1" } } +{"execute": "x-colo-lost-heartbeat" } == Secondary Failover == The Primary died, resume on the Secondary and prepare to become the new Primary -{'execute': 'nbd-server-stop'} -{'execute': 'x-colo-lost-heartbeat'} +{"execute": "nbd-server-stop"} +{"execute": "x-colo-lost-heartbeat"} -{'execute': 'object-del', 'arguments':{ 'id': 'f2' } } -{'execute': 'object-del', 'arguments':{ 'id': 'f1' } } -{'execute': 'chardev-remove', 'arguments':{ 'id': 'red1' } } -{'execute': 'chardev-remove', 'arguments':{ 'id': 'red0' } } +{"execute": "object-del", "arguments":{ "id": "f2" } } +{"execute": "object-del", "arguments":{ "id": "f1" } } +{"execute": "chardev-remove", "arguments":{ "id": "red1" } } +{"execute": "chardev-remove", "arguments":{ "id": "red0" } } -{'execute': 'chardev-add', 'arguments':{ 'id': 'mirror0', 'backend': {'type': 'socket', 'data': {'addr': { 'type': 'inet', 'data': { 'host': '0.0.0.0', 'port': '9003' } }, 'server': true } } } } -{'execute': 'chardev-add', 'arguments':{ 'id': 'compare1', 'backend': {'type': 'socket', 'data': {'addr': { 'type': 'inet', 'data': { 'host': '0.0.0.0', 'port': '9004' } }, 'server': true } } } } -{'execute': 'chardev-add', 'arguments':{ 'id': 'compare0', 'backend': {'type': 'socket', 'data': {'addr': { 'type': 'inet', 'data': { 'host': '127.0.0.1', 'port': '9001' } }, 'server': true } } } } -{'execute': 'chardev-add', 'arguments':{ 'id': 'compare0-0', 'backend': {'type': 'socket', 'data': {'addr': { 'type': 'inet', 'data': { 'host': '127.0.0.1', 'port': '9001' } }, 'server': false } } } } -{'execute': 'chardev-add', 'arguments':{ 'id': 'compare_out', 'backend': {'type': 'socket', 'data': {'addr': { 'type': 'inet', 'data': { 'host': '127.0.0.1', 'port': '9005' } }, 'server': true } } } } -{'execute': 'chardev-add', 'arguments':{ 'id': 'compare_out0', 'backend': {'type': 'socket', 'data': {'addr': { 'type': 'inet', 'data': { 'host': '127.0.0.1', 'port': '9005' } }, 'server': false } } } } +{"execute": "chardev-add", "arguments":{ "id": "mirror0", "backend": {"type": "socket", "data": {"addr": { "type": "inet", "data": { "host": "0.0.0.0", "port": "9003" } }, "server": true } } } } +{"execute": "chardev-add", "arguments":{ "id": "compare1", "backend": {"type": "socket", "data": {"addr": { "type": "inet", "data": { "host": "0.0.0.0", "port": "9004" } }, "server": true } } } } +{"execute": "chardev-add", "arguments":{ "id": "compare0", "backend": {"type": "socket", "data": {"addr": { "type": "inet", "data": { "host": "127.0.0.1", "port": "9001" } }, "server": true } } } } +{"execute": "chardev-add", "arguments":{ "id": "compare0-0", "backend": {"type": "socket", "data": {"addr": { "type": "inet", "data": { "host": "127.0.0.1", "port": "9001" } }, "server": false } } } } +{"execute": "chardev-add", "arguments":{ "id": "compare_out", "backend": {"type": "socket", "data": {"addr": { "type": "inet", "data": { "host": "127.0.0.1", "port": "9005" } }, "server": true } } } } +{"execute": "chardev-add", "arguments":{ "id": "compare_out0", "backend": {"type": "socket", "data": {"addr": { "type": "inet", "data": { "host": "127.0.0.1", "port": "9005" } }, "server": false } } } } == Primary resume replication == Resume replication after new Secondary is up. Start the new Secondary (Steps 2 and 3 above), then on the Primary: -{'execute': 'drive-mirror', 'arguments':{ 'device': 'colo-disk0', 'job-id': 'resync', 'target': 'nbd://127.0.0.2:9999/parent0', 'mode': 'existing', 'format': 'raw', 'sync': 'full'} } +{"execute": "drive-mirror", "arguments":{ "device": "colo-disk0", "job-id": "resync", "target": "nbd://127.0.0.2:9999/parent0", "mode": "existing", "format": "raw", "sync": "full"} } Wait until disk is synced, then: -{'execute': 'stop'} -{'execute': 'block-job-cancel', 'arguments':{ 'device': 'resync'} } +{"execute": "stop"} +{"execute": "block-job-cancel", "arguments":{ "device": "resync"} } -{'execute': 'human-monitor-command', 'arguments':{ 'command-line': 'drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.2,file.port=9999,file.export=parent0,node-name=replication0'}} -{'execute': 'x-blockdev-change', 'arguments':{ 'parent': 'colo-disk0', 'node': 'replication0' } } +{"execute": "human-monitor-command", "arguments":{ "command-line": "drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.2,file.port=9999,file.export=parent0,node-name=replication0"}} +{"execute": "x-blockdev-change", "arguments":{ "parent": "colo-disk0", "node": "replication0" } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-mirror', 'id': 'm0', 'netdev': 'hn0', 'queue': 'tx', 'outdev': 'mirror0' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire0', 'netdev': 'hn0', 'queue': 'rx', 'indev': 'compare_out' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire1', 'netdev': 'hn0', 'queue': 'rx', 'outdev': 'compare0' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'iothread', 'id': 'iothread1' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'colo-compare', 'id': 'comp0', 'primary_in': 'compare0-0', 'secondary_in': 'compare1', 'outdev': 'compare_out0', 'iothread': 'iothread1' } } +{"execute": "object-add", "arguments":{ "qom-type": "filter-mirror", "id": "m0", "netdev": "hn0", "queue": "tx", "outdev": "mirror0" } } +{"execute": "object-add", "arguments":{ "qom-type": "filter-redirector", "id": "redire0", "netdev": "hn0", "queue": "rx", "indev": "compare_out" } } +{"execute": "object-add", "arguments":{ "qom-type": "filter-redirector", "id": "redire1", "netdev": "hn0", "queue": "rx", "outdev": "compare0" } } +{"execute": "object-add", "arguments":{ "qom-type": "iothread", "id": "iothread1" } } +{"execute": "object-add", "arguments":{ "qom-type": "colo-compare", "id": "comp0", "primary_in": "compare0-0", "secondary_in": "compare1", "outdev": "compare_out0", "iothread": "iothread1" } } -{'execute': 'migrate-set-capabilities', 'arguments':{ 'capabilities': [ {'capability': 'x-colo', 'state': true } ] } } -{'execute': 'migrate', 'arguments':{ 'uri': 'tcp:127.0.0.2:9998' } } +{"execute": "migrate-set-capabilities", "arguments":{ "capabilities": [ {"capability": "x-colo", "state": true } ] } } +{"execute": "migrate", "arguments":{ "uri": "tcp:127.0.0.2:9998" } } Note: If this Primary previously was a Secondary, then we need to insert the filters before the filter-rewriter by using the -"'insert': 'before', 'position': 'id=rew0'" Options. See below. +""insert": "before", "position": "id=rew0"" Options. See below. == Secondary resume replication == Become Primary and resume replication after new Secondary is up. Note @@ -309,23 +309,23 @@ that now 127.0.0.1 is the Secondary and 127.0.0.2 is the Primary. Start the new Secondary (Steps 2 and 3 above, but with primary_ip=127.0.0.2), then on the old Secondary: -{'execute': 'drive-mirror', 'arguments':{ 'device': 'colo-disk0', 'job-id': 'resync', 'target': 'nbd://127.0.0.1:9999/parent0', 'mode': 'existing', 'format': 'raw', 'sync': 'full'} } +{"execute": "drive-mirror", "arguments":{ "device": "colo-disk0", "job-id": "resync", "target": "nbd://127.0.0.1:9999/parent0", "mode": "existing", "format": "raw", "sync": "full"} } Wait until disk is synced, then: -{'execute': 'stop'} -{'execute': 'block-job-cancel', 'arguments':{ 'device': 'resync' } } +{"execute": "stop"} +{"execute": "block-job-cancel", "arguments":{ "device": "resync" } } -{'execute': 'human-monitor-command', 'arguments':{ 'command-line': 'drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.1,file.port=9999,file.export=parent0,node-name=replication0'}} -{'execute': 'x-blockdev-change', 'arguments':{ 'parent': 'colo-disk0', 'node': 'replication0' } } +{"execute": "human-monitor-command", "arguments":{ "command-line": "drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=127.0.0.1,file.port=9999,file.export=parent0,node-name=replication0"}} +{"execute": "x-blockdev-change", "arguments":{ "parent": "colo-disk0", "node": "replication0" } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-mirror', 'id': 'm0', 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'tx', 'outdev': 'mirror0' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire0', 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'rx', 'indev': 'compare_out' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'filter-redirector', 'id': 'redire1', 'insert': 'before', 'position': 'id=rew0', 'netdev': 'hn0', 'queue': 'rx', 'outdev': 'compare0' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'iothread', 'id': 'iothread1' } } -{'execute': 'object-add', 'arguments':{ 'qom-type': 'colo-compare', 'id': 'comp0', 'primary_in': 'compare0-0', 'secondary_in': 'compare1', 'outdev': 'compare_out0', 'iothread': 'iothread1' } } +{"execute": "object-add", "arguments":{ "qom-type": "filter-mirror", "id": "m0", "insert": "before", "position": "id=rew0", "netdev": "hn0", "queue": "tx", "outdev": "mirror0" } } +{"execute": "object-add", "arguments":{ "qom-type": "filter-redirector", "id": "redire0", "insert": "before", "position": "id=rew0", "netdev": "hn0", "queue": "rx", "indev": "compare_out" } } +{"execute": "object-add", "arguments":{ "qom-type": "filter-redirector", "id": "redire1", "insert": "before", "position": "id=rew0", "netdev": "hn0", "queue": "rx", "outdev": "compare0" } } +{"execute": "object-add", "arguments":{ "qom-type": "iothread", "id": "iothread1" } } +{"execute": "object-add", "arguments":{ "qom-type": "colo-compare", "id": "comp0", "primary_in": "compare0-0", "secondary_in": "compare1", "outdev": "compare_out0", "iothread": "iothread1" } } -{'execute': 'migrate-set-capabilities', 'arguments':{ 'capabilities': [ {'capability': 'x-colo', 'state': true } ] } } -{'execute': 'migrate', 'arguments':{ 'uri': 'tcp:127.0.0.1:9998' } } +{"execute": "migrate-set-capabilities", "arguments":{ "capabilities": [ {"capability": "x-colo", "state": true } ] } } +{"execute": "migrate", "arguments":{ "uri": "tcp:127.0.0.1:9998" } } == TODO == 1. Support shared storage. diff --git a/docs/block-replication.txt b/docs/block-replication.txt index 59eb2b33b3..b0f23761c6 100644 --- a/docs/block-replication.txt +++ b/docs/block-replication.txt @@ -156,15 +156,15 @@ Primary: children.0.driver=raw Run qmp command in primary qemu: - { 'execute': 'human-monitor-command', - 'arguments': { - 'command-line': 'drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=xxxx,file.port=xxxx,file.export=colo1,node-name=nbd_client1' + { "execute": "human-monitor-command", + "arguments": { + "command-line": "drive_add -n buddy driver=replication,mode=primary,file.driver=nbd,file.host=xxxx,file.port=xxxx,file.export=colo1,node-name=nbd_client1" } } - { 'execute': 'x-blockdev-change', - 'arguments': { - 'parent': 'colo1', - 'node': 'nbd_client1' + { "execute": "x-blockdev-change", + "arguments": { + "parent": "colo1", + "node": "nbd_client1" } } Note: @@ -189,21 +189,21 @@ Secondary: vote-threshold=1,children.0=childs1 Then run qmp command in secondary qemu: - { 'execute': 'nbd-server-start', - 'arguments': { - 'addr': { - 'type': 'inet', - 'data': { - 'host': 'xxx', - 'port': 'xxx' + { "execute": "nbd-server-start", + "arguments": { + "addr": { + "type": "inet", + "data": { + "host": "xxx", + "port": "xxx" } } } } - { 'execute': 'nbd-server-add', - 'arguments': { - 'device': 'colo1', - 'writable': true + { "execute": "nbd-server-add", + "arguments": { + "device": "colo1", + "writable": true } } @@ -223,22 +223,22 @@ After Failover: Primary: The secondary host is down, so we should run the following qmp command to remove the nbd child from the quorum: - { 'execute': 'x-blockdev-change', - 'arguments': { - 'parent': 'colo1', - 'child': 'children.1' + { "execute": "x-blockdev-change", + "arguments": { + "parent": "colo1", + "child": "children.1" } } - { 'execute': 'human-monitor-command', - 'arguments': { - 'command-line': 'drive_del xxxx' + { "execute": "human-monitor-command", + "arguments": { + "command-line": "drive_del xxxx" } } Note: there is no qmp command to remove the blockdev now Secondary: The primary host is down, so we should do the following thing: - { 'execute': 'nbd-server-stop' } + { "execute": "nbd-server-stop" } Promote Secondary to Primary: see COLO-FT.txt From c5ba62195427d65a44472901cff3dddffc14b3b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Thu, 18 Nov 2021 20:27:44 +0100 Subject: [PATCH 036/421] docs: Render binary names as monospaced text MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211118192744.64325-1-philmd@redhat.com> Reviewed-by: Darren Kenny Signed-off-by: Thomas Huth --- docs/about/removed-features.rst | 8 ++++---- docs/devel/build-system.rst | 6 +++--- docs/devel/multi-process.rst | 6 +++--- docs/devel/testing.rst | 8 ++++---- docs/image-fuzzer.txt | 6 +++--- docs/system/arm/orangepi.rst | 2 +- docs/system/images.rst | 2 +- docs/system/qemu-block-drivers.rst.inc | 6 +++--- docs/system/tls.rst | 2 +- docs/tools/qemu-img.rst | 18 +++++++++--------- docs/tools/qemu-nbd.rst | 4 ++-- docs/tools/qemu-storage-daemon.rst | 7 ++++--- docs/tools/virtiofsd.rst | 4 ++-- 13 files changed, 40 insertions(+), 39 deletions(-) diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index 9d0d90c90d..d42c3341de 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -658,8 +658,8 @@ enforce that any failure to open the backing image (including if the backing file is missing or an incorrect format was specified) is an error when ``-u`` is not used. -qemu-img amend to adjust backing file (removed in 6.1) -'''''''''''''''''''''''''''''''''''''''''''''''''''''' +``qemu-img amend`` to adjust backing file (removed in 6.1) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' The use of ``qemu-img amend`` to modify the name or format of a qcow2 backing image was never fully documented or tested, and interferes @@ -670,8 +670,8 @@ backing chain should be performed with ``qemu-img rebase -u`` either before or after the remaining changes being performed by amend, as appropriate. -qemu-img backing file without format (removed in 6.1) -''''''''''''''''''''''''''''''''''''''''''''''''''''' +``qemu-img`` backing file without format (removed in 6.1) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''' The use of ``qemu-img create``, ``qemu-img rebase``, or ``qemu-img convert`` to create or modify an image that depends on a backing file diff --git a/docs/devel/build-system.rst b/docs/devel/build-system.rst index 7a83f5fc0d..431caba7aa 100644 --- a/docs/devel/build-system.rst +++ b/docs/devel/build-system.rst @@ -121,11 +121,11 @@ process for: 1) executables, which include: - - Tools - qemu-img, qemu-nbd, qga (guest agent), etc + - Tools - ``qemu-img``, ``qemu-nbd``, ``qga`` (guest agent), etc - - System emulators - qemu-system-$ARCH + - System emulators - ``qemu-system-$ARCH`` - - Userspace emulators - qemu-$ARCH + - Userspace emulators - ``qemu-$ARCH`` - Unit tests diff --git a/docs/devel/multi-process.rst b/docs/devel/multi-process.rst index 5c857ff3b9..e4801751f2 100644 --- a/docs/devel/multi-process.rst +++ b/docs/devel/multi-process.rst @@ -187,9 +187,9 @@ desired, in which the emulation application should only be allowed to access the files or devices the VM it's running on behalf of can access. #### qemu-io model -Qemu-io is a test harness used to test changes to the QEMU block backend -object code. (e.g., the code that implements disk images for disk driver -emulation) Qemu-io is not a device emulation application per se, but it +``qemu-io`` is a test harness used to test changes to the QEMU block backend +object code (e.g., the code that implements disk images for disk driver +emulation). ``qemu-io`` is not a device emulation application per se, but it does compile the QEMU block objects into a separate binary from the main QEMU one. This could be useful for disk device emulation, since its emulation applications will need to include the QEMU block objects. diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index 60c59023e5..755343c7dd 100644 --- a/docs/devel/testing.rst +++ b/docs/devel/testing.rst @@ -564,11 +564,11 @@ exploiting a QEMU security bug to compromise the host. QEMU binaries ~~~~~~~~~~~~~ -By default, qemu-system-x86_64 is searched in $PATH to run the guest. If there -isn't one, or if it is older than 2.10, the test won't work. In this case, +By default, ``qemu-system-x86_64`` is searched in $PATH to run the guest. If +there isn't one, or if it is older than 2.10, the test won't work. In this case, provide the QEMU binary in env var: ``QEMU=/path/to/qemu-2.10+``. -Likewise the path to qemu-img can be set in QEMU_IMG environment variable. +Likewise the path to ``qemu-img`` can be set in QEMU_IMG environment variable. Make jobs ~~~~~~~~~ @@ -650,7 +650,7 @@ supported. To start the fuzzer, run tests/image-fuzzer/runner.py -c '[["qemu-img", "info", "$test_img"]]' /tmp/test qcow2 -Alternatively, some command different from "qemu-img info" can be tested, by +Alternatively, some command different from ``qemu-img info`` can be tested, by changing the ``-c`` option. Integration tests using the Avocado Framework diff --git a/docs/image-fuzzer.txt b/docs/image-fuzzer.txt index 3e23ebec33..279cc8c807 100644 --- a/docs/image-fuzzer.txt +++ b/docs/image-fuzzer.txt @@ -51,10 +51,10 @@ assumes that core dumps will be generated in the current working directory. For comprehensive test results, please, set up your test environment properly. -Paths to binaries under test (SUTs) qemu-img and qemu-io are retrieved from -environment variables. If the environment check fails the runner will +Paths to binaries under test (SUTs) ``qemu-img`` and ``qemu-io`` are retrieved +from environment variables. If the environment check fails the runner will use SUTs installed in system paths. -qemu-img is required for creation of backing files, so it's mandatory to set +``qemu-img`` is required for creation of backing files, so it's mandatory to set the related environment variable if it's not installed in the system path. For details about environment variables see qemu-iotests/check. diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst index c55694dd91..83c7445197 100644 --- a/docs/system/arm/orangepi.rst +++ b/docs/system/arm/orangepi.rst @@ -128,7 +128,7 @@ Alternatively, you can also choose to build you own image with buildroot using the orangepi_pc_defconfig. Also see https://buildroot.org for more information. When using an image as an SD card, it must be resized to a power of two. This can be -done with the qemu-img command. It is recommended to only increase the image size +done with the ``qemu-img`` command. It is recommended to only increase the image size instead of shrinking it to a power of two, to avoid loss of data. For example, to prepare a downloaded Armbian image, first extract it and then increase its size to one gigabyte as follows: diff --git a/docs/system/images.rst b/docs/system/images.rst index 3d9144e625..d000bd6b6f 100644 --- a/docs/system/images.rst +++ b/docs/system/images.rst @@ -20,7 +20,7 @@ where myimage.img is the disk image filename and mysize is its size in kilobytes. You can add an ``M`` suffix to give the size in megabytes and a ``G`` suffix for gigabytes. -See the qemu-img invocation documentation for more information. +See the ``qemu-img`` invocation documentation for more information. .. _disk_005fimages_005fsnapshot_005fmode: diff --git a/docs/system/qemu-block-drivers.rst.inc b/docs/system/qemu-block-drivers.rst.inc index 16225710eb..e313784426 100644 --- a/docs/system/qemu-block-drivers.rst.inc +++ b/docs/system/qemu-block-drivers.rst.inc @@ -511,13 +511,13 @@ of an inet socket: |qemu_system| linux.img -hdb nbd+unix://?socket=/tmp/my_socket -In this case, the block device must be exported using qemu-nbd: +In this case, the block device must be exported using ``qemu-nbd``: .. parsed-literal:: qemu-nbd --socket=/tmp/my_socket my_disk.qcow2 -The use of qemu-nbd allows sharing of a disk between several guests: +The use of ``qemu-nbd`` allows sharing of a disk between several guests: .. parsed-literal:: @@ -530,7 +530,7 @@ and then you can use it with two guests: |qemu_system| linux1.img -hdb nbd+unix://?socket=/tmp/my_socket |qemu_system| linux2.img -hdb nbd+unix://?socket=/tmp/my_socket -If the nbd-server uses named exports (supported since NBD 2.9.18, or with QEMU's +If the ``nbd-server`` uses named exports (supported since NBD 2.9.18, or with QEMU's own embedded NBD server), you must specify an export name in the URI: .. parsed-literal:: diff --git a/docs/system/tls.rst b/docs/system/tls.rst index b0973afe1b..1a04674362 100644 --- a/docs/system/tls.rst +++ b/docs/system/tls.rst @@ -311,7 +311,7 @@ containing one or more usernames and random keys:: mkdir -m 0700 /tmp/keys psktool -u rich -p /tmp/keys/keys.psk -TLS-enabled servers such as qemu-nbd can use this directory like so:: +TLS-enabled servers such as ``qemu-nbd`` can use this directory like so:: qemu-nbd \ -t -x / \ diff --git a/docs/tools/qemu-img.rst b/docs/tools/qemu-img.rst index c0a4443146..d663dd92bd 100644 --- a/docs/tools/qemu-img.rst +++ b/docs/tools/qemu-img.rst @@ -127,9 +127,9 @@ by the used format or see the format descriptions below for details. .. option:: -S SIZE Indicates the consecutive number of bytes that must contain only zeros - for qemu-img to create a sparse image during conversion. This value is rounded - down to the nearest 512 bytes. You may use the common size suffixes like - ``k`` for kilobytes. + for ``qemu-img`` to create a sparse image during conversion. This value is + rounded down to the nearest 512 bytes. You may use the common size suffixes + like ``k`` for kilobytes. .. option:: -t CACHE @@ -431,7 +431,7 @@ Command description: suppressed from the destination image. *SPARSE_SIZE* indicates the consecutive number of bytes (defaults to 4k) - that must contain only zeros for qemu-img to create a sparse image during + that must contain only zeros for ``qemu-img`` to create a sparse image during conversion. If *SPARSE_SIZE* is 0, the source will not be scanned for unallocated or zero sectors, and the destination image will always be fully allocated. @@ -447,7 +447,7 @@ Command description: If the ``-n`` option is specified, the target volume creation will be skipped. This is useful for formats such as ``rbd`` if the target volume has already been created with site specific options that cannot - be supplied through qemu-img. + be supplied through ``qemu-img``. Out of order writes can be enabled with ``-W`` to improve performance. This is only recommended for preallocated devices like host devices or other @@ -472,7 +472,7 @@ Command description: If the option *BACKING_FILE* is specified, then the image will record only the differences from *BACKING_FILE*. No size needs to be specified in this case. *BACKING_FILE* will never be modified unless you use the - ``commit`` monitor command (or qemu-img commit). + ``commit`` monitor command (or ``qemu-img commit``). If a relative path name is given, the backing file is looked up relative to the directory containing *FILENAME*. @@ -684,7 +684,7 @@ Command description: Safe mode This is the default mode and performs a real rebase operation. The - new backing file may differ from the old one and qemu-img rebase + new backing file may differ from the old one and ``qemu-img rebase`` will take care of keeping the guest-visible content of *FILENAME* unchanged. @@ -697,7 +697,7 @@ Command description: exists. Unsafe mode - qemu-img uses the unsafe mode if ``-u`` is specified. In this + ``qemu-img`` uses the unsafe mode if ``-u`` is specified. In this mode, only the backing file name and format of *FILENAME* is changed without any checks on the file contents. The user must take care of specifying the correct new backing file, or the guest-visible @@ -735,7 +735,7 @@ Command description: sizes accordingly. Failure to do so will result in data loss! When shrinking images, the ``--shrink`` option must be given. This informs - qemu-img that the user acknowledges all loss of data beyond the truncated + ``qemu-img`` that the user acknowledges all loss of data beyond the truncated image's end. After using this command to grow a disk image, you must use file system and diff --git a/docs/tools/qemu-nbd.rst b/docs/tools/qemu-nbd.rst index 726cd18960..6031f96893 100644 --- a/docs/tools/qemu-nbd.rst +++ b/docs/tools/qemu-nbd.rst @@ -38,7 +38,7 @@ driver options if ``--image-opts`` is specified. supported. The common object types that it makes sense to define are the ``secret`` object, which is used to supply passwords and/or encryption keys, and the ``tls-creds`` object, which is used to supply TLS - credentials for the qemu-nbd server or client. + credentials for the ``qemu-nbd`` server or client. .. option:: -p, --port=PORT @@ -238,7 +238,7 @@ daemon: Expose the guest-visible contents of a qcow2 file via a block device /dev/nbd0 (and possibly creating /dev/nbd0p1 and friends for partitions found within), then disconnect the device when done. -Access to bind qemu-nbd to an /dev/nbd device generally requires root +Access to bind ``qemu-nbd`` to a /dev/nbd device generally requires root privileges, and may also require the execution of ``modprobe nbd`` to enable the kernel NBD client module. *CAUTION*: Do not use this method to mount filesystems from an untrusted guest image - a diff --git a/docs/tools/qemu-storage-daemon.rst b/docs/tools/qemu-storage-daemon.rst index b8ef4486f1..3e5a9dc032 100644 --- a/docs/tools/qemu-storage-daemon.rst +++ b/docs/tools/qemu-storage-daemon.rst @@ -10,9 +10,10 @@ Synopsis Description ----------- -qemu-storage-daemon provides disk image functionality from QEMU, qemu-img, and -qemu-nbd in a long-running process controlled via QMP commands without running -a virtual machine. It can export disk images, run block job operations, and +``qemu-storage-daemon`` provides disk image functionality from QEMU, +``qemu-img``, and ``qemu-nbd`` in a long-running process controlled via QMP +commands without running a virtual machine. +It can export disk images, run block job operations, and perform other disk-related operations. The daemon is controlled via a QMP monitor and initial configuration from the command-line. diff --git a/docs/tools/virtiofsd.rst b/docs/tools/virtiofsd.rst index cc31402830..07ac0be551 100644 --- a/docs/tools/virtiofsd.rst +++ b/docs/tools/virtiofsd.rst @@ -136,8 +136,8 @@ Extended attribute (xattr) mapping By default the name of xattr's used by the client are passed through to the server file system. This can be a problem where either those xattr names are used by something on the server (e.g. selinux client/server confusion) or if the -virtiofsd is running in a container with restricted privileges where it cannot -access some attributes. +``virtiofsd`` is running in a container with restricted privileges where it +cannot access some attributes. Mapping syntax ~~~~~~~~~~~~~~ From 33a0c404fb90a3fa8eea6ebf5c535fc7bc0b9912 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Mon, 22 Nov 2021 18:17:17 +0000 Subject: [PATCH 037/421] hw/intc/arm_gicv3_its: Revert version increments in vmstate_its Commit 18f6290a6a ("hw/intc: GICv3 ITS initial framework") incremented version_id and minimum_version_id fields of VMStateDescription vmstate_its. This breaks the migration between 6.2 and 6.1 with the following message: qemu-system-aarch64: savevm: unsupported version 1 for 'arm_gicv3_its' v0 qemu-system-aarch64: load of migration failed: Invalid argument Revert that change. Signed-off-by: Eric Auger Message-id: 20211122171020.1195483-1-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_common.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 7d7f3882e7..90b85f1e25 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -50,8 +50,6 @@ static int gicv3_its_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_its = { .name = "arm_gicv3_its", - .version_id = 1, - .minimum_version_id = 1, .pre_save = gicv3_its_pre_save, .post_load = gicv3_its_post_load, .priority = MIG_PRI_GICV3_ITS, From 87bf1fe5cbffefe6b7ee13a7015ae285250ad2db Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:14 -0500 Subject: [PATCH 038/421] python/machine: add @sock_dir property Analogous to temp_dir and log_dir, add a sock_dir property that defaults to @temp_dir -- instead of base_temp_dir -- when the user hasn't overridden the sock dir value in the initializer. This gives us a much more unique directory to put sockfiles in by default. Signed-off-by: John Snow Reviewed-by: Willian Rampazzo Message-id: 20211118204620.1897674-2-jsnow@redhat.com Signed-off-by: John Snow --- python/qemu/machine/machine.py | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py index a487c39745..b1dd77b538 100644 --- a/python/qemu/machine/machine.py +++ b/python/qemu/machine/machine.py @@ -134,8 +134,9 @@ class QEMUMachine: self._qmp_timer = qmp_timer self._name = name or "qemu-%d" % os.getpid() + self._temp_dir: Optional[str] = None self._base_temp_dir = base_temp_dir - self._sock_dir = sock_dir or self._base_temp_dir + self._sock_dir = sock_dir self._log_dir = log_dir if monitor_address is not None: @@ -143,7 +144,7 @@ class QEMUMachine: self._remove_monitor_sockfile = False else: self._monitor_address = os.path.join( - self._sock_dir, f"{self._name}-monitor.sock" + self.sock_dir, f"{self._name}-monitor.sock" ) self._remove_monitor_sockfile = True @@ -163,14 +164,13 @@ class QEMUMachine: self._qmp_set = True # Enable QMP monitor by default. self._qmp_connection: Optional[QEMUMonitorProtocol] = None self._qemu_full_args: Tuple[str, ...] = () - self._temp_dir: Optional[str] = None self._launched = False self._machine: Optional[str] = None self._console_index = 0 self._console_set = False self._console_device_type: Optional[str] = None self._console_address = os.path.join( - self._sock_dir, f"{self._name}-console.sock" + self.sock_dir, f"{self._name}-console.sock" ) self._console_socket: Optional[socket.socket] = None self._remove_files: List[str] = [] @@ -816,6 +816,15 @@ class QEMUMachine: dir=self._base_temp_dir) return self._temp_dir + @property + def sock_dir(self) -> str: + """ + Returns the directory used for sockfiles by this machine. + """ + if self._sock_dir: + return self._sock_dir + return self.temp_dir + @property def log_dir(self) -> str: """ From 6eeb3de7e1aff91ce6e092a39f85946d12664385 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:15 -0500 Subject: [PATCH 039/421] python/machine: remove _remove_monitor_sockfile property It doesn't matter if it was the user or the class itself that specified where the sockfile should be created; the fact is that if we are using a sockfile here, we created it and we can clean it up. Signed-off-by: John Snow Reviewed-by: Willian Rampazzo Message-id: 20211118204620.1897674-3-jsnow@redhat.com Signed-off-by: John Snow --- python/qemu/machine/machine.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py index b1dd77b538..ea9e07805d 100644 --- a/python/qemu/machine/machine.py +++ b/python/qemu/machine/machine.py @@ -141,12 +141,10 @@ class QEMUMachine: if monitor_address is not None: self._monitor_address = monitor_address - self._remove_monitor_sockfile = False else: self._monitor_address = os.path.join( self.sock_dir, f"{self._name}-monitor.sock" ) - self._remove_monitor_sockfile = True self._console_log_path = console_log if self._console_log_path: @@ -315,8 +313,7 @@ class QEMUMachine: self._remove_files.append(self._console_address) if self._qmp_set: - if self._remove_monitor_sockfile: - assert isinstance(self._monitor_address, str) + if isinstance(self._monitor_address, str): self._remove_files.append(self._monitor_address) self._qmp_connection = QEMUMonitorProtocol( self._monitor_address, From 72b17fe715056c96ea73f187ab46721788b3a782 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:16 -0500 Subject: [PATCH 040/421] python/machine: add instance disambiguator to default nickname MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If you create two instances of QEMUMachine(), they'll both create the same nickname by default -- which is not that helpful. Luckily, they'll both create unique temporary directories ... but due to user configuration, they may share logging and sockfile directories, meaning two instances can collide. The Python logging will also be quite confusing, with no differentiation between the two instances. Add an instance disambiguator (The memory address of the instance) to the default nickname to foolproof this in all cases. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Willian Rampazzo Message-id: 20211118204620.1897674-4-jsnow@redhat.com Signed-off-by: John Snow --- python/qemu/machine/machine.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py index ea9e07805d..ad529fd92a 100644 --- a/python/qemu/machine/machine.py +++ b/python/qemu/machine/machine.py @@ -133,7 +133,7 @@ class QEMUMachine: self._wrapper = wrapper self._qmp_timer = qmp_timer - self._name = name or "qemu-%d" % os.getpid() + self._name = name or f"qemu-{os.getpid()}-{id(self):02x}" self._temp_dir: Optional[str] = None self._base_temp_dir = base_temp_dir self._sock_dir = sock_dir From b1ca99199320fcc010f407b84ac00d96e7e4baa1 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:17 -0500 Subject: [PATCH 041/421] python/machine: move more variable initializations to _pre_launch No need to clear them only to set them later. Signed-off-by: John Snow Reviewed-by: Willian Rampazzo Message-id: 20211118204620.1897674-5-jsnow@redhat.com Signed-off-by: John Snow --- python/qemu/machine/machine.py | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py index ad529fd92a..f92e73de40 100644 --- a/python/qemu/machine/machine.py +++ b/python/qemu/machine/machine.py @@ -327,6 +327,14 @@ class QEMUMachine: self._qemu_log_path = os.path.join(self.log_dir, self._name + ".log") self._qemu_log_file = open(self._qemu_log_path, 'wb') + self._iolog = None + self._qemu_full_args = tuple(chain( + self._wrapper, + [self._binary], + self._base_args, + self._args + )) + def _post_launch(self) -> None: if self._qmp_connection: self._qmp.accept(self._qmp_timer) @@ -390,8 +398,6 @@ class QEMUMachine: if self._launched: raise QEMUMachineError('VM already launched') - self._iolog = None - self._qemu_full_args = () try: self._launch() self._launched = True @@ -410,12 +416,6 @@ class QEMUMachine: Launch the VM and establish a QMP connection """ self._pre_launch() - self._qemu_full_args = tuple( - chain(self._wrapper, - [self._binary], - self._base_args, - self._args) - ) LOG.debug('VM launch command: %r', ' '.join(self._qemu_full_args)) # Cleaning up of this subprocess is guaranteed by _do_shutdown. From 1611e6cf4e7163f6102b37010a8b7e7120f468b5 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:18 -0500 Subject: [PATCH 042/421] python/machine: handle "fast" QEMU terminations In the case that the QEMU process actually launches -- but then dies so quickly that we can't establish a QMP connection to it -- QEMUMachine currently calls _post_shutdown() assuming that it never launched the VM process. This isn't true, though: it "merely" may have failed to establish a QMP connection and the process is in the middle of its own exit path. If we don't wait for the subprocess, the caller may get a bogus `None` return for .exitcode(). This behavior was observed from device-crash-test; after the switch to Async QMP, the timings were changed such that it was now seemingly possible to witness the failure of "vm.launch()" *prior* to the exitcode becoming available. The semantic of the `_launched` property is changed in this patch. Instead of representing the condition "launch() executed successfully", it will now represent "has forked a child process successfully". This way, wait() when called in the exit path won't become a no-op. Signed-off-by: John Snow Reviewed-by: Willian Rampazzo Message-id: 20211118204620.1897674-6-jsnow@redhat.com Signed-off-by: John Snow --- python/qemu/machine/machine.py | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/python/qemu/machine/machine.py b/python/qemu/machine/machine.py index f92e73de40..67ab06ca2b 100644 --- a/python/qemu/machine/machine.py +++ b/python/qemu/machine/machine.py @@ -349,9 +349,6 @@ class QEMUMachine: Called to cleanup the VM instance after the process has exited. May also be called after a failed launch. """ - # Comprehensive reset for the failed launch case: - self._early_cleanup() - try: self._close_qmp_connection() except Exception as err: # pylint: disable=broad-except @@ -400,9 +397,16 @@ class QEMUMachine: try: self._launch() - self._launched = True except: - self._post_shutdown() + # We may have launched the process but it may + # have exited before we could connect via QMP. + # Assume the VM didn't launch or is exiting. + # If we don't wait for the process, exitcode() may still be + # 'None' by the time control is ceded back to the caller. + if self._launched: + self.wait() + else: + self._post_shutdown() LOG.debug('Error launching VM') if self._qemu_full_args: @@ -426,6 +430,7 @@ class QEMUMachine: stderr=subprocess.STDOUT, shell=False, close_fds=False) + self._launched = True self._post_launch() def _close_qmp_connection(self) -> None: @@ -457,8 +462,8 @@ class QEMUMachine: """ Perform any cleanup that needs to happen before the VM exits. - May be invoked by both soft and hard shutdown in failover scenarios. - Called additionally by _post_shutdown for comprehensive cleanup. + This method may be called twice upon shutdown, once each by soft + and hard shutdown in failover scenarios. """ # If we keep the console socket open, we may deadlock waiting # for QEMU to exit, while QEMU is waiting for the socket to From 206439cd8937a3dc556537074d5d37e5d74eb0d0 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:19 -0500 Subject: [PATCH 043/421] scripts/device-crash-test: Use a QMP timeout Despite all the previous fixes, it's still possible for device-crash-test to wedge itself in the case that QEMU terminates *so quickly* that it doesn't even begin a connection attempt to our QMP client. Python will just joyfully wait ad infinitum for a connection that will now never arrive. The real fix is to use asyncio to simultaneously poll both the health of the launched process AND the connection attempt. That's quite a bit more invasive than just setting a connection timeout, though. Do the very simplest thing for now. Signed-off-by: John Snow Message-id: 20211118204620.1897674-7-jsnow@redhat.com Signed-off-by: John Snow --- scripts/device-crash-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/device-crash-test b/scripts/device-crash-test index 1c73dac93e..7fbd99158b 100755 --- a/scripts/device-crash-test +++ b/scripts/device-crash-test @@ -353,7 +353,7 @@ def checkOneCase(args, testcase): '-device', qemuOptsEscape(device)] cmdline = ' '.join([binary] + args) dbg("will launch QEMU: %s", cmdline) - vm = QEMUMachine(binary=binary, args=args) + vm = QEMUMachine(binary=binary, args=args, qmp_timer=15) exc = None exc_traceback = None From a57cb3e23d5ac918a69d0aab918470ff0b429ff9 Mon Sep 17 00:00:00 2001 From: John Snow Date: Thu, 18 Nov 2021 15:46:20 -0500 Subject: [PATCH 044/421] python/aqmp: fix send_fd_scm for python 3.6.x 3.6 doesn't play keepaway with the socket object, so we don't need to go fishing for it on this version. In fact, so long as 'sendmsg' is still available, it's probably preferable to just use that method and only go fishing for forbidden details when we absolutely have to. Reported-by: Thomas Huth Signed-off-by: John Snow Reviewed-by: Willian Rampazzo Message-id: 20211118204620.1897674-8-jsnow@redhat.com Signed-off-by: John Snow --- python/qemu/aqmp/qmp_client.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/python/qemu/aqmp/qmp_client.py b/python/qemu/aqmp/qmp_client.py index f987da02eb..8105e29fa8 100644 --- a/python/qemu/aqmp/qmp_client.py +++ b/python/qemu/aqmp/qmp_client.py @@ -639,9 +639,12 @@ class QMPClient(AsyncProtocol[Message], Events): if sock.family != socket.AF_UNIX: raise AQMPError("Sending file descriptors requires a UNIX socket.") - # Void the warranty sticker. - # Access to sendmsg in asyncio is scheduled for removal in Python 3.11. - sock = sock._sock # pylint: disable=protected-access + if not hasattr(sock, 'sendmsg'): + # We need to void the warranty sticker. + # Access to sendmsg is scheduled for removal in Python 3.11. + # Find the real backing socket to use it anyway. + sock = sock._sock # pylint: disable=protected-access + sock.sendmsg( [b' '], [(socket.SOL_SOCKET, socket.SCM_RIGHTS, struct.pack('@i', fd))] From c6cda6a44a8adaeb30bd6dc185f021809625433d Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Fri, 12 Nov 2021 21:55:59 -0700 Subject: [PATCH 045/421] linux-user: Add host_signal_set_pc to set pc in mcontext MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a new function host_signal_set_pc to set the next pc in an mcontext. The caller should ensure this is a valid PC for execution. Acked-by: Laurent Vivier Signed-off-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211113045603.60391-2-imp@bsdimp.com> Signed-off-by: Richard Henderson --- linux-user/host/aarch64/host-signal.h | 5 +++++ linux-user/host/alpha/host-signal.h | 5 +++++ linux-user/host/arm/host-signal.h | 5 +++++ linux-user/host/i386/host-signal.h | 5 +++++ linux-user/host/mips/host-signal.h | 5 +++++ linux-user/host/ppc/host-signal.h | 5 +++++ linux-user/host/riscv/host-signal.h | 5 +++++ linux-user/host/s390/host-signal.h | 5 +++++ linux-user/host/sparc/host-signal.h | 9 +++++++++ linux-user/host/x86_64/host-signal.h | 5 +++++ 10 files changed, 54 insertions(+) diff --git a/linux-user/host/aarch64/host-signal.h b/linux-user/host/aarch64/host-signal.h index 0c0b08383a..9770b36dc1 100644 --- a/linux-user/host/aarch64/host-signal.h +++ b/linux-user/host/aarch64/host-signal.h @@ -35,6 +35,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.pc; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.pc = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { struct _aarch64_ctx *hdr; diff --git a/linux-user/host/alpha/host-signal.h b/linux-user/host/alpha/host-signal.h index e080be412f..f4c942948a 100644 --- a/linux-user/host/alpha/host-signal.h +++ b/linux-user/host/alpha/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.sc_pc; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.sc_pc = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { uint32_t *pc = (uint32_t *)host_signal_pc(uc); diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index efb165c0c5..6c095773c0 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.arm_pc; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.arm_pc = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { /* diff --git a/linux-user/host/i386/host-signal.h b/linux-user/host/i386/host-signal.h index 4c8eef99ce..abe1ece5c9 100644 --- a/linux-user/host/i386/host-signal.h +++ b/linux-user/host/i386/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.gregs[REG_EIP]; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.gregs[REG_EIP] = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe diff --git a/linux-user/host/mips/host-signal.h b/linux-user/host/mips/host-signal.h index ef341f7c20..c666ed8c3f 100644 --- a/linux-user/host/mips/host-signal.h +++ b/linux-user/host/mips/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.pc; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.pc = pc; +} + #if defined(__misp16) || defined(__mips_micromips) #error "Unsupported encoding" #endif diff --git a/linux-user/host/ppc/host-signal.h b/linux-user/host/ppc/host-signal.h index a491c413dc..1d8e658ff7 100644 --- a/linux-user/host/ppc/host-signal.h +++ b/linux-user/host/ppc/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.regs->nip; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.regs->nip = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { return uc->uc_mcontext.regs->trap != 0x400 diff --git a/linux-user/host/riscv/host-signal.h b/linux-user/host/riscv/host-signal.h index 3b168cb58b..a4f170efb0 100644 --- a/linux-user/host/riscv/host-signal.h +++ b/linux-user/host/riscv/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.__gregs[REG_PC]; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.__gregs[REG_PC] = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { /* diff --git a/linux-user/host/s390/host-signal.h b/linux-user/host/s390/host-signal.h index 26990e4893..a524f2ab00 100644 --- a/linux-user/host/s390/host-signal.h +++ b/linux-user/host/s390/host-signal.h @@ -16,6 +16,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.psw.addr; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.psw.addr = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { uint16_t *pinsn = (uint16_t *)host_signal_pc(uc); diff --git a/linux-user/host/sparc/host-signal.h b/linux-user/host/sparc/host-signal.h index 5e71d33f8e..7342936071 100644 --- a/linux-user/host/sparc/host-signal.h +++ b/linux-user/host/sparc/host-signal.h @@ -20,6 +20,15 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) #endif } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ +#ifdef __arch64__ + uc->uc_mcontext.mc_gregs[MC_PC] = pc; +#else + uc->uc_mcontext.gregs[REG_PC] = pc; +#endif +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { uint32_t insn = *(uint32_t *)host_signal_pc(uc); diff --git a/linux-user/host/x86_64/host-signal.h b/linux-user/host/x86_64/host-signal.h index 883d2fcf65..c71d597eb2 100644 --- a/linux-user/host/x86_64/host-signal.h +++ b/linux-user/host/x86_64/host-signal.h @@ -15,6 +15,11 @@ static inline uintptr_t host_signal_pc(ucontext_t *uc) return uc->uc_mcontext.gregs[REG_RIP]; } +static inline void host_signal_set_pc(ucontext_t *uc, uintptr_t pc) +{ + uc->uc_mcontext.gregs[REG_RIP] = pc; +} + static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) { return uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe From 07637888687bfecf3c0cc8351c5c24f29a611691 Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Fri, 12 Nov 2021 21:56:00 -0700 Subject: [PATCH 046/421] linux-user/signal.c: Create a common rewind_if_in_safe_syscall MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All instances of rewind_if_in_safe_syscall are the same, differing only in how the instruction point is fetched from the ucontext and the size of the registers. Use host_signal_pc and new host_signal_set_pc interfaces to fetch the pointer to the PC and adjust if needed. Delete all the old copies of rewind_if_in_safe_syscall. Acked-by: Laurent Vivier Signed-off-by: Warner Losh Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211113045603.60391-3-imp@bsdimp.com> [rth: include safe-syscall.h, simplify ifdefs] Signed-off-by: Richard Henderson --- linux-user/host/aarch64/hostdep.h | 20 -------------------- linux-user/host/arm/hostdep.h | 20 -------------------- linux-user/host/i386/hostdep.h | 20 -------------------- linux-user/host/ppc64/hostdep.h | 20 -------------------- linux-user/host/riscv/hostdep.h | 20 -------------------- linux-user/host/s390x/hostdep.h | 20 -------------------- linux-user/host/x86_64/hostdep.h | 20 -------------------- linux-user/safe-syscall.h | 3 +++ linux-user/signal.c | 15 ++++++++++++--- 9 files changed, 15 insertions(+), 143 deletions(-) diff --git a/linux-user/host/aarch64/hostdep.h b/linux-user/host/aarch64/hostdep.h index a8d41a21ad..39299d798a 100644 --- a/linux-user/host/aarch64/hostdep.h +++ b/linux-user/host/aarch64/hostdep.h @@ -15,24 +15,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - __u64 *pcreg = &uc->uc_mcontext.pc; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/host/arm/hostdep.h b/linux-user/host/arm/hostdep.h index 9276fe6ceb..86b137875a 100644 --- a/linux-user/host/arm/hostdep.h +++ b/linux-user/host/arm/hostdep.h @@ -15,24 +15,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.arm_pc; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/host/i386/hostdep.h b/linux-user/host/i386/hostdep.h index 073be74d87..ce7136501f 100644 --- a/linux-user/host/i386/hostdep.h +++ b/linux-user/host/i386/hostdep.h @@ -15,24 +15,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - greg_t *pcreg = &uc->uc_mcontext.gregs[REG_EIP]; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/host/ppc64/hostdep.h b/linux-user/host/ppc64/hostdep.h index 98979ad917..0c290dd904 100644 --- a/linux-user/host/ppc64/hostdep.h +++ b/linux-user/host/ppc64/hostdep.h @@ -15,24 +15,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.gp_regs[PT_NIP]; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/host/riscv/hostdep.h b/linux-user/host/riscv/hostdep.h index 2ba07456ae..7f67c22868 100644 --- a/linux-user/host/riscv/hostdep.h +++ b/linux-user/host/riscv/hostdep.h @@ -11,24 +11,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.__gregs[REG_PC]; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/host/s390x/hostdep.h b/linux-user/host/s390x/hostdep.h index 4f0171f36f..d801145854 100644 --- a/linux-user/host/s390x/hostdep.h +++ b/linux-user/host/s390x/hostdep.h @@ -15,24 +15,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - unsigned long *pcreg = &uc->uc_mcontext.psw.addr; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/host/x86_64/hostdep.h b/linux-user/host/x86_64/hostdep.h index a4fefb5114..9c62bd26bd 100644 --- a/linux-user/host/x86_64/hostdep.h +++ b/linux-user/host/x86_64/hostdep.h @@ -15,24 +15,4 @@ /* We have a safe-syscall.inc.S */ #define HAVE_SAFE_SYSCALL -#ifndef __ASSEMBLER__ - -/* These are defined by the safe-syscall.inc.S file */ -extern char safe_syscall_start[]; -extern char safe_syscall_end[]; - -/* Adjust the signal context to rewind out of safe-syscall if we're in it */ -static inline void rewind_if_in_safe_syscall(void *puc) -{ - ucontext_t *uc = puc; - greg_t *pcreg = &uc->uc_mcontext.gregs[REG_RIP]; - - if (*pcreg > (uintptr_t)safe_syscall_start - && *pcreg < (uintptr_t)safe_syscall_end) { - *pcreg = (uintptr_t)safe_syscall_start; - } -} - -#endif /* __ASSEMBLER__ */ - #endif diff --git a/linux-user/safe-syscall.h b/linux-user/safe-syscall.h index 6bc0390262..aaa9ffc0e2 100644 --- a/linux-user/safe-syscall.h +++ b/linux-user/safe-syscall.h @@ -127,6 +127,9 @@ #ifdef HAVE_SAFE_SYSCALL /* The core part of this function is implemented in assembly */ extern long safe_syscall_base(int *pending, long number, ...); +/* These are defined by the safe-syscall.inc.S file */ +extern char safe_syscall_start[]; +extern char safe_syscall_end[]; #define safe_syscall(...) \ ({ \ diff --git a/linux-user/signal.c b/linux-user/signal.c index 81c45bfce9..6d5e5b698c 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -31,6 +31,7 @@ #include "trace.h" #include "signal-common.h" #include "host-signal.h" +#include "safe-syscall.h" static struct target_sigaction sigact_table[TARGET_NSIG]; @@ -793,12 +794,20 @@ int queue_signal(CPUArchState *env, int sig, int si_type, return 1; /* indicates that the signal was queued */ } -#ifndef HAVE_SAFE_SYSCALL + +/* Adjust the signal context to rewind out of safe-syscall if we're in it */ static inline void rewind_if_in_safe_syscall(void *puc) { - /* Default version: never rewind */ -} +#ifdef HAVE_SAFE_SYSCALL + ucontext_t *uc = (ucontext_t *)puc; + uintptr_t pcreg = host_signal_pc(uc); + + if (pcreg > (uintptr_t)safe_syscall_start + && pcreg < (uintptr_t)safe_syscall_end) { + host_signal_set_pc(uc, (uintptr_t)safe_syscall_start); + } #endif +} static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { From 22c36b75c8a07f34a6516a8d79f38c74530727a1 Mon Sep 17 00:00:00 2001 From: Daniella Lee Date: Fri, 19 Nov 2021 19:25:53 +0800 Subject: [PATCH 047/421] block/vvfat.c fix leak when failure occurs Function vvfat_open called function enable_write_target and init_directories, and these functions malloc new memory for BDRVVVFATState::qcow_filename, BDRVVVFATState::used_clusters, and BDRVVVFATState::cluster_buff. When the specified folder does not exist ,it may contains memory leak. After init_directories function is executed, the vvfat_open return -EIO, and bdrv_open_driver goto label open_failed, the program use g_free(bs->opaque) to release BDRVVVFATState struct without members mentioned. command line: qemu-system-x86_64 -hdb -usb -device usb-storage,drive=fat16 -drive file=fat:rw:fat-type=16:"", id=fat16,format=raw,if=none enable_write_target called: (gdb) bt at ../block/vvfat.c:3114 flags=155650, errp=0x7fffffffd780) at ../block/vvfat.c:1236 node_name=0x0, options=0x555556fa45d0, open_flags=155650, errp=0x7fffffffd890) at ../block.c:1558 errp=0x7fffffffd890) at ../block.c:1852 reference=0x0, options=0x555556fa45d0, flags=40962, parent=0x555556f98cd0, child_class=0x555556b1d6a0 , child_role=19, errp=0x7fffffffda90) at ../block.c:3779 options=0x555556f9cfc0, bdref_key=0x555556239bb8 "file", parent=0x555556f98cd0, child_class=0x555556b1d6a0 , child_role=19, allow_none=true, errp=0x7fffffffda90) at ../block.c:3419 reference=0x0, options=0x555556f9cfc0, flags=8194, parent=0x0, child_class=0x0, child_role=0, errp=0x555556c98c40 ) at ../block.c:3726 options=0x555556f757b0, flags=0, errp=0x555556c98c40 ) at ../block.c:3872 options=0x555556f757b0, flags=0, errp=0x555556c98c40 ) at ../block/block-backend.c:436 bs_opts=0x555556f757b0, errp=0x555556c98c40 ) at ../blockdev.c:608 errp=0x555556c98c40 ) at ../blockdev.c:992 ...... Signed-off-by: Daniella Lee Message-Id: <20211119112553.352222-1-daniellalee111@gmail.com> [hreitz: Took commit message from v1] Signed-off-by: Hanna Reitz --- block/vvfat.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/block/vvfat.c b/block/vvfat.c index 05e78e3c27..5dacc6cfac 100644 --- a/block/vvfat.c +++ b/block/vvfat.c @@ -1279,8 +1279,18 @@ static int vvfat_open(BlockDriverState *bs, QDict *options, int flags, qemu_co_mutex_init(&s->lock); - ret = 0; + qemu_opts_del(opts); + + return 0; + fail: + g_free(s->qcow_filename); + s->qcow_filename = NULL; + g_free(s->cluster_buffer); + s->cluster_buffer = NULL; + g_free(s->used_clusters); + s->used_clusters = NULL; + qemu_opts_del(opts); return ret; } @@ -3118,7 +3128,7 @@ static int enable_write_target(BlockDriverState *bs, Error **errp) int size = sector2cluster(s, s->sector_count); QDict *options; - s->used_clusters = calloc(size, 1); + s->used_clusters = g_malloc0(size); array_init(&(s->commits), sizeof(commit_t)); @@ -3166,8 +3176,6 @@ static int enable_write_target(BlockDriverState *bs, Error **errp) return 0; err: - g_free(s->qcow_filename); - s->qcow_filename = NULL; return ret; } From cb5a24d7f692ad129f019f3b670531eccfe14415 Mon Sep 17 00:00:00 2001 From: Hanna Reitz Date: Wed, 17 Nov 2021 16:17:06 +0100 Subject: [PATCH 048/421] iotests: Use aes-128-cbc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Our gnutls crypto backend (which is the default as of 8bd0931f6) supports neither twofish-128 nor the CTR mode. CBC and aes-128 are supported by all of our backends (as far as I can tell), so use aes-128-cbc in our iotests. (We could also use e.g. aes-256-cbc, but the different key sizes would lead to different key slot offsets and so change the reference output more, which is why I went with aes-128.) Signed-off-by: Hanna Reitz Message-Id: <20211117151707.52549-2-hreitz@redhat.com> Reviewed-by: Daniel P. Berrangé Tested-by: Thomas Huth --- tests/qemu-iotests/206 | 4 ++-- tests/qemu-iotests/206.out | 6 +++--- tests/qemu-iotests/210 | 4 ++-- tests/qemu-iotests/210.out | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/tests/qemu-iotests/206 b/tests/qemu-iotests/206 index c3cdad4ce4..10eff343f7 100755 --- a/tests/qemu-iotests/206 +++ b/tests/qemu-iotests/206 @@ -162,8 +162,8 @@ with iotests.FilePath('t.qcow2') as disk_path, \ 'encrypt': { 'format': 'luks', 'key-secret': 'keysec0', - 'cipher-alg': 'twofish-128', - 'cipher-mode': 'ctr', + 'cipher-alg': 'aes-128', + 'cipher-mode': 'cbc', 'ivgen-alg': 'plain64', 'ivgen-hash-alg': 'md5', 'hash-alg': 'sha1', diff --git a/tests/qemu-iotests/206.out b/tests/qemu-iotests/206.out index 3593e8e9c2..80cd274223 100644 --- a/tests/qemu-iotests/206.out +++ b/tests/qemu-iotests/206.out @@ -97,7 +97,7 @@ Format specific information: === Successful image creation (encrypted) === -{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "qcow2", "encrypt": {"cipher-alg": "twofish-128", "cipher-mode": "ctr", "format": "luks", "hash-alg": "sha1", "iter-time": 10, "ivgen-alg": "plain64", "ivgen-hash-alg": "md5", "key-secret": "keysec0"}, "file": {"driver": "file", "filename": "TEST_DIR/PID-t.qcow2"}, "size": 33554432}}} +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "qcow2", "encrypt": {"cipher-alg": "aes-128", "cipher-mode": "cbc", "format": "luks", "hash-alg": "sha1", "iter-time": 10, "ivgen-alg": "plain64", "ivgen-hash-alg": "md5", "key-secret": "keysec0"}, "file": {"driver": "file", "filename": "TEST_DIR/PID-t.qcow2"}, "size": 33554432}}} {"return": {}} {"execute": "job-dismiss", "arguments": {"id": "job0"}} {"return": {}} @@ -115,10 +115,10 @@ Format specific information: encrypt: ivgen alg: plain64 hash alg: sha1 - cipher alg: twofish-128 + cipher alg: aes-128 uuid: XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX format: luks - cipher mode: ctr + cipher mode: cbc slots: [0]: active: true diff --git a/tests/qemu-iotests/210 b/tests/qemu-iotests/210 index 5a62ed4dd1..a4dcc5fe59 100755 --- a/tests/qemu-iotests/210 +++ b/tests/qemu-iotests/210 @@ -83,8 +83,8 @@ with iotests.FilePath('t.luks') as disk_path, \ }, 'size': size, 'key-secret': 'keysec0', - 'cipher-alg': 'twofish-128', - 'cipher-mode': 'ctr', + 'cipher-alg': 'aes-128', + 'cipher-mode': 'cbc', 'ivgen-alg': 'plain64', 'ivgen-hash-alg': 'md5', 'hash-alg': 'sha1', diff --git a/tests/qemu-iotests/210.out b/tests/qemu-iotests/210.out index 55c0844370..96d9f749dd 100644 --- a/tests/qemu-iotests/210.out +++ b/tests/qemu-iotests/210.out @@ -59,7 +59,7 @@ Format specific information: {"execute": "job-dismiss", "arguments": {"id": "job0"}} {"return": {}} -{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"cipher-alg": "twofish-128", "cipher-mode": "ctr", "driver": "luks", "file": {"driver": "file", "filename": "TEST_DIR/PID-t.luks"}, "hash-alg": "sha1", "iter-time": 10, "ivgen-alg": "plain64", "ivgen-hash-alg": "md5", "key-secret": "keysec0", "size": 67108864}}} +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"cipher-alg": "aes-128", "cipher-mode": "cbc", "driver": "luks", "file": {"driver": "file", "filename": "TEST_DIR/PID-t.luks"}, "hash-alg": "sha1", "iter-time": 10, "ivgen-alg": "plain64", "ivgen-hash-alg": "md5", "key-secret": "keysec0", "size": 67108864}}} {"return": {}} {"execute": "job-dismiss", "arguments": {"id": "job0"}} {"return": {}} @@ -71,9 +71,9 @@ encrypted: yes Format specific information: ivgen alg: plain64 hash alg: sha1 - cipher alg: twofish-128 + cipher alg: aes-128 uuid: XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX - cipher mode: ctr + cipher mode: cbc slots: [0]: active: true From 4dd218fd0717ed3cddb69c01eeb9da630107d89d Mon Sep 17 00:00:00 2001 From: Hanna Reitz Date: Wed, 17 Nov 2021 16:17:07 +0100 Subject: [PATCH 049/421] iotests/149: Skip on unsupported ciphers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Whenever qemu-img or qemu-io report that some cipher is unsupported, skip the whole test, because that is probably because qemu has been configured with the gnutls crypto backend. We could taylor the algorithm list to what gnutls supports, but this is a test that is run rather rarely anyway (because it requires password-less sudo), and so it seems better and easier to skip it. When this test is intentionally run to check LUKS compatibility, it seems better not to limit the algorithms but keep the list extensive. Signed-off-by: Hanna Reitz Message-Id: <20211117151707.52549-3-hreitz@redhat.com> Reviewed-by: Daniel P. Berrangé --- tests/qemu-iotests/149 | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/tests/qemu-iotests/149 b/tests/qemu-iotests/149 index 328fd05a4c..d49646ca60 100755 --- a/tests/qemu-iotests/149 +++ b/tests/qemu-iotests/149 @@ -230,6 +230,18 @@ def create_image(config, size_mb): fn.truncate(size_mb * 1024 * 1024) +def check_cipher_support(config, output): + """Check the output of qemu-img or qemu-io for mention of the respective + cipher algorithm being unsupported, and if so, skip this test. + (Returns `output` for convenience.)""" + + if 'Unsupported cipher algorithm' in output: + iotests.notrun('Unsupported cipher algorithm ' + f'{config.cipher}-{config.keylen}-{config.mode}; ' + 'consider configuring qemu with a different crypto ' + 'backend') + return output + def qemu_img_create(config, size_mb): """Create and format a disk image with LUKS using qemu-img""" @@ -253,7 +265,8 @@ def qemu_img_create(config, size_mb): "%dM" % size_mb] iotests.log("qemu-img " + " ".join(args), filters=[iotests.filter_test_dir]) - iotests.log(iotests.qemu_img_pipe(*args), filters=[iotests.filter_test_dir]) + iotests.log(check_cipher_support(config, iotests.qemu_img_pipe(*args)), + filters=[iotests.filter_test_dir]) def qemu_io_image_args(config, dev=False): """Get the args for access an image or device with qemu-io""" @@ -279,8 +292,8 @@ def qemu_io_write_pattern(config, pattern, offset_mb, size_mb, dev=False): args = ["-c", "write -P 0x%x %dM %dM" % (pattern, offset_mb, size_mb)] args.extend(qemu_io_image_args(config, dev)) iotests.log("qemu-io " + " ".join(args), filters=[iotests.filter_test_dir]) - iotests.log(iotests.qemu_io(*args), filters=[iotests.filter_test_dir, - iotests.filter_qemu_io]) + iotests.log(check_cipher_support(config, iotests.qemu_io(*args)), + filters=[iotests.filter_test_dir, iotests.filter_qemu_io]) def qemu_io_read_pattern(config, pattern, offset_mb, size_mb, dev=False): @@ -291,8 +304,8 @@ def qemu_io_read_pattern(config, pattern, offset_mb, size_mb, dev=False): args = ["-c", "read -P 0x%x %dM %dM" % (pattern, offset_mb, size_mb)] args.extend(qemu_io_image_args(config, dev)) iotests.log("qemu-io " + " ".join(args), filters=[iotests.filter_test_dir]) - iotests.log(iotests.qemu_io(*args), filters=[iotests.filter_test_dir, - iotests.filter_qemu_io]) + iotests.log(check_cipher_support(config, iotests.qemu_io(*args)), + filters=[iotests.filter_test_dir, iotests.filter_qemu_io]) def test_once(config, qemu_img=False): From 14d02cfbe4adaeebe7cb833a8cc71191352cf03b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 24 Nov 2021 16:50:54 +0100 Subject: [PATCH 050/421] Update version for v6.2.0-rc2 release Signed-off-by: Richard Henderson --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 61d04b724a..030e1ce3b5 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.2.91 +6.2.92 From dd4b0de45965538f19bb40c7ddaaba384a8c613a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 25 Nov 2021 10:44:43 +0100 Subject: [PATCH 051/421] Fix version for v6.2.0-rc2 release Typo while setting VERSION in the tag commit. Signed-off-by: Richard Henderson --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 030e1ce3b5..f5664554ca 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.2.92 +6.1.92 From bede01170e9cb8f9ac9c6a0665ee9f3989a57e6a Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 23 Nov 2021 13:28:59 +0100 Subject: [PATCH 052/421] hw/arm/virt: Extend nested and mte checks to hvf The virt machine has properties to enable MTE and Nested Virtualization support. However, its check to ensure the backing accel implementation supports it today only looks for KVM and bails out if it finds it. Extend the checks to HVF as well as it does not support either today. This will cause QEMU to print a useful error message rather than silently ignoring the attempt by the user to enable either MTE or the Virtualization extensions. Reported-by: saar amar Signed-off-by: Alexander Graf Message-id: 20211123122859.22452-1-agraf@csgraf.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 369552ad45..30da05dfe0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -49,6 +49,7 @@ #include "sysemu/runstate.h" #include "sysemu/tpm.h" #include "sysemu/kvm.h" +#include "sysemu/hvf.h" #include "hw/loader.h" #include "qapi/error.h" #include "qemu/bitops.h" @@ -1969,15 +1970,17 @@ static void machvirt_init(MachineState *machine) exit(1); } - if (vms->virt && kvm_enabled()) { - error_report("mach-virt: KVM does not support providing " - "Virtualization extensions to the guest CPU"); + if (vms->virt && (kvm_enabled() || hvf_enabled())) { + error_report("mach-virt: %s does not support providing " + "Virtualization extensions to the guest CPU", + kvm_enabled() ? "KVM" : "HVF"); exit(1); } - if (vms->mte && kvm_enabled()) { - error_report("mach-virt: KVM does not support providing " - "MTE to the guest CPU"); + if (vms->mte && (kvm_enabled() || hvf_enabled())) { + error_report("mach-virt: %s does not support providing " + "MTE to the guest CPU", + kvm_enabled() ? "KVM" : "HVF"); exit(1); } From 2f459cd1a80d24189598fd3416e270d1feb7dc87 Mon Sep 17 00:00:00 2001 From: Shashi Mallela Date: Wed, 24 Nov 2021 13:22:46 -0500 Subject: [PATCH 053/421] hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When Enabled bit is cleared in GITS_CTLR,ITS feature continues to be enabled.This patch fixes the issue. Signed-off-by: Shashi Mallela Tested-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 20211124182246.67691-1-shashi.mallela@linaro.org Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 84bcbb5f56..c929a9cb5c 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -896,13 +896,14 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, switch (offset) { case GITS_CTLR: - s->ctlr |= (value & ~(s->ctlr)); - - if (s->ctlr & ITS_CTLR_ENABLED) { + if (value & R_GITS_CTLR_ENABLED_MASK) { + s->ctlr |= ITS_CTLR_ENABLED; extract_table_params(s); extract_cmdq_params(s); s->creadr = 0; process_cmdq(s); + } else { + s->ctlr &= ~ITS_CTLR_ENABLED; } break; case GITS_CBASER: From 101f27f3c834842238624b6c0205be3281883878 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 24 Nov 2021 20:20:05 +0000 Subject: [PATCH 054/421] hw/intc/arm_gicv3: Update cached state after LPI state changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The logic of gicv3_redist_update() is as follows: * it must be called in any code path that changes the state of (only) redistributor interrupts * if it finds a redistributor interrupt that is (now) higher priority than the previous highest-priority pending interrupt, then this must be the new highest-priority pending interrupt * if it does *not* find a better redistributor interrupt, then: - if the previous state was "no interrupts pending" then the new state is still "no interrupts pending" - if the previous best interrupt was not a redistributor interrupt then that remains the best interrupt - if the previous best interrupt *was* a redistributor interrupt, then the new best interrupt must be some non-redistributor interrupt, but we don't know which so must do a full scan In commit 17fb5e36aabd4b2c125 we effectively added the LPI interrupts as a kind of "redistributor interrupt" for this purpose, by adding cs->hpplpi to the set of things that gicv3_redist_update() considers before it gives up and decides to do a full scan of distributor interrupts. However we didn't quite get this right: * the condition check for "was the previous best interrupt a redistributor interrupt" must be updated to include LPIs in what it considers to be redistributor interrupts * every code path which updates the LPI state which gicv3_redist_update() checks must also call gicv3_redist_update(): this is cs->hpplpi and the GICR_CTLR ENABLE_LPIS bit This commit fixes this by: * correcting the test on cs->hppi.irq in gicv3_redist_update() * making gicv3_redist_update_lpi() always call gicv3_redist_update() * introducing a new gicv3_redist_update_lpi_only() for the one callsite (the post-load hook) which must not call gicv3_redist_update() * making gicv3_redist_lpi_pending() always call gicv3_redist_update(), either directly or via gicv3_redist_update_lpi() * removing a couple of now-unnecessary calls to gicv3_redist_update() from some callers of those two functions * calling gicv3_redist_update() when the GICR_CTLR ENABLE_LPIS bit is cleared (This means that the not-file-local gicv3_redist_* LPI related functions now all take care of the updates of internally cached GICv3 information, in the same way the older functions gicv3_redist_set_irq() and gicv3_redist_send_sgi() do.) The visible effect of this bug was that when the guest acknowledged an LPI by reading ICC_IAR1_EL1, we marked it as not pending in the LPI data structure but still left it in cs->hppi so we would offer it to the guest again. In particular for setups using an emulated GICv3 and ITS and using devices which use LPIs (ie PCI devices) a Linux guest would complain "irq 54: nobody cared" and then hang. (The hang was intermittent, presumably depending on the timing between different interrupts arriving and being completed.) Signed-off-by: Peter Maydell Tested-by: Alex Bennée Reviewed-by: Alex Bennée Message-id: 20211124202005.989935-1-peter.maydell@linaro.org --- hw/intc/arm_gicv3.c | 6 ++++-- hw/intc/arm_gicv3_redist.c | 14 ++++++++++---- hw/intc/gicv3_internal.h | 17 +++++++++++++++++ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index c6282984b1..9f5f815db9 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -186,7 +186,9 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs) * interrupt has reduced in priority and any other interrupt could * now be the new best one). */ - if (!seenbetter && cs->hppi.prio != 0xff && cs->hppi.irq < GIC_INTERNAL) { + if (!seenbetter && cs->hppi.prio != 0xff && + (cs->hppi.irq < GIC_INTERNAL || + cs->hppi.irq >= GICV3_LPI_INTID_START)) { gicv3_full_update_noirqset(cs->gic); } } @@ -354,7 +356,7 @@ static void arm_gicv3_post_load(GICv3State *s) * pending interrupt, but don't set IRQ or FIQ lines. */ for (i = 0; i < s->num_cpu; i++) { - gicv3_redist_update_lpi(&s->cpu[i]); + gicv3_redist_update_lpi_only(&s->cpu[i]); } gicv3_full_update_noirqset(s); /* Repopulate the cache of GICv3CPUState pointers for target CPUs */ diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 424e7e28a8..c8ff3eca08 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -256,9 +256,10 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS; /* Check for any pending interr in pending table */ gicv3_redist_update_lpi(cs); - gicv3_redist_update(cs); } else { cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS; + /* cs->hppi might have been an LPI; recalculate */ + gicv3_redist_update(cs); } } return MEMTX_OK; @@ -571,7 +572,7 @@ static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq) } } -void gicv3_redist_update_lpi(GICv3CPUState *cs) +void gicv3_redist_update_lpi_only(GICv3CPUState *cs) { /* * This function scans the LPI pending table and for each pending @@ -614,6 +615,12 @@ void gicv3_redist_update_lpi(GICv3CPUState *cs) } } +void gicv3_redist_update_lpi(GICv3CPUState *cs) +{ + gicv3_redist_update_lpi_only(cs); + gicv3_redist_update(cs); +} + void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level) { /* @@ -651,6 +658,7 @@ void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level) */ if (level) { gicv3_redist_check_lpi_priority(cs, irq); + gicv3_redist_update(cs); } else { if (irq == cs->hpplpi.irq) { gicv3_redist_update_lpi(cs); @@ -673,8 +681,6 @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level) /* set/clear the pending bit for this irq */ gicv3_redist_lpi_pending(cs, irq, level); - - gicv3_redist_update(cs); } void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index a0369dace7..70f34ee495 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -463,7 +463,24 @@ void gicv3_dist_set_irq(GICv3State *s, int irq, int level); void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level); void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level); void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level); +/** + * gicv3_redist_update_lpi: + * @cs: GICv3CPUState + * + * Scan the LPI pending table and recalculate the highest priority + * pending LPI and also the overall highest priority pending interrupt. + */ void gicv3_redist_update_lpi(GICv3CPUState *cs); +/** + * gicv3_redist_update_lpi_only: + * @cs: GICv3CPUState + * + * Scan the LPI pending table and recalculate cs->hpplpi only, + * without calling gicv3_redist_update() to recalculate the overall + * highest priority pending interrupt. This should be called after + * an incoming migration has loaded new state. + */ +void gicv3_redist_update_lpi_only(GICv3CPUState *cs); void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); From b74d7c0e50ac4bde85c0ff629bfc23cdf378e62c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 26 Nov 2021 16:39:14 +0000 Subject: [PATCH 055/421] hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GICv3/v4 pseudocode has a function IsSpecial() which returns true if passed a "special" interrupt ID number (anything between 1020 and 1023 inclusive). We open-code this condition in a couple of places, so abstract it out into a new function gicv3_intid_is_special(). Signed-off-by: Peter Maydell Reviewed-by: Marc Zyngier Reviewed-by: Alex Bennée --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- hw/intc/gicv3_internal.h | 13 +++++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 3fe5de8ad7..7fbc36ff41 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -997,7 +997,7 @@ static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri) intid = icc_hppir0_value(cs, env); } - if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) { + if (!gicv3_intid_is_special(intid)) { icc_activate_irq(cs, intid); } @@ -1020,7 +1020,7 @@ static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri) intid = icc_hppir1_value(cs, env); } - if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) { + if (!gicv3_intid_is_special(intid)) { icc_activate_irq(cs, intid); } diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 70f34ee495..b9c37453b0 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -411,6 +411,19 @@ FIELD(MAPC, RDBASE, 16, 32) /* Functions internal to the emulated GICv3 */ +/** + * gicv3_intid_is_special: + * @intid: interrupt ID + * + * Return true if @intid is a special interrupt ID (1020 to + * 1023 inclusive). This corresponds to the GIC spec pseudocode + * IsSpecial() function. + */ +static inline bool gicv3_intid_is_special(int intid) +{ + return intid >= INTID_SECURE && intid <= INTID_SPURIOUS; +} + /** * gicv3_redist_update: * @cs: GICv3CPUState for this redistributor From 7abba7c638ab809e626f379617cb8590a733eabf Mon Sep 17 00:00:00 2001 From: Cindy Lu Date: Tue, 9 Nov 2021 10:37:44 +0800 Subject: [PATCH 056/421] virtio-mmio : fix the crash in the vm shutdown The root cause for this crash is the ioeventfd not stopped while the VM stop. The callback for vmstate_change was not implement in virtio-mmio bus Reproduce step load the vm with -M microvm \ -netdev tap,id=net0,vhostforce,script=no,downscript=no \ -device virtio-net-device,netdev=net0\ After the VM boot, login the vm and then shutdown the vm System will crash [Current thread is 1 (Thread 0x7ffff6edde00 (LWP 374378))] (gdb) bt 0 0x00005555558f18b4 in qemu_flush_or_purge_queued_packets (purge=false, nc=0x55500252e850) at ../net/net.c:636 1 qemu_flush_queued_packets (nc=0x55500252e850) at ../net/net.c:656 2 0x0000555555b6c363 in virtio_queue_notify_vq (vq=0x7fffe7e2b010) at ../hw/virtio/virtio.c:2339 3 virtio_queue_host_notifier_read (n=0x7fffe7e2b08c) at ../hw/virtio/virtio.c:3583 4 0x0000555555de7b5a in aio_dispatch_handler (ctx=ctx@entry=0x5555567c5780, node=0x555556b83fd0) at ../util/aio-posix.c:329 5 0x0000555555de8454 in aio_dispatch_ready_handlers (ready_list=, ctx=) at ../util/aio-posix.c:359 6 aio_poll (ctx=0x5555567c5780, blocking=blocking@entry=false) at ../util/aio-posix.c:662 7 0x0000555555cce0cc in monitor_cleanup () at ../monitor/monitor.c:645 8 0x0000555555b06bd2 in qemu_cleanup () at ../softmmu/runstate.c:822 9 0x000055555586e693 in main (argc=, argv=, envp=) at ../softmmu/main.c:51 Signed-off-by: Cindy Lu Message-Id: <20211109023744.22387-1-lulu@redhat.com> Acked-by: Jason Wang Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio-mmio.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 7b3ebca178..72da12fea5 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -817,6 +817,17 @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) return path; } +static void virtio_mmio_vmstate_change(DeviceState *d, bool running) +{ + VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d); + + if (running) { + virtio_mmio_start_ioeventfd(proxy); + } else { + virtio_mmio_stop_ioeventfd(proxy); + } +} + static void virtio_mmio_bus_class_init(ObjectClass *klass, void *data) { BusClass *bus_class = BUS_CLASS(klass); @@ -832,6 +843,7 @@ static void virtio_mmio_bus_class_init(ObjectClass *klass, void *data) k->ioeventfd_enabled = virtio_mmio_ioeventfd_enabled; k->ioeventfd_assign = virtio_mmio_ioeventfd_assign; k->pre_plugged = virtio_mmio_pre_plugged; + k->vmstate_change = virtio_mmio_vmstate_change; k->has_variable_vring_alignment = true; bus_class->max_dev = 1; bus_class->get_dev_path = virtio_mmio_bus_get_dev_path; From 9323f892b39d133eb69b301484bf7b2f3f49737d Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Thu, 18 Nov 2021 14:32:23 +0100 Subject: [PATCH 057/421] failover: fix unplug pending detection Failover needs to detect the end of the PCI unplug to start migration after the VFIO card has been unplugged. To do that, a flag is set in pcie_cap_slot_unplug_request_cb() and reset in pcie_unplug_device(). But since 17858a169508 ("hw/acpi/ich9: Set ACPI PCI hot-plug as default on Q35") we have switched to ACPI unplug and these functions are not called anymore and the flag not set. So failover migration is not able to detect if card is really unplugged and acts as it's done as soon as it's started. So it doesn't wait the end of the unplug to start the migration. We don't see any problem when we test that because ACPI unplug is faster than PCIe native hotplug and when the migration really starts the unplug operation is already done. See c000a9bd06ea ("pci: mark device having guest unplug request pending") a99c4da9fc2a ("pci: mark devices partially unplugged") Signed-off-by: Laurent Vivier Reviewed-by: Ani Sinha Message-Id: <20211118133225.324937-4-lvivier@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/acpi/pcihp.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index f610a25d2e..30405b5113 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -222,9 +222,27 @@ static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slo PCIDevice *dev = PCI_DEVICE(qdev); if (PCI_SLOT(dev->devfn) == slot) { if (!acpi_pcihp_pc_no_hotplug(s, dev)) { - hotplug_ctrl = qdev_get_hotplug_handler(qdev); - hotplug_handler_unplug(hotplug_ctrl, qdev, &error_abort); - object_unparent(OBJECT(qdev)); + /* + * partially_hotplugged is used by virtio-net failover: + * failover has asked the guest OS to unplug the device + * but we need to keep some references to the device + * to be able to plug it back in case of failure so + * we don't execute hotplug_handler_unplug(). + */ + if (dev->partially_hotplugged) { + /* + * pending_deleted_event is set to true when + * virtio-net failover asks to unplug the device, + * and set to false here when the operation is done + * This is used by the migration loop to detect the + * end of the operation and really start the migration. + */ + qdev->pending_deleted_event = false; + } else { + hotplug_ctrl = qdev_get_hotplug_handler(qdev); + hotplug_handler_unplug(hotplug_ctrl, qdev, &error_abort); + object_unparent(OBJECT(qdev)); + } } } } @@ -396,6 +414,12 @@ void acpi_pcihp_device_unplug_request_cb(HotplugHandler *hotplug_dev, return; } + /* + * pending_deleted_event is used by virtio-net failover to detect the + * end of the unplug operation, the flag is set to false in + * acpi_pcihp_eject_slot() when the operation is completed. + */ + pdev->qdev.pending_deleted_event = true; s->acpi_pcihp_pci_status[bsel].down |= (1U << slot); acpi_send_event(DEVICE(hotplug_dev), ACPI_PCI_HOTPLUG_STATUS); } From 846a1e85da646c6006db429648389fc110f92d75 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eugenio=20P=C3=A9rez?= Date: Thu, 25 Nov 2021 11:16:13 +0100 Subject: [PATCH 058/421] vdpa: Add dummy receive callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Qemu falls back on userland handlers even if vhost-user and vhost-vdpa cases. These assumes a tap device can handle the packets. If a vdpa device fail to start, it can trigger a sigsegv because of that. Add dummy receiver that returns no progress so it can keep running. Fixes: 1e0a84ea49 ("vhost-vdpa: introduce vhost-vdpa net client") Signed-off-by: Eugenio Pérez Message-Id: <20211125101614.76927-2-eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- net/vhost-vdpa.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index 2e3c22a8c7..25dd6dd975 100644 --- a/net/vhost-vdpa.c +++ b/net/vhost-vdpa.c @@ -170,9 +170,17 @@ static bool vhost_vdpa_check_peer_type(NetClientState *nc, ObjectClass *oc, return true; } +/** Dummy receive in case qemu falls back to userland tap networking */ +static ssize_t vhost_vdpa_receive(NetClientState *nc, const uint8_t *buf, + size_t size) +{ + return 0; +} + static NetClientInfo net_vhost_vdpa_info = { .type = NET_CLIENT_DRIVER_VHOST_VDPA, .size = sizeof(VhostVDPAState), + .receive = vhost_vdpa_receive, .cleanup = vhost_vdpa_cleanup, .has_vnet_hdr = vhost_vdpa_has_vnet_hdr, .has_ufo = vhost_vdpa_has_ufo, From 90feffad2aafe856ed2af75313b2c1669ba671e9 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 26 Nov 2021 16:39:15 +0000 Subject: [PATCH 059/421] hw/intc/arm_gicv3: fix handling of LPIs in list registers It is valid for an OS to put virtual interrupt ID values into the list registers ICH_LR which are greater than 1023. This corresponds to (for example) KVM using the in-kernel emulated ITS to give a (nested) guest an ITS. LPIs are delivered by the L1 kernel to the L2 guest via the list registers in the same way as non-LPI interrupts. QEMU's code for handling writes to ICV_IARn (which happen when the L2 guest acknowledges an interrupt) and to ICV_EOIRn (which happen at the end of the interrupt) did not consider LPIs, so it would incorrectly treat interrupt IDs above 1023 as invalid. Fix this by using the correct condition, which is gicv3_intid_is_special(). Note that the condition in icv_dir_write() is correct -- LPIs are not valid there and so we want to ignore both "special" ID values and LPIs. (In the pseudocode this logic is in: - VirtualReadIAR0(), VirtualReadIAR1(), which call IsSpecial() - VirtualWriteEOIR0(), VirtualWriteEOIR1(), which call VirtualIdentifierValid(data, TRUE) meaning "LPIs OK" - VirtualWriteDIR(), which calls VirtualIdentifierValid(data, FALSE) meaning "LPIs not OK") This bug doesn't seem to have any visible effect on Linux L2 guests most of the time, because the two bugs cancel each other out: we neither mark the interrupt active nor deactivate it. However it does mean that the L2 vCPU priority while the LPI handler is running will not be correct, so the interrupt handler could be unexpectedly interrupted by a different interrupt. (NB: this has nothing to do with using QEMU's emulated ITS.) Signed-off-by: Peter Maydell Reviewed-by: Marc Zyngier --- hw/intc/arm_gicv3_cpuif.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7fbc36ff41..7fba931450 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -653,7 +653,7 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { intid = ich_lr_vintid(lr); - if (intid < INTID_SECURE) { + if (!gicv3_intid_is_special(intid)) { icv_activate_irq(cs, idx, grp); } else { /* Interrupt goes from Pending to Invalid */ @@ -1265,8 +1265,7 @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), value); - if (irq >= GICV3_MAXIRQ) { - /* Also catches special interrupt numbers and LPIs */ + if (gicv3_intid_is_special(irq)) { return; } From 0fe7245d8b938f371556c100b0b6ec1d2b41e584 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Mon, 29 Nov 2021 11:08:40 +0800 Subject: [PATCH 060/421] virtio-balloon: process all in sgs for free_page_vq We only process the first in sg which may lead to the bitmap of the pages belongs to following sgs were not cleared. This may result more pages to be migrated. Fixing this by process all in sgs for free_page_vq. Acked-by: David Hildenbrand Signed-off-by: Jason Wang Message-Id: <20211129030841.3611-1-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio-balloon.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index c6962fcbfe..17de2558cb 100644 --- a/hw/virtio/virtio-balloon.c +++ b/hw/virtio/virtio-balloon.c @@ -510,6 +510,7 @@ static bool get_free_page_hints(VirtIOBalloon *dev) VirtIODevice *vdev = VIRTIO_DEVICE(dev); VirtQueue *vq = dev->free_page_vq; bool ret = true; + int i; while (dev->block_iothread) { qemu_cond_wait(&dev->free_page_cond, &dev->free_page_lock); @@ -544,8 +545,10 @@ static bool get_free_page_hints(VirtIOBalloon *dev) } if (elem->in_num && dev->free_page_hint_status == FREE_PAGE_HINT_S_START) { - qemu_guest_free_page_hint(elem->in_sg[0].iov_base, - elem->in_sg[0].iov_len); + for (i = 0; i < elem->in_num; i++) { + qemu_guest_free_page_hint(elem->in_sg[i].iov_base, + elem->in_sg[i].iov_len); + } } out: From d3f1f940ebe43403feb1d12e4b5b9236aba50cb9 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Mon, 29 Nov 2021 11:08:41 +0800 Subject: [PATCH 061/421] virtio-balloon: correct used length Spec said: "and len the total of bytes written into the buffer." For inflateq, deflateq and statsq, we don't process in_sg so the used length should be zero. For free_page_vq, tough the pages could be changed by the device (in the destination), spec said: "Note: len is particularly useful for drivers using untrusted buffers: if a driver does not know exactly how much has been written by the device, the driver would have to zero the buffer in advance to ensure no data leakage occurs." So 0 should be used as well here. Signed-off-by: Jason Wang Message-Id: <20211129030841.3611-2-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: David Hildenbrand --- hw/virtio/virtio-balloon.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index 17de2558cb..9a4f491b54 100644 --- a/hw/virtio/virtio-balloon.c +++ b/hw/virtio/virtio-balloon.c @@ -231,7 +231,7 @@ static void balloon_stats_poll_cb(void *opaque) return; } - virtqueue_push(s->svq, s->stats_vq_elem, s->stats_vq_offset); + virtqueue_push(s->svq, s->stats_vq_elem, 0); virtio_notify(vdev, s->svq); g_free(s->stats_vq_elem); s->stats_vq_elem = NULL; @@ -438,7 +438,7 @@ static void virtio_balloon_handle_output(VirtIODevice *vdev, VirtQueue *vq) memory_region_unref(section.mr); } - virtqueue_push(vq, elem, offset); + virtqueue_push(vq, elem, 0); virtio_notify(vdev, vq); g_free(elem); virtio_balloon_pbp_free(&pbp); @@ -552,7 +552,7 @@ static bool get_free_page_hints(VirtIOBalloon *dev) } out: - virtqueue_push(vq, elem, 1); + virtqueue_push(vq, elem, 0); g_free(elem); return ret; } From 0192d6677c383d812fb23f572fda4e449e89d3f1 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Mon, 29 Nov 2021 11:36:18 +0800 Subject: [PATCH 062/421] intel-iommu: ignore leaf SNP bit in scalable mode When booting with scalable mode, I hit this error: qemu-system-x86_64: vtd_iova_to_slpte: detected splte reserve non-zero iova=0xfffff002, level=0x1slpte=0x102681803) qemu-system-x86_64: vtd_iommu_translate: detected translation failure (dev=01:00:00, iova=0xfffff002) qemu-system-x86_64: New fault is not recorded due to compression of faults This is because the SNP bit is set for second level page table since Linux kernel commit 6c00612d0cba1 ("iommu/vt-d: Report right snoop capability when using FL for IOVA") even if SC is not supported by the hardware. To unbreak the guest, ignore the leaf SNP bit for scalable mode first. In the future we may consider to add SC support. Signed-off-by: Jason Wang Message-Id: <20211129033618.3857-1-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Peter Xu --- hw/i386/intel_iommu.c | 6 ++++++ hw/i386/intel_iommu_internal.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 294499ee20..f584449d8d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3629,6 +3629,12 @@ static void vtd_init(IntelIOMMUState *s) vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); + if (s->scalable_mode) { + vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP; + vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP; + vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP; + } + if (x86_iommu_ir_supported(x86_iommu)) { s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV; if (s->intr_eim == ON_OFF_AUTO_ON) { diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 3d5487fe2c..a6c788049b 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -388,6 +388,8 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 /* Rsvd field masks for spte */ +#define VTD_SPTE_SNP 0x800ULL + #define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ dt_supported ? \ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ From bacf58ca18f06f0b464466bf8c19945f19791feb Mon Sep 17 00:00:00 2001 From: Daniella Lee Date: Fri, 26 Nov 2021 14:13:24 +0800 Subject: [PATCH 063/421] Fix bad overflow check in hw/pci/pcie.c Orginal qemu commit hash:14d02cfbe4adaeebe7cb833a8cc71191352cf03b In function pcie_add_capability, an assert contains the "offset < offset + size" expression. Both variable offset and variable size are uint16_t, the comparison is always true due to type promotion. The next expression may be the same. It might be like this: Thread 1 "qemu-system-x86" hit Breakpoint 1, pcie_add_capability ( dev=0x555557ce5f10, cap_id=1, cap_ver=2 '\002', offset=256, size=72) at ../hw/pci/pcie.c:930 930 { (gdb) n 931 assert(offset >= PCI_CONFIG_SPACE_SIZE); (gdb) n 932 assert(offset < offset + size); (gdb) p offset $1 = 256 (gdb) p offset < offset + size $2 = 1 (gdb) set offset=65533 (gdb) p offset < offset + size $3 = 1 (gdb) p offset < (uint16_t)(offset + size) $4 = 0 Signed-off-by: Daniella Lee Message-Id: <20211126061324.47331-1-daniellalee111@gmail.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/pci/pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index c5ed266337..d7d73a31e4 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -929,8 +929,8 @@ void pcie_add_capability(PCIDevice *dev, uint16_t offset, uint16_t size) { assert(offset >= PCI_CONFIG_SPACE_SIZE); - assert(offset < offset + size); - assert(offset + size <= PCIE_CONFIG_SPACE_SIZE); + assert(offset < (uint16_t)(offset + size)); + assert((uint16_t)(offset + size) <= PCIE_CONFIG_SPACE_SIZE); assert(size >= 8); assert(pci_is_express(dev)); From 0a761ce30338526213f74dfe9900b9213d4bbb0b Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Mon, 22 Nov 2021 16:56:02 +0100 Subject: [PATCH 064/421] linux-user: implement more loop ioctls LOOP_CONFIGURE is now used by losetup, and it cannot cope with ENOSYS. Signed-off-by: Andreas Schwab Reviewed-by: Laurent Vivier Message-Id: Signed-off-by: Laurent Vivier --- linux-user/ioctls.h | 4 ++++ linux-user/linux_loop.h | 2 ++ linux-user/syscall_defs.h | 4 ++++ linux-user/syscall_types.h | 6 ++++++ 4 files changed, 16 insertions(+) diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h index 7193c3b226..f182d40190 100644 --- a/linux-user/ioctls.h +++ b/linux-user/ioctls.h @@ -637,6 +637,10 @@ IOCTL(LOOP_SET_STATUS64, IOC_W, MK_PTR(MK_STRUCT(STRUCT_loop_info64))) IOCTL(LOOP_GET_STATUS64, IOC_R, MK_PTR(MK_STRUCT(STRUCT_loop_info64))) IOCTL(LOOP_CHANGE_FD, 0, TYPE_INT) + IOCTL(LOOP_SET_CAPACITY, 0, TYPE_INT) + IOCTL(LOOP_SET_DIRECT_IO, 0, TYPE_INT) + IOCTL(LOOP_SET_BLOCK_SIZE, 0, TYPE_INT) + IOCTL(LOOP_CONFIGURE, IOC_W, MK_PTR(MK_STRUCT(STRUCT_loop_config))) IOCTL(LOOP_CTL_ADD, 0, TYPE_INT) IOCTL(LOOP_CTL_REMOVE, 0, TYPE_INT) diff --git a/linux-user/linux_loop.h b/linux-user/linux_loop.h index c69fea11e4..f80b96f1ff 100644 --- a/linux-user/linux_loop.h +++ b/linux-user/linux_loop.h @@ -96,6 +96,8 @@ struct loop_info64 { #define LOOP_CHANGE_FD 0x4C06 #define LOOP_SET_CAPACITY 0x4C07 #define LOOP_SET_DIRECT_IO 0x4C08 +#define LOOP_SET_BLOCK_SIZE 0x4C09 +#define LOOP_CONFIGURE 0x4C0A /* /dev/loop-control interface */ #define LOOP_CTL_ADD 0x4C80 diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 41aaafbac1..0b13975937 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1219,6 +1219,10 @@ struct target_rtc_pll_info { #define TARGET_LOOP_SET_STATUS64 0x4C04 #define TARGET_LOOP_GET_STATUS64 0x4C05 #define TARGET_LOOP_CHANGE_FD 0x4C06 +#define TARGET_LOOP_SET_CAPACITY 0x4C07 +#define TARGET_LOOP_SET_DIRECT_IO 0x4C08 +#define TARGET_LOOP_SET_BLOCK_SIZE 0x4C09 +#define TARGET_LOOP_CONFIGURE 0x4C0A #define TARGET_LOOP_CTL_ADD 0x4C80 #define TARGET_LOOP_CTL_REMOVE 0x4C81 diff --git a/linux-user/syscall_types.h b/linux-user/syscall_types.h index ba2c1518eb..c3b43f8022 100644 --- a/linux-user/syscall_types.h +++ b/linux-user/syscall_types.h @@ -201,6 +201,12 @@ STRUCT(loop_info64, MK_ARRAY(TYPE_CHAR, 32), /* lo_encrypt_key */ MK_ARRAY(TYPE_ULONGLONG, 2)) /* lo_init */ +STRUCT(loop_config, + TYPE_INT, /* fd */ + TYPE_INT, /* block_size */ + MK_STRUCT(STRUCT_loop_info64), /* info */ + MK_ARRAY(TYPE_ULONGLONG, 8)) /* __reserved */ + /* mag tape ioctls */ STRUCT(mtop, TYPE_SHORT, TYPE_INT) STRUCT(mtget, TYPE_LONG, TYPE_LONG, TYPE_LONG, TYPE_LONG, TYPE_LONG, From 48e14066ac10581db4e69f75eda107cfdafa6022 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 29 Nov 2021 14:09:25 +0000 Subject: [PATCH 065/421] accel/tcg: introduce CF_NOIRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Here we introduce a new compiler flag to disable the checking of exit request (icount_decr.u32). This is useful when we want to ensure the next block cannot be preempted by an asynchronous event. Suggested-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20211129140932.4115115-2-alex.bennee@linaro.org> --- include/exec/exec-all.h | 1 + include/exec/gen-icount.h | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6bb2a0f7ec..35d8e93976 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -503,6 +503,7 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x00020000 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 610cba58fe..c57204ddad 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -21,7 +21,6 @@ static inline void gen_tb_start(const TranslationBlock *tb) { TCGv_i32 count; - tcg_ctx->exitreq_label = gen_new_label(); if (tb_cflags(tb) & CF_USE_ICOUNT) { count = tcg_temp_local_new_i32(); } else { @@ -42,7 +41,19 @@ static inline void gen_tb_start(const TranslationBlock *tb) icount_start_insn = tcg_last_op(); } - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); + /* + * Emit the check against icount_decr.u32 to see if we should exit + * unless we suppress the check with CF_NOIRQ. If we are using + * icount and have suppressed interruption the higher level code + * should have ensured we don't run more instructions than the + * budget. + */ + if (tb_cflags(tb) & CF_NOIRQ) { + tcg_ctx->exitreq_label = NULL; + } else { + tcg_ctx->exitreq_label = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); + } if (tb_cflags(tb) & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, cpu_env, @@ -74,8 +85,10 @@ static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) tcgv_i32_arg(tcg_constant_i32(num_insns))); } - gen_set_label(tcg_ctx->exitreq_label); - tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED); + if (tcg_ctx->exitreq_label) { + gen_set_label(tcg_ctx->exitreq_label); + tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED); + } } #endif From aff0e204cb1f1c036a496c94c15f5dfafcd9b4b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 29 Nov 2021 14:09:26 +0000 Subject: [PATCH 066/421] accel/tcg: suppress IRQ check for special TBs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we set cpu->cflags_next_tb it is because we want to carefully control the execution of the next TB. Currently there is a race that causes the second stage of watchpoint handling to get ignored if an IRQ is processed before we finish executing the instruction that triggers the watchpoint. Use the new CF_NOIRQ facility to avoid the race. We also suppress IRQs when handling precise self modifying code to avoid unnecessary bouncing. Signed-off-by: Alex Bennée Cc: Pavel Dovgalyuk Fixes: https://gitlab.com/qemu-project/qemu/-/issues/245 Reviewed-by: Richard Henderson Message-Id: <20211129140932.4115115-3-alex.bennee@linaro.org> --- accel/tcg/cpu-exec.c | 9 +++++++++ accel/tcg/translate-all.c | 4 ++-- softmmu/physmem.c | 4 ++-- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2d14d02f6c..409ec8c38c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -721,6 +721,15 @@ static inline bool need_replay_interrupt(int interrupt_request) static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { + /* + * If we have requested custom cflags with CF_NOIRQ we should + * skip checking here. Any pending interrupts will get picked up + * by the next TB we execute under normal cflags. + */ + if (cpu->cflags_next_tb != -1 && cpu->cflags_next_tb & CF_NOIRQ) { + return false; + } + /* Clear the interrupt flag now since we're processing * cpu->interrupt_request and cpu->exit_request. * Ensure zeroing happens before reading cpu->exit_request or diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bd0bb81d08..bd71db59a9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1738,7 +1738,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(cpu); + cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } @@ -1906,7 +1906,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(cpu); + cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); return true; } #endif diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 314f8b439c..3524c04c2a 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -912,7 +912,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, */ if (!cpu->can_do_io) { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_LAST_IO | curr_cflags(cpu); + cpu->cflags_next_tb = 1 | CF_LAST_IO | CF_NOIRQ | curr_cflags(cpu); cpu_loop_exit_restore(cpu, ra); } /* @@ -946,7 +946,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu_loop_exit(cpu); } else { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_LAST_IO | curr_cflags(cpu); + cpu->cflags_next_tb = 1 | CF_LAST_IO | CF_NOIRQ | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } From a7c6e562e6f3f4e009c5dfa4e44cbbe908c4bf05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 29 Nov 2021 14:09:27 +0000 Subject: [PATCH 067/421] tests/avocado: fix tcg_plugin mem access count test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we cleaned up argument handling the test was missed. Fixes: 5ae589faad ("tests/plugins/mem: introduce "track" arg and make args not positional") Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211129140932.4115115-4-alex.bennee@linaro.org> --- tests/avocado/tcg_plugins.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/avocado/tcg_plugins.py b/tests/avocado/tcg_plugins.py index 9ca1515c3b..642d2e49e3 100644 --- a/tests/avocado/tcg_plugins.py +++ b/tests/avocado/tcg_plugins.py @@ -131,7 +131,7 @@ class PluginKernelNormal(PluginKernelBase): suffix=".log") self.run_vm(kernel_path, kernel_command_line, - "tests/plugin/libmem.so,arg=both", plugin_log.name, + "tests/plugin/libmem.so,inline=true,callback=true", plugin_log.name, console_pattern, args=('-icount', 'shift=1')) From 86a41ac7fd488ce084175a30d1e5fd92dc37596b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 29 Nov 2021 14:09:28 +0000 Subject: [PATCH 068/421] plugins/meson.build: fix linker issue with weird paths MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alex Bennée Tested-by: Stefan Weil Fixes: https://gitlab.com/qemu-project/qemu/-/issues/712 Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211129140932.4115115-5-alex.bennee@linaro.org> --- plugins/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/plugins/meson.build b/plugins/meson.build index aeb386ebae..b3de57853b 100644 --- a/plugins/meson.build +++ b/plugins/meson.build @@ -2,9 +2,9 @@ plugin_ldflags = [] # Modules need more symbols than just those in plugins/qemu-plugins.symbols if not enable_modules if 'CONFIG_HAS_LD_DYNAMIC_LIST' in config_host - plugin_ldflags = ['-Wl,--dynamic-list=' + (meson.project_build_root() / 'qemu-plugins-ld.symbols')] + plugin_ldflags = ['-Wl,--dynamic-list=qemu-plugins-ld.symbols'] elif 'CONFIG_HAS_LD_EXPORTED_SYMBOLS_LIST' in config_host - plugin_ldflags = ['-Wl,-exported_symbols_list,' + (meson.project_build_root() / 'qemu-plugins-ld64.symbols')] + plugin_ldflags = ['-Wl,-exported_symbols_list,qemu-plugins-ld64.symbols'] endif endif From a8e537fa4d61b29c5c0ab1395918ad63f7752b25 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 29 Nov 2021 14:09:29 +0000 Subject: [PATCH 069/421] gdbstub: handle a potentially racing TaskState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When dealing with multi-threaded userspace programs there is a race condition with the addition of cpu->opaque (aka TaskState). This is due to cpu_copy calling cpu_create which updates the global vCPU list. However the task state isn't set until later. This shouldn't be a problem because the new thread can't have executed anything yet but the gdbstub code does liberally iterate through the CPU list in various places. This sticking plaster ensure the not yet fully realized vCPU is given an pid of -1 which should be enough to ensure it doesn't show up anywhere else. In the longer term I think the code that manages the association between vCPUs and attached GDB processes could do with a clean-up and re-factor. Signed-off-by: Alex Bennée Tested-by: Richard Henderson Reviewed-by: Richard Henderson Cc: Richard Henderson Resolves: https://gitlab.com/qemu-project/qemu/-/issues/730 Message-Id: <20211129140932.4115115-6-alex.bennee@linaro.org> --- gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbstub.c b/gdbstub.c index 23baaef40e..141d7bc4ec 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -94,7 +94,7 @@ static inline int cpu_gdb_index(CPUState *cpu) { #if defined(CONFIG_USER_ONLY) TaskState *ts = (TaskState *) cpu->opaque; - return ts->ts_tid; + return ts ? ts->ts_tid : -1; #else return cpu->cpu_index + 1; #endif From 40525be5cbe768b23b427c6535c0b11bda80c851 Mon Sep 17 00:00:00 2001 From: Willian Rampazzo Date: Mon, 29 Nov 2021 14:09:30 +0000 Subject: [PATCH 070/421] MAINTAINERS: Remove me as a reviewer for the build and test/avocado MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove me as a reviewer for the Build and test automation and the Integration Testing with the Avocado Framework and add Beraldo Leal. Signed-off-by: Willian Rampazzo Reviewed-by: Beraldo Leal Message-Id: <20211122191124.31620-1-willianr@redhat.com> Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211129140932.4115115-7-alex.bennee@linaro.org> --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d3879aa3c1..8f5156bfa7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3469,7 +3469,7 @@ M: Alex Bennée M: Philippe Mathieu-Daudé M: Thomas Huth R: Wainer dos Santos Moschetta -R: Willian Rampazzo +R: Beraldo Leal S: Maintained F: .github/lockdown.yml F: .gitlab-ci.yml @@ -3507,7 +3507,7 @@ W: https://trello.com/b/6Qi1pxVn/avocado-qemu R: Cleber Rosa R: Philippe Mathieu-Daudé R: Wainer dos Santos Moschetta -R: Willian Rampazzo +R: Beraldo Leal S: Odd Fixes F: tests/avocado/ From 1e970158be18ed1142a8ba996448113f90848aa4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 29 Nov 2021 14:09:31 +0000 Subject: [PATCH 071/421] MAINTAINERS: Add section for Aarch64 GitLab custom runner MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a MAINTAINERS section to cover the GitLab YAML config file containing the jobs run on the custom runner sponsored by the Works On Arm project [*]. [*] https://developer.arm.com/solutions/infrastructure/works-on-arm Suggested-by: Thomas Huth Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Alex Bennée Message-Id: <20211116163226.2719320-1-f4bug@amsat.org> Message-Id: <20211129140932.4115115-8-alex.bennee@linaro.org> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8f5156bfa7..006a2293ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3511,6 +3511,12 @@ R: Beraldo Leal S: Odd Fixes F: tests/avocado/ +GitLab custom runner (Works On Arm Sponsored) +M: Alex Bennée +M: Philippe Mathieu-Daudé +S: Maintained +F: .gitlab-ci.d/custom-runners/ubuntu-20.04-aarch64.yml + Documentation ------------- Build system architecture From d5615bbf9103f01911df683cc3e4e85c49a92593 Mon Sep 17 00:00:00 2001 From: Juro Bystricky Date: Mon, 29 Nov 2021 14:09:32 +0000 Subject: [PATCH 072/421] tests/plugin/syscall.c: fix compiler warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix compiler warnings. The warnings can result in a broken build. This patch fixes warnings such as: In file included from /usr/include/glib-2.0/glib.h:111, from ../tests/plugin/syscall.c:13: ../tests/plugin/syscall.c: In function ‘print_entry’: /usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: error: ‘out’ may be used uninitialized in this function [-Werror=maybe-uninitialized] g_free (*pp); ^~~~~~~~~~~~ ../tests/plugin/syscall.c:82:23: note: ‘out’ was declared here g_autofree gchar *out; ^~~ In file included from /usr/include/glib-2.0/glib.h:111, from ../tests/plugin/syscall.c:13: ../tests/plugin/syscall.c: In function ‘vcpu_syscall_ret’: /usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: error: ‘out’ may be used uninitialized in this function [-Werror=maybe-uninitialized] g_free (*pp); ^~~~~~~~~~~~ ../tests/plugin/syscall.c:73:27: note: ‘out’ was declared here g_autofree gchar *out; ^~~ cc1: all warnings being treated as errors Signed-off-by: Juro Bystricky Signed-off-by: Alex Bennée Message-Id: <20211128011551.2115468-1-juro.bystricky@intel.com> Reviewed-by: Richard Henderson Message-Id: <20211129140932.4115115-9-alex.bennee@linaro.org> --- tests/plugin/syscall.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tests/plugin/syscall.c b/tests/plugin/syscall.c index 484b48de49..96040c578f 100644 --- a/tests/plugin/syscall.c +++ b/tests/plugin/syscall.c @@ -70,19 +70,17 @@ static void vcpu_syscall_ret(qemu_plugin_id_t id, unsigned int vcpu_idx, } g_mutex_unlock(&lock); } else { - g_autofree gchar *out; - out = g_strdup_printf("syscall #%" PRIi64 " returned -> %" PRIi64 "\n", - num, ret); + g_autofree gchar *out = g_strdup_printf( + "syscall #%" PRIi64 " returned -> %" PRIi64 "\n", num, ret); qemu_plugin_outs(out); } } static void print_entry(gpointer val, gpointer user_data) { - g_autofree gchar *out; SyscallStats *entry = (SyscallStats *) val; int64_t syscall_num = entry->num; - out = g_strdup_printf( + g_autofree gchar *out = g_strdup_printf( "%-13" PRIi64 "%-6" PRIi64 " %" PRIi64 "\n", syscall_num, entry->calls, entry->errors); qemu_plugin_outs(out); From 7bf00dfb51566070960e0b7977e41abba96c130e Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Mon, 29 Nov 2021 15:57:51 -0300 Subject: [PATCH 073/421] target/ppc: fix Hash64 MMU update of PTE bit R MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When updating the R bit of a PTE, the Hash64 MMU was using a wrong byte offset, causing the first byte of the adjacent PTE to be corrupted. This caused a panic when booting FreeBSD, using the Hash MMU. Fixes: a2dd4e83e76b ("ppc/hash64: Rework R and C bit updates") Signed-off-by: Leandro Lupori Signed-off-by: Cédric Le Goater --- hw/ppc/spapr.c | 8 ++++---- hw/ppc/spapr_softmmu.c | 2 +- target/ppc/mmu-hash64.c | 4 ++-- target/ppc/mmu-hash64.h | 5 +++++ 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 163c90388a..3b5fd749be 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1414,7 +1414,7 @@ void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, kvmppc_write_hpte(ptex, pte0, pte1); } else { if (pte0 & HPTE64_V_VALID) { - stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); + stq_p(spapr->htab + offset + HPTE64_DW1, pte1); /* * When setting valid, we write PTE1 first. This ensures * proper synchronization with the reading code in @@ -1430,7 +1430,7 @@ void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, * ppc_hash64_pteg_search() */ smp_wmb(); - stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); + stq_p(spapr->htab + offset + HPTE64_DW1, pte1); } } } @@ -1438,7 +1438,7 @@ void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1) { - hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15; + hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); if (!spapr->htab) { @@ -1454,7 +1454,7 @@ static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1) { - hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14; + hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); if (!spapr->htab) { diff --git a/hw/ppc/spapr_softmmu.c b/hw/ppc/spapr_softmmu.c index f8924270ef..4ee03c83e4 100644 --- a/hw/ppc/spapr_softmmu.c +++ b/hw/ppc/spapr_softmmu.c @@ -426,7 +426,7 @@ static void new_hpte_store(void *htab, uint64_t pteg, int slot, addr += slot * HASH_PTE_SIZE_64; stq_p(addr, pte0); - stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); + stq_p(addr + HPTE64_DW1, pte1); } static int rehash_hpte(PowerPCCPU *cpu, diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 19832c4b46..da9fe99ff8 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -786,7 +786,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) { - hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16; + hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; if (cpu->vhyp) { PPCVirtualHypervisorClass *vhc = @@ -803,7 +803,7 @@ static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) { - hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15; + hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; if (cpu->vhyp) { PPCVirtualHypervisorClass *vhc = diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index c5b2f97ff7..1496955d38 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -97,6 +97,11 @@ void ppc_hash64_finalize(PowerPCCPU *cpu); #define HPTE64_V_1TB_SEG 0x4000000000000000ULL #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL +/* PTE offsets */ +#define HPTE64_DW1 (HASH_PTE_SIZE_64 / 2) +#define HPTE64_DW1_R (HPTE64_DW1 + 6) +#define HPTE64_DW1_C (HPTE64_DW1 + 7) + /* Format changes for ARCH v3 */ #define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL #define HPTE64_R_3_0_SSIZE_SHIFT 58 From 4051a1f062c9b336343e22efa291ed15d235cd4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 23 Nov 2021 12:17:31 +0100 Subject: [PATCH 074/421] hw/scsi/lsi53c895a: Do not abort when DMA requested and no data queued MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If asked for DMA request and no data is available, simply wait for data to be queued, do not abort. This fixes: $ cat << EOF | \ qemu-system-i386 -nographic -M q35,accel=qtest -serial none \ -monitor none -qtest stdio -trace lsi* \ -drive if=none,id=drive0,file=null-co://,file.read-zeroes=on,format=raw \ -device lsi53c895a,id=scsi0 -device scsi-hd,drive=drive0,bus=scsi0.0,channel=0,scsi-id=0,lun=0 lsi_reset Reset lsi_reg_write Write reg DSP2 0x2e = 0xff lsi_reg_write Write reg DSP3 0x2f = 0xff lsi_execute_script SCRIPTS dsp=0xffff0000 opcode 0x184a3900 arg 0x4a8b2d75 qemu-system-i386: hw/scsi/lsi53c895a.c:624: lsi_do_dma: Assertion `s->current' failed. (gdb) bt #5 0x00007ffff4e8a3a6 in __GI___assert_fail (assertion=0x5555560accbc "s->current", file=0x5555560acc28 "hw/scsi/lsi53c895a.c", line=624, function=0x5555560adb18 "lsi_do_dma") at assert.c:101 #6 0x0000555555aa33b9 in lsi_do_dma (s=0x555557805ac0, out=1) at hw/scsi/lsi53c895a.c:624 #7 0x0000555555aa5042 in lsi_execute_script (s=0x555557805ac0) at hw/scsi/lsi53c895a.c:1250 #8 0x0000555555aa757a in lsi_reg_writeb (s=0x555557805ac0, offset=47, val=255 '\377') at hw/scsi/lsi53c895a.c:1984 #9 0x0000555555aa875b in lsi_mmio_write (opaque=0x555557805ac0, addr=47, val=255, size=1) at hw/scsi/lsi53c895a.c:2095 Cc: qemu-stable@nongnu.org Cc: Gerd Hoffmann Cc: Vadim Rozenfeld Cc: Stefan Hajnoczi Reported-by: Jérôme Poulin Reported-by: Ruhr-University Reported-by: Gaoning Pan Reported-by: Cheolwoo Myung Fixes: b96a0da06bd ("lsi: move dma_len+dma_buf into lsi_request") BugLink: https://bugs.launchpad.net/qemu/+bug/697510 BugLink: https://bugs.launchpad.net/qemu/+bug/1905521 BugLink: https://bugs.launchpad.net/qemu/+bug/1908515 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/84 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/305 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/552 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20211123111732.83137-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- hw/scsi/lsi53c895a.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 85e907a785..4c431adb77 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -621,8 +621,7 @@ static void lsi_do_dma(LSIState *s, int out) dma_addr_t addr; SCSIDevice *dev; - assert(s->current); - if (!s->current->dma_len) { + if (!s->current || !s->current->dma_len) { /* Wait until data is available. */ trace_lsi_do_dma_unavailable(); return; From aa62976c9d207d85fd503af7dc397c19e5782dae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 23 Nov 2021 12:17:32 +0100 Subject: [PATCH 075/421] tests/qtest: Add fuzz-lsi53c895a-test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without the previous commit, this test triggers: $ make check-qtest-x86_64 [...] Running test qtest-x86_64/fuzz-lsi53c895a-test qemu-system-x86_64: hw/scsi/lsi53c895a.c:624: lsi_do_dma: Assertion `s->current' failed. ERROR qtest-x86_64/fuzz-lsi53c895a-test - too few tests run (expected 1, got 0) Suggested-by: Alexander Bulekov Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-Id: <20211123111732.83137-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- MAINTAINERS | 1 + tests/qtest/fuzz-lsi53c895a-test.c | 52 ++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 3 files changed, 54 insertions(+) create mode 100644 tests/qtest/fuzz-lsi53c895a-test.c diff --git a/MAINTAINERS b/MAINTAINERS index 006a2293ba..4d2143ff23 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1825,6 +1825,7 @@ F: hw/scsi/* F: tests/qtest/virtio-scsi-test.c F: tests/qtest/fuzz-virtio-scsi-test.c F: tests/qtest/am53c974-test.c +F: tests/qtest/fuzz-lsi53c895a-test.c T: git https://github.com/bonzini/qemu.git scsi-next SSI diff --git a/tests/qtest/fuzz-lsi53c895a-test.c b/tests/qtest/fuzz-lsi53c895a-test.c new file mode 100644 index 0000000000..ba5d468970 --- /dev/null +++ b/tests/qtest/fuzz-lsi53c895a-test.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QTest fuzzer-generated testcase for LSI53C895A device + * + * Copyright (c) Red Hat + */ + +#include "qemu/osdep.h" +#include "libqos/libqtest.h" + +/* + * This used to trigger the assert in lsi_do_dma() + * https://bugs.launchpad.net/qemu/+bug/697510 + * https://bugs.launchpad.net/qemu/+bug/1905521 + * https://bugs.launchpad.net/qemu/+bug/1908515 + */ +static void test_lsi_do_dma_empty_queue(void) +{ + QTestState *s; + + s = qtest_init("-M q35 -nographic -monitor none -serial none " + "-drive if=none,id=drive0," + "file=null-co://,file.read-zeroes=on,format=raw " + "-device lsi53c895a,id=scsi0 " + "-device scsi-hd,drive=drive0," + "bus=scsi0.0,channel=0,scsi-id=0,lun=0"); + qtest_outl(s, 0xcf8, 0x80001814); + qtest_outl(s, 0xcfc, 0xe1068000); + qtest_outl(s, 0xcf8, 0x80001818); + qtest_outl(s, 0xcf8, 0x80001804); + qtest_outw(s, 0xcfc, 0x7); + qtest_outl(s, 0xcf8, 0x80002010); + + qtest_writeb(s, 0xe106802e, 0xff); /* Fill DSP bits 16-23 */ + qtest_writeb(s, 0xe106802f, 0xff); /* Fill DSP bits 24-31: trigger SCRIPT */ + + qtest_quit(s); +} + +int main(int argc, char **argv) +{ + const char *arch = qtest_get_arch(); + + g_test_init(&argc, &argv, NULL); + + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + qtest_add_func("fuzz/lsi53c895a/lsi_do_dma_empty_queue", + test_lsi_do_dma_empty_queue); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c9d8458062..d2ce20d304 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -19,6 +19,7 @@ slow_qtests = { qtests_generic = \ (config_all_devices.has_key('CONFIG_MEGASAS_SCSI_PCI') ? ['fuzz-megasas-test'] : []) + \ + (config_all_devices.has_key('CONFIG_LSI_SCSI_PCI') ? ['fuzz-lsi53c895a-test'] : []) + \ (config_all_devices.has_key('CONFIG_VIRTIO_SCSI') ? ['fuzz-virtio-scsi-test'] : []) + \ (config_all_devices.has_key('CONFIG_SB16') ? ['fuzz-sb16-test'] : []) + \ (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \ From 226fad7371c6559d4f0bdca66d0e08d45d3cb767 Mon Sep 17 00:00:00 2001 From: Yanan Wang Date: Mon, 22 Nov 2021 11:26:51 +0800 Subject: [PATCH 076/421] qapi/machine.json: Fix incorrect description for die-id In terms of scope, die-id should mean "the die number within socket the CPU belongs to" instead of "the die number within node/board the CPU belongs to". Fix it to avoid confusing the Doc reader. Fixes: 176d2cda0d ("i386/cpu: Consolidate die-id validity in smp context") Signed-off-by: Yanan Wang Reviewed-by: Eric Blake Message-Id: <20211122032651.16064-1-wangyanan55@huawei.com> Signed-off-by: Paolo Bonzini --- qapi/machine.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qapi/machine.json b/qapi/machine.json index 067e3f5378..f1839acf20 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -867,7 +867,7 @@ # # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to -# @die-id: die number within node/board the CPU belongs to (Since 4.1) +# @die-id: die number within socket the CPU belongs to (since 4.1) # @core-id: core number within die the CPU belongs to # @thread-id: thread number within core the CPU belongs to # From 4006a27c5e44734350009262efb0e2ec8da5ff09 Mon Sep 17 00:00:00 2001 From: Evan Miller Date: Tue, 30 Nov 2021 12:30:12 -0500 Subject: [PATCH 077/421] scripts/entitlement.sh: Use backward-compatible cp flags Older versions of Mac OS X do not support cp -a. The cp man page indicates that -a is equivalent to -pPR. Signed-off-by: Evan Miller Message-Id: <40635C6E-059A-4146-B1E2-F6376700EE85@gmail.com> [Leave out -R, these are files and not directories. - Paolo] Signed-off-by: Paolo Bonzini --- scripts/entitlement.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/entitlement.sh b/scripts/entitlement.sh index e2c956a3ac..0f412949ec 100755 --- a/scripts/entitlement.sh +++ b/scripts/entitlement.sh @@ -15,7 +15,7 @@ ENTITLEMENT="$4" if $in_place; then trap 'rm "$DST.tmp"' exit - cp -af "$SRC" "$DST.tmp" + cp -pPf "$SRC" "$DST.tmp" SRC="$DST.tmp" else cd "$MESON_INSTALL_DESTDIR_PREFIX" From 24c4cd1311a45fa8ecfcde2f7b7afe84eb17dfac Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Tue, 30 Nov 2021 15:47:22 -0500 Subject: [PATCH 078/421] MAINTAINERS: Change my email address The ehabkost@redhat.com email address will stop working on 2021-12-01, change it to my personal email address. Signed-off-by: Eduardo Habkost Message-Id: <20211129163053.2506734-1-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost Message-Id: <20211130204722.2732997-2-ehabkost@redhat.com> Signed-off-by: Richard Henderson --- MAINTAINERS | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 006a2293ba..7543eb4d59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,7 +324,7 @@ F: disas/sparc.c X86 TCG CPUs M: Paolo Bonzini M: Richard Henderson -M: Eduardo Habkost +M: Eduardo Habkost S: Maintained F: target/i386/tcg/ F: tests/tcg/i386/ @@ -1628,7 +1628,7 @@ F: include/hw/i386/microvm.h F: pc-bios/bios-microvm.bin Machine core -M: Eduardo Habkost +M: Eduardo Habkost M: Marcel Apfelbaum R: Philippe Mathieu-Daudé S: Supported @@ -2648,13 +2648,13 @@ F: backends/cryptodev*.c Python library M: John Snow M: Cleber Rosa -R: Eduardo Habkost +R: Eduardo Habkost S: Maintained F: python/ T: git https://gitlab.com/jsnow/qemu.git python Python scripts -M: Eduardo Habkost +M: Eduardo Habkost M: Cleber Rosa S: Odd Fixes F: scripts/*.py @@ -2730,7 +2730,7 @@ T: git https://github.com/mdroth/qemu.git qga QOM M: Paolo Bonzini R: Daniel P. Berrange -R: Eduardo Habkost +R: Eduardo Habkost S: Supported F: docs/qdev-device-use.txt F: hw/core/qdev* @@ -2750,7 +2750,7 @@ F: tests/unit/check-qom-proplist.c F: tests/unit/test-qdev-global-props.c QOM boilerplate conversion script -M: Eduardo Habkost +M: Eduardo Habkost S: Maintained F: scripts/codeconverter/ From 682aa69b1f4dd5f2905a94066fa4c853adc33251 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 1 Dec 2021 07:20:06 +0100 Subject: [PATCH 079/421] Update version for v6.2.0-rc3 release Signed-off-by: Richard Henderson --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index f5664554ca..cbd3fe98d1 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.1.92 +6.1.93 From b154791e7b6d4ca5cdcd54443484d97360bd7ad2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 24 Nov 2021 17:15:34 +0100 Subject: [PATCH 080/421] hw/block/fdc: Extract blk_create_empty_drive() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are going to re-use this code in the next commit, so extract it as a new blk_create_empty_drive() function. Inspired-by: Hanna Reitz Signed-off-by: Philippe Mathieu-Daudé Message-id: 20211124161536.631563-2-philmd@redhat.com Signed-off-by: John Snow --- hw/block/fdc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/block/fdc.c b/hw/block/fdc.c index fa933cd326..1dbf3f6028 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -61,6 +61,12 @@ } while (0) +/* Anonymous BlockBackend for empty drive */ +static BlockBackend *blk_create_empty_drive(void) +{ + return blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL); +} + /********************************************************/ /* qdev floppy bus */ @@ -486,8 +492,7 @@ static void floppy_drive_realize(DeviceState *qdev, Error **errp) } if (!dev->conf.blk) { - /* Anonymous BlockBackend for an empty drive */ - dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL); + dev->conf.blk = blk_create_empty_drive(); ret = blk_attach_dev(dev->conf.blk, qdev); assert(ret == 0); From 1ab95af033a419e7a64e2d58e67dd96b20af5233 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 24 Nov 2021 17:15:35 +0100 Subject: [PATCH 081/421] hw/block/fdc: Kludge missing floppy drive to fix CVE-2021-20196 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Guest might select another drive on the bus by setting the DRIVE_SEL bit of the DIGITAL OUTPUT REGISTER (DOR). The current controller model doesn't expect a BlockBackend to be NULL. A simple way to fix CVE-2021-20196 is to create an empty BlockBackend when it is missing. All further accesses will be safely handled, and the controller state machines keep behaving correctly. Cc: qemu-stable@nongnu.org Fixes: CVE-2021-20196 Reported-by: Gaoning Pan (Ant Security Light-Year Lab) Reviewed-by: Darren Kenny Reviewed-by: Hanna Reitz Signed-off-by: Philippe Mathieu-Daudé Message-id: 20211124161536.631563-3-philmd@redhat.com BugLink: https://bugs.launchpad.net/qemu/+bug/1912780 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/338 Reviewed-by: Darren Kenny Reviewed-by: Hanna Reitz Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: John Snow --- hw/block/fdc.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/block/fdc.c b/hw/block/fdc.c index 1dbf3f6028..21d18ac2e3 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -1166,7 +1166,19 @@ static FDrive *get_drv(FDCtrl *fdctrl, int unit) static FDrive *get_cur_drv(FDCtrl *fdctrl) { - return get_drv(fdctrl, fdctrl->cur_drv); + FDrive *cur_drv = get_drv(fdctrl, fdctrl->cur_drv); + + if (!cur_drv->blk) { + /* + * Kludge: empty drive line selected. Create an anonymous + * BlockBackend to avoid NULL deref with various BlockBackend + * API calls within this model (CVE-2021-20196). + * Due to the controller QOM model limitations, we don't + * attach the created to the controller device. + */ + cur_drv->blk = blk_create_empty_drive(); + } + return cur_drv; } /* Status A register : 0x00 (read-only) */ From cc20926e9b8077bff6813efc8dcdeae90d1a3b10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 24 Nov 2021 17:15:36 +0100 Subject: [PATCH 082/421] tests/qtest/fdc-test: Add a regression test for CVE-2021-20196 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without the previous commit, when running 'make check-qtest-i386' with QEMU configured with '--enable-sanitizers' we get: AddressSanitizer:DEADLYSIGNAL ================================================================= ==287878==ERROR: AddressSanitizer: SEGV on unknown address 0x000000000344 ==287878==The signal is caused by a WRITE memory access. ==287878==Hint: address points to the zero page. #0 0x564b2e5bac27 in blk_inc_in_flight block/block-backend.c:1346:5 #1 0x564b2e5bb228 in blk_pwritev_part block/block-backend.c:1317:5 #2 0x564b2e5bcd57 in blk_pwrite block/block-backend.c:1498:11 #3 0x564b2ca1cdd3 in fdctrl_write_data hw/block/fdc.c:2221:17 #4 0x564b2ca1b2f7 in fdctrl_write hw/block/fdc.c:829:9 #5 0x564b2dc49503 in portio_write softmmu/ioport.c:201:9 Add the reproducer for CVE-2021-20196. Suggested-by: Alexander Bulekov Reviewed-by: Darren Kenny Signed-off-by: Philippe Mathieu-Daudé Message-id: 20211124161536.631563-4-philmd@redhat.com Signed-off-by: John Snow --- tests/qtest/fdc-test.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/tests/qtest/fdc-test.c b/tests/qtest/fdc-test.c index 26b69f7c5c..8f6eee84a4 100644 --- a/tests/qtest/fdc-test.c +++ b/tests/qtest/fdc-test.c @@ -32,6 +32,9 @@ /* TODO actually test the results and get rid of this */ #define qmp_discard_response(...) qobject_unref(qmp(__VA_ARGS__)) +#define DRIVE_FLOPPY_BLANK \ + "-drive if=floppy,file=null-co://,file.read-zeroes=on,format=raw,size=1440k" + #define TEST_IMAGE_SIZE 1440 * 1024 #define FLOPPY_BASE 0x3f0 @@ -546,6 +549,40 @@ static void fuzz_registers(void) } } +static bool qtest_check_clang_sanitizer(void) +{ +#if defined(__SANITIZE_ADDRESS__) || __has_feature(address_sanitizer) + return true; +#else + g_test_skip("QEMU not configured using --enable-sanitizers"); + return false; +#endif +} +static void test_cve_2021_20196(void) +{ + QTestState *s; + + if (!qtest_check_clang_sanitizer()) { + return; + } + + s = qtest_initf("-nographic -m 32M -nodefaults " DRIVE_FLOPPY_BLANK); + + qtest_outw(s, 0x3f4, 0x0500); + qtest_outb(s, 0x3f5, 0x00); + qtest_outb(s, 0x3f5, 0x00); + qtest_outw(s, 0x3f4, 0x0000); + qtest_outb(s, 0x3f5, 0x00); + qtest_outw(s, 0x3f1, 0x0400); + qtest_outw(s, 0x3f4, 0x0000); + qtest_outw(s, 0x3f4, 0x0000); + qtest_outb(s, 0x3f5, 0x00); + qtest_outb(s, 0x3f5, 0x01); + qtest_outw(s, 0x3f1, 0x0500); + qtest_outb(s, 0x3f5, 0x00); + qtest_quit(s); +} + int main(int argc, char **argv) { int fd; @@ -576,6 +613,7 @@ int main(int argc, char **argv) qtest_add_func("/fdc/read_no_dma_18", test_read_no_dma_18); qtest_add_func("/fdc/read_no_dma_19", test_read_no_dma_19); qtest_add_func("/fdc/fuzz-registers", fuzz_registers); + qtest_add_func("/fdc/fuzz/cve_2021_20196", test_cve_2021_20196); ret = g_test_run(); From e7fa3377ccee50b0fd4596c06d2e62815e74328b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 3 Dec 2021 07:01:08 +0100 Subject: [PATCH 083/421] seabios: update submodule to 1.15.0 Update seabios to the final release. No code changes compared to the snapshot merged a few weeks ago. shortlog 64f37cc530f1..rel-1.15.0 --------------------------------- Kevin O'Connor (1): docs: Note v1.15.0 release Signed-off-by: Gerd Hoffmann --- roms/seabios | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/roms/seabios b/roms/seabios index 64f37cc530..2dd4b9b3f8 160000 --- a/roms/seabios +++ b/roms/seabios @@ -1 +1 @@ -Subproject commit 64f37cc530f144e53c190c9e8209a51b58fd5c43 +Subproject commit 2dd4b9b3f84019668719344b40dba79d681be41c From 3bc90ac567f64fbe07b17b1174c85ec8a3e17d94 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 3 Dec 2021 07:09:22 +0100 Subject: [PATCH 084/421] seabios: update binaries to 1.15.0 Signed-off-by: Gerd Hoffmann --- pc-bios/bios-256k.bin | Bin 262144 -> 262144 bytes pc-bios/bios-microvm.bin | Bin 131072 -> 131072 bytes pc-bios/bios.bin | Bin 131072 -> 131072 bytes pc-bios/vgabios-ati.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-bochs-display.bin | Bin 28672 -> 28672 bytes pc-bios/vgabios-cirrus.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-qxl.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-ramfb.bin | Bin 28672 -> 28672 bytes pc-bios/vgabios-stdvga.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-virtio.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios-vmware.bin | Bin 39424 -> 39424 bytes pc-bios/vgabios.bin | Bin 38912 -> 38912 bytes 12 files changed, 0 insertions(+), 0 deletions(-) diff --git a/pc-bios/bios-256k.bin b/pc-bios/bios-256k.bin index dea01da468932e67251e9ca3d443ec91d870a2ec..26f863b60926cb5dc768cff39fe944c9d297de80 100644 GIT binary patch delta 135 zcmZo@5NH6R7RDB)EzBu_InG7-#l;GShI&SNhPsBD3Q3uHr6rj;#a0SssYS(^`FRRP zddB9u#(HVV#-xAioGno9g%LOq%S_=TJy)8xn delta 105 zcmZo@5NH6R7RDB)EzBu_)3XAZ<+)7tjC9TP(vpo$rauf}7S=6F&CxZ~Gc?gN&^0pG zO*b=1Gd537HZ?X#Gt@08N=+)w%qh_;OwBFT%P&fw{?Lt4e4>ELbe|w*k!hjKEZY@= Im>;YK0D%@DXaE2J diff --git a/pc-bios/bios-microvm.bin b/pc-bios/bios-microvm.bin index ca6375d65c9d0b77dda0da82f6a0575d7c800f00..ddeb24391d158c7b4625674ba23151e70032339b 100644 GIT binary patch delta 125 zcmZo@;AjA%EsQM-Gn|X^i;EQu4fTxl40R1P6_PUZN=q_ximepNQj3Z+^Yavp^o-4Q zjrG!!jZGQSCLqJ2)Er$yJwsDH16>2%bfc6MlO)R|<1`Bs1Kon6)TGkPoD#jl)Z9|N R{G#;f2bMF6EL+4F2LMWlDu4h0 delta 99 zcmZo@;AjA%EsQM-r*|!6l=m^!GtxEFOG`F3VMv>R4vSKAbPe?kP4oRF-$J-)} diff --git a/pc-bios/bios.bin b/pc-bios/bios.bin index e9fa99f006b74fa2c835dacf5ba8fb3c6825f426..6e6cde8c7fa722f28651e884a4c80573563baacb 100644 GIT binary patch delta 125 zcmZo@;AjA%EsQMj+0I4z#l;GShI&SNhPsBD3Q3uHr6rj;#a0SssYS(^`FRRPddB9u z#(HVV#--PM3#)%66@7F1` delta 86 zcmZo@;AjA%EsQMj)4Adq<+)7tjC9TP(vpo$rYj~f3hNi8=I9#g8Jg%B=o*>prkk0h o8Jj03n;ILW8R`}kr6!eT=9K6arskIFLNy&KtMXXZE;l*8&B^#SEq)kAEMX5QuhI)pkdIq`%y6HwKDJDslNycdwCI-3%MX5=p XnK>nTg{irvdih1^3=B*x69WwZz>+JV delta 103 zcmZqJ!ql*Zi9K|c@5>LNDI3{iXHL$VDer5lXQXSUmzHd7!jLur9TuhL=o;!7n&=tm t8ky^+o0+5;nJ}8GCY5I9l;{l*8&B^#SEq)kAEMX5QuhI)pkdIq`%y6HwKDJDslNycdwCI-3%MX5=p anK>nTg{irvdih1^3=B*xn-9iKU<3f#i7aaX delta 105 zcmZqJ!ql*Zi9K|c@5_+D2OHV{PM^#*L*Ca^&q&uyFD=>FgduGLIxI@f(KXaFG|@BA vH8R&tH#12yHcw7AH8w~y)Ga7VO)AaIDbXuT%`Mf-FG^=%V%dB!ZUQ3!9a$w? diff --git a/pc-bios/vgabios-qxl.bin b/pc-bios/vgabios-qxl.bin index 420f9ed3319025db97dd895ae574c0ee8aa41433..0cc20678a3faf187c6f5e3a83560e9f1a64dc986 100644 GIT binary patch delta 131 zcmZqJ!ql*Zi9K|c@5{HLw>Glxosr{QlwVw|U}&gkq-UsWsHu>YnO9npnNw_~P?lO$ zoSC1eV5Dbku4}B9mTYXwkTwAs7NzFs8tNIE>KW)7=%yQ`q?jaGCK;z$m>B356s0DW ZX6BUW6{hBv>g5-uGcYi*Om2+700276EqVX| delta 104 zcmZqJ!ql*Zi9K|c@5{HL8#l7=oiX{;40&HuJtJK+y|iRw6Na=2=&&d?N7qo#&_vHb u*T`Hq-OMD-*gQGe)Yu@+P`98cHK{Z+r$nzXHMdkRzbKu7iDhzQ`~?6>XC^8D diff --git a/pc-bios/vgabios-ramfb.bin b/pc-bios/vgabios-ramfb.bin index b9b2e230a5d568112dab419a67cfb8e32d9742d5..a7c5ae7c8f5e99a172c4639d4ec37df7d884e856 100644 GIT binary patch delta 135 zcmZp8z}WDBkv(*k#mmDsijx_g#W%_w%gb>t$}cWfFf`ON(lgXG)Ko~y%quO)%qg}~ zC`&CW&dkqKFw!$N*EQBlOExxTNSlBRi&ArR4fPC7^$c_kbkmJeQcRL8lZ?|WObm1j dic*tGGjmGx3R81S_413-85o#YCO5io003&PEo%S( delta 108 zcmZp8z}WDBkv(*k#mmDsKPEFei*J-WmN)rTp1iNAo{_GZURtuT2}9ZhbXb&{qid*V yXrgDJYh)uUzEewWosr{QlwVw|U}&gkq-UsWsHu>YnO9npnNw_~P?lO$ zoSC1eV5Dbku4}B9mTYXwkTwAs7NzFs8tNIE>KW)7=%yQ`q?jaGCK;z$m>B356s0DW ZX6BUW6{hBv>g5-uGcYi*Om2+7001zjEo1-y delta 104 zcmZqJ!ql*Zi9K|c@5{HLvp2HuoiX{;40&HuJtJK+y|iRw6Na=2=&&d?N7qo#&_vHb u*T`Hq-OMD-*gQGe)Yu@+P`98cHK{Z+r$nzXHMdkRzbKu7iDhzQ`~?6(l_nGb diff --git a/pc-bios/vgabios-virtio.bin b/pc-bios/vgabios-virtio.bin index c00414ab835a0a1b1a9dec207626a352eee48e91..806647a009fb64645adc7054f21cbd200d4d6f1a 100644 GIT binary patch delta 131 zcmZqJ!ql*Zi9K|c@5{HL`!=%gosr{QlwVw|U}&gkq-UsWsHu>YnO9npnNw_~P?lO$ zoSC1eV5Dbku4}B9mTYXwkTwAs7NzFs8tNIE>KW)7=%yQ`q?jaGCK;z$m>B356s0DW ZX6BUW6{hBv>g5-uGcYi*Om2+7001rHEnWZs delta 104 zcmZqJ!ql*Zi9K|c@5{HLQ#Z2joiX{;40&HuJtJK+y|iRw6Na=2=&&d?N7qo#&_vHb u*T`Hq-OMD-*gQGe)Yu@+P`98cHK{Z+r$nzXHMdkRzbKu7iDhzQ`~?6%b0!V| diff --git a/pc-bios/vgabios-vmware.bin b/pc-bios/vgabios-vmware.bin index 5454aceda8b8ddae807bb7ac245a4c7eec924206..39e3093667d608a34891ded7745af9ab266c38d1 100644 GIT binary patch delta 131 zcmZqJ!ql*Zi9K|c@5{HLi5uDX&d6~t$}cWfFf`ON(lgXG)Ko~y%quO)%qg}~C`&CW z&dkqKFw!$N*EQBlOExxTNSlBRi&ArR4fPC7^$c_kbkmJeQcRL8lZ?|WObm1jic*tG ZGjmGx3R81S_413-85o#YCO5`k00098Edc-k delta 104 zcmZqJ!ql*Zi9K|c@5{HL78}|3&X{~^hP)uUzEu93NJx|vCuv3YW`sj)$tp>9D@YEo%tPKjP&YHq1seo;CD6ARGf4FK;UC(r-@ From 24ade8c5decd092bde5e863bc542db45d924ae12 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 30 Nov 2021 21:17:28 +0000 Subject: [PATCH 085/421] hw/mips/bootloader: Fix write_ulong() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit bl_gen_write_ulong uses sd for both 32 and 64 bit CPU, while sd is illegal on 32 bit CPUs. Replace sd with sw on 32bit CPUs. Fixes: 3ebbf86128f ("hw/mips: Add a bootloader helper") Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211130211729.7116-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/bootloader.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 6ec8314490..99991f8b2b 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -182,7 +182,11 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + if (bootcpu_supports_isa(ISA_MIPS3)) { + bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + } else { + bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + } } void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val) From d77c462bf25001cc2ae03824a547ed761cd0c5bc Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 30 Nov 2021 21:17:29 +0000 Subject: [PATCH 086/421] hw/mips/boston: Fix load_elf() error detection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit load_elf() gives negative return in case of error, not zero. Fixes: 10e3f30ff73 ("hw/mips/boston: Allow loading elf kernel and dtb") Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211130211729.7116-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 0e3cca5511..59ca08b93a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -777,14 +777,15 @@ static void boston_mach_init(MachineState *machine) exit(1); } } else if (machine->kernel_filename) { - uint64_t kernel_entry, kernel_high, kernel_size; + uint64_t kernel_entry, kernel_high; + ssize_t kernel_size; kernel_size = load_elf(machine->kernel_filename, NULL, cpu_mips_kseg0_to_phys, NULL, &kernel_entry, NULL, &kernel_high, NULL, 0, EM_MIPS, 1, 0); - if (kernel_size) { + if (kernel_size > 0) { int dt_size; g_autofree const void *dtb_file_data, *dtb_load_data; hwaddr dtb_paddr = QEMU_ALIGN_UP(kernel_high, 64 * KiB); From ac5837e330ec33e2df2d83338713a5c4272c8cc8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 2 Dec 2021 16:49:29 +0000 Subject: [PATCH 087/421] Revert "vga: don't abort when adding a duplicate isa-vga device" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 7852a77f598635a67a222b6c1463c8b46098aed2. The check is bogus as it ends up finding itself and falling over. Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/733 Reviewed-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206095209.2332376-1-alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- hw/display/vga-isa.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index 8cea84f2be..90851e730b 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -33,7 +33,6 @@ #include "hw/loader.h" #include "hw/qdev-properties.h" #include "qom/object.h" -#include "qapi/error.h" #define TYPE_ISA_VGA "isa-vga" OBJECT_DECLARE_SIMPLE_TYPE(ISAVGAState, ISA_VGA) @@ -62,15 +61,6 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp) MemoryRegion *vga_io_memory; const MemoryRegionPortio *vga_ports, *vbe_ports; - /* - * make sure this device is not being added twice, if so - * exit without crashing qemu - */ - if (object_resolve_path_type("", TYPE_ISA_VGA, NULL)) { - error_setg(errp, "at most one %s device is permitted", TYPE_ISA_VGA); - return; - } - s->global_vmstate = true; vga_common_init(s, OBJECT(dev)); s->legacy_address_space = isa_address_space(isadev); From 5b807181c27a940a3a7ad1f221a2e76a132cbdc0 Mon Sep 17 00:00:00 2001 From: Mark Mielke Date: Thu, 2 Dec 2021 11:26:51 -0500 Subject: [PATCH 088/421] virtio-blk: Fix clean up of host notifiers for single MR transaction. The code that introduced "virtio-blk: Configure all host notifiers in a single MR transaction" introduced a second loop variable to perform cleanup in second loop, but mistakenly still refers to the first loop variable within the second loop body. Fixes: d0267da61489 ("virtio-blk: Configure all host notifiers in a single MR transaction") Signed-off-by: Mark Mielke Message-id: CALm7yL08qarOu0dnQkTN+pa=BSRC92g31YpQQNDeAiT4yLZWQQ@mail.gmail.com Signed-off-by: Stefan Hajnoczi --- hw/block/dataplane/virtio-blk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index 252c3a7a23..ee5a5352dc 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -222,7 +222,7 @@ int virtio_blk_data_plane_start(VirtIODevice *vdev) memory_region_transaction_commit(); while (j--) { - virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), i); + virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), j); } goto fail_host_notifiers; } From b9537d5904f6e3df896264a6144883ab07db9608 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 12 Sep 2021 10:49:25 -0700 Subject: [PATCH 089/421] tcg/arm: Reduce vector alignment requirement for NEON MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With arm32, the ABI gives us 8-byte alignment for the stack. While it's possible to realign the stack to provide 16-byte alignment, it's far easier to simply not encode 16-byte alignment in the VLD1 and VST1 instructions that we emit. Remove the assertion in temp_allocate_frame, limit natural alignment to the provided stack alignment, and add a comment. Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1999878 Reported-by: Richard W.M. Jones Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Message-Id: <20210912174925.200132-1-richard.henderson@linaro.org> Message-Id: <20211206191335.230683-2-richard.henderson@linaro.org> --- tcg/arm/tcg-target.c.inc | 13 +++++++++---- tcg/tcg.c | 8 +++++++- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 633b8a37ba..9d322cdba6 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2523,8 +2523,13 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); return; case TCG_TYPE_V128: - /* regs 2; size 8; align 16 */ - tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2); + /* + * We have only 8-byte alignment for the stack per the ABI. + * Rather than dynamically re-align the stack, it's easier + * to simply not request alignment beyond that. So: + * regs 2; size 8; align 8 + */ + tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); return; default: g_assert_not_reached(); @@ -2543,8 +2548,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); return; case TCG_TYPE_V128: - /* regs 2; size 8; align 16 */ - tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2); + /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ + tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); return; default: g_assert_not_reached(); diff --git a/tcg/tcg.c b/tcg/tcg.c index 57f17a4649..934aa8510b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3061,7 +3061,13 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) g_assert_not_reached(); } - assert(align <= TCG_TARGET_STACK_ALIGN); + /* + * Assume the stack is sufficiently aligned. + * This affects e.g. ARM NEON, where we have 8 byte stack alignment + * and do not require 16 byte vector alignment. This seems slightly + * easier than fully parameterizing the above switch statement. + */ + align = MIN(TCG_TARGET_STACK_ALIGN, align); off = ROUND_UP(s->current_frame_offset, align); /* If we've exhausted the stack frame, restart with a smaller TB. */ From 2958e5150dfa297dd5a51fe57a29156b8744f07f Mon Sep 17 00:00:00 2001 From: Damien Hedde Date: Tue, 7 Dec 2021 10:44:27 +0100 Subject: [PATCH 090/421] gicv3: fix ICH_MISR's LRENP computation According to the "Arm Generic Interrupt Controller Architecture Specification GIC architecture version 3 and 4" (version G: page 345 for aarch64 or 509 for aarch32): LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and ICH_HCR.EOIcount is non-zero. When only LRENPIE was set (and EOI count was zero), the LRENP bit was wrongly set and MISR value was wrong. As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE, the maintenance interrupt was constantly fired. It happens since patch 9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1") which fixed another bug about maintenance interrupt (most significant bits of misr, including this one, were ignored in the interrupt trigger). Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers") Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7fba931450..85fc369e55 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -351,7 +351,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) /* Scan list registers and fill in the U, NP and EOI bits */ eoi_maintenance_interrupt_state(cs, &value); - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { value |= ICH_MISR_EL2_LRENP; } From a3607def89f9cd68c1b994e1030527df33aa91d0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 7 Dec 2021 17:51:38 -0800 Subject: [PATCH 091/421] Update version for v6.2.0-rc4 release Signed-off-by: Richard Henderson --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index cbd3fe98d1..01bef4de71 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.1.93 +6.1.94 From cf4fbc3030c974fff726756a7ceef8386cdf500b Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Wed, 8 Dec 2021 15:22:46 +0000 Subject: [PATCH 092/421] block/nvme: fix infinite loop in nvme_free_req_queue_cb() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When the request free list is exhausted the coroutine waits on q->free_req_queue for the next free request. Whenever a request is completed a BH is scheduled to invoke nvme_free_req_queue_cb() and wake up waiting coroutines. 1. nvme_get_free_req() waits for a free request: while (q->free_req_head == -1) { ... trace_nvme_free_req_queue_wait(q->s, q->index); qemu_co_queue_wait(&q->free_req_queue, &q->lock); ... } 2. nvme_free_req_queue_cb() wakes up the coroutine: while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { ^--- infinite loop when free_req_head == -1 } nvme_free_req_queue_cb() and the coroutine form an infinite loop when q->free_req_head == -1. Fix this by checking q->free_req_head in nvme_free_req_queue_cb(). If the free request list is exhausted, don't wake waiting coroutines. Eventually an in-flight request will complete and the BH will be scheduled again, guaranteeing forward progress. Signed-off-by: Stefan Hajnoczi Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211208152246.244585-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi --- block/nvme.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index e4f336d79c..fa360b9b3c 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -206,8 +206,9 @@ static void nvme_free_req_queue_cb(void *opaque) NVMeQueuePair *q = opaque; qemu_mutex_lock(&q->lock); - while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { - /* Retry all pending requests */ + while (q->free_req_head != -1 && + qemu_co_enter_next(&q->free_req_queue, &q->lock)) { + /* Retry waiting requests */ } qemu_mutex_unlock(&q->lock); } From a4663f1a5506626175fc64c86e52135587c36872 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 11 Nov 2021 12:06:00 +0100 Subject: [PATCH 093/421] virtio-gpu: do not byteswap padding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In Linux 5.16, the padding of struct virtio_gpu_ctrl_hdr has become a single-byte field followed by a uint8_t[3] array of padding bytes, and virtio_gpu_ctrl_hdr_bswap does not compile anymore. Signed-off-by: Paolo Bonzini Acked-by: Cornelia Huck Reviewed-by: Alex Bennée Reviewed-by: Michael S. Tsirkin Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211111110604.207376-2-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- include/hw/virtio/virtio-gpu-bswap.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/virtio/virtio-gpu-bswap.h b/include/hw/virtio/virtio-gpu-bswap.h index e2bee8f595..5faac0d8d5 100644 --- a/include/hw/virtio/virtio-gpu-bswap.h +++ b/include/hw/virtio/virtio-gpu-bswap.h @@ -24,7 +24,6 @@ virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr) le32_to_cpus(&hdr->flags); le64_to_cpus(&hdr->fence_id); le32_to_cpus(&hdr->ctx_id); - le32_to_cpus(&hdr->padding); } static inline void From 43709a0ca3b09e952bde3f38112f1d7fbf7c65b1 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 11 Nov 2021 12:06:01 +0100 Subject: [PATCH 094/421] linux-headers: update to 5.16-rc1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Paolo Bonzini Acked-by: Cornelia Huck Reviewed-by: Alex Bennée Message-Id: <20211111110604.207376-3-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- include/standard-headers/drm/drm_fourcc.h | 121 +++++++++++++++++- include/standard-headers/linux/ethtool.h | 31 +++++ include/standard-headers/linux/fuse.h | 10 +- include/standard-headers/linux/pci_regs.h | 6 + include/standard-headers/linux/virtio_gpu.h | 18 ++- include/standard-headers/linux/virtio_ids.h | 24 ++++ include/standard-headers/linux/virtio_vsock.h | 3 +- linux-headers/asm-arm64/unistd.h | 1 + linux-headers/asm-generic/unistd.h | 22 +++- linux-headers/asm-mips/unistd_n32.h | 1 + linux-headers/asm-mips/unistd_n64.h | 1 + linux-headers/asm-mips/unistd_o32.h | 1 + linux-headers/asm-powerpc/unistd_32.h | 1 + linux-headers/asm-powerpc/unistd_64.h | 1 + linux-headers/asm-s390/unistd_32.h | 1 + linux-headers/asm-s390/unistd_64.h | 1 + linux-headers/asm-x86/kvm.h | 5 + linux-headers/asm-x86/unistd_32.h | 3 + linux-headers/asm-x86/unistd_64.h | 3 + linux-headers/asm-x86/unistd_x32.h | 3 + linux-headers/linux/kvm.h | 40 +++++- 21 files changed, 276 insertions(+), 21 deletions(-) diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h index 352b51fd0a..2c025cb4fe 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -103,6 +103,12 @@ extern "C" { /* 8 bpp Red */ #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ +/* 10 bpp Red */ +#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ + +/* 12 bpp Red */ +#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ + /* 16 bpp Red */ #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ @@ -372,6 +378,12 @@ extern "C" { #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#define fourcc_mod_get_vendor(modifier) \ + (((modifier) >> 56) & 0xff) + +#define fourcc_mod_is_vendor(modifier, vendor) \ + (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) + #define fourcc_mod_code(vendor, val) \ ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) @@ -899,9 +911,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) /* * The top 4 bits (out of the 56 bits alloted for specifying vendor specific - * modifiers) denote the category for modifiers. Currently we have only two - * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen - * different categories. + * modifiers) denote the category for modifiers. Currently we have three + * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of + * sixteen different categories. */ #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) @@ -1016,6 +1028,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) */ #define AFBC_FORMAT_MOD_USM (1ULL << 12) +/* + * Arm Fixed-Rate Compression (AFRC) modifiers + * + * AFRC is a proprietary fixed rate image compression protocol and format, + * designed to provide guaranteed bandwidth and memory footprint + * reductions in graphics and media use-cases. + * + * AFRC buffers consist of one or more planes, with the same components + * and meaning as an uncompressed buffer using the same pixel format. + * + * Within each plane, the pixel/luma/chroma values are grouped into + * "coding unit" blocks which are individually compressed to a + * fixed size (in bytes). All coding units within a given plane of a buffer + * store the same number of values, and have the same compressed size. + * + * The coding unit size is configurable, allowing different rates of compression. + * + * The start of each AFRC buffer plane must be aligned to an alignment granule which + * depends on the coding unit size. + * + * Coding Unit Size Plane Alignment + * ---------------- --------------- + * 16 bytes 1024 bytes + * 24 bytes 512 bytes + * 32 bytes 2048 bytes + * + * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned + * to a multiple of the paging tile dimensions. + * The dimensions of each paging tile depend on whether the buffer is optimised for + * scanline (SCAN layout) or rotated (ROT layout) access. + * + * Layout Paging Tile Width Paging Tile Height + * ------ ----------------- ------------------ + * SCAN 16 coding units 4 coding units + * ROT 8 coding units 8 coding units + * + * The dimensions of each coding unit depend on the number of components + * in the compressed plane and whether the buffer is optimised for + * scanline (SCAN layout) or rotated (ROT layout) access. + * + * Number of Components in Plane Layout Coding Unit Width Coding Unit Height + * ----------------------------- --------- ----------------- ------------------ + * 1 SCAN 16 samples 4 samples + * Example: 16x4 luma samples in a 'Y' plane + * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 1 ROT 8 samples 8 samples + * Example: 8x8 luma samples in a 'Y' plane + * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 2 DONT CARE 8 samples 4 samples + * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 3 DONT CARE 4 samples 4 samples + * Example: 4x4 pixels in an RGB buffer without alpha + * ----------------------------- --------- ----------------- ------------------ + * 4 DONT CARE 4 samples 4 samples + * Example: 4x4 pixels in an RGB buffer with alpha + */ + +#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 + +#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) + +/* + * AFRC coding unit size modifier. + * + * Indicates the number of bytes used to store each compressed coding unit for + * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance + * is the same for both Cb and Cr, which may be stored in separate planes. + * + * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store + * each compressed coding unit in the first plane of the buffer. For RGBA buffers + * this is the only plane, while for semi-planar and fully-planar YUV buffers, + * this corresponds to the luma plane. + * + * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store + * each compressed coding unit in the second and third planes in the buffer. + * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). + * + * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified + * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. + * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and + * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. + */ +#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf +#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) +#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) +#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) + +#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) +#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) + +/* + * AFRC scanline memory layout. + * + * Indicates if the buffer uses the scanline-optimised layout + * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. + * The memory layout is the same for all planes. + */ +#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) + /* * Arm 16x16 Block U-Interleaved modifier * diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h index 053d3fafdf..688eb8dc39 100644 --- a/include/standard-headers/linux/ethtool.h +++ b/include/standard-headers/linux/ethtool.h @@ -603,6 +603,7 @@ enum ethtool_link_ext_state { ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, ETHTOOL_LINK_EXT_STATE_OVERHEAT, + ETHTOOL_LINK_EXT_STATE_MODULE, }; /* More information in addition to ETHTOOL_LINK_EXT_STATE_AUTONEG. */ @@ -639,6 +640,8 @@ enum ethtool_link_ext_substate_link_logical_mismatch { enum ethtool_link_ext_substate_bad_signal_integrity { ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1, ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE, + ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST, + ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS, }; /* More information in addition to ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE. */ @@ -647,6 +650,11 @@ enum ethtool_link_ext_substate_cable_issue { ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE, }; +/* More information in addition to ETHTOOL_LINK_EXT_STATE_MODULE. */ +enum ethtool_link_ext_substate_module { + ETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1, +}; + #define ETH_GSTRING_LEN 32 /** @@ -704,6 +712,29 @@ enum ethtool_stringset { ETH_SS_COUNT }; +/** + * enum ethtool_module_power_mode_policy - plug-in module power mode policy + * @ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH: Module is always in high power mode. + * @ETHTOOL_MODULE_POWER_MODE_POLICY_AUTO: Module is transitioned by the host + * to high power mode when the first port using it is put administratively + * up and to low power mode when the last port using it is put + * administratively down. + */ +enum ethtool_module_power_mode_policy { + ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1, + ETHTOOL_MODULE_POWER_MODE_POLICY_AUTO, +}; + +/** + * enum ethtool_module_power_mode - plug-in module power mode + * @ETHTOOL_MODULE_POWER_MODE_LOW: Module is in low power mode. + * @ETHTOOL_MODULE_POWER_MODE_HIGH: Module is in high power mode. + */ +enum ethtool_module_power_mode { + ETHTOOL_MODULE_POWER_MODE_LOW = 1, + ETHTOOL_MODULE_POWER_MODE_HIGH, +}; + /** * struct ethtool_gstrings - string set for data tagging * @cmd: Command number = %ETHTOOL_GSTRINGS diff --git a/include/standard-headers/linux/fuse.h b/include/standard-headers/linux/fuse.h index cce105bfba..23ea31708b 100644 --- a/include/standard-headers/linux/fuse.h +++ b/include/standard-headers/linux/fuse.h @@ -181,6 +181,9 @@ * - add FUSE_OPEN_KILL_SUIDGID * - extend fuse_setxattr_in, add FUSE_SETXATTR_EXT * - add FUSE_SETXATTR_ACL_KILL_SGID + * + * 7.34 + * - add FUSE_SYNCFS */ #ifndef _LINUX_FUSE_H @@ -212,7 +215,7 @@ #define FUSE_KERNEL_VERSION 7 /** Minor version number of this interface */ -#define FUSE_KERNEL_MINOR_VERSION 33 +#define FUSE_KERNEL_MINOR_VERSION 34 /** The node ID of the root inode */ #define FUSE_ROOT_ID 1 @@ -505,6 +508,7 @@ enum fuse_opcode { FUSE_COPY_FILE_RANGE = 47, FUSE_SETUPMAPPING = 48, FUSE_REMOVEMAPPING = 49, + FUSE_SYNCFS = 50, /* CUSE specific operations */ CUSE_INIT = 4096, @@ -967,4 +971,8 @@ struct fuse_removemapping_one { #define FUSE_REMOVEMAPPING_MAX_ENTRY \ (PAGE_SIZE / sizeof(struct fuse_removemapping_one)) +struct fuse_syncfs_in { + uint64_t padding; +}; + #endif /* _LINUX_FUSE_H */ diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index e709ae8235..ff6ccbc6ef 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -504,6 +504,12 @@ #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */ #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ diff --git a/include/standard-headers/linux/virtio_gpu.h b/include/standard-headers/linux/virtio_gpu.h index 1357e4774e..2da48d3d4c 100644 --- a/include/standard-headers/linux/virtio_gpu.h +++ b/include/standard-headers/linux/virtio_gpu.h @@ -59,6 +59,11 @@ * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */ #define VIRTIO_GPU_F_RESOURCE_BLOB 3 +/* + * VIRTIO_GPU_CMD_CREATE_CONTEXT with + * context_init and multiple timelines + */ +#define VIRTIO_GPU_F_CONTEXT_INIT 4 enum virtio_gpu_ctrl_type { VIRTIO_GPU_UNDEFINED = 0, @@ -122,14 +127,20 @@ enum virtio_gpu_shm_id { VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 }; -#define VIRTIO_GPU_FLAG_FENCE (1 << 0) +#define VIRTIO_GPU_FLAG_FENCE (1 << 0) +/* + * If the following flag is set, then ring_idx contains the index + * of the command ring that needs to used when creating the fence + */ +#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1) struct virtio_gpu_ctrl_hdr { uint32_t type; uint32_t flags; uint64_t fence_id; uint32_t ctx_id; - uint32_t padding; + uint8_t ring_idx; + uint8_t padding[3]; }; /* data passed in the cursor vq */ @@ -269,10 +280,11 @@ struct virtio_gpu_resource_create_3d { }; /* VIRTIO_GPU_CMD_CTX_CREATE */ +#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff struct virtio_gpu_ctx_create { struct virtio_gpu_ctrl_hdr hdr; uint32_t nlen; - uint32_t padding; + uint32_t context_init; char debug_name[64]; }; diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h index 4fe842c3a3..80d76b75bc 100644 --- a/include/standard-headers/linux/virtio_ids.h +++ b/include/standard-headers/linux/virtio_ids.h @@ -54,7 +54,31 @@ #define VIRTIO_ID_SOUND 25 /* virtio sound */ #define VIRTIO_ID_FS 26 /* virtio filesystem */ #define VIRTIO_ID_PMEM 27 /* virtio pmem */ +#define VIRTIO_ID_RPMB 28 /* virtio rpmb */ #define VIRTIO_ID_MAC80211_HWSIM 29 /* virtio mac80211-hwsim */ +#define VIRTIO_ID_VIDEO_ENCODER 30 /* virtio video encoder */ +#define VIRTIO_ID_VIDEO_DECODER 31 /* virtio video decoder */ +#define VIRTIO_ID_SCMI 32 /* virtio SCMI */ +#define VIRTIO_ID_NITRO_SEC_MOD 33 /* virtio nitro secure module*/ +#define VIRTIO_ID_I2C_ADAPTER 34 /* virtio i2c adapter */ +#define VIRTIO_ID_WATCHDOG 35 /* virtio watchdog */ +#define VIRTIO_ID_CAN 36 /* virtio can */ +#define VIRTIO_ID_DMABUF 37 /* virtio dmabuf */ +#define VIRTIO_ID_PARAM_SERV 38 /* virtio parameter server */ +#define VIRTIO_ID_AUDIO_POLICY 39 /* virtio audio policy */ #define VIRTIO_ID_BT 40 /* virtio bluetooth */ +#define VIRTIO_ID_GPIO 41 /* virtio gpio */ + +/* + * Virtio Transitional IDs + */ + +#define VIRTIO_TRANS_ID_NET 1000 /* transitional virtio net */ +#define VIRTIO_TRANS_ID_BLOCK 1001 /* transitional virtio block */ +#define VIRTIO_TRANS_ID_BALLOON 1002 /* transitional virtio balloon */ +#define VIRTIO_TRANS_ID_CONSOLE 1003 /* transitional virtio console */ +#define VIRTIO_TRANS_ID_SCSI 1004 /* transitional virtio SCSI */ +#define VIRTIO_TRANS_ID_RNG 1005 /* transitional virtio rng */ +#define VIRTIO_TRANS_ID_9P 1009 /* transitional virtio 9p console */ #endif /* _LINUX_VIRTIO_IDS_H */ diff --git a/include/standard-headers/linux/virtio_vsock.h b/include/standard-headers/linux/virtio_vsock.h index 3a23488e42..467e751b17 100644 --- a/include/standard-headers/linux/virtio_vsock.h +++ b/include/standard-headers/linux/virtio_vsock.h @@ -97,7 +97,8 @@ enum virtio_vsock_shutdown { /* VIRTIO_VSOCK_OP_RW flags values */ enum virtio_vsock_rw { - VIRTIO_VSOCK_SEQ_EOR = 1, + VIRTIO_VSOCK_SEQ_EOM = 1, + VIRTIO_VSOCK_SEQ_EOR = 2, }; #endif /* _LINUX_VIRTIO_VSOCK_H */ diff --git a/linux-headers/asm-arm64/unistd.h b/linux-headers/asm-arm64/unistd.h index f83a70e07d..ce2ee8f1e3 100644 --- a/linux-headers/asm-arm64/unistd.h +++ b/linux-headers/asm-arm64/unistd.h @@ -20,5 +20,6 @@ #define __ARCH_WANT_SET_GET_RLIMIT #define __ARCH_WANT_TIME32_SYSCALLS #define __ARCH_WANT_SYS_CLONE3 +#define __ARCH_WANT_MEMFD_SECRET #include diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h index f211961ce1..4557a8b608 100644 --- a/linux-headers/asm-generic/unistd.h +++ b/linux-headers/asm-generic/unistd.h @@ -673,15 +673,15 @@ __SYSCALL(__NR_madvise, sys_madvise) #define __NR_remap_file_pages 234 __SYSCALL(__NR_remap_file_pages, sys_remap_file_pages) #define __NR_mbind 235 -__SC_COMP(__NR_mbind, sys_mbind, compat_sys_mbind) +__SYSCALL(__NR_mbind, sys_mbind) #define __NR_get_mempolicy 236 -__SC_COMP(__NR_get_mempolicy, sys_get_mempolicy, compat_sys_get_mempolicy) +__SYSCALL(__NR_get_mempolicy, sys_get_mempolicy) #define __NR_set_mempolicy 237 -__SC_COMP(__NR_set_mempolicy, sys_set_mempolicy, compat_sys_set_mempolicy) +__SYSCALL(__NR_set_mempolicy, sys_set_mempolicy) #define __NR_migrate_pages 238 -__SC_COMP(__NR_migrate_pages, sys_migrate_pages, compat_sys_migrate_pages) +__SYSCALL(__NR_migrate_pages, sys_migrate_pages) #define __NR_move_pages 239 -__SC_COMP(__NR_move_pages, sys_move_pages, compat_sys_move_pages) +__SYSCALL(__NR_move_pages, sys_move_pages) #endif #define __NR_rt_tgsigqueueinfo 240 @@ -873,8 +873,18 @@ __SYSCALL(__NR_landlock_add_rule, sys_landlock_add_rule) #define __NR_landlock_restrict_self 446 __SYSCALL(__NR_landlock_restrict_self, sys_landlock_restrict_self) +#ifdef __ARCH_WANT_MEMFD_SECRET +#define __NR_memfd_secret 447 +__SYSCALL(__NR_memfd_secret, sys_memfd_secret) +#endif +#define __NR_process_mrelease 448 +__SYSCALL(__NR_process_mrelease, sys_process_mrelease) + +#define __NR_futex_waitv 449 +__SYSCALL(__NR_futex_waitv, sys_futex_waitv) + #undef __NR_syscalls -#define __NR_syscalls 447 +#define __NR_syscalls 450 /* * 32 bit systems traditionally used different diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h index 09cd297698..4b3e7ad1ec 100644 --- a/linux-headers/asm-mips/unistd_n32.h +++ b/linux-headers/asm-mips/unistd_n32.h @@ -376,5 +376,6 @@ #define __NR_landlock_create_ruleset (__NR_Linux + 444) #define __NR_landlock_add_rule (__NR_Linux + 445) #define __NR_landlock_restrict_self (__NR_Linux + 446) +#define __NR_process_mrelease (__NR_Linux + 448) #endif /* _ASM_UNISTD_N32_H */ diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h index 780e0cead6..488d9298d9 100644 --- a/linux-headers/asm-mips/unistd_n64.h +++ b/linux-headers/asm-mips/unistd_n64.h @@ -352,5 +352,6 @@ #define __NR_landlock_create_ruleset (__NR_Linux + 444) #define __NR_landlock_add_rule (__NR_Linux + 445) #define __NR_landlock_restrict_self (__NR_Linux + 446) +#define __NR_process_mrelease (__NR_Linux + 448) #endif /* _ASM_UNISTD_N64_H */ diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h index 06a2b3b55e..f47399870a 100644 --- a/linux-headers/asm-mips/unistd_o32.h +++ b/linux-headers/asm-mips/unistd_o32.h @@ -422,5 +422,6 @@ #define __NR_landlock_create_ruleset (__NR_Linux + 444) #define __NR_landlock_add_rule (__NR_Linux + 445) #define __NR_landlock_restrict_self (__NR_Linux + 446) +#define __NR_process_mrelease (__NR_Linux + 448) #endif /* _ASM_UNISTD_O32_H */ diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h index cd5a8a41b2..11d54696dc 100644 --- a/linux-headers/asm-powerpc/unistd_32.h +++ b/linux-headers/asm-powerpc/unistd_32.h @@ -429,6 +429,7 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h index 8458effa8d..cf740bab13 100644 --- a/linux-headers/asm-powerpc/unistd_64.h +++ b/linux-headers/asm-powerpc/unistd_64.h @@ -401,6 +401,7 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h index 0c3cd299e4..8f97d98128 100644 --- a/linux-headers/asm-s390/unistd_32.h +++ b/linux-headers/asm-s390/unistd_32.h @@ -419,5 +419,6 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_S390_UNISTD_32_H */ diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h index 8dfc08b5e6..021ffc30e6 100644 --- a/linux-headers/asm-s390/unistd_64.h +++ b/linux-headers/asm-s390/unistd_64.h @@ -367,5 +367,6 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_S390_UNISTD_64_H */ diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index a6c327f8ad..5a776a08f7 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -295,6 +295,7 @@ struct kvm_debug_exit_arch { #define KVM_GUESTDBG_USE_HW_BP 0x00020000 #define KVM_GUESTDBG_INJECT_DB 0x00040000 #define KVM_GUESTDBG_INJECT_BP 0x00080000 +#define KVM_GUESTDBG_BLOCKIRQ 0x00100000 /* for KVM_SET_GUEST_DEBUG */ struct kvm_guest_debug_arch { @@ -503,4 +504,8 @@ struct kvm_pmu_event_filter { #define KVM_PMU_EVENT_ALLOW 0 #define KVM_PMU_EVENT_DENY 1 +/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */ +#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */ +#define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */ + #endif /* _ASM_X86_KVM_H */ diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h index 66e96c0c68..9c9ffe312b 100644 --- a/linux-headers/asm-x86/unistd_32.h +++ b/linux-headers/asm-x86/unistd_32.h @@ -437,6 +437,9 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_memfd_secret 447 +#define __NR_process_mrelease 448 +#define __NR_futex_waitv 449 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h index b8ff6f14ee..084f1eef9c 100644 --- a/linux-headers/asm-x86/unistd_64.h +++ b/linux-headers/asm-x86/unistd_64.h @@ -359,6 +359,9 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_memfd_secret 447 +#define __NR_process_mrelease 448 +#define __NR_futex_waitv 449 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h index 06a1097c15..a2441affc2 100644 --- a/linux-headers/asm-x86/unistd_x32.h +++ b/linux-headers/asm-x86/unistd_x32.h @@ -312,6 +312,9 @@ #define __NR_landlock_create_ruleset (__X32_SYSCALL_BIT + 444) #define __NR_landlock_add_rule (__X32_SYSCALL_BIT + 445) #define __NR_landlock_restrict_self (__X32_SYSCALL_BIT + 446) +#define __NR_memfd_secret (__X32_SYSCALL_BIT + 447) +#define __NR_process_mrelease (__X32_SYSCALL_BIT + 448) +#define __NR_futex_waitv (__X32_SYSCALL_BIT + 449) #define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512) #define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513) #define __NR_ioctl (__X32_SYSCALL_BIT + 514) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index bcaf66cc4d..02c5e7b7bb 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -269,6 +269,7 @@ struct kvm_xen_exit { #define KVM_EXIT_AP_RESET_HOLD 32 #define KVM_EXIT_X86_BUS_LOCK 33 #define KVM_EXIT_XEN 34 +#define KVM_EXIT_RISCV_SBI 35 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -397,13 +398,23 @@ struct kvm_run { * "ndata" is correct, that new fields are enumerated in "flags", * and that each flag enumerates fields that are 64-bit aligned * and sized (so that ndata+internal.data[] is valid/accurate). + * + * Space beyond the defined fields may be used to store arbitrary + * debug information relating to the emulation failure. It is + * accounted for in "ndata" but the format is unspecified and is + * not represented in "flags". Any such information is *not* ABI! */ struct { __u32 suberror; __u32 ndata; __u64 flags; - __u8 insn_size; - __u8 insn_bytes[15]; + union { + struct { + __u8 insn_size; + __u8 insn_bytes[15]; + }; + }; + /* Arbitrary debug data may follow. */ } emulation_failure; /* KVM_EXIT_OSI */ struct { @@ -469,6 +480,13 @@ struct kvm_run { } msr; /* KVM_EXIT_XEN */ struct kvm_xen_exit xen; + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; /* Fix the size of the union. */ char padding[256]; }; @@ -1223,11 +1241,16 @@ struct kvm_irqfd { /* Do not use 1, KVM_CHECK_EXTENSION returned it before we had flags. */ #define KVM_CLOCK_TSC_STABLE 2 +#define KVM_CLOCK_REALTIME (1 << 2) +#define KVM_CLOCK_HOST_TSC (1 << 3) struct kvm_clock_data { __u64 clock; __u32 flags; - __u32 pad[9]; + __u32 pad0; + __u64 realtime; + __u64 host_tsc; + __u32 pad[4]; }; /* For KVM_CAP_SW_TLB */ @@ -1965,7 +1988,9 @@ struct kvm_stats_header { #define KVM_STATS_TYPE_CUMULATIVE (0x0 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_INSTANT (0x1 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_PEAK (0x2 << KVM_STATS_TYPE_SHIFT) -#define KVM_STATS_TYPE_MAX KVM_STATS_TYPE_PEAK +#define KVM_STATS_TYPE_LINEAR_HIST (0x3 << KVM_STATS_TYPE_SHIFT) +#define KVM_STATS_TYPE_LOG_HIST (0x4 << KVM_STATS_TYPE_SHIFT) +#define KVM_STATS_TYPE_MAX KVM_STATS_TYPE_LOG_HIST #define KVM_STATS_UNIT_SHIFT 4 #define KVM_STATS_UNIT_MASK (0xF << KVM_STATS_UNIT_SHIFT) @@ -1988,8 +2013,9 @@ struct kvm_stats_header { * @size: The number of data items for this stats. * Every data item is of type __u64. * @offset: The offset of the stats to the start of stat structure in - * struture kvm or kvm_vcpu. - * @unused: Unused field for future usage. Always 0 for now. + * structure kvm or kvm_vcpu. + * @bucket_size: A parameter value used for histogram stats. It is only used + * for linear histogram stats, specifying the size of the bucket; * @name: The name string for the stats. Its size is indicated by the * &kvm_stats_header->name_size. */ @@ -1998,7 +2024,7 @@ struct kvm_stats_desc { __s16 exponent; __u16 size; __u32 offset; - __u32 unused; + __u32 bucket_size; char name[]; }; From ecd39d620b0a3938dc3a80721e8aa436075d2916 Mon Sep 17 00:00:00 2001 From: Maxim Levitsky Date: Thu, 11 Nov 2021 12:06:02 +0100 Subject: [PATCH 095/421] gdbstub: reject unsupported flags in handle_set_qemu_sstep MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit handle_query_qemu_sstepbits is reporting NOIRQ and NOTIMER bits even if they are not supported (as is the case with record/replay). Instead, store the supported singlestep flags and reject any unsupported bits in handle_set_qemu_sstep. This removes the need for the get_sstep_flags() wrapper. While at it, move the variables in GDBState, instead of using global variables. Signed-off-by: Maxim Levitsky [Extracted from Maxim's patch into a separate commit. - Paolo] Signed-off-by: Paolo Bonzini Reviewed-by: Alex Bennée Message-Id: <20211111110604.207376-4-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- gdbstub.c | 75 ++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 49 insertions(+), 26 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 141d7bc4ec..a955175fd4 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -368,27 +368,10 @@ typedef struct GDBState { gdb_syscall_complete_cb current_syscall_cb; GString *str_buf; GByteArray *mem_buf; + int sstep_flags; + int supported_sstep_flags; } GDBState; -/* By default use no IRQs and no timers while single stepping so as to - * make single stepping like an ICE HW step. - */ -static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; - -/* Retrieves flags for single step mode. */ -static int get_sstep_flags(void) -{ - /* - * In replay mode all events written into the log should be replayed. - * That is why NOIRQ flag is removed in this mode. - */ - if (replay_mode != REPLAY_MODE_NONE) { - return SSTEP_ENABLE; - } else { - return sstep_flags; - } -} - static GDBState gdbserver_state; static void init_gdbserver_state(void) @@ -399,6 +382,26 @@ static void init_gdbserver_state(void) gdbserver_state.str_buf = g_string_new(NULL); gdbserver_state.mem_buf = g_byte_array_sized_new(MAX_PACKET_LENGTH); gdbserver_state.last_packet = g_byte_array_sized_new(MAX_PACKET_LENGTH + 4); + + /* + * In replay mode all events will come from the log and can't be + * suppressed otherwise we would break determinism. However as those + * events are tied to the number of executed instructions we won't see + * them occurring every time we single step. + */ + if (replay_mode != REPLAY_MODE_NONE) { + gdbserver_state.supported_sstep_flags = SSTEP_ENABLE; + } else { + gdbserver_state.supported_sstep_flags = + SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + } + + /* + * By default use no IRQs and no timers while single stepping so as to + * make single stepping like an ICE HW step. + */ + gdbserver_state.sstep_flags = gdbserver_state.supported_sstep_flags; + } #ifndef CONFIG_USER_ONLY @@ -505,7 +508,7 @@ static int gdb_continue_partial(char *newstates) CPU_FOREACH(cpu) { if (newstates[cpu->cpu_index] == 's') { trace_gdbstub_op_stepping(cpu->cpu_index); - cpu_single_step(cpu, sstep_flags); + cpu_single_step(cpu, gdbserver_state.sstep_flags); } } gdbserver_state.running_state = 1; @@ -524,7 +527,7 @@ static int gdb_continue_partial(char *newstates) break; /* nothing to do here */ case 's': trace_gdbstub_op_stepping(cpu->cpu_index); - cpu_single_step(cpu, get_sstep_flags()); + cpu_single_step(cpu, gdbserver_state.sstep_flags); cpu_resume(cpu); flag = 1; break; @@ -1883,7 +1886,7 @@ static void handle_step(GArray *params, void *user_ctx) gdb_set_cpu_pc((target_ulong)get_param(params, 0)->val_ull); } - cpu_single_step(gdbserver_state.c_cpu, get_sstep_flags()); + cpu_single_step(gdbserver_state.c_cpu, gdbserver_state.sstep_flags); gdb_continue(); } @@ -2017,24 +2020,44 @@ static void handle_v_commands(GArray *params, void *user_ctx) static void handle_query_qemu_sstepbits(GArray *params, void *user_ctx) { - g_string_printf(gdbserver_state.str_buf, "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", - SSTEP_ENABLE, SSTEP_NOIRQ, SSTEP_NOTIMER); + g_string_printf(gdbserver_state.str_buf, "ENABLE=%x", SSTEP_ENABLE); + + if (gdbserver_state.supported_sstep_flags & SSTEP_NOIRQ) { + g_string_append_printf(gdbserver_state.str_buf, ",NOIRQ=%x", + SSTEP_NOIRQ); + } + + if (gdbserver_state.supported_sstep_flags & SSTEP_NOTIMER) { + g_string_append_printf(gdbserver_state.str_buf, ",NOTIMER=%x", + SSTEP_NOTIMER); + } + put_strbuf(); } static void handle_set_qemu_sstep(GArray *params, void *user_ctx) { + int new_sstep_flags; + if (!params->len) { return; } - sstep_flags = get_param(params, 0)->val_ul; + new_sstep_flags = get_param(params, 0)->val_ul; + + if (new_sstep_flags & ~gdbserver_state.supported_sstep_flags) { + put_packet("E22"); + return; + } + + gdbserver_state.sstep_flags = new_sstep_flags; put_packet("OK"); } static void handle_query_qemu_sstep(GArray *params, void *user_ctx) { - g_string_printf(gdbserver_state.str_buf, "0x%x", sstep_flags); + g_string_printf(gdbserver_state.str_buf, "0x%x", + gdbserver_state.sstep_flags); put_strbuf(); } From 12bc5b4cd5e59b3f8689b71d9d038a55e2777cdc Mon Sep 17 00:00:00 2001 From: Maxim Levitsky Date: Thu, 11 Nov 2021 12:06:03 +0100 Subject: [PATCH 096/421] gdbstub, kvm: let KVM report supported singlestep flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Maxim Levitsky [Extracted from Maxim's patch into a separate commit. - Paolo] Signed-off-by: Paolo Bonzini Reviewed-by: Alex Bennée Message-Id: <20211111110604.207376-5-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- accel/kvm/kvm-all.c | 12 ++++++++++++ gdbstub.c | 10 +++++++++- include/sysemu/kvm.h | 15 +++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index eecd8031cf..2f5597572a 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -168,6 +168,8 @@ bool kvm_vm_attributes_allowed; bool kvm_direct_msi_allowed; bool kvm_ioeventfd_any_length_allowed; bool kvm_msi_use_devid; +bool kvm_has_guest_debug; +int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size = ~0; @@ -2564,6 +2566,16 @@ static int kvm_init(MachineState *ms) kvm_ioeventfd_any_length_allowed = (kvm_check_extension(s, KVM_CAP_IOEVENTFD_ANY_LENGTH) > 0); +#ifdef KVM_CAP_SET_GUEST_DEBUG + kvm_has_guest_debug = + (kvm_check_extension(s, KVM_CAP_SET_GUEST_DEBUG) > 0); +#endif + + kvm_sstep_flags = 0; + if (kvm_has_guest_debug) { + kvm_sstep_flags = SSTEP_ENABLE; + } + kvm_state = s; ret = kvm_arch_init(ms, s); diff --git a/gdbstub.c b/gdbstub.c index a955175fd4..3c14c6a038 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -391,6 +391,8 @@ static void init_gdbserver_state(void) */ if (replay_mode != REPLAY_MODE_NONE) { gdbserver_state.supported_sstep_flags = SSTEP_ENABLE; + } else if (kvm_enabled()) { + gdbserver_state.supported_sstep_flags = kvm_get_supported_sstep_flags(); } else { gdbserver_state.supported_sstep_flags = SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; @@ -400,7 +402,8 @@ static void init_gdbserver_state(void) * By default use no IRQs and no timers while single stepping so as to * make single stepping like an ICE HW step. */ - gdbserver_state.sstep_flags = gdbserver_state.supported_sstep_flags; + gdbserver_state.sstep_flags = SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + gdbserver_state.sstep_flags &= gdbserver_state.supported_sstep_flags; } @@ -3520,6 +3523,11 @@ int gdbserver_start(const char *device) return -1; } + if (kvm_enabled() && !kvm_supports_guest_debug()) { + error_report("gdbstub: KVM doesn't support guest debugging"); + return -1; + } + if (!device) return -1; if (strcmp(device, "none") != 0) { diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 7b22aeb6ae..6eb39a088b 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -46,6 +46,8 @@ extern bool kvm_readonly_mem_allowed; extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; +extern bool kvm_has_guest_debug; +extern int kvm_sstep_flags; #define kvm_enabled() (kvm_allowed) /** @@ -167,6 +169,17 @@ extern bool kvm_msi_use_devid; */ #define kvm_msi_devid_required() (kvm_msi_use_devid) +/* + * Does KVM support guest debugging + */ +#define kvm_supports_guest_debug() (kvm_has_guest_debug) + +/* + * kvm_supported_sstep_flags + * Returns: SSTEP_* flags that KVM supports for guest debug + */ +#define kvm_get_supported_sstep_flags() (kvm_sstep_flags) + #else #define kvm_enabled() (0) @@ -184,6 +197,8 @@ extern bool kvm_msi_use_devid; #define kvm_direct_msi_enabled() (false) #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) +#define kvm_supports_guest_debug() (false) +#define kvm_get_supported_sstep_flags() (0) #endif /* CONFIG_KVM_IS_POSSIBLE */ From fd2ddd168935690056a42b0ffe8f2480d8537751 Mon Sep 17 00:00:00 2001 From: Maxim Levitsky Date: Thu, 11 Nov 2021 12:06:04 +0100 Subject: [PATCH 097/421] kvm: add support for KVM_GUESTDBG_BLOCKIRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the KVM_GUESTDBG_BLOCKIRQ debug flag if supported. Signed-off-by: Maxim Levitsky [Extracted from Maxim's patch into a separate commit. - Paolo] Signed-off-by: Paolo Bonzini Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211111110604.207376-6-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- accel/kvm/kvm-all.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 2f5597572a..0e66ebb497 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -61,6 +61,10 @@ #endif #define PAGE_SIZE qemu_real_host_page_size +#ifndef KVM_GUESTDBG_BLOCKIRQ +#define KVM_GUESTDBG_BLOCKIRQ 0 +#endif + //#define DEBUG_KVM #ifdef DEBUG_KVM @@ -2574,6 +2578,15 @@ static int kvm_init(MachineState *ms) kvm_sstep_flags = 0; if (kvm_has_guest_debug) { kvm_sstep_flags = SSTEP_ENABLE; + +#if defined KVM_CAP_SET_GUEST_DEBUG2 + int guest_debug_flags = + kvm_check_extension(s, KVM_CAP_SET_GUEST_DEBUG2); + + if (guest_debug_flags & KVM_GUESTDBG_BLOCKIRQ) { + kvm_sstep_flags |= SSTEP_NOIRQ; + } +#endif } kvm_state = s; @@ -3205,6 +3218,10 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) if (cpu->singlestep_enabled) { data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP; + + if (cpu->singlestep_enabled & SSTEP_NOIRQ) { + data.dbg.control |= KVM_GUESTDBG_BLOCKIRQ; + } } kvm_arch_update_guest_debug(cpu, &data.dbg); From 1105812382e1126d86dddc16b3700f8c79dc93d1 Mon Sep 17 00:00:00 2001 From: Yang Zhong Date: Mon, 1 Nov 2021 12:20:05 -0400 Subject: [PATCH 098/421] numa: Enable numa for SGX EPC sections The basic SGX did not enable numa for SGX EPC sections, which result in all EPC sections located in numa node 0. This patch enable SGX numa function in the guest and the EPC section can work with RAM as one numa node. The Guest kernel related log: [ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff] [ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff] The SRAT table can normally show SGX EPC sections menory info in different numa nodes. The SGX EPC numa related command: ...... -m 4G,maxmem=20G \ -smp sockets=2,cores=2 \ -cpu host,+sgx-provisionkey \ -object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \ -object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \ -numa node,nodeid=0,cpus=0-1,memdev=node0 \ -object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \ -object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \ -numa node,nodeid=1,cpus=2-3,memdev=node1 \ -M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \ ...... Signed-off-by: Yang Zhong Message-Id: <20211101162009.62161-2-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini --- hw/core/numa.c | 5 ++--- hw/i386/acpi-build.c | 2 ++ hw/i386/sgx-epc.c | 3 +++ hw/i386/sgx-stub.c | 4 ++++ hw/i386/sgx.c | 44 +++++++++++++++++++++++++++++++++++++++ include/hw/i386/sgx-epc.h | 3 +++ monitor/hmp-cmds.c | 1 + qapi/machine.json | 10 ++++++++- qemu-options.hx | 4 ++-- 9 files changed, 70 insertions(+), 6 deletions(-) diff --git a/hw/core/numa.c b/hw/core/numa.c index e6050b2273..1aa05dcf42 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -784,9 +784,8 @@ static void numa_stat_memory_devices(NumaNodeMem node_mem[]) break; case MEMORY_DEVICE_INFO_KIND_SGX_EPC: se = value->u.sgx_epc.data; - /* TODO: once we support numa, assign to right node */ - node_mem[0].node_mem += se->size; - node_mem[0].node_plugged_mem += se->size; + node_mem[se->node].node_mem += se->size; + node_mem[se->node].node_plugged_mem = 0; break; default: g_assert_not_reached(); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a99c6e4fe3..8383b83ee3 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2068,6 +2068,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) nvdimm_build_srat(table_data); } + sgx_epc_build_srat(table_data); + /* * TODO: this part is not in ACPI spec and current linux kernel boots fine * without these entries. But I recall there were issues the last time I diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c index e508827e78..96b2940d75 100644 --- a/hw/i386/sgx-epc.c +++ b/hw/i386/sgx-epc.c @@ -21,6 +21,7 @@ static Property sgx_epc_properties[] = { DEFINE_PROP_UINT64(SGX_EPC_ADDR_PROP, SGXEPCDevice, addr, 0), + DEFINE_PROP_UINT32(SGX_EPC_NUMA_NODE_PROP, SGXEPCDevice, node, 0), DEFINE_PROP_LINK(SGX_EPC_MEMDEV_PROP, SGXEPCDevice, hostmem, TYPE_MEMORY_BACKEND_EPC, HostMemoryBackendEpc *), DEFINE_PROP_END_OF_LIST(), @@ -139,6 +140,8 @@ static void sgx_epc_md_fill_device_info(const MemoryDeviceState *md, se->memaddr = epc->addr; se->size = object_property_get_uint(OBJECT(epc), SGX_EPC_SIZE_PROP, NULL); + se->node = object_property_get_uint(OBJECT(epc), SGX_EPC_NUMA_NODE_PROP, + NULL); se->memdev = object_get_canonical_path(OBJECT(epc->hostmem)); info->u.sgx_epc.data = se; diff --git a/hw/i386/sgx-stub.c b/hw/i386/sgx-stub.c index c9b379e665..26833eb233 100644 --- a/hw/i386/sgx-stub.c +++ b/hw/i386/sgx-stub.c @@ -6,6 +6,10 @@ #include "qapi/error.h" #include "qapi/qapi-commands-misc-target.h" +void sgx_epc_build_srat(GArray *table_data) +{ +} + SGXInfo *qmp_query_sgx(Error **errp) { error_setg(errp, "SGX support is not compiled in"); diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index 8fef3dd8fa..d04299904a 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -23,6 +23,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/reset.h" #include +#include "hw/acpi/aml-build.h" #define SGX_MAX_EPC_SECTIONS 8 #define SGX_CPUID_EPC_INVALID 0x0 @@ -36,6 +37,46 @@ #define RETRY_NUM 2 +static int sgx_epc_device_list(Object *obj, void *opaque) +{ + GSList **list = opaque; + + if (object_dynamic_cast(obj, TYPE_SGX_EPC)) { + *list = g_slist_append(*list, DEVICE(obj)); + } + + object_child_foreach(obj, sgx_epc_device_list, opaque); + return 0; +} + +static GSList *sgx_epc_get_device_list(void) +{ + GSList *list = NULL; + + object_child_foreach(qdev_get_machine(), sgx_epc_device_list, &list); + return list; +} + +void sgx_epc_build_srat(GArray *table_data) +{ + GSList *device_list = sgx_epc_get_device_list(); + + for (; device_list; device_list = device_list->next) { + DeviceState *dev = device_list->data; + Object *obj = OBJECT(dev); + uint64_t addr, size; + int node; + + node = object_property_get_uint(obj, SGX_EPC_NUMA_NODE_PROP, + &error_abort); + addr = object_property_get_uint(obj, SGX_EPC_ADDR_PROP, &error_abort); + size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP, &error_abort); + + build_srat_memory(table_data, addr, size, node, MEM_AFFINITY_ENABLED); + } + g_slist_free(device_list); +} + static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high) { return (low & MAKE_64BIT_MASK(12, 20)) + @@ -226,6 +267,9 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) /* set the memdev link with memory backend */ object_property_parse(obj, SGX_EPC_MEMDEV_PROP, list->value->memdev, &error_fatal); + /* set the numa node property for sgx epc object */ + object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, list->value->node, + &error_fatal); object_property_set_bool(obj, "realized", true, &error_fatal); object_unref(obj); } diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h index a6a65be854..581fac389a 100644 --- a/include/hw/i386/sgx-epc.h +++ b/include/hw/i386/sgx-epc.h @@ -25,6 +25,7 @@ #define SGX_EPC_ADDR_PROP "addr" #define SGX_EPC_SIZE_PROP "size" #define SGX_EPC_MEMDEV_PROP "memdev" +#define SGX_EPC_NUMA_NODE_PROP "node" /** * SGXEPCDevice: @@ -38,6 +39,7 @@ typedef struct SGXEPCDevice { /* public */ uint64_t addr; + uint32_t node; HostMemoryBackendEpc *hostmem; } SGXEPCDevice; @@ -56,6 +58,7 @@ typedef struct SGXEPCState { } SGXEPCState; bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size); +void sgx_epc_build_srat(GArray *table_data); static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc) { diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index 9c91bf93e9..2669156b28 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -1810,6 +1810,7 @@ void hmp_info_memory_devices(Monitor *mon, const QDict *qdict) se->id ? se->id : ""); monitor_printf(mon, " memaddr: 0x%" PRIx64 "\n", se->memaddr); monitor_printf(mon, " size: %" PRIu64 "\n", se->size); + monitor_printf(mon, " node: %" PRId64 "\n", se->node); monitor_printf(mon, " memdev: %s\n", se->memdev); break; default: diff --git a/qapi/machine.json b/qapi/machine.json index f1839acf20..edeab6084b 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1207,12 +1207,15 @@ # # @memdev: memory backend linked with device # +# @node: the numa node +# # Since: 6.2 ## { 'struct': 'SgxEPCDeviceInfo', 'data': { '*id': 'str', 'memaddr': 'size', 'size': 'size', + 'node': 'int', 'memdev': 'str' } } @@ -1285,10 +1288,15 @@ # # @memdev: memory backend linked with device # +# @node: the numa node +# # Since: 6.2 ## { 'struct': 'SgxEPC', - 'data': { 'memdev': 'str' } } + 'data': { 'memdev': 'str', + 'node': 'int' + } +} ## # @SgxEPCProperties: diff --git a/qemu-options.hx b/qemu-options.hx index ae2c6dbbfc..489b58e151 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -127,11 +127,11 @@ SRST ERST DEF("M", HAS_ARG, QEMU_OPTION_M, - " sgx-epc.0.memdev=memid\n", + " sgx-epc.0.memdev=memid,sgx-epc.0.node=numaid\n", QEMU_ARCH_ALL) SRST -``sgx-epc.0.memdev=@var{memid}`` +``sgx-epc.0.memdev=@var{memid},sgx-epc.0.node=@var{numaid}`` Define an SGX EPC section. ERST From 4755927ae12547c2e7cb22c5fa1b39038c6c11b1 Mon Sep 17 00:00:00 2001 From: Yang Zhong Date: Mon, 1 Nov 2021 12:20:07 -0400 Subject: [PATCH 099/421] numa: Support SGX numa in the monitor and Libvirt interfaces Add the SGXEPCSection list into SGXInfo to show the multiple SGX EPC sections detailed info, not the total size like before. This patch can enable numa support for 'info sgx' command and QMP interfaces. The new interfaces show each EPC section info in one numa node. Libvirt can use QMP interface to get the detailed host SGX EPC capabilities to decide how to allocate host EPC sections to guest. (qemu) info sgx SGX support: enabled SGX1 support: enabled SGX2 support: enabled FLC support: enabled NUMA node #0: size=67108864 NUMA node #1: size=29360128 The QMP interface show: (QEMU) query-sgx {"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \ [{"node": 0, "size": 67108864}, {"node": 1, "size": 29360128}], "flc": true}} (QEMU) query-sgx-capabilities {"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \ [{"node": 0, "size": 17070817280}, {"node": 1, "size": 17079205888}], "flc": true}} Signed-off-by: Yang Zhong Message-Id: <20211101162009.62161-4-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini --- hw/i386/sgx.c | 51 +++++++++++++++++++++++++++++++++++-------- qapi/misc-target.json | 19 ++++++++++++++-- 2 files changed, 59 insertions(+), 11 deletions(-) diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index d04299904a..5de5dd0893 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -83,11 +83,13 @@ static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high) ((high & MAKE_64BIT_MASK(0, 20)) << 32); } -static uint64_t sgx_calc_host_epc_section_size(void) +static SGXEPCSectionList *sgx_calc_host_epc_sections(void) { + SGXEPCSectionList *head = NULL, **tail = &head; + SGXEPCSection *section; uint32_t i, type; uint32_t eax, ebx, ecx, edx; - uint64_t size = 0; + uint32_t j = 0; for (i = 0; i < SGX_MAX_EPC_SECTIONS; i++) { host_cpuid(0x12, i + 2, &eax, &ebx, &ecx, &edx); @@ -101,10 +103,13 @@ static uint64_t sgx_calc_host_epc_section_size(void) break; } - size += sgx_calc_section_metric(ecx, edx); + section = g_new0(SGXEPCSection, 1); + section->node = j++; + section->size = sgx_calc_section_metric(ecx, edx); + QAPI_LIST_APPEND(tail, section); } - return size; + return head; } static void sgx_epc_reset(void *opaque) @@ -168,13 +173,35 @@ SGXInfo *qmp_query_sgx_capabilities(Error **errp) info->sgx1 = eax & (1U << 0) ? true : false; info->sgx2 = eax & (1U << 1) ? true : false; - info->section_size = sgx_calc_host_epc_section_size(); + info->sections = sgx_calc_host_epc_sections(); close(fd); return info; } +static SGXEPCSectionList *sgx_get_epc_sections_list(void) +{ + GSList *device_list = sgx_epc_get_device_list(); + SGXEPCSectionList *head = NULL, **tail = &head; + SGXEPCSection *section; + + for (; device_list; device_list = device_list->next) { + DeviceState *dev = device_list->data; + Object *obj = OBJECT(dev); + + section = g_new0(SGXEPCSection, 1); + section->node = object_property_get_uint(obj, SGX_EPC_NUMA_NODE_PROP, + &error_abort); + section->size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP, + &error_abort); + QAPI_LIST_APPEND(tail, section); + } + g_slist_free(device_list); + + return head; +} + SGXInfo *qmp_query_sgx(Error **errp) { SGXInfo *info = NULL; @@ -193,14 +220,13 @@ SGXInfo *qmp_query_sgx(Error **errp) return NULL; } - SGXEPCState *sgx_epc = &pcms->sgx_epc; info = g_new0(SGXInfo, 1); info->sgx = true; info->sgx1 = true; info->sgx2 = true; info->flc = true; - info->section_size = sgx_epc->size; + info->sections = sgx_get_epc_sections_list(); return info; } @@ -208,6 +234,7 @@ SGXInfo *qmp_query_sgx(Error **errp) void hmp_info_sgx(Monitor *mon, const QDict *qdict) { Error *err = NULL; + SGXEPCSectionList *section_list, *section; g_autoptr(SGXInfo) info = qmp_query_sgx(&err); if (err) { @@ -222,8 +249,14 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict) info->sgx2 ? "enabled" : "disabled"); monitor_printf(mon, "FLC support: %s\n", info->flc ? "enabled" : "disabled"); - monitor_printf(mon, "size: %" PRIu64 "\n", - info->section_size); + + section_list = info->sections; + for (section = section_list; section; section = section->next) { + monitor_printf(mon, "NUMA node #%" PRId64 ": ", + section->value->node); + monitor_printf(mon, "size=%" PRIu64 "\n", + section->value->size); + } } bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size) diff --git a/qapi/misc-target.json b/qapi/misc-target.json index 5aa2b95b7d..1022aa0184 100644 --- a/qapi/misc-target.json +++ b/qapi/misc-target.json @@ -337,6 +337,21 @@ 'if': 'TARGET_ARM' } +## +# @SGXEPCSection: +# +# Information about intel SGX EPC section info +# +# @node: the numa node +# +# @size: the size of epc section +# +# Since: 6.2 +## +{ 'struct': 'SGXEPCSection', + 'data': { 'node': 'int', + 'size': 'uint64'}} + ## # @SGXInfo: # @@ -350,7 +365,7 @@ # # @flc: true if FLC is supported # -# @section-size: The EPC section size for guest +# @sections: The EPC sections info for guest # # Since: 6.2 ## @@ -359,7 +374,7 @@ 'sgx1': 'bool', 'sgx2': 'bool', 'flc': 'bool', - 'section-size': 'uint64'}, + 'sections': ['SGXEPCSection']}, 'if': 'TARGET_I386' } ## From d1889b36098c79e2e6ac90faf3d0dc5ec0057677 Mon Sep 17 00:00:00 2001 From: Yang Zhong Date: Mon, 1 Nov 2021 12:20:08 -0400 Subject: [PATCH 100/421] doc: Add the SGX numa description Add the SGX numa reference command and how to check if SGX numa is support or not with multiple EPC sections. Signed-off-by: Yang Zhong Message-Id: <20211101162009.62161-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini --- docs/system/i386/sgx.rst | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/docs/system/i386/sgx.rst b/docs/system/i386/sgx.rst index f8fade5ac2..0f0a73f758 100644 --- a/docs/system/i386/sgx.rst +++ b/docs/system/i386/sgx.rst @@ -141,8 +141,7 @@ To launch a SGX guest: |qemu_system_x86| \\ -cpu host,+sgx-provisionkey \\ -object memory-backend-epc,id=mem1,size=64M,prealloc=on \\ - -object memory-backend-epc,id=mem2,size=28M \\ - -M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2 + -M sgx-epc.0.memdev=mem1,sgx-epc.0.node=0 Utilizing SGX in the guest requires a kernel/OS with SGX support. The support can be determined in guest by:: @@ -152,8 +151,32 @@ The support can be determined in guest by:: and SGX epc info by:: $ dmesg | grep sgx - [ 1.242142] sgx: EPC section 0x180000000-0x181bfffff - [ 1.242319] sgx: EPC section 0x181c00000-0x1837fffff + [ 0.182807] sgx: EPC section 0x140000000-0x143ffffff + [ 0.183695] sgx: [Firmware Bug]: Unable to map EPC section to online node. Fallback to the NUMA node 0. + +To launch a SGX numa guest: + +.. parsed-literal:: + + |qemu_system_x86| \\ + -cpu host,+sgx-provisionkey \\ + -object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \\ + -object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \\ + -numa node,nodeid=0,cpus=0-1,memdev=node0 \\ + -object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \\ + -object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \\ + -numa node,nodeid=1,cpus=2-3,memdev=node1 \\ + -M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 + +and SGX epc numa info by:: + + $ dmesg | grep sgx + [ 0.369937] sgx: EPC section 0x180000000-0x183ffffff + [ 0.370259] sgx: EPC section 0x184000000-0x185bfffff + + $ dmesg | grep SRAT + [ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff] + [ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff] References ---------- From cbe08c35cfa8f96125512a8aa3e1bf251b1410a5 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Nov 2021 10:16:01 +0100 Subject: [PATCH 101/421] configure: remove dead variables Signed-off-by: Paolo Bonzini --- configure | 5 ----- 1 file changed, 5 deletions(-) diff --git a/configure b/configure index 48c21775f3..d3aac031a5 100755 --- a/configure +++ b/configure @@ -626,7 +626,6 @@ fi case $targetos in MINGW32*) mingw32="yes" - supported_os="yes" plugins="no" pie="no" ;; @@ -668,7 +667,6 @@ SunOS) QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" ;; Haiku) - haiku="yes" pie="no" QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -D_BSD_SOURCE -fPIC $QEMU_CFLAGS" ;; @@ -3472,9 +3470,6 @@ fi if test "$solaris" = "yes" ; then echo "CONFIG_SOLARIS=y" >> $config_host_mak fi -if test "$haiku" = "yes" ; then - echo "CONFIG_HAIKU=y" >> $config_host_mak -fi if test "$static" = "yes" ; then echo "CONFIG_STATIC=y" >> $config_host_mak fi From 44f28df24767cf9dca1ddc9b23157737c4cbb645 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 14 Dec 2021 12:35:01 -0800 Subject: [PATCH 102/421] Update version for v6.2.0 release Signed-off-by: Richard Henderson --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 01bef4de71..6abaeb2f90 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.1.94 +6.2.0 From af1719795c888938855b412b33192dfc7072962d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 14 Dec 2021 12:40:12 -0800 Subject: [PATCH 103/421] Open 6.3 development tree Signed-off-by: Richard Henderson --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 6abaeb2f90..8e8e37d75b 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.2.0 +6.2.50 From efe84f03ea88db49ae9180a9ffe4634349333c4e Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Wed, 8 Dec 2021 14:03:47 +0100 Subject: [PATCH 104/421] qtest/libqos: add a function to initialize secondary PCI buses Scan the PCI devices to find bridge and set PCI_SECONDARY_BUS and PCI_SUBORDINATE_BUS (algorithm from seabios) Signed-off-by: Laurent Vivier Acked-by: Thomas Huth Message-Id: <20211208130350.10178-2-lvivier@redhat.com> Signed-off-by: Thomas Huth --- include/hw/pci/pci_bridge.h | 8 +++ tests/qtest/libqos/pci.c | 119 ++++++++++++++++++++++++++++++++++++ tests/qtest/libqos/pci.h | 1 + 3 files changed, 128 insertions(+) diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index a94d350034..30691a6e57 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -138,6 +138,7 @@ typedef struct PCIBridgeQemuCap { uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */ } PCIBridgeQemuCap; +#define REDHAT_PCI_CAP_TYPE_OFFSET 3 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 /* @@ -152,6 +153,13 @@ typedef struct PCIResReserve { uint64_t mem_pref_64; } PCIResReserve; +#define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES 4 +#define REDHAT_PCI_CAP_RES_RESERVE_IO 8 +#define REDHAT_PCI_CAP_RES_RESERVE_MEM 16 +#define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20 +#define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24 +#define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE 32 + int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, PCIResReserve res_reserve, Error **errp); diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index e1e96189c8..3a9076ae58 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -13,6 +13,8 @@ #include "qemu/osdep.h" #include "pci.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_regs.h" #include "qemu/host-utils.h" #include "qgraph.h" @@ -99,6 +101,123 @@ void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr) g_assert(!addr->device_id || device_id == addr->device_id); } +static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev) +{ + uint16_t device_id; + uint8_t cap = 0; + + if (qpci_config_readw(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) { + return 0; + } + + device_id = qpci_config_readw(dev, PCI_DEVICE_ID); + + if (device_id != PCI_DEVICE_ID_REDHAT_PCIE_RP && + device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) { + return 0; + } + + do { + cap = qpci_find_capability(dev, PCI_CAP_ID_VNDR, cap); + } while (cap && + qpci_config_readb(dev, cap + REDHAT_PCI_CAP_TYPE_OFFSET) != + REDHAT_PCI_CAP_RESOURCE_RESERVE); + if (cap) { + uint8_t cap_len = qpci_config_readb(dev, cap + PCI_CAP_FLAGS); + if (cap_len < REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE) { + return 0; + } + } + return cap; +} + +static void qpci_secondary_buses_rec(QPCIBus *qbus, int bus, int *pci_bus) +{ + QPCIDevice *dev; + uint16_t class; + uint8_t pribus, secbus, subbus; + int index; + + for (index = 0; index < 32; index++) { + dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0)); + if (dev == NULL) { + continue; + } + class = qpci_config_readw(dev, PCI_CLASS_DEVICE); + if (class == PCI_CLASS_BRIDGE_PCI) { + qpci_config_writeb(dev, PCI_SECONDARY_BUS, 255); + qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 0); + } + g_free(dev); + } + + for (index = 0; index < 32; index++) { + dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0)); + if (dev == NULL) { + continue; + } + class = qpci_config_readw(dev, PCI_CLASS_DEVICE); + if (class != PCI_CLASS_BRIDGE_PCI) { + g_free(dev); + continue; + } + + pribus = qpci_config_readb(dev, PCI_PRIMARY_BUS); + if (pribus != bus) { + qpci_config_writeb(dev, PCI_PRIMARY_BUS, bus); + } + + secbus = qpci_config_readb(dev, PCI_SECONDARY_BUS); + (*pci_bus)++; + if (*pci_bus != secbus) { + secbus = *pci_bus; + qpci_config_writeb(dev, PCI_SECONDARY_BUS, secbus); + } + + subbus = qpci_config_readb(dev, PCI_SUBORDINATE_BUS); + qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 255); + + qpci_secondary_buses_rec(qbus, secbus << 5, pci_bus); + + if (subbus != *pci_bus) { + uint8_t res_bus = *pci_bus; + uint8_t cap = qpci_find_resource_reserve_capability(dev); + + if (cap) { + uint32_t tmp_res_bus; + + tmp_res_bus = qpci_config_readl(dev, cap + + REDHAT_PCI_CAP_RES_RESERVE_BUS_RES); + if (tmp_res_bus != (uint32_t)-1) { + res_bus = tmp_res_bus & 0xFF; + if ((uint8_t)(res_bus + secbus) < secbus || + (uint8_t)(res_bus + secbus) < res_bus) { + res_bus = 0; + } + if (secbus + res_bus > *pci_bus) { + res_bus = secbus + res_bus; + } + } + } + subbus = res_bus; + *pci_bus = res_bus; + } + + qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, subbus); + g_free(dev); + } +} + +int qpci_secondary_buses_init(QPCIBus *bus) +{ + int last_bus = 0; + + qpci_secondary_buses_rec(bus, 0, &last_bus); + + return last_bus; +} + + void qpci_device_enable(QPCIDevice *dev) { uint16_t cmd; diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index ee64fdecbd..becb800f9e 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -81,6 +81,7 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, void *data); QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn); void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr); +int qpci_secondary_buses_init(QPCIBus *bus); bool qpci_has_buggy_msi(QPCIDevice *dev); bool qpci_check_buggy_msi(QPCIDevice *dev); From e32b96b559cefb8cbb7038e913b94567e1a18045 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Wed, 8 Dec 2021 14:03:48 +0100 Subject: [PATCH 105/421] tests/qtest: add some tests for virtio-net failover Add test cases to test several error cases that must be generated by invalid failover configuration. Add a combination of coldplug and hotplug test cases to be sure the primary is correctly managed according the presence or not of the STANDBY feature. Signed-off-by: Laurent Vivier Message-Id: <20211208130350.10178-3-lvivier@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/meson.build | 4 + tests/qtest/virtio-net-failover.c | 788 ++++++++++++++++++++++++++++++ 2 files changed, 792 insertions(+) create mode 100644 tests/qtest/virtio-net-failover.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c9d8458062..975a0f2f5f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -68,6 +68,10 @@ qtests_i386 = \ (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : []) + \ (config_all_devices.has_key('CONFIG_E1000E_PCI_EXPRESS') ? ['fuzz-e1000e-test'] : []) + \ (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \ + (config_all_devices.has_key('CONFIG_VIRTIO_NET') and \ + config_all_devices.has_key('CONFIG_Q35') and \ + config_all_devices.has_key('CONFIG_VIRTIO_PCI') and \ + slirp.found() ? ['virtio-net-failover'] : []) + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ qtests_pci + \ ['fdc-test', diff --git a/tests/qtest/virtio-net-failover.c b/tests/qtest/virtio-net-failover.c new file mode 100644 index 0000000000..fd7821deaf --- /dev/null +++ b/tests/qtest/virtio-net-failover.c @@ -0,0 +1,788 @@ +/* + * QTest testcase for virtio-net failover + * + * See docs/system/virtio-net-failover.rst + * + * Copyright (c) 2021 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "libqos/libqtest.h" +#include "libqos/pci.h" +#include "libqos/pci-pc.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qlist.h" +#include "qapi/qmp/qjson.h" +#include "libqos/malloc-pc.h" +#include "libqos/virtio-pci.h" +#include "hw/pci/pci.h" + +#define ACPI_PCIHP_ADDR_ICH9 0x0cc0 +#define PCI_EJ_BASE 0x0008 + +#define BASE_MACHINE "-M q35 -nodefaults " \ + "-device pcie-root-port,id=root0,addr=0x1,bus=pcie.0,chassis=1 " \ + "-device pcie-root-port,id=root1,addr=0x2,bus=pcie.0,chassis=2 " + +#define MAC_PRIMARY0 "52:54:00:11:11:11" +#define MAC_STANDBY0 "52:54:00:22:22:22" + +static QGuestAllocator guest_malloc; +static QPCIBus *pcibus; + +static QTestState *machine_start(const char *args, int numbus) +{ + QTestState *qts; + QPCIDevice *dev; + int bus; + + qts = qtest_init(args); + + pc_alloc_init(&guest_malloc, qts, 0); + pcibus = qpci_new_pc(qts, &guest_malloc); + g_assert(qpci_secondary_buses_init(pcibus) == numbus); + + for (bus = 1; bus <= numbus; bus++) { + dev = qpci_device_find(pcibus, QPCI_DEVFN(bus, 0)); + g_assert_nonnull(dev); + + qpci_device_enable(dev); + qpci_iomap(dev, 4, NULL); + + g_free(dev); + } + + return qts; +} + +static void machine_stop(QTestState *qts) +{ + qpci_free_pc(pcibus); + alloc_destroy(&guest_malloc); + qtest_quit(qts); +} + +static void test_error_id(void) +{ + QTestState *qts; + QDict *resp; + QDict *err; + + qts = machine_start(BASE_MACHINE + "-device virtio-net,bus=root0,id=standby0,failover=on", + 2); + + resp = qtest_qmp(qts, "{'execute': 'device_add'," + "'arguments': {" + "'driver': 'virtio-net'," + "'bus': 'root1'," + "'failover_pair_id': 'standby0'" + "} }"); + g_assert(qdict_haskey(resp, "error")); + + err = qdict_get_qdict(resp, "error"); + g_assert(qdict_haskey(err, "desc")); + + g_assert_cmpstr(qdict_get_str(err, "desc"), ==, + "Device with failover_pair_id needs to have id"); + + qobject_unref(resp); + + machine_stop(qts); +} + +static void test_error_pcie(void) +{ + QTestState *qts; + QDict *resp; + QDict *err; + + qts = machine_start(BASE_MACHINE + "-device virtio-net,bus=root0,id=standby0,failover=on", + 2); + + resp = qtest_qmp(qts, "{'execute': 'device_add'," + "'arguments': {" + "'driver': 'virtio-net'," + "'id': 'primary0'," + "'bus': 'pcie.0'," + "'failover_pair_id': 'standby0'" + "} }"); + g_assert(qdict_haskey(resp, "error")); + + err = qdict_get_qdict(resp, "error"); + g_assert(qdict_haskey(err, "desc")); + + g_assert_cmpstr(qdict_get_str(err, "desc"), ==, + "Bus 'pcie.0' does not support hotplugging"); + + qobject_unref(resp); + + machine_stop(qts); +} + +static QDict *find_device(QDict *bus, const char *name) +{ + const QObject *obj; + QList *devices; + QList *list; + + devices = qdict_get_qlist(bus, "devices"); + if (devices == NULL) { + return NULL; + } + + list = qlist_copy(devices); + while ((obj = qlist_pop(list))) { + QDict *device; + + device = qobject_to(QDict, obj); + + if (qdict_haskey(device, "pci_bridge")) { + QDict *bridge; + QDict *bridge_device; + + bridge = qdict_get_qdict(device, "pci_bridge"); + + if (qdict_haskey(bridge, "devices")) { + bridge_device = find_device(bridge, name); + if (bridge_device) { + qobject_unref(device); + qobject_unref(list); + return bridge_device; + } + } + } + + if (!qdict_haskey(device, "qdev_id")) { + qobject_unref(device); + continue; + } + + if (strcmp(qdict_get_str(device, "qdev_id"), name) == 0) { + qobject_unref(list); + return device; + } + qobject_unref(device); + } + qobject_unref(list); + + return NULL; +} + +static QDict *get_bus(QTestState *qts, int num) +{ + QObject *obj; + QDict *resp; + QList *ret; + + resp = qtest_qmp(qts, "{ 'execute': 'query-pci' }"); + g_assert(qdict_haskey(resp, "return")); + + ret = qdict_get_qlist(resp, "return"); + g_assert_nonnull(ret); + + while ((obj = qlist_pop(ret))) { + QDict *bus; + + bus = qobject_to(QDict, obj); + if (!qdict_haskey(bus, "bus")) { + qobject_unref(bus); + continue; + } + if (qdict_get_int(bus, "bus") == num) { + qobject_unref(resp); + return bus; + } + qobject_ref(bus); + } + qobject_unref(resp); + + return NULL; +} + +static char *get_mac(QTestState *qts, const char *name) +{ + QDict *resp; + char *mac; + + resp = qtest_qmp(qts, "{ 'execute': 'qom-get', " + "'arguments': { " + "'path': %s, " + "'property': 'mac' } }", name); + + g_assert(qdict_haskey(resp, "return")); + + mac = g_strdup(qdict_get_str(resp, "return")); + + qobject_unref(resp); + + return mac; +} + +static void check_one_card(QTestState *qts, bool present, + const char *id, const char *mac) +{ + QDict *device; + QDict *bus; + char *addr; + + bus = get_bus(qts, 0); + device = find_device(bus, id); + if (present) { + char *path; + + g_assert_nonnull(device); + qobject_unref(device); + + path = g_strdup_printf("/machine/peripheral/%s", id); + addr = get_mac(qts, path); + g_free(path); + g_assert_cmpstr(mac, ==, addr); + g_free(addr); + } else { + g_assert_null(device); + } + + qobject_unref(bus); +} + +static void test_on(void) +{ + QTestState *qts; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0, + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + machine_stop(qts); +} + +static void test_on_mismatch(void) +{ + QTestState *qts; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby1,netdev=hs1,mac="MAC_PRIMARY0, + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + machine_stop(qts); +} + +static void test_off(void) +{ + QTestState *qts; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=off,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0, + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + machine_stop(qts); +} + +static QDict *get_failover_negociated_event(QTestState *qts) +{ + QDict *resp; + QDict *data; + + resp = qtest_qmp_eventwait_ref(qts, "FAILOVER_NEGOTIATED"); + g_assert(qdict_haskey(resp, "data")); + + data = qdict_get_qdict(resp, "data"); + g_assert(qdict_haskey(data, "device-id")); + qobject_ref(data); + qobject_unref(resp); + + return data; +} + +static QVirtioPCIDevice *start_virtio_net(QTestState *qts, int bus, int slot, + const char *id) +{ + QVirtioPCIDevice *dev; + uint64_t features; + QPCIAddress addr; + QDict *resp; + + addr.devfn = QPCI_DEVFN((bus << 5) + slot, 0); + dev = virtio_pci_new(pcibus, &addr); + g_assert_nonnull(dev); + qvirtio_pci_device_enable(dev); + qvirtio_start_device(&dev->vdev); + features = qvirtio_get_features(&dev->vdev); + features = features & ~(QVIRTIO_F_BAD_FEATURE | + (1ull << VIRTIO_RING_F_INDIRECT_DESC) | + (1ull << VIRTIO_RING_F_EVENT_IDX)); + qvirtio_set_features(&dev->vdev, features); + qvirtio_set_driver_ok(&dev->vdev); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, id); + qobject_unref(resp); + + return dev; +} + +static void test_enabled(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0" ", + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_1(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 ", 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_1_reverse(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0" ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_2(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_2_reverse(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_STANDBY0"'}"); + + /* + * XXX: sounds like a bug: + * The primary should be hidden until the virtio-net driver + * negotiates the VIRTIO_NET_F_STANDBY feature by start_virtio_net() + */ + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static QDict *migrate_status(QTestState *qts) +{ + QDict *resp, *ret; + + resp = qtest_qmp(qts, "{ 'execute': 'query-migrate' }"); + g_assert(qdict_haskey(resp, "return")); + + ret = qdict_get_qdict(resp, "return"); + g_assert(qdict_haskey(ret, "status")); + qobject_ref(ret); + qobject_unref(resp); + + return ret; +} + +static QDict *get_unplug_primary_event(QTestState *qts) +{ + QDict *resp; + QDict *data; + + resp = qtest_qmp_eventwait_ref(qts, "UNPLUG_PRIMARY"); + g_assert(qdict_haskey(resp, "data")); + + data = qdict_get_qdict(resp, "data"); + g_assert(qdict_haskey(data, "device-id")); + qobject_ref(data); + qobject_unref(resp); + + return data; +} + +static void test_migrate_out(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + /* wait the end of the migration setup phase */ + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "wait-unplug") == 0) { + qobject_unref(ret); + break; + } + + /* The migration must not start if the card is not ejected */ + g_assert_cmpstr(status, !=, "active"); + g_assert_cmpstr(status, !=, "completed"); + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + + qobject_unref(ret); + } + + if (g_test_slow()) { + /* check we stay in wait-unplug while the card is not ejected */ + for (int i = 0; i < 5; i++) { + sleep(1); + ret = migrate_status(qts); + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "wait-unplug"); + qobject_unref(ret); + } + } + + /* OS unplugs the cards, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "completed") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + qobject_unref(ret); + } + + qtest_qmp_eventwait(qts, "STOP"); + + /* + * in fact, the card is ejected from the point of view of kernel + * but not really from QEMU to be able to hotplug it back if + * migration fails. So we can't check that: + * check_one_card(qts, true, "standby0", MAC_STANDBY0); + * check_one_card(qts, false, "primary0", MAC_PRIMARY0); + */ + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static QDict *get_migration_event(QTestState *qts) +{ + QDict *resp; + QDict *data; + + resp = qtest_qmp_eventwait_ref(qts, "MIGRATION"); + g_assert(qdict_haskey(resp, "data")); + + data = qdict_get_qdict(resp, "data"); + g_assert(qdict_haskey(data, "status")); + qobject_ref(data); + qobject_unref(resp); + + return data; +} + +static void test_migrate_in(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat %s", (gchar *)opaque); + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-incoming defer ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate-incoming', 'arguments': %p}", + args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + resp = get_migration_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "status"), ==, "setup"); + qobject_unref(resp); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "standby0"); + qobject_unref(resp); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qtest_qmp_eventwait(qts, "RESUME"); + + ret = migrate_status(qts); + g_assert_cmpstr(qdict_get_str(ret, "status"), ==, "completed"); + qobject_unref(ret); + + machine_stop(qts); +} + +int main(int argc, char **argv) +{ + const gchar *tmpdir = g_get_tmp_dir(); + gchar *tmpfile = g_strdup_printf("%s/failover_test_migrate-%u-%u", + tmpdir, getpid(), g_test_rand_int()); + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_add_func("failover-virtio-net/params/error/id", test_error_id); + qtest_add_func("failover-virtio-net/params/error/pcie", test_error_pcie); + qtest_add_func("failover-virtio-net/params/on", test_on); + qtest_add_func("failover-virtio-net/params/on_mismatch", + test_on_mismatch); + qtest_add_func("failover-virtio-net/params/off", test_off); + qtest_add_func("failover-virtio-net/params/enabled", test_enabled); + qtest_add_func("failover-virtio-net/hotplug_1", test_hotplug_1); + qtest_add_func("failover-virtio-net/hotplug_1_reverse", + test_hotplug_1_reverse); + qtest_add_func("failover-virtio-net/hotplug_2", test_hotplug_2); + qtest_add_func("failover-virtio-net/hotplug_2_reverse", + test_hotplug_2_reverse); + qtest_add_data_func("failover-virtio-net/migrate/out", tmpfile, + test_migrate_out); + qtest_add_data_func("failover-virtio-net/migrate/in", tmpfile, + test_migrate_in); + + ret = g_test_run(); + + unlink(tmpfile); + g_free(tmpfile); + + return ret; +} From 1e2077e22332c4d2867043bbea2337d331106bfd Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Wed, 8 Dec 2021 14:03:49 +0100 Subject: [PATCH 106/421] tests/libqtest: add some virtio-net failover migration cancelling tests Add some tests to check the state of the machine if the migration is cancelled while we are using virtio-net failover. Signed-off-by: Laurent Vivier Acked-by: Thomas Huth Message-Id: <20211208130350.10178-4-lvivier@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/virtio-net-failover.c | 282 ++++++++++++++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/tests/qtest/virtio-net-failover.c b/tests/qtest/virtio-net-failover.c index fd7821deaf..e998a546b0 100644 --- a/tests/qtest/virtio-net-failover.c +++ b/tests/qtest/virtio-net-failover.c @@ -752,6 +752,280 @@ static void test_migrate_in(gconstpointer opaque) machine_stop(qts); } +static void test_migrate_abort_wait_unplug(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate_cancel' }"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* migration has been cancelled while the unplug was in progress */ + + /* while the card is not ejected, we must be in "cancelling" state */ + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "cancelling"); + qobject_unref(ret); + + /* OS unplugs the cards, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "cancelled") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "active"); + qobject_unref(ret); + } + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_migrate_abort_active(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + /* OS unplugs the cards, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "wait-unplug") != 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + qobject_unref(ret); + } + + resp = qtest_qmp(qts, "{ 'execute': 'migrate_cancel' }"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "cancelled") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "active"); + qobject_unref(ret); + } + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_migrate_abort_timeout(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + int total; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate_cancel' }"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* migration has been cancelled while the unplug was in progress */ + + /* while the card is not ejected, we must be in "cancelling" state */ + + total = 0; + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "cancelled") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, ==, "cancelling"); + g_assert(qdict_haskey(ret, "total-time")); + total = qdict_get_int(ret, "total-time"); + qobject_unref(ret); + } + + /* + * migration timeout in this case is 30 seconds + * check we exit on the timeout (ms) + */ + g_assert_cmpint(total, >, 30000); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + int main(int argc, char **argv) { const gchar *tmpdir = g_get_tmp_dir(); @@ -778,6 +1052,14 @@ int main(int argc, char **argv) test_migrate_out); qtest_add_data_func("failover-virtio-net/migrate/in", tmpfile, test_migrate_in); + qtest_add_data_func("failover-virtio-net/migrate/abort/wait-unplug", + tmpfile, test_migrate_abort_wait_unplug); + qtest_add_data_func("failover-virtio-net/migrate/abort/active", tmpfile, + test_migrate_abort_active); + if (g_test_slow()) { + qtest_add_data_func("failover-virtio-net/migrate/abort/timeout", + tmpfile, test_migrate_abort_timeout); + } ret = g_test_run(); From e1e3d3211815c407cacb845fc0f6c2c328b2e684 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Wed, 8 Dec 2021 14:03:50 +0100 Subject: [PATCH 107/421] tests/libqtest: add a migration test with two couples of failover devices Signed-off-by: Laurent Vivier Acked-by: Thomas Huth Message-Id: <20211208130350.10178-5-lvivier@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/virtio-net-failover.c | 282 ++++++++++++++++++++++++++++++ 1 file changed, 282 insertions(+) diff --git a/tests/qtest/virtio-net-failover.c b/tests/qtest/virtio-net-failover.c index e998a546b0..4b2ba8a106 100644 --- a/tests/qtest/virtio-net-failover.c +++ b/tests/qtest/virtio-net-failover.c @@ -20,6 +20,7 @@ #define ACPI_PCIHP_ADDR_ICH9 0x0cc0 #define PCI_EJ_BASE 0x0008 +#define PCI_SEL_BASE 0x0010 #define BASE_MACHINE "-M q35 -nodefaults " \ "-device pcie-root-port,id=root0,addr=0x1,bus=pcie.0,chassis=1 " \ @@ -27,6 +28,8 @@ #define MAC_PRIMARY0 "52:54:00:11:11:11" #define MAC_STANDBY0 "52:54:00:22:22:22" +#define MAC_PRIMARY1 "52:54:00:33:33:33" +#define MAC_STANDBY1 "52:54:00:44:44:44" static QGuestAllocator guest_malloc; static QPCIBus *pcibus; @@ -1026,6 +1029,281 @@ static void test_migrate_abort_timeout(gconstpointer opaque) machine_stop(qts); } +static void test_multi_out(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status, *expected; + QVirtioPCIDevice *vdev0, *vdev1; + + qts = machine_start(BASE_MACHINE + "-device pcie-root-port,id=root2,addr=0x3,bus=pcie.0,chassis=3 " + "-device pcie-root-port,id=root3,addr=0x4,bus=pcie.0,chassis=4 " + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-netdev user,id=hs2 " + "-netdev user,id=hs3 ", + 4); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + vdev0 = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby1", + "{'bus': 'root2'," + "'failover': 'on'," + "'netdev': 'hs2'," + "'mac': '"MAC_STANDBY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary1", + "{'bus': 'root3'," + "'failover_pair_id': 'standby1'," + "'netdev': 'hs3'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + vdev1 = start_virtio_net(qts, 3, 0, "standby1"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, true, "primary1", MAC_PRIMARY1); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + if (strcmp(qdict_get_str(resp, "device-id"), "primary0") == 0) { + expected = "primary1"; + } else if (strcmp(qdict_get_str(resp, "device-id"), "primary1") == 0) { + expected = "primary0"; + } else { + g_assert_not_reached(); + } + qobject_unref(resp); + + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, expected); + qobject_unref(resp); + + /* wait the end of the migration setup phase */ + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "wait-unplug") == 0) { + qobject_unref(ret); + break; + } + + /* The migration must not start if the card is not ejected */ + g_assert_cmpstr(status, !=, "active"); + g_assert_cmpstr(status, !=, "completed"); + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + + qobject_unref(ret); + } + + /* OS unplugs primary1, but we must wait the second */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + ret = migrate_status(qts); + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "wait-unplug"); + qobject_unref(ret); + + if (g_test_slow()) { + /* check we stay in wait-unplug while the card is not ejected */ + for (int i = 0; i < 5; i++) { + sleep(1); + ret = migrate_status(qts); + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "wait-unplug"); + qobject_unref(ret); + } + } + + /* OS unplugs primary0, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_SEL_BASE, 2); + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "completed") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + qobject_unref(ret); + } + + qtest_qmp_eventwait(qts, "STOP"); + + qos_object_destroy((QOSGraphObject *)vdev0); + qos_object_destroy((QOSGraphObject *)vdev1); + machine_stop(qts); +} + +static void test_multi_in(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat %s", (gchar *)opaque); + + qts = machine_start(BASE_MACHINE + "-device pcie-root-port,id=root2,addr=0x3,bus=pcie.0,chassis=3 " + "-device pcie-root-port,id=root3,addr=0x4,bus=pcie.0,chassis=4 " + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-netdev user,id=hs2 " + "-netdev user,id=hs3 " + "-incoming defer ", + 4); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby1", + "{'bus': 'root2'," + "'failover': 'on'," + "'netdev': 'hs2'," + "'mac': '"MAC_STANDBY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary1", + "{'bus': 'root3'," + "'failover_pair_id': 'standby1'," + "'netdev': 'hs3'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate-incoming', 'arguments': %p}", + args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + resp = get_migration_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "status"), ==, "setup"); + qobject_unref(resp); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "standby0"); + qobject_unref(resp); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "standby1"); + qobject_unref(resp); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, true, "primary1", MAC_PRIMARY1); + + qtest_qmp_eventwait(qts, "RESUME"); + + ret = migrate_status(qts); + g_assert_cmpstr(qdict_get_str(ret, "status"), ==, "completed"); + qobject_unref(ret); + + machine_stop(qts); +} + int main(int argc, char **argv) { const gchar *tmpdir = g_get_tmp_dir(); @@ -1060,6 +1338,10 @@ int main(int argc, char **argv) qtest_add_data_func("failover-virtio-net/migrate/abort/timeout", tmpfile, test_migrate_abort_timeout); } + qtest_add_data_func("failover-virtio-net/multi/out", + tmpfile, test_multi_out); + qtest_add_data_func("failover-virtio-net/multi/in", + tmpfile, test_multi_in); ret = g_test_run(); From a9697d0947798ec9cc8387308e1d353123639ec3 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Wed, 1 Dec 2021 11:43:44 +0100 Subject: [PATCH 108/421] tests/qtest: Run the PPC 32-bit tests with the 64-bit target binary, too The ppc64 target is a superset of the 32-bit target, so we should include the tests here, too. This used to be done in the past already, but it got lost during the conversion to meson. Fixes: a2ce7dbd91 ("meson: convert tests/qtest to meson") Message-Id: <20211201104347.51922-2-thuth@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 975a0f2f5f..36ca175660 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -138,6 +138,7 @@ qtests_ppc = \ ['boot-order-test', 'prom-env-test', 'boot-serial-test'] \ qtests_ppc64 = \ + qtests_ppc + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + \ From bf22f15114b2a1d5eefbcbc18f939d5006d77f72 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Wed, 1 Dec 2021 11:43:45 +0100 Subject: [PATCH 109/421] tests/qtest: Fence the tests that need xlnx-zcu102 with CONFIG_XLNX_ZYNQMP_ARM The 'xlnx-can-test' and the 'fuzz-xlnx-dp-test' need the "xlnx-zcu102" machine and thus should only be built and run if CONFIG_XLNX_ZYNQMP_ARM is enabled. Message-Id: <20211201104347.51922-3-thuth@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/meson.build | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 36ca175660..9ff3eaf3d0 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -188,11 +188,10 @@ qtests_aarch64 = \ (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ + (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'xlnx-can-test', - 'fuzz-xlnx-dp-test', 'migration-test'] qtests_s390x = \ From 5516a3b592def4de7fa78153912470f160814e5a Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Wed, 1 Dec 2021 11:43:46 +0100 Subject: [PATCH 110/421] tests/qtest: Add a function that gets a list with available machine types For the upcoming patches, we will need a way to gets a list with all available machine types. Refactor the qtest_cb_for_every_machine() to split the related code out into a separate new function, and gather the aliases of the various machine types, too. Message-Id: <20211201104347.51922-4-thuth@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/libqtest.c | 64 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 11 deletions(-) diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 25aeea385b..7ae2dc4e1d 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1321,16 +1321,29 @@ static bool qtest_is_old_versioned_machine(const char *mname) return res; } -void qtest_cb_for_every_machine(void (*cb)(const char *machine), - bool skip_old_versioned) +struct MachInfo { + char *name; + char *alias; +}; + +/* + * Returns an array with pointers to the available machine names. + * The terminating entry has the name set to NULL. + */ +static struct MachInfo *qtest_get_machines(void) { + static struct MachInfo *machines; QDict *response, *minfo; QList *list; const QListEntry *p; QObject *qobj; QString *qstr; - const char *mname; QTestState *qts; + int idx; + + if (machines) { + return machines; + } qts = qtest_init("-machine none"); response = qtest_qmp(qts, "{ 'execute': 'query-machines' }"); @@ -1338,25 +1351,54 @@ void qtest_cb_for_every_machine(void (*cb)(const char *machine), list = qdict_get_qlist(response, "return"); g_assert(list); - for (p = qlist_first(list); p; p = qlist_next(p)) { + machines = g_new(struct MachInfo, qlist_size(list) + 1); + + for (p = qlist_first(list), idx = 0; p; p = qlist_next(p), idx++) { minfo = qobject_to(QDict, qlist_entry_obj(p)); g_assert(minfo); + qobj = qdict_get(minfo, "name"); g_assert(qobj); qstr = qobject_to(QString, qobj); g_assert(qstr); - mname = qstring_get_str(qstr); - /* Ignore machines that cannot be used for qtests */ - if (!strncmp("xenfv", mname, 5) || g_str_equal("xenpv", mname)) { - continue; - } - if (!skip_old_versioned || !qtest_is_old_versioned_machine(mname)) { - cb(mname); + machines[idx].name = g_strdup(qstring_get_str(qstr)); + + qobj = qdict_get(minfo, "alias"); + if (qobj) { /* The alias is optional */ + qstr = qobject_to(QString, qobj); + g_assert(qstr); + machines[idx].alias = g_strdup(qstring_get_str(qstr)); + } else { + machines[idx].alias = NULL; } } qtest_quit(qts); qobject_unref(response); + + memset(&machines[idx], 0, sizeof(struct MachInfo)); /* Terminating entry */ + return machines; +} + +void qtest_cb_for_every_machine(void (*cb)(const char *machine), + bool skip_old_versioned) +{ + struct MachInfo *machines; + int i; + + machines = qtest_get_machines(); + + for (i = 0; machines[i].name != NULL; i++) { + /* Ignore machines that cannot be used for qtests */ + if (!strncmp("xenfv", machines[i].name, 5) || + g_str_equal("xenpv", machines[i].name)) { + continue; + } + if (!skip_old_versioned || + !qtest_is_old_versioned_machine(machines[i].name)) { + cb(machines[i].name); + } + } } /* From 719051ca3fd0ee765d8a80670df1a0292aa566f0 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Wed, 1 Dec 2021 11:43:47 +0100 Subject: [PATCH 111/421] tests/qtest: Add a function to check whether a machine is available It is nowadays possible to build QEMU with a reduced set of machines in each binary. However, the qtests still hard-code the expected machines and fail if the binary does not feature the required machine. Let's get a little bit more flexible here: Add a function that can be used to query whether a certain machine is available or not, and use it in some tests as an example (more work has to be done in other tests which will follow later). Message-Id: <20211201104347.51922-5-thuth@redhat.com> Acked-by: John Snow Signed-off-by: Thomas Huth --- tests/qtest/boot-serial-test.c | 3 ++- tests/qtest/cdrom-test.c | 8 +++++--- tests/qtest/libqos/libqtest.h | 8 ++++++++ tests/qtest/libqtest.c | 17 +++++++++++++++++ tests/qtest/prom-env-test.c | 8 +++++--- 5 files changed, 37 insertions(+), 7 deletions(-) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index 83828ba270..4d8e1343bd 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -285,7 +285,8 @@ int main(int argc, char *argv[]) g_test_init(&argc, &argv, NULL); for (i = 0; tests[i].arch != NULL; i++) { - if (strcmp(arch, tests[i].arch) == 0) { + if (g_str_equal(arch, tests[i].arch) && + qtest_has_machine(tests[i].machine)) { char *name = g_strdup_printf("boot-serial/%s", tests[i].machine); qtest_add_data_func(name, &tests[i], test_machine); g_free(name); diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index 5af944a5fb..c1fcac5c45 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -109,9 +109,11 @@ static void test_cdrom_param(gconstpointer data) static void add_cdrom_param_tests(const char **machines) { while (*machines) { - char *testname = g_strdup_printf("cdrom/param/%s", *machines); - qtest_add_data_func(testname, *machines, test_cdrom_param); - g_free(testname); + if (qtest_has_machine(*machines)) { + char *testname = g_strdup_printf("cdrom/param/%s", *machines); + qtest_add_data_func(testname, *machines, test_cdrom_param); + g_free(testname); + } machines++; } } diff --git a/tests/qtest/libqos/libqtest.h b/tests/qtest/libqos/libqtest.h index 59e9271195..dff6b31cf0 100644 --- a/tests/qtest/libqos/libqtest.h +++ b/tests/qtest/libqos/libqtest.h @@ -710,6 +710,14 @@ QDict *qmp_fd(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); void qtest_cb_for_every_machine(void (*cb)(const char *machine), bool skip_old_versioned); +/** + * qtest_has_machine: + * @machine: The machine to look for + * + * Returns: true if the machine is available in the target binary. + */ +bool qtest_has_machine(const char *machine); + /** * qtest_qmp_device_add_qdict: * @qts: QTestState instance to operate on diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 7ae2dc4e1d..65ed949685 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1401,6 +1401,23 @@ void qtest_cb_for_every_machine(void (*cb)(const char *machine), } } +bool qtest_has_machine(const char *machine) +{ + struct MachInfo *machines; + int i; + + machines = qtest_get_machines(); + + for (i = 0; machines[i].name != NULL; i++) { + if (g_str_equal(machine, machines[i].name) || + (machines[i].alias && g_str_equal(machine, machines[i].alias))) { + return true; + } + } + + return false; +} + /* * Generic hot-plugging test via the device_add QMP commands. */ diff --git a/tests/qtest/prom-env-test.c b/tests/qtest/prom-env-test.c index f41d80154a..bdbb01d8e5 100644 --- a/tests/qtest/prom-env-test.c +++ b/tests/qtest/prom-env-test.c @@ -71,9 +71,11 @@ static void add_tests(const char *machines[]) char *name; for (i = 0; machines[i] != NULL; i++) { - name = g_strdup_printf("prom-env/%s", machines[i]); - qtest_add_data_func(name, machines[i], test_machine); - g_free(name); + if (qtest_has_machine(machines[i])) { + name = g_strdup_printf("prom-env/%s", machines[i]); + qtest_add_data_func(name, machines[i], test_machine); + g_free(name); + } } } From e6a52b3651a3b2be41ee3309bc05f9b1e2cf8b90 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Thu, 9 Dec 2021 15:48:01 +0100 Subject: [PATCH 112/421] Move the libssh setup from configure to meson.build It's easier to do this in meson.build now. Message-Id: <20211209144801.148388-1-thuth@redhat.com> Acked-by: Richard W.M. Jones Signed-off-by: Thomas Huth --- configure | 27 --------------------------- meson.build | 13 +++++++++---- meson_options.txt | 2 ++ scripts/meson-buildoptions.sh | 3 +++ 4 files changed, 14 insertions(+), 31 deletions(-) diff --git a/configure b/configure index 48c21775f3..bb99a40ed0 100755 --- a/configure +++ b/configure @@ -344,7 +344,6 @@ debug_stack_usage="no" crypto_afalg="no" tls_priority="NORMAL" tpm="$default_feature" -libssh="$default_feature" live_block_migration=${default_feature:-yes} numa="$default_feature" replication=${default_feature:-yes} @@ -1078,10 +1077,6 @@ for opt do ;; --enable-tpm) tpm="yes" ;; - --disable-libssh) libssh="no" - ;; - --enable-libssh) libssh="yes" - ;; --disable-live-block-migration) live_block_migration="no" ;; --enable-live-block-migration) live_block_migration="yes" @@ -1448,7 +1443,6 @@ cat << EOF live-block-migration Block migration in the main migration stream coroutine-pool coroutine freelist (better performance) tpm TPM support - libssh ssh block device support numa libnuma support avx2 AVX2 optimization support avx512f AVX512F optimization support @@ -2561,21 +2555,6 @@ if test "$modules" = yes; then fi fi -########################################## -# libssh probe -if test "$libssh" != "no" ; then - if $pkg_config --exists "libssh >= 0.8.7"; then - libssh_cflags=$($pkg_config libssh --cflags) - libssh_libs=$($pkg_config libssh --libs) - libssh=yes - else - if test "$libssh" = "yes" ; then - error_exit "libssh required for --enable-libssh" - fi - libssh=no - fi -fi - ########################################## # TPM emulation is only on POSIX @@ -3636,12 +3615,6 @@ if test "$cmpxchg128" = "yes" ; then echo "CONFIG_CMPXCHG128=y" >> $config_host_mak fi -if test "$libssh" = "yes" ; then - echo "CONFIG_LIBSSH=y" >> $config_host_mak - echo "LIBSSH_CFLAGS=$libssh_cflags" >> $config_host_mak - echo "LIBSSH_LIBS=$libssh_libs" >> $config_host_mak -fi - if test "$live_block_migration" = "yes" ; then echo "CONFIG_LIVE_BLOCK_MIGRATION=y" >> $config_host_mak fi diff --git a/meson.build b/meson.build index 96de1a6ef9..ae67ca28ab 100644 --- a/meson.build +++ b/meson.build @@ -874,11 +874,15 @@ if not get_option('glusterfs').auto() or have_block ''', dependencies: glusterfs) endif endif + libssh = not_found -if 'CONFIG_LIBSSH' in config_host - libssh = declare_dependency(compile_args: config_host['LIBSSH_CFLAGS'].split(), - link_args: config_host['LIBSSH_LIBS'].split()) +if not get_option('libssh').auto() or have_block + libssh = dependency('libssh', version: '>=0.8.7', + method: 'pkg-config', + required: get_option('libssh'), + kwargs: static_kwargs) endif + libbzip2 = not_found if not get_option('bzip2').auto() or have_block libbzip2 = cc.find_library('bz2', has_headers: ['bzlib.h'], @@ -1451,6 +1455,7 @@ config_host_data.set('CONFIG_EBPF', libbpf.found()) config_host_data.set('CONFIG_LIBDAXCTL', libdaxctl.found()) config_host_data.set('CONFIG_LIBISCSI', libiscsi.found()) config_host_data.set('CONFIG_LIBNFS', libnfs.found()) +config_host_data.set('CONFIG_LIBSSH', libssh.found()) config_host_data.set('CONFIG_LINUX_AIO', libaio.found()) config_host_data.set('CONFIG_LINUX_IO_URING', linux_io_uring.found()) config_host_data.set('CONFIG_LIBPMEM', libpmem.found()) @@ -3430,7 +3435,7 @@ endif summary_info += {'seccomp support': seccomp} summary_info += {'GlusterFS support': glusterfs} summary_info += {'TPM support': config_host.has_key('CONFIG_TPM')} -summary_info += {'libssh support': config_host.has_key('CONFIG_LIBSSH')} +summary_info += {'libssh support': libssh} summary_info += {'lzo support': lzo} summary_info += {'snappy support': snappy} summary_info += {'bzip2 support': libbzip2} diff --git a/meson_options.txt b/meson_options.txt index e392323732..4114bfcaa4 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -105,6 +105,8 @@ option('libdaxctl', type : 'feature', value : 'auto', description: 'libdaxctl support') option('libpmem', type : 'feature', value : 'auto', description: 'libpmem support') +option('libssh', type : 'feature', value : 'auto', + description: 'ssh block device support') option('libudev', type : 'feature', value : 'auto', description: 'Use libudev to enumerate host devices') option('libusb', type : 'feature', value : 'auto', diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 7a17ff4218..ae8f18edc2 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -53,6 +53,7 @@ meson_options_help() { printf "%s\n" ' libiscsi libiscsi userspace initiator' printf "%s\n" ' libnfs libnfs block device driver' printf "%s\n" ' libpmem libpmem support' + printf "%s\n" ' libssh ssh block device support' printf "%s\n" ' libudev Use libudev to enumerate host devices' printf "%s\n" ' libusb libusb support for USB passthrough' printf "%s\n" ' libxml2 libxml2 support for Parallels image format' @@ -177,6 +178,8 @@ _meson_option_parse() { --disable-libnfs) printf "%s" -Dlibnfs=disabled ;; --enable-libpmem) printf "%s" -Dlibpmem=enabled ;; --disable-libpmem) printf "%s" -Dlibpmem=disabled ;; + --enable-libssh) printf "%s" -Dlibssh=enabled ;; + --disable-libssh) printf "%s" -Dlibssh=disabled ;; --enable-libudev) printf "%s" -Dlibudev=enabled ;; --disable-libudev) printf "%s" -Dlibudev=disabled ;; --enable-libusb) printf "%s" -Dlibusb=enabled ;; From f462be4c062959b6c5bf78df235c16b6c09792ab Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 26 Nov 2021 17:27:24 +0100 Subject: [PATCH 113/421] gitlab-ci.d/buildtest: Add jobs that run the device-crash-test MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The device-crash-test script has been quite neglected in the past, so that it bit-rot quite often. Let's add CI jobs that run this script for at least some targets, so that this script does not regress that easily anymore. Message-Id: <20211126162724.1162049-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- .gitlab-ci.d/buildtest.yml | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 71d0f407ad..7e1cb0b3c2 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -100,6 +100,17 @@ avocado-system-debian: IMAGE: debian-amd64 MAKE_CHECK_ARGS: check-avocado +crash-test-debian: + extends: .native_test_job_template + needs: + - job: build-system-debian + artifacts: true + variables: + IMAGE: debian-amd64 + script: + - cd build + - scripts/device-crash-test -q ./qemu-system-i386 + build-system-fedora: extends: .native_build_job_template needs: @@ -134,6 +145,18 @@ avocado-system-fedora: IMAGE: fedora MAKE_CHECK_ARGS: check-avocado +crash-test-fedora: + extends: .native_test_job_template + needs: + - job: build-system-fedora + artifacts: true + variables: + IMAGE: fedora + script: + - cd build + - scripts/device-crash-test -q ./qemu-system-ppc + - scripts/device-crash-test -q ./qemu-system-riscv32 + build-system-centos: extends: .native_build_job_template needs: From f11b0a4892ae22b8729a75b2232073fb4090ff28 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Thu, 9 Dec 2021 11:31:24 +0100 Subject: [PATCH 114/421] gitlab-ci: Add cirrus-ci based tests for NetBSD and OpenBSD Cirrus-CI provides KVM in their Linux containers, so we can also run our VM-based NetBSD and OpenBSD build jobs there. Since the VM installation might take a while, we only run the "help" target on the first invocation to avoid timeouts, and then only check the build during the next run, once the base image has been cached. For the the build tests, we also only use very a limited set of target CPUs since compiling in these VMs is not very fast (especially the build on OpenBSD seems to be incredibly slow). The jobs are marked as "manual" only, since this double-indirect setup (with the cirrus-run script and VMs in the Cirrus-CI containers) might fail more often than the other jobs, and since we can trigger a limited amount of Cirrus-CI jobs at a time anyway (due to the restrictions in the free tier of Cirrus). Thus these jobs are rather added as convenience for contributors who would like to run the NetBSD/OpenBSD tests without the need of downloading and installing the corresponding VM images on their local machines. Message-Id: <20211209103124.121942-1-thuth@redhat.com> Signed-off-by: Thomas Huth --- .gitlab-ci.d/cirrus.yml | 35 +++++++++++++++++++++++++++++++ .gitlab-ci.d/cirrus/kvm-build.yml | 31 +++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 .gitlab-ci.d/cirrus/kvm-build.yml diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml index d273a9e713..19e6c21401 100644 --- a/.gitlab-ci.d/cirrus.yml +++ b/.gitlab-ci.d/cirrus.yml @@ -89,3 +89,38 @@ x64-macos-11-base-build: PATH_EXTRA: /usr/local/opt/ccache/libexec:/usr/local/opt/gettext/bin PKG_CONFIG_PATH: /usr/local/opt/curl/lib/pkgconfig:/usr/local/opt/ncurses/lib/pkgconfig:/usr/local/opt/readline/lib/pkgconfig TEST_TARGETS: check-unit check-block check-qapi-schema check-softfloat check-qtest-x86_64 + + +# The following jobs run VM-based tests via KVM on a Linux-based Cirrus-CI job +.cirrus_kvm_job: + stage: build + image: registry.gitlab.com/libvirt/libvirt-ci/cirrus-run:master + needs: [] + timeout: 80m + allow_failure: true + script: + - sed -e "s|[@]CI_REPOSITORY_URL@|$CI_REPOSITORY_URL|g" + -e "s|[@]CI_COMMIT_REF_NAME@|$CI_COMMIT_REF_NAME|g" + -e "s|[@]CI_COMMIT_SHA@|$CI_COMMIT_SHA|g" + -e "s|[@]NAME@|$NAME|g" + -e "s|[@]CONFIGURE_ARGS@|$CONFIGURE_ARGS|g" + -e "s|[@]TEST_TARGETS@|$TEST_TARGETS|g" + <.gitlab-ci.d/cirrus/kvm-build.yml >.gitlab-ci.d/cirrus/$NAME.yml + - cat .gitlab-ci.d/cirrus/$NAME.yml + - cirrus-run -v --show-build-log always .gitlab-ci.d/cirrus/$NAME.yml + rules: + - when: manual + +x86-netbsd: + extends: .cirrus_kvm_job + variables: + NAME: netbsd + CONFIGURE_ARGS: --target-list=x86_64-softmmu,ppc64-softmmu,aarch64-softmmu + TEST_TARGETS: check + +x86-openbsd: + extends: .cirrus_kvm_job + variables: + NAME: openbsd + CONFIGURE_ARGS: --target-list=i386-softmmu,riscv64-softmmu,mips64-softmmu + TEST_TARGETS: check diff --git a/.gitlab-ci.d/cirrus/kvm-build.yml b/.gitlab-ci.d/cirrus/kvm-build.yml new file mode 100644 index 0000000000..4334fabf39 --- /dev/null +++ b/.gitlab-ci.d/cirrus/kvm-build.yml @@ -0,0 +1,31 @@ +container: + image: fedora:35 + cpu: 4 + memory: 8Gb + kvm: true + +env: + CIRRUS_CLONE_DEPTH: 1 + CI_REPOSITORY_URL: "@CI_REPOSITORY_URL@" + CI_COMMIT_REF_NAME: "@CI_COMMIT_REF_NAME@" + CI_COMMIT_SHA: "@CI_COMMIT_SHA@" + +@NAME@_task: + @NAME@_vm_cache: + folder: $HOME/.cache/qemu-vm + install_script: + - dnf update -y + - dnf install -y git make openssh-clients qemu-img qemu-system-x86 wget + clone_script: + - git clone --depth 100 "$CI_REPOSITORY_URL" . + - git fetch origin "$CI_COMMIT_REF_NAME" + - git reset --hard "$CI_COMMIT_SHA" + build_script: + - if [ -f $HOME/.cache/qemu-vm/images/@NAME@.img ]; then + make vm-build-@NAME@ J=$(getconf _NPROCESSORS_ONLN) + EXTRA_CONFIGURE_OPTS="@CONFIGURE_ARGS@" + BUILD_TARGET="@TEST_TARGETS@" ; + else + make vm-build-@NAME@ J=$(getconf _NPROCESSORS_ONLN) BUILD_TARGET=help + EXTRA_CONFIGURE_OPTS="--disable-system --disable-user --disable-tools" ; + fi From 7b140d23598650326b2bdefbf2b134eacf995d31 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Sat, 27 Nov 2021 08:29:07 +0100 Subject: [PATCH 115/421] virtio-iommu: Remove set_config callback The spec says "the driver must not write to device configuration fields". So remove the set_config() callback which anyway did not do anything. Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker Message-Id: <20211127072910.1261824-2-eric.auger@redhat.com> Signed-off-by: Thomas Huth --- hw/virtio/trace-events | 1 - hw/virtio/virtio-iommu.c | 14 -------------- 2 files changed, 15 deletions(-) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 650e521e35..54bd7da00c 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -92,7 +92,6 @@ virtio_iommu_device_reset(void) "reset!" virtio_iommu_get_features(uint64_t features) "device supports features=0x%"PRIx64 virtio_iommu_device_status(uint8_t status) "driver status = %d" virtio_iommu_get_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_range, uint32_t probe_size) "page_size_mask=0x%"PRIx64" start=0x%"PRIx64" end=0x%"PRIx64" domain_range=%d probe_size=0x%x" -virtio_iommu_set_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_range, uint32_t probe_size) "page_size_mask=0x%"PRIx64" start=0x%"PRIx64" end=0x%"PRIx64" domain_bits=%d probe_size=0x%x" virtio_iommu_attach(uint32_t domain_id, uint32_t ep_id) "domain=%d endpoint=%d" virtio_iommu_detach(uint32_t domain_id, uint32_t ep_id) "domain=%d endpoint=%d" virtio_iommu_map(uint32_t domain_id, uint64_t virt_start, uint64_t virt_end, uint64_t phys_start, uint32_t flags) "domain=%d virt_start=0x%"PRIx64" virt_end=0x%"PRIx64 " phys_start=0x%"PRIx64" flags=%d" diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 1b23e8e18c..645c0aa399 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -832,19 +832,6 @@ static void virtio_iommu_get_config(VirtIODevice *vdev, uint8_t *config_data) memcpy(config_data, &dev->config, sizeof(struct virtio_iommu_config)); } -static void virtio_iommu_set_config(VirtIODevice *vdev, - const uint8_t *config_data) -{ - struct virtio_iommu_config config; - - memcpy(&config, config_data, sizeof(struct virtio_iommu_config)); - trace_virtio_iommu_set_config(config.page_size_mask, - config.input_range.start, - config.input_range.end, - config.domain_range.end, - config.probe_size); -} - static uint64_t virtio_iommu_get_features(VirtIODevice *vdev, uint64_t f, Error **errp) { @@ -1185,7 +1172,6 @@ static void virtio_iommu_class_init(ObjectClass *klass, void *data) vdc->unrealize = virtio_iommu_device_unrealize; vdc->reset = virtio_iommu_device_reset; vdc->get_config = virtio_iommu_get_config; - vdc->set_config = virtio_iommu_set_config; vdc->get_features = virtio_iommu_get_features; vdc->set_status = virtio_iommu_set_status; vdc->vmsd = &vmstate_virtio_iommu_device; From 3a411b2d9660234c8b6855d1b2861085a4ee5943 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Sat, 27 Nov 2021 08:29:08 +0100 Subject: [PATCH 116/421] virtio-iommu: Fix endianness in get_config Endianess is not properly handled when populating the returned config. Use the cpu_to_le* primitives for each separate field. Also, while at it, trace the domain range start. Reported-by: Thomas Huth Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker Message-Id: <20211127072910.1261824-3-eric.auger@redhat.com> Signed-off-by: Thomas Huth --- hw/virtio/trace-events | 2 +- hw/virtio/virtio-iommu.c | 22 +++++++++++++++------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 54bd7da00c..f7ad6be5fb 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -91,7 +91,7 @@ virtio_mmio_setting_irq(int level) "virtio_mmio setting IRQ %d" virtio_iommu_device_reset(void) "reset!" virtio_iommu_get_features(uint64_t features) "device supports features=0x%"PRIx64 virtio_iommu_device_status(uint8_t status) "driver status = %d" -virtio_iommu_get_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_range, uint32_t probe_size) "page_size_mask=0x%"PRIx64" start=0x%"PRIx64" end=0x%"PRIx64" domain_range=%d probe_size=0x%x" +virtio_iommu_get_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_start, uint32_t domain_end, uint32_t probe_size) "page_size_mask=0x%"PRIx64" input range start=0x%"PRIx64" input range end=0x%"PRIx64" domain range start=%d domain range end=%d probe_size=0x%x" virtio_iommu_attach(uint32_t domain_id, uint32_t ep_id) "domain=%d endpoint=%d" virtio_iommu_detach(uint32_t domain_id, uint32_t ep_id) "domain=%d endpoint=%d" virtio_iommu_map(uint32_t domain_id, uint64_t virt_start, uint64_t virt_end, uint64_t phys_start, uint32_t flags) "domain=%d virt_start=0x%"PRIx64" virt_end=0x%"PRIx64 " phys_start=0x%"PRIx64" flags=%d" diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 645c0aa399..30ee09187b 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -822,14 +822,22 @@ unlock: static void virtio_iommu_get_config(VirtIODevice *vdev, uint8_t *config_data) { VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev); - struct virtio_iommu_config *config = &dev->config; + struct virtio_iommu_config *dev_config = &dev->config; + struct virtio_iommu_config *out_config = (void *)config_data; - trace_virtio_iommu_get_config(config->page_size_mask, - config->input_range.start, - config->input_range.end, - config->domain_range.end, - config->probe_size); - memcpy(config_data, &dev->config, sizeof(struct virtio_iommu_config)); + out_config->page_size_mask = cpu_to_le64(dev_config->page_size_mask); + out_config->input_range.start = cpu_to_le64(dev_config->input_range.start); + out_config->input_range.end = cpu_to_le64(dev_config->input_range.end); + out_config->domain_range.start = cpu_to_le32(dev_config->domain_range.start); + out_config->domain_range.end = cpu_to_le32(dev_config->domain_range.end); + out_config->probe_size = cpu_to_le32(dev_config->probe_size); + + trace_virtio_iommu_get_config(dev_config->page_size_mask, + dev_config->input_range.start, + dev_config->input_range.end, + dev_config->domain_range.start, + dev_config->domain_range.end, + dev_config->probe_size); } static uint64_t virtio_iommu_get_features(VirtIODevice *vdev, uint64_t f, From 6b77ae0531d1a70a87c08408f6c9cd3389439686 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Sat, 27 Nov 2021 08:29:09 +0100 Subject: [PATCH 117/421] virtio-iommu: Fix the domain_range end in old times the domain range was defined by a domain_bits le32. This was then converted into a domain_range struct. During the upgrade the original value of '32' (bits) has been kept while the end field now is the max value of the domain id (UINT32_MAX). Fix that and also use UINT64_MAX for the input_range.end. Reported-by: Jean-Philippe Brucker Signed-off-by: Eric Auger Reviewed-by: Jean-Philippe Brucker Message-Id: <20211127072910.1261824-4-eric.auger@redhat.com> Signed-off-by: Thomas Huth --- hw/virtio/virtio-iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 30ee09187b..aa9c16a17b 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -978,8 +978,8 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) s->event_vq = virtio_add_queue(vdev, VIOMMU_DEFAULT_QUEUE_SIZE, NULL); s->config.page_size_mask = TARGET_PAGE_MASK; - s->config.input_range.end = -1UL; - s->config.domain_range.end = 32; + s->config.input_range.end = UINT64_MAX; + s->config.domain_range.end = UINT32_MAX; s->config.probe_size = VIOMMU_PROBE_SIZE; virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX); From becf88730b86c94137cad20c98ef3b8d24559b9b Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Sat, 27 Nov 2021 08:29:10 +0100 Subject: [PATCH 118/421] tests: qtest: Add virtio-iommu test Add the framework to test the virtio-iommu-pci device and tests exercising the attach/detach, map/unmap API. Signed-off-by: Eric Auger Tested-by: Jean-Philippe Brucker Reviewed-by: Jean-Philippe Brucker Acked-by: Thomas Huth Message-Id: <20211127072910.1261824-5-eric.auger@redhat.com> Signed-off-by: Thomas Huth --- tests/qtest/libqos/meson.build | 1 + tests/qtest/libqos/virtio-iommu.c | 126 ++++++++++++ tests/qtest/libqos/virtio-iommu.h | 40 ++++ tests/qtest/meson.build | 1 + tests/qtest/virtio-iommu-test.c | 326 ++++++++++++++++++++++++++++++ 5 files changed, 494 insertions(+) create mode 100644 tests/qtest/libqos/virtio-iommu.c create mode 100644 tests/qtest/libqos/virtio-iommu.h create mode 100644 tests/qtest/virtio-iommu-test.c diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build index 4af1f04787..e988d15791 100644 --- a/tests/qtest/libqos/meson.build +++ b/tests/qtest/libqos/meson.build @@ -41,6 +41,7 @@ libqos_srcs = files('../libqtest.c', 'virtio-rng.c', 'virtio-scsi.c', 'virtio-serial.c', + 'virtio-iommu.c', # qgraph machines: 'aarch64-xlnx-zcu102-machine.c', diff --git a/tests/qtest/libqos/virtio-iommu.c b/tests/qtest/libqos/virtio-iommu.c new file mode 100644 index 0000000000..18cba4ca36 --- /dev/null +++ b/tests/qtest/libqos/virtio-iommu.c @@ -0,0 +1,126 @@ +/* + * libqos driver virtio-iommu-pci framework + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at your + * option) any later version. See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/module.h" +#include "qgraph.h" +#include "virtio-iommu.h" +#include "hw/virtio/virtio-iommu.h" + +static QGuestAllocator *alloc; + +/* virtio-iommu-device */ +static void *qvirtio_iommu_get_driver(QVirtioIOMMU *v_iommu, + const char *interface) +{ + if (!g_strcmp0(interface, "virtio-iommu")) { + return v_iommu; + } + if (!g_strcmp0(interface, "virtio")) { + return v_iommu->vdev; + } + + fprintf(stderr, "%s not present in virtio-iommu-device\n", interface); + g_assert_not_reached(); +} + +static void virtio_iommu_cleanup(QVirtioIOMMU *interface) +{ + qvirtqueue_cleanup(interface->vdev->bus, interface->vq, alloc); +} + +static void virtio_iommu_setup(QVirtioIOMMU *interface) +{ + QVirtioDevice *vdev = interface->vdev; + uint64_t features; + + features = qvirtio_get_features(vdev); + features &= ~(QVIRTIO_F_BAD_FEATURE | + (1ull << VIRTIO_RING_F_INDIRECT_DESC) | + (1ull << VIRTIO_RING_F_EVENT_IDX) | + (1ull << VIRTIO_IOMMU_F_BYPASS)); + qvirtio_set_features(vdev, features); + interface->vq = qvirtqueue_setup(interface->vdev, alloc, 0); + qvirtio_set_driver_ok(interface->vdev); +} + +/* virtio-iommu-pci */ +static void *qvirtio_iommu_pci_get_driver(void *object, const char *interface) +{ + QVirtioIOMMUPCI *v_iommu = object; + if (!g_strcmp0(interface, "pci-device")) { + return v_iommu->pci_vdev.pdev; + } + return qvirtio_iommu_get_driver(&v_iommu->iommu, interface); +} + +static void qvirtio_iommu_pci_destructor(QOSGraphObject *obj) +{ + QVirtioIOMMUPCI *iommu_pci = (QVirtioIOMMUPCI *) obj; + QVirtioIOMMU *interface = &iommu_pci->iommu; + QOSGraphObject *pci_vobj = &iommu_pci->pci_vdev.obj; + + virtio_iommu_cleanup(interface); + qvirtio_pci_destructor(pci_vobj); +} + +static void qvirtio_iommu_pci_start_hw(QOSGraphObject *obj) +{ + QVirtioIOMMUPCI *iommu_pci = (QVirtioIOMMUPCI *) obj; + QVirtioIOMMU *interface = &iommu_pci->iommu; + QOSGraphObject *pci_vobj = &iommu_pci->pci_vdev.obj; + + qvirtio_pci_start_hw(pci_vobj); + virtio_iommu_setup(interface); +} + + +static void *virtio_iommu_pci_create(void *pci_bus, QGuestAllocator *t_alloc, + void *addr) +{ + QVirtioIOMMUPCI *virtio_rpci = g_new0(QVirtioIOMMUPCI, 1); + QVirtioIOMMU *interface = &virtio_rpci->iommu; + QOSGraphObject *obj = &virtio_rpci->pci_vdev.obj; + + virtio_pci_init(&virtio_rpci->pci_vdev, pci_bus, addr); + interface->vdev = &virtio_rpci->pci_vdev.vdev; + alloc = t_alloc; + + obj->get_driver = qvirtio_iommu_pci_get_driver; + obj->start_hw = qvirtio_iommu_pci_start_hw; + obj->destructor = qvirtio_iommu_pci_destructor; + + return obj; +} + +static void virtio_iommu_register_nodes(void) +{ + QPCIAddress addr = { + .devfn = QPCI_DEVFN(4, 0), + }; + + QOSGraphEdgeOptions opts = { + .extra_device_opts = "addr=04.0", + }; + + /* virtio-iommu-pci */ + add_qpci_address(&opts, &addr); + qos_node_create_driver("virtio-iommu-pci", virtio_iommu_pci_create); + qos_node_consumes("virtio-iommu-pci", "pci-bus", &opts); + qos_node_produces("virtio-iommu-pci", "pci-device"); + qos_node_produces("virtio-iommu-pci", "virtio"); + qos_node_produces("virtio-iommu-pci", "virtio-iommu"); +} + +libqos_init(virtio_iommu_register_nodes); diff --git a/tests/qtest/libqos/virtio-iommu.h b/tests/qtest/libqos/virtio-iommu.h new file mode 100644 index 0000000000..d753761958 --- /dev/null +++ b/tests/qtest/libqos/virtio-iommu.h @@ -0,0 +1,40 @@ +/* + * libqos driver virtio-iommu-pci framework + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at your + * option) any later version. See the COPYING file in the top-level directory. + * + */ + +#ifndef TESTS_LIBQOS_VIRTIO_IOMMU_H +#define TESTS_LIBQOS_VIRTIO_IOMMU_H + +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" + +typedef struct QVirtioIOMMU QVirtioIOMMU; +typedef struct QVirtioIOMMUPCI QVirtioIOMMUPCI; +typedef struct QVirtioIOMMUDevice QVirtioIOMMUDevice; + +struct QVirtioIOMMU { + QVirtioDevice *vdev; + QVirtQueue *vq; +}; + +struct QVirtioIOMMUPCI { + QVirtioPCIDevice pci_vdev; + QVirtioIOMMU iommu; +}; + +struct QVirtioIOMMUDevice { + QOSGraphObject obj; + QVirtioIOMMU iommu; +}; + +#endif diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 9ff3eaf3d0..acc7de5067 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -234,6 +234,7 @@ qos_test_ss.add( 'virtio-rng-test.c', 'virtio-scsi-test.c', 'virtio-serial-test.c', + 'virtio-iommu-test.c', 'vmxnet3-test.c', ) if have_virtfs diff --git a/tests/qtest/virtio-iommu-test.c b/tests/qtest/virtio-iommu-test.c new file mode 100644 index 0000000000..47e68388a0 --- /dev/null +++ b/tests/qtest/virtio-iommu-test.c @@ -0,0 +1,326 @@ +/* + * QTest testcase for VirtIO IOMMU + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at your + * option) any later version. See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "qemu/module.h" +#include "libqos/qgraph.h" +#include "libqos/virtio-iommu.h" +#include "hw/virtio/virtio-iommu.h" + +#define PCI_SLOT_HP 0x06 +#define QVIRTIO_IOMMU_TIMEOUT_US (30 * 1000 * 1000) + +static QGuestAllocator *alloc; + +static void pci_config(void *obj, void *data, QGuestAllocator *t_alloc) +{ + QVirtioIOMMU *v_iommu = obj; + QVirtioDevice *dev = v_iommu->vdev; + uint64_t input_range_start = qvirtio_config_readq(dev, 8); + uint64_t input_range_end = qvirtio_config_readq(dev, 16); + uint32_t domain_range_start = qvirtio_config_readl(dev, 24); + uint32_t domain_range_end = qvirtio_config_readl(dev, 28); + + g_assert_cmpint(input_range_start, ==, 0); + g_assert_cmphex(input_range_end, ==, UINT64_MAX); + g_assert_cmpint(domain_range_start, ==, 0); + g_assert_cmpint(domain_range_end, ==, UINT32_MAX); +} + +static int read_tail_status(struct virtio_iommu_req_tail *buffer) +{ + int i; + + for (i = 0; i < 3; i++) { + g_assert_cmpint(buffer->reserved[i], ==, 0); + } + return buffer->status; +} + +/** + * send_attach_detach - Send an attach/detach command to the device + * @type: VIRTIO_IOMMU_T_ATTACH/VIRTIO_IOMMU_T_DETACH + * @domain: domain the endpoint is attached to + * @ep: endpoint + */ +static int send_attach_detach(QTestState *qts, QVirtioIOMMU *v_iommu, + uint8_t type, uint32_t domain, uint32_t ep) +{ + QVirtioDevice *dev = v_iommu->vdev; + QVirtQueue *vq = v_iommu->vq; + uint64_t ro_addr, wr_addr; + uint32_t free_head; + struct virtio_iommu_req_attach req = {}; /* same layout as detach */ + size_t ro_size = sizeof(req) - sizeof(struct virtio_iommu_req_tail); + size_t wr_size = sizeof(struct virtio_iommu_req_tail); + struct virtio_iommu_req_tail buffer; + int ret; + + req.head.type = type; + req.domain = cpu_to_le32(domain); + req.endpoint = cpu_to_le32(ep); + + ro_addr = guest_alloc(alloc, ro_size); + wr_addr = guest_alloc(alloc, wr_size); + + qtest_memwrite(qts, ro_addr, &req, ro_size); + free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); + qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); + qvirtqueue_kick(qts, dev, vq, free_head); + qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, + QVIRTIO_IOMMU_TIMEOUT_US); + qtest_memread(qts, wr_addr, &buffer, wr_size); + ret = read_tail_status(&buffer); + guest_free(alloc, ro_addr); + guest_free(alloc, wr_addr); + return ret; +} + +/** + * send_map - Send a map command to the device + * @domain: domain the new mapping is attached to + * @virt_start: iova start + * @virt_end: iova end + * @phys_start: base physical address + * @flags: mapping flags + */ +static int send_map(QTestState *qts, QVirtioIOMMU *v_iommu, + uint32_t domain, uint64_t virt_start, uint64_t virt_end, + uint64_t phys_start, uint32_t flags) +{ + QVirtioDevice *dev = v_iommu->vdev; + QVirtQueue *vq = v_iommu->vq; + uint64_t ro_addr, wr_addr; + uint32_t free_head; + struct virtio_iommu_req_map req; + size_t ro_size = sizeof(req) - sizeof(struct virtio_iommu_req_tail); + size_t wr_size = sizeof(struct virtio_iommu_req_tail); + struct virtio_iommu_req_tail buffer; + int ret; + + req.head.type = VIRTIO_IOMMU_T_MAP; + req.domain = cpu_to_le32(domain); + req.virt_start = cpu_to_le64(virt_start); + req.virt_end = cpu_to_le64(virt_end); + req.phys_start = cpu_to_le64(phys_start); + req.flags = cpu_to_le32(flags); + + ro_addr = guest_alloc(alloc, ro_size); + wr_addr = guest_alloc(alloc, wr_size); + + qtest_memwrite(qts, ro_addr, &req, ro_size); + free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); + qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); + qvirtqueue_kick(qts, dev, vq, free_head); + qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, + QVIRTIO_IOMMU_TIMEOUT_US); + qtest_memread(qts, wr_addr, &buffer, wr_size); + ret = read_tail_status(&buffer); + guest_free(alloc, ro_addr); + guest_free(alloc, wr_addr); + return ret; +} + +/** + * send_unmap - Send an unmap command to the device + * @domain: domain the new binding is attached to + * @virt_start: iova start + * @virt_end: iova end + */ +static int send_unmap(QTestState *qts, QVirtioIOMMU *v_iommu, + uint32_t domain, uint64_t virt_start, uint64_t virt_end) +{ + QVirtioDevice *dev = v_iommu->vdev; + QVirtQueue *vq = v_iommu->vq; + uint64_t ro_addr, wr_addr; + uint32_t free_head; + struct virtio_iommu_req_unmap req; + size_t ro_size = sizeof(req) - sizeof(struct virtio_iommu_req_tail); + size_t wr_size = sizeof(struct virtio_iommu_req_tail); + struct virtio_iommu_req_tail buffer; + int ret; + + req.head.type = VIRTIO_IOMMU_T_UNMAP; + req.domain = cpu_to_le32(domain); + req.virt_start = cpu_to_le64(virt_start); + req.virt_end = cpu_to_le64(virt_end); + + ro_addr = guest_alloc(alloc, ro_size); + wr_addr = guest_alloc(alloc, wr_size); + + qtest_memwrite(qts, ro_addr, &req, ro_size); + free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); + qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); + qvirtqueue_kick(qts, dev, vq, free_head); + qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, + QVIRTIO_IOMMU_TIMEOUT_US); + qtest_memread(qts, wr_addr, &buffer, wr_size); + ret = read_tail_status(&buffer); + guest_free(alloc, ro_addr); + guest_free(alloc, wr_addr); + return ret; +} + +static void test_attach_detach(void *obj, void *data, QGuestAllocator *t_alloc) +{ + QVirtioIOMMU *v_iommu = obj; + QTestState *qts = global_qtest; + int ret; + + alloc = t_alloc; + + /* type, domain, ep */ + + /* attach ep0 to domain 0 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 0, 0); + g_assert_cmpint(ret, ==, 0); + + /* attach a non existing device */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 0, 444); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + /* detach a non existing device (1) */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 0, 1); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + /* move ep0 from domain 0 to domain 1 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + + /* detach ep0 from domain 0 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 0, 0); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_INVAL); + + /* detach ep0 from domain 1 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 0x0, 0xFFF, 0xa1000, + VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 0x2000, 0x2FFF, 0xb1000, + VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 1, 0); + g_assert_cmpint(ret, ==, 0); +} + +/* Test map/unmap scenari documented in the spec */ +static void test_map_unmap(void *obj, void *data, QGuestAllocator *t_alloc) +{ + QVirtioIOMMU *v_iommu = obj; + QTestState *qts = global_qtest; + int ret; + + alloc = t_alloc; + + /* attach ep0 to domain 1 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + + ret = send_map(qts, v_iommu, 0, 0, 0xFFF, 0xa1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + /* domain, virt start, virt end, phys start, flags */ + ret = send_map(qts, v_iommu, 1, 0x0, 0xFFF, 0xa1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + + /* send a new mapping overlapping the previous one */ + ret = send_map(qts, v_iommu, 1, 0, 0xFFFF, 0xb1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_INVAL); + + ret = send_unmap(qts, v_iommu, 4, 0x10, 0xFFF); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + ret = send_unmap(qts, v_iommu, 1, 0x10, 0xFFF); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_RANGE); + + ret = send_unmap(qts, v_iommu, 1, 0, 0x1000); + g_assert_cmpint(ret, ==, 0); /* unmap everything */ + + /* Spec example sequence */ + + /* 1 */ + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, 0); /* doesn't unmap anything */ + + /* 2 */ + ret = send_map(qts, v_iommu, 1, 0, 9, 0xa1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 9); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,9] */ + + /* 3 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xb1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 5, 9, 0xb2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 9); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] and [5,9] */ + + /* 4 */ + ret = send_map(qts, v_iommu, 1, 0, 9, 0xc1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_RANGE); /* doesn't unmap anything */ + + ret = send_unmap(qts, v_iommu, 1, 0, 10); + g_assert_cmpint(ret, ==, 0); + + /* 5 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xd1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 5, 9, 0xd2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] */ + + ret = send_unmap(qts, v_iommu, 1, 5, 9); + g_assert_cmpint(ret, ==, 0); + + /* 6 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xe2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 9); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] */ + + /* 7 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xf2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 10, 14, 0xf3000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 14); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] and [10,14] */ + + ret = send_map(qts, v_iommu, 1, 10, 14, 0xf3000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 0, 4, 0xf2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, 0); /* only unmaps [0,4] */ + ret = send_map(qts, v_iommu, 1, 10, 14, 0xf3000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_INVAL); /* 10-14 still is mapped */ +} + +static void register_virtio_iommu_test(void) +{ + qos_add_test("config", "virtio-iommu", pci_config, NULL); + qos_add_test("attach_detach", "virtio-iommu", test_attach_detach, NULL); + qos_add_test("map_unmap", "virtio-iommu", test_map_unmap, NULL); +} + +libqos_init(register_virtio_iommu_test); From 7876cba8fc0cab9a4c803a30f427d4b20b95a868 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Mon, 15 Nov 2021 15:06:23 +0100 Subject: [PATCH 119/421] gitlab-ci: Test compilation on Windows with MSYS2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Gitlab also provides runners with Windows, we can use them to test compilation with MSYS2, in both, 64-bit and 32-bit. However, it takes quite a long time to set up the VM, so to stay in a reasonable time frame, we can only compile and check one target here. Message-Id: <20211115140623.104116-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- .gitlab-ci.d/qemu-project.yml | 1 + .gitlab-ci.d/windows.yml | 98 +++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 .gitlab-ci.d/windows.yml diff --git a/.gitlab-ci.d/qemu-project.yml b/.gitlab-ci.d/qemu-project.yml index b3d79bc429..871262fe0e 100644 --- a/.gitlab-ci.d/qemu-project.yml +++ b/.gitlab-ci.d/qemu-project.yml @@ -11,3 +11,4 @@ include: - local: '/.gitlab-ci.d/static_checks.yml' - local: '/.gitlab-ci.d/custom-runners.yml' - local: '/.gitlab-ci.d/cirrus.yml' + - local: '/.gitlab-ci.d/windows.yml' diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml new file mode 100644 index 0000000000..309f7e7fb8 --- /dev/null +++ b/.gitlab-ci.d/windows.yml @@ -0,0 +1,98 @@ +.shared_msys2_builder: + tags: + - shared-windows + - windows + - windows-1809 + cache: + key: "${CI_JOB_NAME}-cache" + paths: + - ${CI_PROJECT_DIR}/msys64/var/cache + needs: [] + stage: build + timeout: 70m + before_script: + - If ( !(Test-Path -Path msys64\var\cache ) ) { + mkdir msys64\var\cache + } + - If ( !(Test-Path -Path msys64\var\cache\msys2.exe ) ) { + Invoke-WebRequest + "https://github.com/msys2/msys2-installer/releases/download/2021-07-25/msys2-base-x86_64-20210725.sfx.exe" + -outfile "msys64\var\cache\msys2.exe" + } + - msys64\var\cache\msys2.exe -y + - ((Get-Content -path .\msys64\etc\\post-install\\07-pacman-key.post -Raw) + -replace '--refresh-keys', '--version') | + Set-Content -Path ${CI_PROJECT_DIR}\msys64\etc\\post-install\\07-pacman-key.post + - .\msys64\usr\bin\bash -lc "sed -i 's/^CheckSpace/#CheckSpace/g' /etc/pacman.conf" + - .\msys64\usr\bin\bash -lc 'pacman --noconfirm -Syuu' # Core update + - .\msys64\usr\bin\bash -lc 'pacman --noconfirm -Syuu' # Normal update + - taskkill /F /FI "MODULES eq msys-2.0.dll" + +msys2-64bit: + extends: .shared_msys2_builder + script: + - .\msys64\usr\bin\bash -lc "pacman -Sy --noconfirm --needed + diffutils git grep make sed + mingw-w64-x86_64-capstone + mingw-w64-x86_64-curl + mingw-w64-x86_64-cyrus-sasl + mingw-w64-x86_64-gcc + mingw-w64-x86_64-glib2 + mingw-w64-x86_64-gnutls + mingw-w64-x86_64-libnfs + mingw-w64-x86_64-libpng + mingw-w64-x86_64-libssh + mingw-w64-x86_64-libtasn1 + mingw-w64-x86_64-libusb + mingw-w64-x86_64-libxml2 + mingw-w64-x86_64-nettle + mingw-w64-x86_64-ninja + mingw-w64-x86_64-pixman + mingw-w64-x86_64-pkgconf + mingw-w64-x86_64-python + mingw-w64-x86_64-SDL2 + mingw-w64-x86_64-SDL2_image + mingw-w64-x86_64-snappy + mingw-w64-x86_64-usbredir + mingw-w64-x86_64-zstd " + - $env:CHERE_INVOKING = 'yes' # Preserve the current working directory + - $env:MSYSTEM = 'MINGW64' # Start a 64 bit Mingw environment + - .\msys64\usr\bin\bash -lc './configure --target-list=x86_64-softmmu + --enable-capstone=system' + - .\msys64\usr\bin\bash -lc "sed -i '/^ROMS=/d' build/config-host.mak" + - .\msys64\usr\bin\bash -lc 'make -j2' + - .\msys64\usr\bin\bash -lc 'make check' + +msys2-32bit: + extends: .shared_msys2_builder + script: + - .\msys64\usr\bin\bash -lc "pacman -Sy --noconfirm --needed + diffutils git grep make sed + mingw-w64-i686-capstone + mingw-w64-i686-curl + mingw-w64-i686-cyrus-sasl + mingw-w64-i686-gcc + mingw-w64-i686-glib2 + mingw-w64-i686-gnutls + mingw-w64-i686-gtk3 + mingw-w64-i686-libgcrypt + mingw-w64-i686-libjpeg-turbo + mingw-w64-i686-libssh + mingw-w64-i686-libtasn1 + mingw-w64-i686-libusb + mingw-w64-i686-libxml2 + mingw-w64-i686-lzo2 + mingw-w64-i686-ninja + mingw-w64-i686-pixman + mingw-w64-i686-pkgconf + mingw-w64-i686-python + mingw-w64-i686-snappy + mingw-w64-i686-usbredir " + - $env:CHERE_INVOKING = 'yes' # Preserve the current working directory + - $env:MSYSTEM = 'MINGW32' # Start a 32-bit MinG environment + - mkdir output + - cd output + - ..\msys64\usr\bin\bash -lc "../configure --target-list=ppc64-softmmu + --enable-capstone=system" + - ..\msys64\usr\bin\bash -lc 'make -j2' + - ..\msys64\usr\bin\bash -lc 'make check' From 36aa285f48d55451bb2eb7a2c0f9635a3c2bbe46 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:33:57 +0100 Subject: [PATCH 120/421] hw/sd/ssi-sd: Do not create SD card within controller's realize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ssi_sd_realize() creates an "sd-card" device. This is inappropriate, and marked FIXME. Move it to the boards that create these devices. Prior art: commit eb4f566bbb for device "generic-sdhci", and commit 26c607b86b for device "pl181". The device remains not user-creatable, because its users should (and do) wire up its GPIO chip-select line. Cc: Peter Maydell Cc: Alistair Francis Cc: Bin Meng Cc: Palmer Dabbelt Cc: "Philippe Mathieu-Daudé" Cc: qemu-arm@nongnu.org Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/stellaris.c | 15 ++++++++++++++- hw/riscv/sifive_u.c | 13 ++++++++++++- hw/sd/ssi-sd.c | 29 +---------------------------- 3 files changed, 27 insertions(+), 30 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 78827ace6b..b6c8a5d609 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/sysbus.h" +#include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "hw/arm/boot.h" #include "qemu/timer.h" @@ -1157,6 +1158,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) void *bus; DeviceState *sddev; DeviceState *ssddev; + DriveInfo *dinfo; + DeviceState *carddev; + BlockBackend *blk; /* * Some boards have both an OLED controller and SD card connected to @@ -1221,8 +1225,17 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) * - Make the ssd0323 OLED controller chipselect active-low */ bus = qdev_get_child_bus(dev, "ssi"); - sddev = ssi_create_peripheral(bus, "ssi-sd"); + + dinfo = drive_get(IF_SD, 0, 0); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + carddev = qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_prop_set_bit(carddev, "spi", true); + qdev_realize_and_unref(carddev, + qdev_get_child_bus(sddev, "sd-bus"), + &error_fatal); + ssddev = ssi_create_peripheral(bus, "ssd0323"); gpio_out[GPIO_D][0] = qemu_irq_split( qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 589ae72a59..a4ecadaf12 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -46,6 +46,7 @@ #include "hw/char/serial.h" #include "hw/cpu/cluster.h" #include "hw/misc/unimp.h" +#include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" @@ -536,7 +537,8 @@ static void sifive_u_machine_init(MachineState *machine) uint32_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; - DeviceState *flash_dev, *sd_dev; + BlockBackend *blk; + DeviceState *flash_dev, *sd_dev, *card_dev; qemu_irq flash_cs, sd_cs; /* Initialize SoC */ @@ -686,6 +688,15 @@ static void sifive_u_machine_init(MachineState *machine) sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); + + dinfo = drive_get(IF_SD, 0, 0); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + card_dev = qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); + qdev_prop_set_bit(card_dev, "spi", true); + qdev_realize_and_unref(card_dev, + qdev_get_child_bus(sd_dev, "sd-bus"), + &error_fatal); } static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index e60854eeef..167c03b780 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -368,36 +368,9 @@ static const VMStateDescription vmstate_ssi_sd = { static void ssi_sd_realize(SSIPeripheral *d, Error **errp) { - ERRP_GUARD(); ssi_sd_state *s = SSI_SD(d); - DeviceState *carddev; - DriveInfo *dinfo; qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus"); - - /* Create and plug in the sd card */ - /* FIXME use a qdev drive property instead of drive_get_next() */ - dinfo = drive_get_next(IF_SD); - carddev = qdev_new(TYPE_SD_CARD); - if (dinfo) { - if (!qdev_prop_set_drive_err(carddev, "drive", - blk_by_legacy_dinfo(dinfo), errp)) { - goto fail; - } - } - - if (!object_property_set_bool(OBJECT(carddev), "spi", true, errp)) { - goto fail; - } - - if (!qdev_realize_and_unref(carddev, BUS(&s->sdbus), errp)) { - goto fail; - } - - return; - -fail: - error_prepend(errp, "failed to init SD card: "); } static void ssi_sd_reset(DeviceState *dev) @@ -426,7 +399,7 @@ static void ssi_sd_class_init(ObjectClass *klass, void *data) k->cs_polarity = SSI_CS_LOW; dc->vmsd = &vmstate_ssi_sd; dc->reset = ssi_sd_reset; - /* Reason: init() method uses drive_get_next() */ + /* Reason: GPIO chip-select line should be wired up */ dc->user_creatable = false; } From 64eaa8209597a580c026d4891c072723a38ff0a6 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:33:58 +0100 Subject: [PATCH 121/421] hw: Replace trivial drive_get_next() by drive_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. A number of machines connect just one backend with drive_get_next(). Change them to use drive_get() directly. This makes the (zero) unit number explicit in the code. Cc: Beniamino Galvani Cc: Peter Maydell Cc: Subbaraya Sundeep Cc: Niek Linnenbank Cc: Andrew Baumann Cc: "Philippe Mathieu-Daudé" Cc: Jean-Christophe Dubois Cc: Alistair Francis Cc: Bin Meng Cc: Palmer Dabbelt Cc: Artyom Tarasenko Cc: Mark Cave-Ayland Cc: Michael Tokarev Cc: Laurent Vivier Cc: qemu-arm@nongnu.org Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-3-armbru@redhat.com> --- hw/arm/cubieboard.c | 2 +- hw/arm/integratorcp.c | 2 +- hw/arm/msf2-som.c | 2 +- hw/arm/orangepi.c | 2 +- hw/arm/raspi.c | 2 +- hw/arm/realview.c | 2 +- hw/arm/sabrelite.c | 2 +- hw/misc/sifive_u_otp.c | 4 ++-- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/sparc64/niagara.c | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 294ba5de6e..5e3372a3c7 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -81,7 +81,7 @@ static void cubieboard_init(MachineState *machine) } /* Retrieve SD bus */ - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, 0); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(a10), "sd-bus"); diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 16e8985953..b109ece3ae 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -649,7 +649,7 @@ static void integratorcp_init(MachineState *machine) qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); qdev_connect_gpio_out_named(dev, "card-inserted", 0, qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 396e8b9913..d9f881690e 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -45,7 +45,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) DeviceState *spi_flash; MSF2State *soc; MachineClass *mc = MACHINE_GET_CLASS(machine); - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); qemu_irq cs_line; BusState *spi_bus; MemoryRegion *sysmem = get_system_memory(); diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 0cf9895ce7..e796382236 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -85,7 +85,7 @@ static void orangepi_init(MachineState *machine) qdev_realize(DEVICE(h3), NULL, &error_abort); /* Retrieve SD bus */ - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, 0); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(h3), "sd-bus"); diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 146d35382b..b4dd6c1e99 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -284,7 +284,7 @@ static void raspi_machine_init(MachineState *machine) qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); /* Create and plug in the SD cards */ - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, 0); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); if (bus == NULL) { diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 1c54316ba3..ddc70b54a5 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -237,7 +237,7 @@ static void realview_init(MachineState *machine, qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 553608e583..cce49aa25c 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -76,7 +76,7 @@ static void sabrelite_init(MachineState *machine) if (spi_bus) { DeviceState *flash_dev; qemu_irq cs_line; - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); flash_dev = qdev_new("sst25vf016b"); if (dinfo) { diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 52fdb750c0..6d5f84e6c2 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -209,9 +209,9 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); - dinfo = drive_get_next(IF_PFLASH); + dinfo = drive_get(IF_PFLASH, 0, 0); if (!dinfo) { - dinfo = drive_get_next(IF_NONE); + dinfo = drive_get(IF_NONE, 0, 0); if (dinfo) { warn_report("using \"-drive if=none\" for the OTP is deprecated, " "use \"-drive if=pflash\" instead."); diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 57d779fb55..d1d065efbc 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -458,7 +458,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) target_ulong firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; uint32_t fdt_load_addr; - DriveInfo *dinfo = drive_get_next(IF_SD); + DriveInfo *dinfo = drive_get(IF_SD, 0, 0); /* Sanity check on RAM size */ if (machine->ram_size < mc->default_ram_size) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a4ecadaf12..aa74e67889 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -672,7 +672,7 @@ static void sifive_u_machine_init(MachineState *machine) /* Connect an SPI flash to SPI0 */ flash_dev = qdev_new("is25wp256"); - dinfo = drive_get_next(IF_MTD); + dinfo = drive_get(IF_MTD, 0, 0); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index f3e42d0326..ccad2c43a3 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -98,7 +98,7 @@ static void add_rom_or_fail(const char *file, const hwaddr addr) static void niagara_init(MachineState *machine) { NiagaraBoardState *s = g_new(NiagaraBoardState, 1); - DriveInfo *dinfo = drive_get_next(IF_PFLASH); + DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); MemoryRegion *sysmem = get_system_memory(); /* init CPUs */ From 93d8bc8f5bc20a3108c9c9592d43d0202778f0c5 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:33:59 +0100 Subject: [PATCH 122/421] hw/arm/npcm7xx_boards: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "quanta-gbs-bmc" connects just one backend with drive_get_next(), but with a helper function. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Havard Skinnemoen Cc: Tyrone Ting Cc: Peter Maydell Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-4-armbru@redhat.com> Reviewed-by: Havard Skinnemoen --- hw/arm/npcm7xx_boards.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index dec7d16ae5..d8a49e4e85 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -84,9 +84,9 @@ static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram) &error_abort); } -static void sdhci_attach_drive(SDHCIState *sdhci) +static void sdhci_attach_drive(SDHCIState *sdhci, int unit) { - DriveInfo *di = drive_get_next(IF_SD); + DriveInfo *di = drive_get(IF_SD, 0, unit); BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus"); @@ -374,7 +374,7 @@ static void quanta_gbs_init(MachineState *machine) drive_get(IF_MTD, 0, 0)); quanta_gbs_i2c_init(soc); - sdhci_attach_drive(&soc->mmc.sdhci); + sdhci_attach_drive(&soc->mmc.sdhci, 0); npcm7xx_load_kernel(machine, soc); } From d83c29e98119570880491dacd8dbed9b45a53c5d Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:00 +0100 Subject: [PATCH 123/421] hw/arm/versatilepb hw/arm/vexpress: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. The versatile and vexpress machines ("versatileab", "versatilepb", "vexpress-a9", "vexpress-a15") connect just one or two backends of a type with drive_get_next(). Change them to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Peter Maydell Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-5-armbru@redhat.com> Reviewed-by: Peter Maydell --- hw/arm/versatilepb.c | 4 ++-- hw/arm/vexpress.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 575399c4fc..ecc1f6cf74 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -310,7 +310,7 @@ static void versatile_init(MachineState *machine, int board_id) qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); dev = sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; @@ -322,7 +322,7 @@ static void versatile_init(MachineState *machine, int board_id) } dev = sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 1); if (dinfo) { DeviceState *card; diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 58481c0762..966758cf82 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -625,7 +625,7 @@ static void vexpress_common_init(MachineState *machine) qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); qdev_connect_gpio_out_named(dev, "card-inserted", 0, qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; @@ -657,7 +657,7 @@ static void vexpress_common_init(MachineState *machine) sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); - dinfo = drive_get_next(IF_PFLASH); + dinfo = drive_get(IF_PFLASH, 0, 0); pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", dinfo); if (!pflash0) { @@ -673,7 +673,7 @@ static void vexpress_common_init(MachineState *machine) memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); } - dinfo = drive_get_next(IF_PFLASH); + dinfo = drive_get(IF_PFLASH, 0, 1); if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo)) { error_report("vexpress: error registering flash 1"); From 6b87668b0813b9cb5ec714dcbcd8f128cfc4a3b1 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:01 +0100 Subject: [PATCH 124/421] hw/arm/imx25_pdk: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "imx25-pdk" connects backends with drive_get_next() in a counting loop. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Peter Maydell Cc: Jean-Christophe Dubois Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-6-armbru@redhat.com> Reviewed-by: Peter Maydell --- hw/arm/imx25_pdk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index bd16acd4d9..6dff000163 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -123,7 +123,7 @@ static void imx25_pdk_init(MachineState *machine) DriveInfo *di; BlockBackend *blk; - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, i); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus"); carddev = qdev_new(TYPE_SD_CARD); From 8acf052f7a70df88c01feccd8992eb50afce1b1d Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:02 +0100 Subject: [PATCH 125/421] hw/arm/mcimx6ul-evk: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "mcimx6ul-evk" connects backends with drive_get_next() in a counting loop. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Peter Maydell Cc: Jean-Christophe Dubois Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-7-armbru@redhat.com> Reviewed-by: Peter Maydell --- hw/arm/mcimx6ul-evk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 77fae874b1..28b4886f48 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -52,7 +52,7 @@ static void mcimx6ul_evk_init(MachineState *machine) DriveInfo *di; BlockBackend *blk; - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, i); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); carddev = qdev_new(TYPE_SD_CARD); From 50659fc479977a7576c0cf0589c7fa31dabe0ad9 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:03 +0100 Subject: [PATCH 126/421] hw/arm/mcimx7d-sabre: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "mcimx7d-sabre" connects backends with drive_get_next() in a counting loop. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Peter Maydell Cc: Andrey Smirnov Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-8-armbru@redhat.com> Reviewed-by: Peter Maydell --- hw/arm/mcimx7d-sabre.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 935d4b0f1c..50a5ecde31 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -52,7 +52,7 @@ static void mcimx7d_sabre_init(MachineState *machine) DriveInfo *di; BlockBackend *blk; - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, i); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); carddev = qdev_new(TYPE_SD_CARD); From c29faeda3f7e770e463a58f7b5b34b409dba6c88 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:04 +0100 Subject: [PATCH 127/421] hw/arm/xlnx-versal-virt: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "xlnx-versal-virt" connects backends with drive_get_next() in a counting loop. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Alistair Francis Cc: "Edgar E. Iglesias" Cc: Peter Maydell Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-9-armbru@redhat.com> Acked-by: Edgar E. Iglesias --- hw/arm/xlnx-versal-virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index d2f55e29b6..0c5edc898e 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -669,7 +669,8 @@ static void versal_virt_init(MachineState *machine) /* Plugin SD cards. */ for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { - sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); + sd_plugin_card(&s->soc.pmc.iou.sd[i], + drive_get(IF_SD, 0, i)); } s->binfo.ram_size = machine->ram_size; From 0de89a863292836e6efb0c40c6f9221c89a2033a Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:05 +0100 Subject: [PATCH 128/421] hw/microblaze: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "petalogix-ml605" connects backends with drive_get_next() in a counting loop. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: "Edgar E. Iglesias" Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-10-armbru@redhat.com> Acked-by: Edgar E. Iglesias --- hw/microblaze/petalogix_ml605_mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 159db6cbe2..a24fadddca 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -183,7 +183,7 @@ petalogix_ml605_init(MachineState *machine) spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); for (i = 0; i < NUM_SPI_FLASHES; i++) { - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, i); qemu_irq cs_line; dev = qdev_new("n25q128"); From 672159a97ce7c1ca2b97bfef439d7994f79b1c61 Mon Sep 17 00:00:00 2001 From: "Rao, Lei" Date: Wed, 10 Nov 2021 16:37:36 +0800 Subject: [PATCH 129/421] migration/ram.c: Remove the qemu_mutex_lock in colo_flush_ram_cache. The code to acquire bitmap_mutex is added in the commit of "63268c4970a5f126cc9af75f3ccb8057abef5ec0". There is no need to acquire bitmap_mutex in colo_flush_ram_cache(). This is because the colo_flush_ram_cache only be called on the COLO secondary VM, which is the destination side. On the COLO secondary VM, only the COLO thread will touch the bitmap of ram cache. Signed-off-by: Lei Rao Reviewed-by: Zhang Chen Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- migration/ram.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index 863035d235..2c688f5bbb 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -3918,7 +3918,6 @@ void colo_flush_ram_cache(void) unsigned long offset = 0; memory_global_dirty_log_sync(); - qemu_mutex_lock(&ram_state->bitmap_mutex); WITH_RCU_READ_LOCK_GUARD() { RAMBLOCK_FOREACH_NOT_IGNORED(block) { ramblock_sync_dirty_bitmap(ram_state, block); @@ -3954,7 +3953,6 @@ void colo_flush_ram_cache(void) } } trace_colo_flush_ram_cache_end(); - qemu_mutex_unlock(&ram_state->bitmap_mutex); } /** From 0e0f0479e28c6c1a1d024b2e5200cade479d6901 Mon Sep 17 00:00:00 2001 From: Zhang Chen Date: Thu, 11 Nov 2021 01:41:56 +0800 Subject: [PATCH 130/421] migration/colo: More accurate update checkpoint time Previous operation(like vm_start and replication_start_all) will consume extra time before update the timer, so reduce time in this patch. Signed-off-by: Zhang Chen Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- migration/colo.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/migration/colo.c b/migration/colo.c index 2415325262..c8fadae956 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -530,7 +530,6 @@ static void colo_process_checkpoint(MigrationState *s) { QIOChannelBuffer *bioc; QEMUFile *fb = NULL; - int64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_HOST); Error *local_err = NULL; int ret; @@ -578,8 +577,8 @@ static void colo_process_checkpoint(MigrationState *s) qemu_mutex_unlock_iothread(); trace_colo_vm_state_change("stop", "run"); - timer_mod(s->colo_delay_timer, - current_time + s->parameters.x_checkpoint_delay); + timer_mod(s->colo_delay_timer, qemu_clock_get_ms(QEMU_CLOCK_HOST) + + s->parameters.x_checkpoint_delay); while (s->state == MIGRATION_STATUS_COLO) { if (failover_get_state() != FAILOVER_STATUS_NONE) { From 795969ab1fe6d5a0f524be92e2e1ecd13f1873eb Mon Sep 17 00:00:00 2001 From: "Rao, Lei" Date: Thu, 11 Nov 2021 10:11:33 +0800 Subject: [PATCH 131/421] Fixed a QEMU hang when guest poweroff in COLO mode When the PVM guest poweroff, the COLO thread may wait a semaphore in colo_process_checkpoint().So, we should wake up the COLO thread before migration shutdown. Signed-off-by: Lei Rao Reviewed-by: Zhang Chen Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- include/migration/colo.h | 1 + migration/colo.c | 20 ++++++++++++++++++++ migration/migration.c | 6 ++++++ 3 files changed, 27 insertions(+) diff --git a/include/migration/colo.h b/include/migration/colo.h index 768e1f04c3..5fbe1a6d5d 100644 --- a/include/migration/colo.h +++ b/include/migration/colo.h @@ -37,4 +37,5 @@ COLOMode get_colo_mode(void); void colo_do_failover(void); void colo_checkpoint_notify(void *opaque); +void colo_shutdown(void); #endif diff --git a/migration/colo.c b/migration/colo.c index c8fadae956..2a85504966 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -819,6 +819,26 @@ static void colo_wait_handle_message(MigrationIncomingState *mis, } } +void colo_shutdown(void) +{ + MigrationIncomingState *mis = NULL; + MigrationState *s = NULL; + + switch (get_colo_mode()) { + case COLO_MODE_PRIMARY: + s = migrate_get_current(); + qemu_event_set(&s->colo_checkpoint_event); + qemu_sem_post(&s->colo_exit_sem); + break; + case COLO_MODE_SECONDARY: + mis = migration_incoming_get_current(); + qemu_sem_post(&mis->colo_incoming_sem); + break; + default: + break; + } +} + void *colo_process_incoming_thread(void *opaque) { MigrationIncomingState *mis = opaque; diff --git a/migration/migration.c b/migration/migration.c index abaf6f9e3d..c0ab86e9a5 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -225,6 +225,12 @@ void migration_cancel(const Error *error) void migration_shutdown(void) { + /* + * When the QEMU main thread exit, the COLO thread + * may wait a semaphore. So, we should wakeup the + * COLO thread before migration shutdown. + */ + colo_shutdown(); /* * Cancel the current migration - that will (eventually) * stop the migration using this structure From 751fe4c608b6e83ea3c19fff2bdbea19645c398f Mon Sep 17 00:00:00 2001 From: Zhang Chen Date: Wed, 17 Nov 2021 16:30:02 +0800 Subject: [PATCH 132/421] migration/colo: Optimize COLO primary node start code path Optimize COLO primary start path from: MIGRATION_STATUS_XXX --> MIGRATION_STATUS_ACTIVE --> MIGRATION_STATUS_COLO --> MIGRATION_STATUS_COMPLETED To: MIGRATION_STATUS_XXX --> MIGRATION_STATUS_COLO --> MIGRATION_STATUS_COMPLETED No need to start primary COLO through "MIGRATION_STATUS_ACTIVE". Signed-off-by: Zhang Chen Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- migration/colo.c | 2 -- migration/migration.c | 13 +++++++------ 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/migration/colo.c b/migration/colo.c index 2a85504966..4a772afe78 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -666,8 +666,6 @@ void migrate_start_colo_process(MigrationState *s) colo_checkpoint_notify, s); qemu_sem_init(&s->colo_exit_sem, 0); - migrate_set_state(&s->state, MIGRATION_STATUS_ACTIVE, - MIGRATION_STATUS_COLO); colo_process_checkpoint(s); qemu_mutex_lock_iothread(); } diff --git a/migration/migration.c b/migration/migration.c index c0ab86e9a5..2c1edb2cb9 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -3613,12 +3613,7 @@ static void migration_iteration_finish(MigrationState *s) migration_calculate_complete(s); runstate_set(RUN_STATE_POSTMIGRATE); break; - - case MIGRATION_STATUS_ACTIVE: - /* - * We should really assert here, but since it's during - * migration, let's try to reduce the usage of assertions. - */ + case MIGRATION_STATUS_COLO: if (!migrate_colo_enabled()) { error_report("%s: critical error: calling COLO code without " "COLO enabled", __func__); @@ -3628,6 +3623,12 @@ static void migration_iteration_finish(MigrationState *s) * Fixme: we will run VM in COLO no matter its old running state. * After exited COLO, we will keep running. */ + /* Fallthrough */ + case MIGRATION_STATUS_ACTIVE: + /* + * We should really assert here, but since it's during + * migration, let's try to reduce the usage of assertions. + */ s->vm_was_running = true; /* Fallthrough */ case MIGRATION_STATUS_FAILED: From bad452a77e017dca97200e94f661e7a563dc6426 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Thu, 18 Nov 2021 15:56:38 +0100 Subject: [PATCH 133/421] migration: Remove is_zero_range() It just calls buffer_is_zero(). Just change the callers. Signed-off-by: Juan Quintela Reviewed-by: Richard Henderson --- migration/ram.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index 2c688f5bbb..57efa67f20 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -81,11 +81,6 @@ /* 0x80 is reserved in migration.h start with 0x100 next */ #define RAM_SAVE_FLAG_COMPRESS_PAGE 0x100 -static inline bool is_zero_range(uint8_t *p, uint64_t size) -{ - return buffer_is_zero(p, size); -} - XBZRLECacheStats xbzrle_counters; /* struct contains XBZRLE cache and a static page @@ -1180,7 +1175,7 @@ static int save_zero_page_to_file(RAMState *rs, QEMUFile *file, uint8_t *p = block->host + offset; int len = 0; - if (is_zero_range(p, TARGET_PAGE_SIZE)) { + if (buffer_is_zero(p, TARGET_PAGE_SIZE)) { len += save_page_header(rs, file, block, offset | RAM_SAVE_FLAG_ZERO); qemu_put_byte(file, 0); len += 1; @@ -3367,7 +3362,7 @@ static inline void *colo_cache_from_block_offset(RAMBlock *block, */ void ram_handle_compressed(void *host, uint8_t ch, uint64_t size) { - if (ch != 0 || !is_zero_range(host, size)) { + if (ch != 0 || !buffer_is_zero(host, size)) { memset(host, ch, size); } } From f13f22badc6767ea160bb77ee09830d44107b36b Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Thu, 18 Nov 2021 15:57:44 +0100 Subject: [PATCH 134/421] dump: Remove is_zero_page() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It just calls buffer_is_zero(). Just change the callers. Signed-off-by: Juan Quintela Reviewed-by: Richard Henderson Reviewed-by: Marc-André Lureau --- dump/dump.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/dump/dump.c b/dump/dump.c index 662d0a62cd..a84d8b1598 100644 --- a/dump/dump.c +++ b/dump/dump.c @@ -1293,14 +1293,6 @@ static size_t get_len_buf_out(size_t page_size, uint32_t flag_compress) return 0; } -/* - * check if the page is all 0 - */ -static inline bool is_zero_page(const uint8_t *buf, size_t page_size) -{ - return buffer_is_zero(buf, page_size); -} - static void write_dump_pages(DumpState *s, Error **errp) { int ret = 0; @@ -1357,7 +1349,7 @@ static void write_dump_pages(DumpState *s, Error **errp) */ while (get_next_page(&block_iter, &pfn_iter, &buf, s)) { /* check zero page */ - if (is_zero_page(buf, s->dump_info.page_size)) { + if (buffer_is_zero(buf, s->dump_info.page_size)) { ret = write_cache(&page_desc, &pd_zero, sizeof(PageDescriptor), false); if (ret < 0) { From 47a17824613fc88b938f4fd9585931e03517f440 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 20:18:28 +0100 Subject: [PATCH 135/421] multifd: Delete useless operation We are dividing by page_size to multiply again in the only use. Once there, improve the comments. Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd-zlib.c | 13 ++++--------- migration/multifd-zstd.c | 13 ++++--------- 2 files changed, 8 insertions(+), 18 deletions(-) diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index ab4ba75d75..3fc7813b44 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -42,7 +42,6 @@ struct zlib_data { */ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zlib_data *z = g_malloc0(sizeof(struct zlib_data)); z_stream *zs = &z->zs; @@ -54,9 +53,8 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) error_setg(errp, "multifd %d: deflate init failed", p->id); return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { deflateEnd(&z->zs); @@ -180,7 +178,6 @@ static int zlib_send_write(MultiFDSendParams *p, uint32_t used, Error **errp) */ static int zlib_recv_setup(MultiFDRecvParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zlib_data *z = g_malloc0(sizeof(struct zlib_data)); z_stream *zs = &z->zs; @@ -194,10 +191,8 @@ static int zlib_recv_setup(MultiFDRecvParams *p, Error **errp) error_setg(errp, "multifd %d: inflate init failed", p->id); return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - /* We know compression "could" use more space */ - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { inflateEnd(zs); diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index 693bddf8c9..cc3b8869c0 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -47,7 +47,6 @@ struct zstd_data { */ static int zstd_send_setup(MultiFDSendParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zstd_data *z = g_new0(struct zstd_data, 1); int res; @@ -67,9 +66,8 @@ static int zstd_send_setup(MultiFDSendParams *p, Error **errp) p->id, ZSTD_getErrorName(res)); return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { ZSTD_freeCStream(z->zcs); @@ -191,7 +189,6 @@ static int zstd_send_write(MultiFDSendParams *p, uint32_t used, Error **errp) */ static int zstd_recv_setup(MultiFDRecvParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zstd_data *z = g_new0(struct zstd_data, 1); int ret; @@ -212,10 +209,8 @@ static int zstd_recv_setup(MultiFDRecvParams *p, Error **errp) return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - /* We know compression "could" use more space */ - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { ZSTD_freeDStream(z->zds); From 144fa06b3431e806057ce1438338395b35a3e544 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 16:21:16 +0100 Subject: [PATCH 136/421] migration: Never call twice qemu_target_page_size() Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/migration.c | 7 ++++--- migration/multifd.c | 7 ++++--- migration/savevm.c | 5 +++-- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/migration/migration.c b/migration/migration.c index 2c1edb2cb9..3de11ae921 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -996,6 +996,8 @@ static void populate_time_info(MigrationInfo *info, MigrationState *s) static void populate_ram_info(MigrationInfo *info, MigrationState *s) { + size_t page_size = qemu_target_page_size(); + info->has_ram = true; info->ram = g_malloc0(sizeof(*info->ram)); info->ram->transferred = ram_counters.transferred; @@ -1004,12 +1006,11 @@ static void populate_ram_info(MigrationInfo *info, MigrationState *s) /* legacy value. It is not used anymore */ info->ram->skipped = 0; info->ram->normal = ram_counters.normal; - info->ram->normal_bytes = ram_counters.normal * - qemu_target_page_size(); + info->ram->normal_bytes = ram_counters.normal * page_size; info->ram->mbps = s->mbps; info->ram->dirty_sync_count = ram_counters.dirty_sync_count; info->ram->postcopy_requests = ram_counters.postcopy_requests; - info->ram->page_size = qemu_target_page_size(); + info->ram->page_size = page_size; info->ram->multifd_bytes = ram_counters.multifd_bytes; info->ram->pages_per_second = s->pages_per_second; diff --git a/migration/multifd.c b/migration/multifd.c index 7c9deb1921..8125d0015c 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -289,7 +289,8 @@ static void multifd_send_fill_packet(MultiFDSendParams *p) static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) { MultiFDPacket_t *packet = p->packet; - uint32_t pages_max = MULTIFD_PACKET_SIZE / qemu_target_page_size(); + size_t page_size = qemu_target_page_size(); + uint32_t pages_max = MULTIFD_PACKET_SIZE / page_size; RAMBlock *block; int i; @@ -358,14 +359,14 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) for (i = 0; i < p->pages->used; i++) { uint64_t offset = be64_to_cpu(packet->offset[i]); - if (offset > (block->used_length - qemu_target_page_size())) { + if (offset > (block->used_length - page_size)) { error_setg(errp, "multifd: offset too long %" PRIu64 " (max " RAM_ADDR_FMT ")", offset, block->used_length); return -1; } p->pages->iov[i].iov_base = block->host + offset; - p->pages->iov[i].iov_len = qemu_target_page_size(); + p->pages->iov[i].iov_len = page_size; } return 0; diff --git a/migration/savevm.c b/migration/savevm.c index d59e976d50..0bef031acb 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -1685,6 +1685,7 @@ static int loadvm_postcopy_handle_advise(MigrationIncomingState *mis, { PostcopyState ps = postcopy_state_set(POSTCOPY_INCOMING_ADVISE); uint64_t remote_pagesize_summary, local_pagesize_summary, remote_tps; + size_t page_size = qemu_target_page_size(); Error *local_err = NULL; trace_loadvm_postcopy_handle_advise(); @@ -1741,13 +1742,13 @@ static int loadvm_postcopy_handle_advise(MigrationIncomingState *mis, } remote_tps = qemu_get_be64(mis->from_src_file); - if (remote_tps != qemu_target_page_size()) { + if (remote_tps != page_size) { /* * Again, some differences could be dealt with, but for now keep it * simple. */ error_report("Postcopy needs matching target page sizes (s=%d d=%zd)", - (int)remote_tps, qemu_target_page_size()); + (int)remote_tps, page_size); return -1; } From 90a3d2f9d5f729147b2827c177932603ae6e2d55 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 11:51:40 +0100 Subject: [PATCH 137/421] multifd: Rename used field to num We will need to split it later in zero_num (number of zero pages) and normal_num (number of normal pages). This name is better. Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd.c | 38 +++++++++++++++++++------------------- migration/multifd.h | 2 +- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/migration/multifd.c b/migration/multifd.c index 8125d0015c..8ea86d81dc 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -252,7 +252,7 @@ static MultiFDPages_t *multifd_pages_init(size_t size) static void multifd_pages_clear(MultiFDPages_t *pages) { - pages->used = 0; + pages->num = 0; pages->allocated = 0; pages->packet_num = 0; pages->block = NULL; @@ -270,7 +270,7 @@ static void multifd_send_fill_packet(MultiFDSendParams *p) packet->flags = cpu_to_be32(p->flags); packet->pages_alloc = cpu_to_be32(p->pages->allocated); - packet->pages_used = cpu_to_be32(p->pages->used); + packet->pages_used = cpu_to_be32(p->pages->num); packet->next_packet_size = cpu_to_be32(p->next_packet_size); packet->packet_num = cpu_to_be64(p->packet_num); @@ -278,7 +278,7 @@ static void multifd_send_fill_packet(MultiFDSendParams *p) strncpy(packet->ramblock, p->pages->block->idstr, 256); } - for (i = 0; i < p->pages->used; i++) { + for (i = 0; i < p->pages->num; i++) { /* there are architectures where ram_addr_t is 32 bit */ uint64_t temp = p->pages->offset[i]; @@ -332,18 +332,18 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) p->pages = multifd_pages_init(packet->pages_alloc); } - p->pages->used = be32_to_cpu(packet->pages_used); - if (p->pages->used > packet->pages_alloc) { + p->pages->num = be32_to_cpu(packet->pages_used); + if (p->pages->num > packet->pages_alloc) { error_setg(errp, "multifd: received packet " "with %d pages and expected maximum pages are %d", - p->pages->used, packet->pages_alloc) ; + p->pages->num, packet->pages_alloc) ; return -1; } p->next_packet_size = be32_to_cpu(packet->next_packet_size); p->packet_num = be64_to_cpu(packet->packet_num); - if (p->pages->used == 0) { + if (p->pages->num == 0) { return 0; } @@ -356,7 +356,7 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) return -1; } - for (i = 0; i < p->pages->used; i++) { + for (i = 0; i < p->pages->num; i++) { uint64_t offset = be64_to_cpu(packet->offset[i]); if (offset > (block->used_length - page_size)) { @@ -443,13 +443,13 @@ static int multifd_send_pages(QEMUFile *f) } qemu_mutex_unlock(&p->mutex); } - assert(!p->pages->used); + assert(!p->pages->num); assert(!p->pages->block); p->packet_num = multifd_send_state->packet_num++; multifd_send_state->pages = p->pages; p->pages = pages; - transferred = ((uint64_t) pages->used) * qemu_target_page_size() + transferred = ((uint64_t) pages->num) * qemu_target_page_size() + p->packet_len; qemu_file_update_transfer(f, transferred); ram_counters.multifd_bytes += transferred; @@ -469,12 +469,12 @@ int multifd_queue_page(QEMUFile *f, RAMBlock *block, ram_addr_t offset) } if (pages->block == block) { - pages->offset[pages->used] = offset; - pages->iov[pages->used].iov_base = block->host + offset; - pages->iov[pages->used].iov_len = qemu_target_page_size(); - pages->used++; + pages->offset[pages->num] = offset; + pages->iov[pages->num].iov_base = block->host + offset; + pages->iov[pages->num].iov_len = qemu_target_page_size(); + pages->num++; - if (pages->used < pages->allocated) { + if (pages->num < pages->allocated) { return 1; } } @@ -586,7 +586,7 @@ void multifd_send_sync_main(QEMUFile *f) if (!migrate_use_multifd()) { return; } - if (multifd_send_state->pages->used) { + if (multifd_send_state->pages->num) { if (multifd_send_pages(f) < 0) { error_report("%s: multifd_send_pages fail", __func__); return; @@ -649,7 +649,7 @@ static void *multifd_send_thread(void *opaque) qemu_mutex_lock(&p->mutex); if (p->pending_job) { - uint32_t used = p->pages->used; + uint32_t used = p->pages->num; uint64_t packet_num = p->packet_num; flags = p->flags; @@ -665,7 +665,7 @@ static void *multifd_send_thread(void *opaque) p->flags = 0; p->num_packets++; p->num_pages += used; - p->pages->used = 0; + p->pages->num = 0; p->pages->block = NULL; qemu_mutex_unlock(&p->mutex); @@ -1091,7 +1091,7 @@ static void *multifd_recv_thread(void *opaque) break; } - used = p->pages->used; + used = p->pages->num; flags = p->flags; /* recv methods don't know how to handle the SYNC flag */ p->flags &= ~MULTIFD_FLAG_SYNC; diff --git a/migration/multifd.h b/migration/multifd.h index 15c50ca0b2..86820dd028 100644 --- a/migration/multifd.h +++ b/migration/multifd.h @@ -55,7 +55,7 @@ typedef struct { typedef struct { /* number of used pages */ - uint32_t used; + uint32_t num; /* number of allocated pages */ uint32_t allocated; /* global number of generated multifd packets */ From 18ede636bc29fd8bda628fe3e5c593f8c1b734f4 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 11:58:41 +0100 Subject: [PATCH 138/421] multifd: Add missing documention Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd-zlib.c | 2 ++ migration/multifd-zstd.c | 2 ++ migration/multifd.c | 1 + 3 files changed, 5 insertions(+) diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index 3fc7813b44..d0437cce2a 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -72,6 +72,7 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) * Close the channel and return memory. * * @p: Params for the channel that we are using + * @errp: pointer to an error */ static void zlib_send_cleanup(MultiFDSendParams *p, Error **errp) { @@ -94,6 +95,7 @@ static void zlib_send_cleanup(MultiFDSendParams *p, Error **errp) * * @p: Params for the channel that we are using * @used: number of pages used + * @errp: pointer to an error */ static int zlib_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) { diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index cc3b8869c0..09ae1cf91a 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -84,6 +84,7 @@ static int zstd_send_setup(MultiFDSendParams *p, Error **errp) * Close the channel and return memory. * * @p: Params for the channel that we are using + * @errp: pointer to an error */ static void zstd_send_cleanup(MultiFDSendParams *p, Error **errp) { @@ -107,6 +108,7 @@ static void zstd_send_cleanup(MultiFDSendParams *p, Error **errp) * * @p: Params for the channel that we are using * @used: number of pages used + * @errp: pointer to an error */ static int zstd_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) { diff --git a/migration/multifd.c b/migration/multifd.c index 8ea86d81dc..cdeffdc4c5 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -66,6 +66,7 @@ static int nocomp_send_setup(MultiFDSendParams *p, Error **errp) * For no compression this function does nothing. * * @p: Params for the channel that we are using + * @errp: pointer to an error */ static void nocomp_send_cleanup(MultiFDSendParams *p, Error **errp) { From 1943c11a62bd0741e5d9fbba78404fe47ebea820 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 10:58:01 +0100 Subject: [PATCH 139/421] multifd: The variable is only used inside the loop Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/migration/multifd.c b/migration/multifd.c index cdeffdc4c5..ce7101cf9d 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -629,7 +629,6 @@ static void *multifd_send_thread(void *opaque) MultiFDSendParams *p = opaque; Error *local_err = NULL; int ret = 0; - uint32_t flags = 0; trace_multifd_send_thread_start(p->id); rcu_register_thread(); @@ -652,7 +651,7 @@ static void *multifd_send_thread(void *opaque) if (p->pending_job) { uint32_t used = p->pages->num; uint64_t packet_num = p->packet_num; - flags = p->flags; + uint32_t flags = p->flags; if (used) { ret = multifd_send_state->ops->send_prepare(p, used, From 02fb81043ecee338e4aeb8f5be09a46325dc5e43 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 12:08:08 +0100 Subject: [PATCH 140/421] multifd: remove used parameter from send_prepare() method It is already there as p->pages->num. Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd-zlib.c | 7 +++---- migration/multifd-zstd.c | 7 +++---- migration/multifd.c | 9 +++------ migration/multifd.h | 2 +- 4 files changed, 10 insertions(+), 15 deletions(-) diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index d0437cce2a..28f0ed933b 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -94,10 +94,9 @@ static void zlib_send_cleanup(MultiFDSendParams *p, Error **errp) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int zlib_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) +static int zlib_send_prepare(MultiFDSendParams *p, Error **errp) { struct iovec *iov = p->pages->iov; struct zlib_data *z = p->data; @@ -106,11 +105,11 @@ static int zlib_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) int ret; uint32_t i; - for (i = 0; i < used; i++) { + for (i = 0; i < p->pages->num; i++) { uint32_t available = z->zbuff_len - out_size; int flush = Z_NO_FLUSH; - if (i == used - 1) { + if (i == p->pages->num - 1) { flush = Z_SYNC_FLUSH; } diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index 09ae1cf91a..4a71e96e06 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -107,10 +107,9 @@ static void zstd_send_cleanup(MultiFDSendParams *p, Error **errp) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int zstd_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) +static int zstd_send_prepare(MultiFDSendParams *p, Error **errp) { struct iovec *iov = p->pages->iov; struct zstd_data *z = p->data; @@ -121,10 +120,10 @@ static int zstd_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) z->out.size = z->zbuff_len; z->out.pos = 0; - for (i = 0; i < used; i++) { + for (i = 0; i < p->pages->num; i++) { ZSTD_EndDirective flush = ZSTD_e_continue; - if (i == used - 1) { + if (i == p->pages->num - 1) { flush = ZSTD_e_flush; } z->in.src = iov[i].iov_base; diff --git a/migration/multifd.c b/migration/multifd.c index ce7101cf9d..098ef8842c 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -82,13 +82,11 @@ static void nocomp_send_cleanup(MultiFDSendParams *p, Error **errp) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int nocomp_send_prepare(MultiFDSendParams *p, uint32_t used, - Error **errp) +static int nocomp_send_prepare(MultiFDSendParams *p, Error **errp) { - p->next_packet_size = used * qemu_target_page_size(); + p->next_packet_size = p->pages->num * qemu_target_page_size(); p->flags |= MULTIFD_FLAG_NOCOMP; return 0; } @@ -654,8 +652,7 @@ static void *multifd_send_thread(void *opaque) uint32_t flags = p->flags; if (used) { - ret = multifd_send_state->ops->send_prepare(p, used, - &local_err); + ret = multifd_send_state->ops->send_prepare(p, &local_err); if (ret != 0) { qemu_mutex_unlock(&p->mutex); break; diff --git a/migration/multifd.h b/migration/multifd.h index 86820dd028..7968cc5c20 100644 --- a/migration/multifd.h +++ b/migration/multifd.h @@ -159,7 +159,7 @@ typedef struct { /* Cleanup for sending side */ void (*send_cleanup)(MultiFDSendParams *p, Error **errp); /* Prepare the send packet */ - int (*send_prepare)(MultiFDSendParams *p, uint32_t used, Error **errp); + int (*send_prepare)(MultiFDSendParams *p, Error **errp); /* Write the send packet */ int (*send_write)(MultiFDSendParams *p, uint32_t used, Error **errp); /* Setup for receiving side */ From 40a4bfe9d3f8ad35a9c3ffb4cbf7367e2777054b Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Mon, 22 Nov 2021 12:49:43 +0100 Subject: [PATCH 141/421] multifd: remove used parameter from send_recv_pages() method It is already there as p->pages->num. Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd-zlib.c | 9 ++++----- migration/multifd-zstd.c | 7 +++---- migration/multifd.c | 7 +++---- migration/multifd.h | 2 +- 4 files changed, 11 insertions(+), 14 deletions(-) diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index 28f0ed933b..e85ef8824d 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -230,17 +230,16 @@ static void zlib_recv_cleanup(MultiFDRecvParams *p) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int zlib_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) +static int zlib_recv_pages(MultiFDRecvParams *p, Error **errp) { struct zlib_data *z = p->data; z_stream *zs = &z->zs; uint32_t in_size = p->next_packet_size; /* we measure the change of total_out */ uint32_t out_size = zs->total_out; - uint32_t expected_size = used * qemu_target_page_size(); + uint32_t expected_size = p->pages->num * qemu_target_page_size(); uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; int ret; int i; @@ -259,12 +258,12 @@ static int zlib_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) zs->avail_in = in_size; zs->next_in = z->zbuff; - for (i = 0; i < used; i++) { + for (i = 0; i < p->pages->num; i++) { struct iovec *iov = &p->pages->iov[i]; int flush = Z_NO_FLUSH; unsigned long start = zs->total_out; - if (i == used - 1) { + if (i == p->pages->num - 1) { flush = Z_SYNC_FLUSH; } diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index 4a71e96e06..a8b104f4ee 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -250,14 +250,13 @@ static void zstd_recv_cleanup(MultiFDRecvParams *p) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int zstd_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) +static int zstd_recv_pages(MultiFDRecvParams *p, Error **errp) { uint32_t in_size = p->next_packet_size; uint32_t out_size = 0; - uint32_t expected_size = used * qemu_target_page_size(); + uint32_t expected_size = p->pages->num * qemu_target_page_size(); uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; struct zstd_data *z = p->data; int ret; @@ -278,7 +277,7 @@ static int zstd_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) z->in.size = in_size; z->in.pos = 0; - for (i = 0; i < used; i++) { + for (i = 0; i < p->pages->num; i++) { struct iovec *iov = &p->pages->iov[i]; z->out.dst = iov->iov_base; diff --git a/migration/multifd.c b/migration/multifd.c index 098ef8842c..55d99a8232 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -141,10 +141,9 @@ static void nocomp_recv_cleanup(MultiFDRecvParams *p) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int nocomp_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) +static int nocomp_recv_pages(MultiFDRecvParams *p, Error **errp) { uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; @@ -153,7 +152,7 @@ static int nocomp_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) p->id, flags, MULTIFD_FLAG_NOCOMP); return -1; } - return qio_channel_readv_all(p->c, p->pages->iov, used, errp); + return qio_channel_readv_all(p->c, p->pages->iov, p->pages->num, errp); } static MultiFDMethods multifd_nocomp_ops = { @@ -1099,7 +1098,7 @@ static void *multifd_recv_thread(void *opaque) qemu_mutex_unlock(&p->mutex); if (used) { - ret = multifd_recv_state->ops->recv_pages(p, used, &local_err); + ret = multifd_recv_state->ops->recv_pages(p, &local_err); if (ret != 0) { break; } diff --git a/migration/multifd.h b/migration/multifd.h index 7968cc5c20..e57adc783b 100644 --- a/migration/multifd.h +++ b/migration/multifd.h @@ -167,7 +167,7 @@ typedef struct { /* Cleanup for receiving side */ void (*recv_cleanup)(MultiFDRecvParams *p); /* Read all pages */ - int (*recv_pages)(MultiFDRecvParams *p, uint32_t used, Error **errp); + int (*recv_pages)(MultiFDRecvParams *p, Error **errp); } MultiFDMethods; void multifd_register_ops(int method, MultiFDMethods *ops); From 01102a2ef6c97acc5cc8a2c3bb62b7665a20f51f Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Fri, 19 Nov 2021 13:15:48 +0100 Subject: [PATCH 142/421] multifd: Fill offset and block for reception We were using the iov directly, but we will need this info on the following patch. Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/migration/multifd.c b/migration/multifd.c index 55d99a8232..0533da154a 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -354,6 +354,7 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) return -1; } + p->pages->block = block; for (i = 0; i < p->pages->num; i++) { uint64_t offset = be64_to_cpu(packet->offset[i]); @@ -363,6 +364,7 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) offset, block->used_length); return -1; } + p->pages->offset[i] = offset; p->pages->iov[i].iov_base = block->host + offset; p->pages->iov[i].iov_len = page_size; } From 077fbb5942b56826f731de16caae3122a30aab22 Mon Sep 17 00:00:00 2001 From: Li Zhang Date: Fri, 3 Dec 2021 12:55:33 +0100 Subject: [PATCH 143/421] multifd: Shut down the QIO channels to avoid blocking the send threads when they are terminated. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When doing live migration with multifd channels 8, 16 or larger number, the guest hangs in the presence of the network errors such as missing TCP ACKs. At sender's side: The main thread is blocked on qemu_thread_join, migration_fd_cleanup is called because one thread fails on qio_channel_write_all when the network problem happens and other send threads are blocked on sendmsg. They could not be terminated. So the main thread is blocked on qemu_thread_join to wait for the threads terminated. (gdb) bt 0 0x00007f30c8dcffc0 in __pthread_clockjoin_ex () at /lib64/libpthread.so.0 1 0x000055cbb716084b in qemu_thread_join (thread=0x55cbb881f418) at ../util/qemu-thread-posix.c:627 2 0x000055cbb6b54e40 in multifd_save_cleanup () at ../migration/multifd.c:542 3 0x000055cbb6b4de06 in migrate_fd_cleanup (s=0x55cbb8024000) at ../migration/migration.c:1808 4 0x000055cbb6b4dfb4 in migrate_fd_cleanup_bh (opaque=0x55cbb8024000) at ../migration/migration.c:1850 5 0x000055cbb7173ac1 in aio_bh_call (bh=0x55cbb7eb98e0) at ../util/async.c:141 6 0x000055cbb7173bcb in aio_bh_poll (ctx=0x55cbb7ebba80) at ../util/async.c:169 7 0x000055cbb715ba4b in aio_dispatch (ctx=0x55cbb7ebba80) at ../util/aio-posix.c:381 8 0x000055cbb7173ffe in aio_ctx_dispatch (source=0x55cbb7ebba80, callback=0x0, user_data=0x0) at ../util/async.c:311 9 0x00007f30c9c8cdf4 in g_main_context_dispatch () at /usr/lib64/libglib-2.0.so.0 10 0x000055cbb71851a2 in glib_pollfds_poll () at ../util/main-loop.c:232 11 0x000055cbb718521c in os_host_main_loop_wait (timeout=42251070366) at ../util/main-loop.c:255 12 0x000055cbb7185321 in main_loop_wait (nonblocking=0) at ../util/main-loop.c:531 13 0x000055cbb6e6ba27 in qemu_main_loop () at ../softmmu/runstate.c:726 14 0x000055cbb6ad6fd7 in main (argc=68, argv=0x7ffc0c578888, envp=0x7ffc0c578ab0) at ../softmmu/main.c:50 To make sure that the send threads could be terminated, IO channels should be shut down to avoid waiting IO. Signed-off-by: Li Zhang Reviewed-by: Daniel P. Berrangé Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- migration/multifd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/migration/multifd.c b/migration/multifd.c index 0533da154a..3242f688e5 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -524,6 +524,9 @@ static void multifd_send_terminate_threads(Error *err) qemu_mutex_lock(&p->mutex); p->quit = true; qemu_sem_post(&p->sem); + if (p->c) { + qio_channel_shutdown(p->c, QIO_CHANNEL_SHUTDOWN_BOTH, NULL); + } qemu_mutex_unlock(&p->mutex); } } From 9c5c8ff24e2cc9b4db76c33aa360563407832656 Mon Sep 17 00:00:00 2001 From: "Rao, Lei" Date: Wed, 15 Dec 2021 01:19:45 +0800 Subject: [PATCH 144/421] COLO: Move some trace code behind qemu_mutex_unlock_iothread() There is no need to put some trace code in the critical section. So, moving it behind qemu_mutex_unlock_iothread() can reduce the lock time. Signed-off-by: Lei Rao Reviewed-by: Juan Quintela Signed-off-by: Juan Quintela --- migration/colo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/migration/colo.c b/migration/colo.c index 4a772afe78..5f7071b3cd 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -680,8 +680,8 @@ static void colo_incoming_process_checkpoint(MigrationIncomingState *mis, qemu_mutex_lock_iothread(); vm_stop_force_state(RUN_STATE_COLO); - trace_colo_vm_state_change("run", "stop"); qemu_mutex_unlock_iothread(); + trace_colo_vm_state_change("run", "stop"); /* FIXME: This is unnecessary for periodic checkpoint mode */ colo_send_message(mis->to_src_file, COLO_MESSAGE_CHECKPOINT_REPLY, @@ -783,8 +783,8 @@ static void colo_incoming_process_checkpoint(MigrationIncomingState *mis, vmstate_loading = false; vm_start(); - trace_colo_vm_state_change("stop", "run"); qemu_mutex_unlock_iothread(); + trace_colo_vm_state_change("stop", "run"); if (failover_get_state() == FAILOVER_STATUS_RELAUNCH) { return; @@ -887,8 +887,8 @@ void *colo_process_incoming_thread(void *opaque) abort(); #endif vm_start(); - trace_colo_vm_state_change("stop", "run"); qemu_mutex_unlock_iothread(); + trace_colo_vm_state_change("stop", "run"); colo_send_message(mis->to_src_file, COLO_MESSAGE_CHECKPOINT_READY, &local_err); From f5ff548774c22b34a0c0e2fef85f1be11160d774 Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Fri, 19 Nov 2021 13:16:25 +0100 Subject: [PATCH 145/421] multifd: Make zstd compression method not use iovs Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd-zstd.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index a8b104f4ee..2d5b61106c 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include #include "qemu/rcu.h" +#include "exec/ramblock.h" #include "exec/target_page.h" #include "qapi/error.h" #include "migration.h" @@ -111,8 +112,8 @@ static void zstd_send_cleanup(MultiFDSendParams *p, Error **errp) */ static int zstd_send_prepare(MultiFDSendParams *p, Error **errp) { - struct iovec *iov = p->pages->iov; struct zstd_data *z = p->data; + size_t page_size = qemu_target_page_size(); int ret; uint32_t i; @@ -126,8 +127,8 @@ static int zstd_send_prepare(MultiFDSendParams *p, Error **errp) if (i == p->pages->num - 1) { flush = ZSTD_e_flush; } - z->in.src = iov[i].iov_base; - z->in.size = iov[i].iov_len; + z->in.src = p->pages->block->host + p->pages->offset[i]; + z->in.size = page_size; z->in.pos = 0; /* @@ -256,7 +257,8 @@ static int zstd_recv_pages(MultiFDRecvParams *p, Error **errp) { uint32_t in_size = p->next_packet_size; uint32_t out_size = 0; - uint32_t expected_size = p->pages->num * qemu_target_page_size(); + size_t page_size = qemu_target_page_size(); + uint32_t expected_size = p->pages->num * page_size; uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; struct zstd_data *z = p->data; int ret; @@ -278,10 +280,8 @@ static int zstd_recv_pages(MultiFDRecvParams *p, Error **errp) z->in.pos = 0; for (i = 0; i < p->pages->num; i++) { - struct iovec *iov = &p->pages->iov[i]; - - z->out.dst = iov->iov_base; - z->out.size = iov->iov_len; + z->out.dst = p->pages->block->host + p->pages->offset[i]; + z->out.size = page_size; z->out.pos = 0; /* @@ -295,8 +295,8 @@ static int zstd_recv_pages(MultiFDRecvParams *p, Error **errp) do { ret = ZSTD_decompressStream(z->zds, &z->out, &z->in); } while (ret > 0 && (z->in.size - z->in.pos > 0) - && (z->out.pos < iov->iov_len)); - if (ret > 0 && (z->out.pos < iov->iov_len)) { + && (z->out.pos < page_size)); + if (ret > 0 && (z->out.pos < page_size)) { error_setg(errp, "multifd %d: decompressStream buffer too small", p->id); return -1; From a5ed22948873b50fcf1415d1ce15c71d61a9388d Mon Sep 17 00:00:00 2001 From: Juan Quintela Date: Fri, 19 Nov 2021 14:14:11 +0100 Subject: [PATCH 146/421] multifd: Make zlib compression method not use iovs Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert --- migration/multifd-zlib.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index e85ef8824d..da6201704c 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include #include "qemu/rcu.h" +#include "exec/ramblock.h" #include "exec/target_page.h" #include "qapi/error.h" #include "migration.h" @@ -98,8 +99,8 @@ static void zlib_send_cleanup(MultiFDSendParams *p, Error **errp) */ static int zlib_send_prepare(MultiFDSendParams *p, Error **errp) { - struct iovec *iov = p->pages->iov; struct zlib_data *z = p->data; + size_t page_size = qemu_target_page_size(); z_stream *zs = &z->zs; uint32_t out_size = 0; int ret; @@ -113,8 +114,8 @@ static int zlib_send_prepare(MultiFDSendParams *p, Error **errp) flush = Z_SYNC_FLUSH; } - zs->avail_in = iov[i].iov_len; - zs->next_in = iov[i].iov_base; + zs->avail_in = page_size; + zs->next_in = p->pages->block->host + p->pages->offset[i]; zs->avail_out = available; zs->next_out = z->zbuff + out_size; @@ -235,6 +236,7 @@ static void zlib_recv_cleanup(MultiFDRecvParams *p) static int zlib_recv_pages(MultiFDRecvParams *p, Error **errp) { struct zlib_data *z = p->data; + size_t page_size = qemu_target_page_size(); z_stream *zs = &z->zs; uint32_t in_size = p->next_packet_size; /* we measure the change of total_out */ @@ -259,7 +261,6 @@ static int zlib_recv_pages(MultiFDRecvParams *p, Error **errp) zs->next_in = z->zbuff; for (i = 0; i < p->pages->num; i++) { - struct iovec *iov = &p->pages->iov[i]; int flush = Z_NO_FLUSH; unsigned long start = zs->total_out; @@ -267,8 +268,8 @@ static int zlib_recv_pages(MultiFDRecvParams *p, Error **errp) flush = Z_SYNC_FLUSH; } - zs->avail_out = iov->iov_len; - zs->next_out = iov->iov_base; + zs->avail_out = page_size; + zs->next_out = p->pages->block->host + p->pages->offset[i]; /* * Welcome to inflate semantics @@ -281,8 +282,8 @@ static int zlib_recv_pages(MultiFDRecvParams *p, Error **errp) do { ret = inflate(zs, flush); } while (ret == Z_OK && zs->avail_in - && (zs->total_out - start) < iov->iov_len); - if (ret == Z_OK && (zs->total_out - start) < iov->iov_len) { + && (zs->total_out - start) < page_size); + if (ret == Z_OK && (zs->total_out - start) < page_size) { error_setg(errp, "multifd %d: inflate generated too few output", p->id); return -1; From 229c57b1986484ea2cd1eb744e3492af7eee063e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Fri, 12 Nov 2021 17:04:54 +0000 Subject: [PATCH 147/421] hw/intc: clean-up error reporting for failed ITS cmd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While trying to debug a GIC ITS failure I saw some guest errors that had poor formatting as well as leaving me confused as to what failed. As most of the checks aren't possible without a valid dte split that check apart and then check the other conditions in steps. This avoids us relying on undefined data. I still get a failure with the current kvm-unit-tests but at least I know (partially) why now: Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588 PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0 INT dev_id=2 event_id=20 process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0) PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap SUMMARY: 6 tests, 1 unexpected failures Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org Cc: Shashi Mallela Cc: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index c929a9cb5c..b99e63d58f 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -274,21 +274,36 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, if (res != MEMTX_OK) { return result; } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n", + __func__, dte, devid, res); + return result; } - if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || - !cte_valid || (eventid > max_eventid)) { + + /* + * In this implementation, in case of guest errors we ignore the + * command and move onto the next command in the queue. + */ + if (devid > s->dt.maxids.max_devids) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes " - "devid %d or eventid %d or invalid dte %d or" - "invalid cte %d or invalid ite %d\n", - __func__, devid, eventid, dte_valid, cte_valid, - ite_valid); - /* - * in this implementation, in case of error - * we ignore this command and move onto the next - * command in the queue - */ + "%s: invalid command attributes: devid %d>%d", + __func__, devid, s->dt.maxids.max_devids); + + } else if (!dte_valid || !ite_valid || !cte_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "dte: %s, ite: %s, cte: %s\n", + __func__, + dte_valid ? "valid" : "invalid", + ite_valid ? "valid" : "invalid", + cte_valid ? "valid" : "invalid"); + } else if (eventid > max_eventid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: eventid %d > %d\n", + __func__, eventid, max_eventid); } else { /* * Current implementation only supports rdbase == procnum From 0b052414bdd4bc8d688a0eaf62f7a9ac417848a5 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 14:57:49 +0800 Subject: [PATCH 148/421] docs: aspeed: Add new boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be removed in v7.0. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Message-id: 20211117065752.330632-2-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index cec87e3743..41a9bd5608 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -14,6 +14,7 @@ AST2400 SoC based machines : - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC - ``quanta-q71l-bmc`` OpenBMC Quanta BMC +- ``supermicrox11-bmc`` Supermicro X11 BMC AST2500 SoC based machines : @@ -21,12 +22,16 @@ AST2500 SoC based machines : - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC - ``sonorapass-bmc`` OCP SonoraPass BMC -- ``swift-bmc`` OpenPOWER Swift BMC POWER9 +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0) +- ``fp5280g2-bmc`` Inspur FP5280G2 BMC +- ``g220a-bmc`` Bytedance G220A BMC AST2600 SoC based machines : - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC +- ``rainier-bmc`` IBM Rainier POWER10 BMC +- ``fuji-bmc`` Facebook Fuji BMC Supported devices ----------------- From 38b1ed6c908c4a7d39897808d0a5c5fd5931d5a7 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 14:57:50 +0800 Subject: [PATCH 149/421] docs: aspeed: Update OpenBMC image URL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the latest URL for the OpenBMC CI. The old URL still works, but redirects. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Message-id: 20211117065752.330632-3-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 41a9bd5608..b87697fcf0 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -82,7 +82,7 @@ The Aspeed machines can be started using the ``-kernel`` option to load a Linux kernel or from a firmware. Images can be downloaded from the OpenBMC jenkins : - https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ or directly from the OpenBMC GitHub release repository : From 9d5dcb8512098ac9dd5ee20f065ac516942d4a26 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 14:57:51 +0800 Subject: [PATCH 150/421] docs: aspeed: Give an example of booting a kernel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A common use case for the ASPEED machine is to boot a Linux kernel. Provide a full example command line. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley Message-id: 20211117065752.330632-4-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index b87697fcf0..6aafd611e9 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -78,9 +78,9 @@ Missing devices Boot options ------------ -The Aspeed machines can be started using the ``-kernel`` option to -load a Linux kernel or from a firmware. Images can be downloaded from -the OpenBMC jenkins : +The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options +to load a Linux kernel or from a firmware. Images can be downloaded from the +OpenBMC jenkins : https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ @@ -88,6 +88,15 @@ or directly from the OpenBMC GitHub release repository : https://github.com/openbmc/openbmc/releases +To boot a kernel directly from a Linux build tree: + +.. code-block:: bash + + $ qemu-system-arm -M ast2600-evb -nographic \ + -kernel arch/arm/boot/zImage \ + -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ + -initrd rootfs.cpio + The image should be attached as an MTD drive. Run : .. code-block:: bash From b662fac6aa800669d3a802f1ddaa1910a42b77ab Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 17 Nov 2021 14:57:52 +0800 Subject: [PATCH 151/421] docs: aspeed: ADC is now modelled Move it to the supported list. Signed-off-by: Joel Stanley Message-id: 20211117065752.330632-5-joel@jms.id.au Signed-off-by: Peter Maydell --- docs/system/arm/aspeed.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 6aafd611e9..d8b102fa0a 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -56,13 +56,13 @@ Supported devices * Front LEDs (PCA9552 on I2C bus) * LPC Peripheral Controller (a subset of subdevices are supported) * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA + * ADC Missing devices --------------- * Coprocessor support - * ADC (out of tree implementation) * PWM and Fan Controller * Slave GPIO Controller * Super I/O Controller From ab08c3467605365b44fab1b66bb6254db86814f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Olivier=20H=C3=A9riveaux?= Date: Sun, 28 Nov 2021 13:07:23 +0100 Subject: [PATCH 152/421] Fix STM32F2XX USART data register readout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix issue where the data register may be overwritten by next character reception before being read and returned. Signed-off-by: Olivier Hériveaux Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr Signed-off-by: Peter Maydell --- hw/char/stm32f2xx_usart.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 8df0832424..fde67f4f03 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -103,10 +103,11 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, return retvalue; case USART_DR: DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); + retvalue = s->usart_dr & 0x3FF; s->usart_sr &= ~USART_SR_RXNE; qemu_chr_fe_accept_input(&s->chr); qemu_set_irq(s->irq, 0); - return s->usart_dr & 0x3FF; + return retvalue; case USART_BRR: return s->usart_brr; case USART_CR1: From a1d742d88b7c4aef31c265ee931dfc51ec4be017 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 15 Nov 2021 23:36:18 +0100 Subject: [PATCH 153/421] hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gicv3_set_gicv3state() is used by arm_gicv3_common.c in arm_gicv3_common_realize(). Since we want to restrict arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state() to a new file. Add this file to the meson 'specific' source set, since it needs access to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-id: 20211115223619.2599282-2-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 10 +--------- hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++ hw/intc/meson.build | 1 + 3 files changed, 24 insertions(+), 9 deletions(-) create mode 100644 hw/intc/arm_gicv3_cpuif_common.c diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 85fc369e55..d7e03d0cab 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1,5 +1,5 @@ /* - * ARM Generic Interrupt Controller v3 + * ARM Generic Interrupt Controller v3 (emulation) * * Copyright (c) 2016 Linaro Limited * Written by Peter Maydell @@ -21,14 +21,6 @@ #include "hw/irq.h" #include "cpu.h" -void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) -{ - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; - - env->gicv3state = (void *)s; -}; - static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { return env->gicv3state; diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c new file mode 100644 index 0000000000..ff1239f65d --- /dev/null +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller v3 + * + * Copyright (c) 2016 Linaro Limited + * Written by Peter Maydell + * + * This code is licensed under the GPL, version 2 or (at your option) + * any later version. + */ + +#include "qemu/osdep.h" +#include "gicv3_internal.h" +#include "cpu.h" + +void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + + env->gicv3state = (void *)s; +}; diff --git a/hw/intc/meson.build b/hw/intc/meson.build index c89d2ca180..11352806db 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -25,6 +25,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) From a8a5546798c3b59d2a6c37734ec1804e706d84e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 15 Nov 2021 23:36:19 +0100 Subject: [PATCH 154/421] hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The TYPE_ARM_GICV3 device is an emulated one. When using KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device (which uses in-kernel support). When using --with-devices-FOO, it is possible to build a binary with a specific set of devices. When this binary is restricted to KVM accelerator, the TYPE_ARM_GICV3 device is irrelevant, and it is desirable to remove it from the binary. Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector which select the files required to have the TYPE_ARM_GICV3 device, but also allowing to de-select this device. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Message-id: 20211115223619.2599282-3-philmd@redhat.com Signed-off-by: Peter Maydell --- hw/intc/Kconfig | 5 +++++ hw/intc/arm_gicv3.c | 2 +- hw/intc/meson.build | 10 ++++++---- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 78aed93c45..010ded7eae 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -25,6 +25,11 @@ config APIC select MSI_NONBROKEN select I8259 +config ARM_GIC_TCG + bool + default y + depends on ARM_GIC && TCG + config ARM_GIC_KVM bool default y diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 9f5f815db9..715df5421d 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -1,5 +1,5 @@ /* - * ARM Generic Interrupt Controller v3 + * ARM Generic Interrupt Controller v3 (emulation) * * Copyright (c) 2015 Huawei. * Copyright (c) 2016 Linaro Limited diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 11352806db..70080bc161 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -3,12 +3,14 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( 'arm_gic.c', 'arm_gic_common.c', 'arm_gicv2m.c', - 'arm_gicv3.c', 'arm_gicv3_common.c', - 'arm_gicv3_dist.c', 'arm_gicv3_its_common.c', - 'arm_gicv3_redist.c', +)) +softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( + 'arm_gicv3.c', + 'arm_gicv3_dist.c', 'arm_gicv3_its.c', + 'arm_gicv3_redist.c', )) softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) @@ -26,7 +28,7 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) From 3b39ba360d5606c8a321e611ad855891b13d08cf Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:43 -0400 Subject: [PATCH 155/421] target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cec672f229..9c4258ccac 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14750,6 +14750,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint64_t pc = s->base.pc_next; uint32_t insn; if (s->ss_active && !s->pstate_ss) { @@ -14769,10 +14770,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) return; } - s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); + s->pc_curr = pc; + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; - s->base.pc_next += 4; + s->base.pc_next = pc + 4; s->fp_access_checked = false; s->sve_access_checked = false; From bf9dd2aa5fd88f0c161ff857342484f0fb42ff3f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:44 -0400 Subject: [PATCH 156/421] target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 98f5925928..c721b2ce42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9548,17 +9548,18 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; unsigned int insn; if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); dc->insn = insn; - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; disas_arm_insn(dc, insn); arm_post_translate_insn(dc); From 0bb72bca7cb1cd282d2a55549db06a54d0319d7f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:45 -0400 Subject: [PATCH 157/421] target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c721b2ce42..1c2a7274df 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9618,25 +9618,25 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; uint32_t insn; bool is_16bit; if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 2; + dc->base.pc_next = pc + 2; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); - dc->base.pc_next += 2; + pc += 2; if (!is_16bit) { - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, - dc->sctlr_b); - + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); insn = insn << 16 | insn2; - dc->base.pc_next += 2; + pc += 2; } + dc->base.pc_next = pc; dc->insn = insn; if (dc->pstate_il) { From 258a00e5a4a59dd4b0360a0aa4b8263b44d55cd0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:46 -0400 Subject: [PATCH 158/421] target/arm: Split arm_pre_translate_insn Create arm_check_ss_active and arm_check_kernelpage. Reverse the order of the tests. While it doesn't matter in practice, because only user-only has a kernel page and user-only never sets ss_active, ss_active has priority over execution exceptions and it is best to keep them in the proper order. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1c2a7274df..0103c75a27 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9502,7 +9502,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9514,7 +9514,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9551,7 +9555,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 4; return; } @@ -9622,7 +9626,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; - if (arm_pre_translate_insn(dc)) { + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 2; return; } From 485088f7425ec7f99d3f21cafb028aa92639618d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:47 -0400 Subject: [PATCH 159/421] target/arm: Advance pc for arch single-step exception The size of the code covered by a TranslationBlock cannot be 0; this is checked via assert in tb_gen_code. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9c4258ccac..2986fe1393 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14767,6 +14767,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; } From 936a6b86030a0db172b09a1ea953091a1555611e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:48 -0400 Subject: [PATCH 160/421] target/arm: Split compute_fsr_fsc out of arm_deliver_fault We will reuse this section of arm_deliver_fault for raising pc alignment faults. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 12a934e924..4cacb9658f 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -49,25 +49,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, + int target_el, int mmu_idx, uint32_t *ret_fsc) { - CPUARMState *env = &cpu->env; - int target_el; - bool same_el; - uint32_t syn, exc, fsr, fsc; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); - - target_el = exception_target_el(env); - if (fi->stage2) { - target_el = 2; - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; - if (arm_is_secure_below_el3(env) && fi->s1ns) { - env->cp15.hpfar_el2 |= HPFAR_NS; - } - } - same_el = (arm_current_el(env) == target_el); + uint32_t fsr, fsc; if (target_el == 2 || arm_el_is_aa64(env, target_el) || arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { @@ -88,6 +74,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, fsc = 0x3f; } + *ret_fsc = fsc; + return fsr; +} + +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) +{ + CPUARMState *env = &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc, fsr, fsc; + + target_el = exception_target_el(env); + if (fi->stage2) { + target_el = 2; + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi->s1ns) { + env->cp15.hpfar_el2 |= HPFAR_NS; + } + } + same_el = (arm_current_el(env) == target_el); + + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + if (access_type == MMU_INST_FETCH) { syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; From ee03027a2cef00f977a3d28242c0a250b8552495 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:49 -0400 Subject: [PATCH 161/421] target/arm: Take an exception if PC is misaligned For A64, any input to an indirect branch can cause this. For A32, many indirect branch paths force the branch to be aligned, but BXWritePC does not. This includes the BX instruction but also other interworking changes to PC. Prior to v8, this case is UNDEFINED. With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an exception or force align the PC. We choose to raise an exception because we have the infrastructure, it makes the generated code for gen_bx simpler, and it has the possibility of catching more guest bugs. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++--------------- target/arm/helper.h | 1 + target/arm/syndrome.h | 5 ++++ target/arm/tlb_helper.c | 18 ++++++++++++++ target/arm/translate-a64.c | 15 ++++++++++++ target/arm/translate.c | 22 ++++++++++++++++- 6 files changed, 87 insertions(+), 20 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 97e0728b67..f9f3473288 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -113,27 +113,35 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ ec = syn_get_ec(env->exception.syndrome); - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc = extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MTESERR; + break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MTESERR; - break; - case 0x21: /* Alignment fault */ + case EC_PCALIGNMENT: si_signo = TARGET_SIGBUS; si_code = TARGET_BUS_ADRALN; break; diff --git a/target/arm/helper.h b/target/arm/helper.h index 448a86edfd..b463d9343b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index f30f4130a2..8cde8e7243 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 4cacb9658f..b79004e0cc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -134,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; + int target_el = exception_target_el(env); + int mmu_idx = cpu_mmu_index(env, true); + uint32_t fsc; + + env->exception.vaddress = pc; + + /* + * Note that the fsc is not applicable to this exception, + * since any syndrome is pcalignment not insn_abort. + */ + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); +} + #if !defined(CONFIG_USER_ONLY) /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2986fe1393..130a9ff8d5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14753,6 +14753,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint64_t pc = s->base.pc_next; uint32_t insn; + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14771,6 +14772,20 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) return; } + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + s->pc_curr = pc; insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; diff --git a/target/arm/translate.c b/target/arm/translate.c index 0103c75a27..45917c3a6d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9555,7 +9555,27 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next = pc + 4; + return; + } + + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should only + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp = DISAS_NORETURN; + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 4; return; } From 7055fe4baf4d8b331863e51a15e93d3bdea29e36 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:50 -0400 Subject: [PATCH 162/421] target/arm: Assert thumb pc is aligned Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere. Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/gdbstub.c | 9 +++++++-- target/arm/machine.c | 10 ++++++++++ target/arm/translate.c | 3 +++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 134da0d0ae..ca1de47511 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n == 15) { tmp &= ~1; } diff --git a/target/arm/machine.c b/target/arm/machine.c index c74d8c3f4b..135d2420b5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } } + + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/translate.c b/target/arm/translate.c index 45917c3a6d..0a3840d227 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9646,6 +9646,9 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) uint32_t insn; bool is_16bit; + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) == 0); + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { dc->base.pc_next = pc + 2; return; From 8dc89f1faa28af0df92d6c63ff249849a3e9c80e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:51 -0400 Subject: [PATCH 163/421] target/arm: Suppress bp for exceptions with more priority Both single-step and pc alignment faults have priority over breakpoint exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..32f3caec23 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + target_ulong pc; int n; /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc = is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; From 0bdce4861f924a5efd5c57a7a40f2d8a4269fa80 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 3 Nov 2021 00:03:52 -0400 Subject: [PATCH 164/421] tests/tcg: Add arm and aarch64 pc alignment tests Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- tests/tcg/aarch64/Makefile.target | 4 +-- tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ tests/tcg/arm/Makefile.target | 4 +++ tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/pcalign-a64.c create mode 100644 tests/tcg/arm/pcalign-a32.c diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2c05c90d17..1d967901bd 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# Float-convert Tests -AARCH64_TESTS=fcvt +# Base architecture tests +AARCH64_TESTS=fcvt pcalign-a64 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c new file mode 100644 index 0000000000..6b9277f919 --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + abort(); +} diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce..f509d823d4 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# PC alignment test +ARM_TESTS += pcalign-a32 +pcalign-a32: CFLAGS+=-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) # Semihosting smoke test for linux-user diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 0000000000..3c9c8cc97b --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} From e0e875a68a1cc699658a40b8449267c7460de60f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 1 Sep 2021 15:10:08 +0100 Subject: [PATCH 165/421] target/i386: Use assert() to sanity-check b1 in SSE decode In the SSE decode function gen_sse(), we combine a byte 'b' and a value 'b1' which can be [0..3], and switch on them: b |= (b1 << 8); switch (b) { ... default: unknown_op: gen_unknown_opcode(env, s); return; } In three cases inside this switch, we were then also checking for "if (b1 >= 2) { goto unknown_op; }". However, this can never happen, because the 'case' values in each place are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3) cases to the default already. This check was added in commit c045af25a52e9 in 2010; the added code was unnecessary then as well, and was apparently intended only to ensure that we never accidentally ended up indexing off the end of an sse_op_table with only 2 entries as a result of future bugs in the decode logic. Change the checks to assert() instead, and make sure they're always immediately before the array access they are protecting. Fixes: Coverity CID 1460207 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e9e1451540..05f9336c9b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3519,9 +3519,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x171: /* shift xmm, im */ case 0x172: case 0x173: - if (b1 >= 2) { - goto unknown_op; - } val = x86_ldub_code(env, s); if (is_xmm) { tcg_gen_movi_tl(s->T0, val); @@ -3540,6 +3537,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } + assert(b1 < 2); sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; if (!sse_fn_epp) { @@ -3770,10 +3768,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = modrm & 7; reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; - if (b1 >= 2) { - goto unknown_op; - } + assert(b1 < 2); sse_fn_epp = sse_op_table6[b].op[b1]; if (!sse_fn_epp) { goto unknown_op; @@ -4200,10 +4196,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = modrm & 7; reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; - if (b1 >= 2) { - goto unknown_op; - } + assert(b1 < 2); sse_fn_eppi = sse_op_table7[b].op[b1]; if (!sse_fn_eppi) { goto unknown_op; From 9cafc0735f5451dd6c8845f2a5c2c73bd7a7580c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 29 Nov 2021 20:05:07 +0000 Subject: [PATCH 166/421] include/hw/i386: Don't include qemu-common.h in .h files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule. In fact, the include is not required at all, so we can just drop it from both files. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org --- include/hw/i386/microvm.h | 1 - include/hw/i386/x86.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 4d9c732d4b..efcbd926fd 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -18,7 +18,6 @@ #ifndef HW_I386_MICROVM_H #define HW_I386_MICROVM_H -#include "qemu-common.h" #include "exec/hwaddr.h" #include "qemu/notify.h" diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index bb1cfb8896..a145a30370 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -17,7 +17,6 @@ #ifndef HW_I386_X86_H #define HW_I386_X86_H -#include "qemu-common.h" #include "exec/hwaddr.h" #include "qemu/notify.h" From 70a37f7faacbff7dcafdd444db15a264e02b8db5 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 29 Nov 2021 20:05:08 +0000 Subject: [PATCH 167/421] target/hexagon/cpu.h: don't include qemu-common.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). Move the include to linux-user/hexagon/cpu_loop.c, which needs it for the declaration of cpu_exec_step_atomic(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org --- linux-user/hexagon/cpu_loop.c | 1 + target/hexagon/cpu.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 6b24cbaba9..e47f8348d5 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" #include "qemu.h" #include "user-internals.h" #include "cpu_loop-common.h" diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index de121d950f..58a0d3870b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -23,7 +23,6 @@ typedef struct CPUHexagonState CPUHexagonState; #include "fpu/softfloat-types.h" -#include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" From d073949f9c2327eddfd9361aa1d94cd129ed4948 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 29 Nov 2021 20:05:09 +0000 Subject: [PATCH 168/421] target/rx/cpu.h: Don't include qemu-common.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The qemu-common.h header is not supposed to be included from any other header files, only from .c files (as documented in a comment at the start of it). Nothing actually relies on target/rx/cpu.h including it, so we can just drop the include. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson Reviewed-by: Yoshinori Sato Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org --- target/rx/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 4ac71aec37..657db84ef0 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -20,7 +20,6 @@ #define RX_CPU_H #include "qemu/bitops.h" -#include "qemu-common.h" #include "hw/registerfields.h" #include "cpu-qom.h" From 3508c0fac2b7055a341d30e67968506c7ed4f797 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 29 Nov 2021 20:05:10 +0000 Subject: [PATCH 169/421] hw/arm: Don't include qemu-common.h unnecessarily MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A lot of C files in hw/arm include qemu-common.h when they don't need anything from it. Drop the include lines. omap1.c, pxa2xx.c and strongarm.c retain the include because they use it for the prototype of qemu_get_timedate(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Taylor Simpson Reviewed-by: Yoshinori Sato Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org --- hw/arm/boot.c | 1 - hw/arm/digic_boards.c | 1 - hw/arm/highbank.c | 1 - hw/arm/npcm7xx_boards.c | 1 - hw/arm/sbsa-ref.c | 1 - hw/arm/stm32f405_soc.c | 1 - hw/arm/vexpress.c | 1 - hw/arm/virt.c | 1 - 8 files changed, 8 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 74ad397b1f..399f8e837c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/error-report.h" #include "qapi/error.h" diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index b771a3d8b7..4093af09cb 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c3cb315dbc..4210894d81 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "hw/sysbus.h" diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index dec7d16ae5..aff8c87042 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -24,7 +24,6 @@ #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "sysemu/blockdev.h" diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 358714bd3e..dd944553f7 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index 0019b7f478..c07947d9f8 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/arm/stm32f405_soc.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 58481c0762..3e6d63c7f9 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "cpu.h" #include "hw/sysbus.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 30da05dfe0..3e2144e31a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -29,7 +29,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" From 52a9f60935d394953dd6b47d01bb7eb47bc2592f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Nov 2021 17:32:57 +0000 Subject: [PATCH 170/421] target/arm: Correct calculation of tlb range invalidate length MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The calculation of the length of TLB range invalidate operations in tlbi_aa64_range_get_length() is incorrect in two ways: * the NUM field is 5 bits, but we read only 4 bits * we miscalculate the page_shift value, because of an off-by-one error: TG 0b00 is invalid TG 0b01 is 4K granule size == 4096 == 2^12 TG 0b10 is 16K granule size == 16384 == 2^14 TG 0b11 is 64K granule size == 65536 == 2^16 so page_shift should be (TG - 1) * 2 + 12 Thanks to the bug report submitter Cha HyunSoo for identifying both these errors. Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org --- target/arm/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b317899a6..db837d53bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4519,18 +4519,18 @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, uint64_t exponent; uint64_t length; - num = extract64(value, 39, 4); + num = extract64(value, 39, 5); scale = extract64(value, 44, 2); page_size_granule = extract64(value, 46, 2); - page_shift = page_size_granule * 2 + 12; - if (page_size_granule == 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); return 0; } + page_shift = (page_size_granule - 1) * 2 + 12; + exponent = (5 * scale) + 1; length = (num + 1) << (exponent + page_shift); From 530cd6c26df47c4f294c6335c9829e6c968fe7a8 Mon Sep 17 00:00:00 2001 From: Patrick Venture Date: Fri, 3 Dec 2021 14:10:02 -0800 Subject: [PATCH 171/421] hw/net: npcm7xx_emc fix missing queue_flush MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rx_active boolean change to true should always trigger a try_read call that flushes the queue. Signed-off-by: Patrick Venture Reviewed-by: Philippe Mathieu-Daudé Message-id: 20211203221002.1719306-1-venture@google.com Signed-off-by: Peter Maydell --- hw/net/npcm7xx_emc.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c index 7c892f820f..545b2b7410 100644 --- a/hw/net/npcm7xx_emc.c +++ b/hw/net/npcm7xx_emc.c @@ -284,6 +284,12 @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) emc_set_mista(emc, mista_flag); } +static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) +{ + emc->rx_active = true; + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); +} + static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, const NPCM7xxEMCTxDesc *tx_desc, uint32_t desc_addr) @@ -581,13 +587,6 @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) return len; } -static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) -{ - if (emc_can_receive(qemu_get_queue(emc->nic))) { - qemu_flush_queued_packets(qemu_get_queue(emc->nic)); - } -} - static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) { NPCM7xxEMCState *emc = opaque; @@ -703,7 +702,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; } if (value & REG_MCMDR_RXON) { - emc->rx_active = true; + emc_enable_rx_and_flush(emc); } else { emc_halt_rx(emc, 0); } @@ -739,8 +738,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, break; case REG_RSDR: if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { - emc->rx_active = true; - emc_try_receive_next_packet(emc); + emc_enable_rx_and_flush(emc); } break; case REG_MIIDA: From cf1a5cc935c0a9e3952eaac480ba02361662a29f Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:09 +0000 Subject: [PATCH 172/421] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu When a virtio-iommu is instantiated, describe it using the ACPI VIOT table. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + hw/arm/virt-acpi-build.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2d37d29f02..e652590943 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -27,6 +27,7 @@ config ARM_VIRT select DIMM select ACPI_HW_REDUCED select ACPI_APEI + select ACPI_VIOT config CHEETAH bool diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 674f902652..d0f4867fdf 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -55,6 +55,7 @@ #include "kvm_arm.h" #include "migration/vmstate.h" #include "hw/acpi/ghes.h" +#include "hw/acpi/viot.h" #define ARM_SPI_BASE 32 @@ -1011,6 +1012,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) } #endif + if (vms->iommu == VIRT_IOMMU_VIRTIO) { + acpi_add_table(table_offsets, tables_blob); + build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, + vms->oem_id, vms->oem_table_id); + } + /* XSDT is pointed to by RSDP */ xsdt = tables_blob->len; build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, From 092cba0350f073d465492c39210a006e5cb18f63 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:10 +0000 Subject: [PATCH 173/421] hw/arm/virt: Remove device tree restriction for virtio-iommu virtio-iommu is now supported with ACPI VIOT as well as device tree. Remove the restriction that prevents from instantiating a virtio-iommu device under ACPI. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-3-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 10 ++-------- hw/virtio/virtio-iommu-pci.c | 12 ++---------- 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3e2144e31a..e621cada99 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2613,16 +2613,10 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, MachineClass *mc = MACHINE_GET_CLASS(machine); if (device_is_dynamic_sysbus(mc, dev) || - (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { + object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { return HOTPLUG_HANDLER(machine); } - if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { - VirtMachineState *vms = VIRT_MACHINE(machine); - - if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { - return HOTPLUG_HANDLER(machine); - } - } return NULL; } diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index a160ae6b41..6a1df7fe50 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -48,16 +48,8 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); - - error_setg(errp, - "%s machine fails to create iommu-map device tree bindings", - mc->name); - error_append_hint(errp, - "Check your machine implements a hotplug handler " - "for the virtio-iommu-pci device\n"); - error_append_hint(errp, "Check the guest is booted without FW or with " - "-no-acpi\n"); + error_setg(errp, "Check your machine implements a hotplug handler " + "for the virtio-iommu-pci device"); return; } for (int i = 0; i < s->nb_reserved_regions; i++) { From 80d28ccdb99de4f256f03977471dbf6544bb0df8 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:11 +0000 Subject: [PATCH 174/421] hw/arm/virt: Reject instantiation of multiple IOMMUs We do not support instantiating multiple IOMMUs. Before adding a virtio-iommu, check that no other IOMMU is present. This will detect both "iommu=smmuv3" machine parameter and another virtio-iommu instance. Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings") Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-4-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e621cada99..41c9808a3f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2493,6 +2493,11 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, hwaddr db_start = 0, db_end = 0; char *resv_prop_str; + if (vms->iommu != VIRT_IOMMU_NONE) { + error_setg(errp, "virt machine does not support multiple IOMMUs"); + return; + } + switch (vms->msi_controller) { case VIRT_MSI_CTRL_NONE: return; From 317500fea815937ecb1b4e2e04b5159ae8bf3b79 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:12 +0000 Subject: [PATCH 175/421] hw/arm/virt: Use object_property_set instead of qdev_prop_set To propagate errors to the caller of the pre_plug callback, use the object_poperty_set*() functions directly instead of the qdev_prop_set*() helpers. Suggested-by: Igor Mammedov Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-5-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 41c9808a3f..6bce595aba 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2517,8 +2517,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, db_start, db_end, VIRTIO_IOMMU_RESV_MEM_T_MSI); - qdev_prop_set_uint32(dev, "len-reserved-regions", 1); - qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); + object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); + object_property_set_str(OBJECT(dev), "reserved-regions[0]", + resv_prop_str, errp); g_free(resv_prop_str); } } From 641f32f6845048eff0e1d729d1be7e26ea3784c5 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:13 +0000 Subject: [PATCH 176/421] tests/acpi: allow updates of VIOT expected data files Create empty data files and allow updates for the upcoming VIOT tests. Acked-by: Igor Mammedov Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-6-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/data/acpi/q35/DSDT.viot | 0 tests/data/acpi/q35/VIOT.viot | 0 tests/data/acpi/virt/VIOT | 0 tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 4 files changed, 3 insertions(+) create mode 100644 tests/data/acpi/q35/DSDT.viot create mode 100644 tests/data/acpi/q35/VIOT.viot create mode 100644 tests/data/acpi/virt/VIOT diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..29b5b1eabc 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/VIOT", +"tests/data/acpi/q35/DSDT.viot", +"tests/data/acpi/q35/VIOT.viot", From 39d7554b2009157571089ab4c7a3630e0090edd7 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:14 +0000 Subject: [PATCH 177/421] tests/acpi: add test case for VIOT Add two test cases for VIOT, one on the q35 machine and the other on virt. To test complex topologies the q35 test has two PCIe buses that bypass the IOMMU (and are therefore not described by VIOT), and two buses that are translated by virtio-iommu. Reviewed-by: Eric Auger Reviewed-by: Igor Mammedov Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-7-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 258874167e..58df53b15b 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1465,6 +1465,42 @@ static void test_acpi_virt_tcg(void) free_test_data(&data); } +static void test_acpi_q35_viot(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".viot", + }; + + /* + * To keep things interesting, two buses bypass the IOMMU. + * VIOT should only describes the other two buses. + */ + test_acpi_one("-machine default_bus_bypass_iommu=on " + "-device virtio-iommu-pci " + "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 " + "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on " + "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0", + &data); + free_test_data(&data); +} + +static void test_acpi_virt_viot(void) +{ + test_data data = { + .machine = "virt", + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57 " + "-device virtio-iommu-pci", &data); + free_test_data(&data); +} + static void test_oem_fields(test_data *data) { int i; @@ -1639,6 +1675,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); } + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); } else if (strcmp(arch, "aarch64") == 0) { if (has_tcg) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); @@ -1646,6 +1683,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); } } ret = g_test_run(); From cf7a348837f43672f721c7d8e9d88c921424fe88 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:15 +0000 Subject: [PATCH 178/421] tests/acpi: add expected blobs for VIOT test on q35 machine Add expected blobs of the VIOT and DSDT table for the VIOT test on the q35 machine. Since the test instantiates a virtio device and two PCIe expander bridges, DSDT.viot has more blocks than the base DSDT. The VIOT table generated for the q35 test is: [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] [004h 0004 4] Table Length : 00000070 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 3D [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 2] Node count : 0003 [026h 0038 2] Node offset : 0030 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] [031h 0049 1] Reserved : 00 [032h 0050 2] Length : 0010 [034h 0052 2] PCI Segment : 0000 [036h 0054 2] PCI BDF number : 0010 [038h 0056 8] Reserved : 0000000000000000 [040h 0064 1] Type : 01 [PCI Range] [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 [044h 0068 4] Endpoint start : 00003000 [048h 0072 2] PCI Segment start : 0000 [04Ah 0074 2] PCI Segment end : 0000 [04Ch 0076 2] PCI BDF start : 3000 [04Eh 0078 2] PCI BDF end : 30FF [050h 0080 2] Output node : 0030 [052h 0082 6] Reserved : 000000000000 [058h 0088 1] Type : 01 [PCI Range] [059h 0089 1] Reserved : 00 [05Ah 0090 2] Length : 0018 [05Ch 0092 4] Endpoint start : 00001000 [060h 0096 2] PCI Segment start : 0000 [062h 0098 2] PCI Segment end : 0000 [064h 0100 2] PCI BDF start : 1000 [066h 0102 2] PCI BDF end : 10FF [068h 0104 2] Output node : 0030 [06Ah 0106 6] Reserved : 000000000000 And the DSDT diff is: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021 + * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00002061 (8289) + * Length 0x000024B6 (9398) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFA + * Checksum 0xA7 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -3114,6 +3114,339 @@ } } + Scope (\_SB) + { + Device (PC30) + { + Name (_UID, 0x30) // _UID: Unique ID + Name (_BBN, 0x30) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0030, // Range Minimum + 0x0030, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + + Scope (\_SB) + { + Device (PC20) + { + Name (_UID, 0x20) // _UID: Unique ID + Name (_BBN, 0x20) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0020, // Range Minimum + 0x0020, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + + Scope (\_SB) + { + Device (PC10) + { + Name (_UID, 0x10) // _UID: Unique ID + Name (_BBN, 0x10) // _BBN: BIOS Bus Number + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0010, // Range Minimum + 0x0010, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + } + } + Scope (\_SB.PCI0) { Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings @@ -3121,9 +3454,9 @@ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum - 0x00FF, // Range Maximum + 0x000F, // Range Maximum 0x0000, // Translation Offset - 0x0100, // Length + 0x0010, // Length ,, ) IO (Decode16, 0x0CF8, // Range Minimum @@ -3278,6 +3611,26 @@ } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + } + + Device (S20) + { + Name (_ADR, 0x00040000) // _ADR: Address + } + + Device (S28) + { + Name (_ADR, 0x00050000) // _ADR: Address + } + Method (PCNT, 0, NotSerialized) { } Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-8-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..1c3b4da5cbe81ecab5e1ef50d383b561c5e0f55f 100644 GIT binary patch literal 9398 zcmeHNO>7&-8J*>iv|O&FB}G~Oi$yp||57BBoWHhc5OS9yDTx$CQgH$r;8Idr*-4Q_ z5(9Az1F`}niVsB-)S~D)a>NF1~WVB6^~_B#yhJ`H+JU@=6aXs`?Yv)J2h=N?drcS zeLZ*n<JRPm3~# z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW% z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^ z;s;dJec!hnzi)ri^I6YN9vtkm{^TdUF8h7gX8-F3atdZn=zv3$#RmZzSHN+6-yyU#8cJb=YDilX&sl}vNm znkgAR^O<3kj4if>{ly5fwRfMWuC5=lrlvKPX~i#654Cp}R_d*JS$9laZ$ra6)LDi%Gxz_v_W8VX$W-Fg-qFWcT}7MCyz{%%{ia7hZ>Law-k6NOr}VI&_48U=2l zwqDKFE8eTwwozDdms#e?x?5a|v>&JF;2_v0L~z5n%BYU^52<*cWuD4|GYUm@1+?)) zte^45>Rz)t*@t@{%?^i#W{i=HAZ*Dc9y59Va-+#P!jrGs;u38a{fLr`N zvT@rUu>DljxJ?^&Z?-?vyJn3C>3D=qux{Y*bs5|5n)Qmi$TD^Zdn4GU$ocJS2Hh-< z`xPI^^+v0nUVdjMos8k`WGl7hA`{03ju%ckUB>FI=~GokB5sOq#dotCE4(sd$KbtW~PNlj-`*NIToiD#j5J#9^= zt?NXn>YUJYPG~wObe#xQos*i*NloXZt`niEb4t@WrRki~bs|)CI+{*L)9L6s5vn>< zn$DD_Go|Z9sOn5>I@6lYw5}7Os&iV?Ij!lO)^#FOb!If38BJ$K*NIToIiu;E(R9w} zIuWWmPiZ<&X*y5oIuWWmF_XaEC!a&Jn$B5WCqh-{X-(&8P3LJ{Cqh-{8P3dyPr@^t zSqL9?X9Uwd3W@23*s~h*tj0X6GZCuHa~kuU#yqDp5vt7d8uPryJg+kms?5hU=3^T3 zF`bD}WnSP+=`t5MQ$FJ_2&Q~+BP6E0f^%BVIW6a$o)e+SX~IDBih-7z6{O~7YTy`& zLjy&Cv?7QikV#>n0>>@MV8oK`Gmun34-FKdlm-J8SZSaNlnhir4-FI{S|bfqV8e)V zss<{chX#reE#g=hsKAC%sF6d-Km}BWs!kZFsFpKfpbC@>6rprQGEjt4Ck#|zITHq| zK*>M_l;3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=xY&!axO< zGhv_#lnhirIg<<&q0|Wj6M_lrzad5lWpf zP=V!47^ngz0~JutBm+e#b;3XemNQ|X3X}{~Ksl2P6rt1!0~J`#gn=qhGEf2KOfpb} zQYQ>lU^x>8szAv=1(Y+%KoLrvFi?TzOcu&LjgxD0RX>1(q{mpbC@>R6seC z3>2Z%2?G^a&V+#~P%=;f=3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=rz^3{+q_69%e4 z$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axxz28u{EP=u<1B2)}iVZuNaCK;&0 zBm-5LFi?dF167!0pbC==RAItE6($T+VUmF=Ofpb~2?JG_Fi?d_2C6X0Kouqo6p_5T zFi=FeV!SiSKoR0H$dH(_Z(*Q_WZ%L-5y`$K14StNmJAdjmWs}HV4N_U)fP6Qy6Nw5mbt9Y(#emWSi66=>tq#xoh#Ue=0qyhxi8ZOUe5y0V7VfPUhp zwX=;ymc+i5%sg9Ja~lZ&8oAV@mHc>&CHP9v4R(jhtT?un;O4e9#pno)Xkh7OWgK&a zyj=3Iv0OuoK_;5rOr5f(Kb~ZXDBO+V`OWYo#_C08imwChQxnjdd?wZLDou8aj;$SD zGDYiA3<$TuEdF(l3VTOM~ghPLRH&q%ZOGrGfON zW73zx^yR_y<0nX8R??Sw`tm^f@-gYlNFSp|* zVReJU*h=ZuVXiS$ohTbw-O#v9>(yZbGE|)?8(H1ZIKvV!jWa0>vy!3eMA^vdhQ>`s zuMSg{q3T50$m)j1!HixV<}X9liL#N^4c*tL^y)CF8LCc{jjV3yKAqL8!%SzWI#H%q z=bSrQ&)%JCRttF5g4Zf`6l?y@>PzD7MA^D>wBlcH6r1ucwJ`a5r3e|z)wcUaqS>nqFQ-8x}eCF4u`OWUxqst-@1rSmUs%WmKP5e0dcb?e2N z;Z|x*!);VwF|Yuhqs^khqOM!@u*jY!WYldISF(V6`BoNd&6Qfk3>X#SuD^7J>p_D= zBPa51y^_n#=cpOt#Zf$ya$Ae9Mfz56n|KnY%4JQfOYS$*uU%f#@$U6`N8I3N-lV?5ErFCdv~xDmu2(wexld4 z4v^;aVAT2k6GJ^m*FD(Wqc(Qg^)6a-Obg6yV`8o$8_`PyJe_;bY5_EMBfBfWU!Q=*9HsG z%_Cda{@_Krr!oHVhv9+y+T5qR8zZ2aZ>5r!$*|f$^U%yBUYfR&B!+EYy_PwL!BeUi zJH^}r3r9Q+B)X@Z)fk=P13w&7x#wBtXTZ)g>WITPg5r&pQc!nmyrmk#S(>>b9xnNr zx_b#v9Xv-Y>jcOVhS*0rS~RS1dA#xhkv@Nct@#q?LyeKS<$uFec!bw>{@uu$gZ6a zyVen1i{1BKd%~`D7|m$;U0a38zM0sT&6X~cwUxUL8G1KT)_XTp!KAbs;vCp{K3&~_X@+ew=-D}v`2MbFV0 zQsVsL=rXi-pI*G|iiz;VTCutgUs)hDzV1+4?8KcoP3xROfS+TT-130 literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..9b179266ccbf84f1c250ee646812d17e27987764 100644 GIT binary patch literal 112 zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj Q0Zb)W9Hva*zW_`e0M!8s0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 29b5b1eabc..8367ffe1d4 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1,2 @@ /* List of comma-separated changed AML files to ignore */ "tests/data/acpi/virt/VIOT", -"tests/data/acpi/q35/DSDT.viot", -"tests/data/acpi/q35/VIOT.viot", From aed176558806674d030a8305d989d4e6a5073359 Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 10 Dec 2021 17:04:16 +0000 Subject: [PATCH 179/421] tests/acpi: add expected blob for VIOT test on virt machine The VIOT blob contains the following: [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] [004h 0004 4] Table Length : 00000058 [008h 0008 1] Revision : 00 [009h 0009 1] Checksum : 66 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 2] Node count : 0002 [026h 0038 2] Node offset : 0030 [028h 0040 8] Reserved : 0000000000000000 [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] [031h 0049 1] Reserved : 00 [032h 0050 2] Length : 0010 [034h 0052 2] PCI Segment : 0000 [036h 0054 2] PCI BDF number : 0008 [038h 0056 8] Reserved : 0000000000000000 [040h 0064 1] Type : 01 [PCI Range] [041h 0065 1] Reserved : 00 [042h 0066 2] Length : 0018 [044h 0068 4] Endpoint start : 00000000 [048h 0072 2] PCI Segment start : 0000 [04Ah 0074 2] PCI Segment end : 0000 [04Ch 0076 2] PCI BDF start : 0000 [04Eh 0078 2] PCI BDF end : 00FF [050h 0080 2] Output node : 0030 [052h 0082 6] Reserved : 000000000000 Acked-by: Ani Sinha Reviewed-by: Eric Auger Signed-off-by: Jean-Philippe Brucker Message-id: 20211210170415.583179-9-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..921f40d88c28ba2171a4d664e119914335309e7d 100644 GIT binary patch literal 88 zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX I{D-Rq0Q5fy0RR91 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index 8367ffe1d4..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/VIOT", From 97ca6c2786e5dd1fd689c52ffe0cb082bc8bd477 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:06 +0100 Subject: [PATCH 180/421] hw/arm/xlnx-zcu102: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "xlnx-zcu102" connects backends with drive_get_next() in several counting loops. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: Alistair Francis Cc: "Edgar E. Iglesias" Cc: Peter Maydell Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-11-armbru@redhat.com> Acked-by: Edgar E. Iglesias --- hw/arm/xlnx-zcu102.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 3dc2b5e8ca..45eb19ab3b 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -169,7 +169,7 @@ static void xlnx_zcu102_init(MachineState *machine) /* Create and plug in the SD cards */ for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { BusState *bus; - DriveInfo *di = drive_get_next(IF_SD); + DriveInfo *di = drive_get(IF_SD, 0, i); BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; DeviceState *carddev; char *bus_name; @@ -190,7 +190,7 @@ static void xlnx_zcu102_init(MachineState *machine) BusState *spi_bus; DeviceState *flash_dev; qemu_irq cs_line; - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, i); gchar *bus_name = g_strdup_printf("spi%d", i); spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name); @@ -212,7 +212,7 @@ static void xlnx_zcu102_init(MachineState *machine) BusState *spi_bus; DeviceState *flash_dev; qemu_irq cs_line; - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, XLNX_ZYNQMP_NUM_SPIS + i); int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; gchar *bus_name = g_strdup_printf("qspi%d", bus); From 94d4bb4ff9c557dcb68cd16a287700dd9218bd1c Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:07 +0100 Subject: [PATCH 181/421] hw/arm/xilinx_zynq: Replace drive_get_next() by drive_get() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. Machine "xlnx-zcu102" connects backends with drive_get_next() in two counting loops, one of them in a helper function. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: "Edgar E. Iglesias" Cc: Alistair Francis Cc: Peter Maydell Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-12-armbru@redhat.com> Acked-by: Edgar E. Iglesias --- hw/arm/xilinx_zynq.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 69c333e91b..50e7268396 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -125,9 +125,10 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } -static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi) +static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, + bool is_qspi, int unit0) { + int unit = unit0; DeviceState *dev; SysBusDevice *busdev; SSIBus *spi; @@ -156,7 +157,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); for (j = 0; j < num_ss; ++j) { - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); flash_dev = qdev_new("n25q128"); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", @@ -170,6 +171,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, } } + return unit; } static void zynq_init(MachineState *machine) @@ -247,9 +249,9 @@ static void zynq_init(MachineState *machine) pic[n] = qdev_get_gpio_in(dev, n); } - zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); - zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); - zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); + n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0); + n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n); + n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); @@ -298,7 +300,7 @@ static void zynq_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, n); blk = di ? blk_by_legacy_dinfo(di) : NULL; carddev = qdev_new(TYPE_SD_CARD); qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); From 8ec239f2d80bed82ad5a361ddfb9ca3560a45ad8 Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:08 +0100 Subject: [PATCH 182/421] hw/arm/aspeed: Replace drive_get_next() by drive_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. The aspeed machines connects backends with drive_get_next() in several counting loops, one of them in a helper function, and a conditional. Change it to use drive_get() directly. This makes the unit numbers explicit in the code. Cc: "Cédric Le Goater" Cc: Peter Maydell Cc: Andrew Jeffery Cc: Joel Stanley Cc: qemu-arm@nongnu.org Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-13-armbru@redhat.com> Reviewed-by: Cédric Le Goater --- hw/arm/aspeed.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a77f46b3ad..cf20ae0db5 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -284,12 +284,13 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, } static void aspeed_board_init_flashes(AspeedSMCState *s, - const char *flashtype) + const char *flashtype, + int unit0) { int i ; for (i = 0; i < s->num_cs; ++i) { - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); qemu_irq cs_line; DeviceState *dev; @@ -382,10 +383,12 @@ static void aspeed_machine_init(MachineState *machine) "max_ram", max_ram_size - machine->ram_size); memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); - aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? - bmc->fmc_model : amc->fmc_model); - aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? - bmc->spi_model : amc->spi_model); + aspeed_board_init_flashes(&bmc->soc.fmc, + bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, + 0); + aspeed_board_init_flashes(&bmc->soc.spi[0], + bmc->spi_model ? bmc->spi_model : amc->spi_model, + bmc->soc.fmc.num_cs); /* Install first FMC flash content as a boot rom. */ if (drive0) { @@ -435,11 +438,13 @@ static void aspeed_machine_init(MachineState *machine) } for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { - sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], + drive_get(IF_SD, 0, i)); } if (bmc->soc.emmc.num_slots) { - sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); + sdhci_attach_drive(&bmc->soc.emmc.slots[0], + drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); } arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); From 95fd260f0a3663ed229b8e0d2ef111a9f8bd93ad Mon Sep 17 00:00:00 2001 From: Markus Armbruster Date: Wed, 17 Nov 2021 17:34:09 +0100 Subject: [PATCH 183/421] blockdev: Drop unused drive_get_next() drive_get_next() is basically a bad idea. It returns the "next" block backend of a certain interface type. "Next" means bus=0,unit=N, where subsequent calls count N up from zero, per interface type. This lets you define unit numbers implicitly by execution order. If the order changes, or new calls appear "in the middle", unit numbers change. ABI break. Hard to spot in review. The previous commits eliminated all uses. Drop the function. Cc: Kevin Wolf Cc: Hanna Reitz Signed-off-by: Markus Armbruster Message-Id: <20211117163409.3587705-14-armbru@redhat.com> Reviewed-by: Hanna Reitz --- blockdev.c | 10 ---------- include/sysemu/blockdev.h | 1 - 2 files changed, 11 deletions(-) diff --git a/blockdev.c b/blockdev.c index b35072644e..0eb2823b1b 100644 --- a/blockdev.c +++ b/blockdev.c @@ -303,16 +303,6 @@ int drive_get_max_bus(BlockInterfaceType type) return max_bus; } -/* Get a block device. This should only be used for single-drive devices - (e.g. SD/Floppy/MTD). Multi-disk devices (scsi/ide) should use the - appropriate bus. */ -DriveInfo *drive_get_next(BlockInterfaceType type) -{ - static int next_block_unit[IF_COUNT]; - - return drive_get(type, 0, next_block_unit[type]++); -} - static void bdrv_format_print(void *opaque, const char *name) { qemu_printf(" %s", name); diff --git a/include/sysemu/blockdev.h b/include/sysemu/blockdev.h index 32c2d6023c..a750f99b79 100644 --- a/include/sysemu/blockdev.h +++ b/include/sysemu/blockdev.h @@ -50,7 +50,6 @@ void drive_check_orphaned(void); DriveInfo *drive_get_by_index(BlockInterfaceType type, int index); int drive_get_max_bus(BlockInterfaceType type); int drive_get_max_devs(BlockInterfaceType type); -DriveInfo *drive_get_next(BlockInterfaceType type); QemuOpts *drive_def(const char *optstr); QemuOpts *drive_add(BlockInterfaceType type, int index, const char *file, From 69a80f14ce5ce7461734698cdb919616ee9459ff Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Thu, 16 Dec 2021 09:15:06 +0000 Subject: [PATCH 184/421] tests/qtest/bios-tables-test: Only run VIOT test on TCG The VIOT test does not always work under KVM on the virt machine: PASS 5 qtest-aarch64/bios-tables-test /aarch64/acpi/virt/oem-fields qemu-system-aarch64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument Broken pipe Make it TCG only. Reported-by: Richard Henderson Signed-off-by: Jean-Philippe Brucker Signed-off-by: Richard Henderson --- tests/qtest/bios-tables-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 58df53b15b..9a468e29eb 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1489,6 +1489,7 @@ static void test_acpi_virt_viot(void) { test_data data = { .machine = "virt", + .tcg_only = true, .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", From c35aff184b2ed5be930da671ea25c857713555af Mon Sep 17 00:00:00 2001 From: Collin Walling Date: Wed, 17 Nov 2021 10:23:03 -0500 Subject: [PATCH 185/421] s390: kvm: adjust diag318 resets to retain data The CPNC portion of the diag318 data is erroneously reset during an initial CPU reset caused by SIGP. Let's go ahead and relocate the diag318_info field within the CPUS390XState struct such that it is only zeroed during a clear reset. This way, the CPNC will be retained for each VCPU in the configuration after the diag318 instruction has been invoked. The s390_machine_reset code already takes care of zeroing the diag318 data on VM resets, which also cover resets caused by diag308. Fixes: fabdada9357b ("s390: guest support for diagnose 0x318") Reported-by: Christian Borntraeger Signed-off-by: Collin Walling Reviewed-by: Janosch Frank Reviewed-by: Christian Borntraeger Message-Id: <20211117152303.627969-1-walling@linux.ibm.com> Signed-off-by: Thomas Huth --- target/s390x/cpu.h | 4 ++-- target/s390x/kvm/kvm.c | 4 ++++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index ca3845d023..a75e559134 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -63,6 +63,8 @@ struct CPUS390XState { uint64_t etoken; /* etoken */ uint64_t etoken_extension; /* etoken extension */ + uint64_t diag318_info; + /* Fields up to this point are not cleared by initial CPU reset */ struct {} start_initial_reset_fields; @@ -118,8 +120,6 @@ struct CPUS390XState { uint16_t external_call_addr; DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); - uint64_t diag318_info; - #if !defined(CONFIG_USER_ONLY) uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ int tlb_fill_exc; /* exception number seen during tlb_fill */ diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 5b1fdb55c4..6acf14d5ec 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1585,6 +1585,10 @@ void kvm_s390_set_diag318(CPUState *cs, uint64_t diag318_info) env->diag318_info = diag318_info; cs->kvm_run->s.regs.diag318 = diag318_info; cs->kvm_run->kvm_dirty_regs |= KVM_SYNC_DIAG318; + /* + * diag 318 info is zeroed during a clear reset and + * diag 308 IPL subcodes. + */ } } From 2c092950a4766307e3d14f3764f7610d551515b9 Mon Sep 17 00:00:00 2001 From: Christian Borntraeger Date: Fri, 26 Nov 2021 11:24:49 +0100 Subject: [PATCH 186/421] MAINTAINERS: update email address of Christian Borntraeger My borntraeger@de.ibm.com email is just a forwarder to the linux.ibm.com address. Let us remove the extra hop to avoid a potential source of errors. While at it, add the relevant email addresses to mailmap. Signed-off-by: Christian Borntraeger Message-Id: <20211126102449.287524-1-borntraeger@linux.ibm.com> Signed-off-by: Thomas Huth --- .mailmap | 1 + MAINTAINERS | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.mailmap b/.mailmap index 8beb2f95ae..c45d1c5301 100644 --- a/.mailmap +++ b/.mailmap @@ -50,6 +50,7 @@ Aleksandar Rikalo Aleksandar Rikalo Alexander Graf Anthony Liguori Anthony Liguori +Christian Borntraeger Filip Bozuta Frederic Konrad Greg Kurz diff --git a/MAINTAINERS b/MAINTAINERS index fbd6d0b174..9a8d1bdf72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -393,7 +393,7 @@ F: target/ppc/kvm.c S390 KVM CPUs M: Halil Pasic -M: Christian Borntraeger +M: Christian Borntraeger S: Supported F: target/s390x/kvm/ F: target/s390x/ioinst.[ch] @@ -1527,7 +1527,7 @@ S390 Machines ------------- S390 Virtio-ccw M: Halil Pasic -M: Christian Borntraeger +M: Christian Borntraeger S: Supported F: hw/char/sclp*.[hc] F: hw/char/terminal3270.c @@ -1541,7 +1541,7 @@ T: git https://github.com/borntraeger/qemu.git s390-next L: qemu-s390x@nongnu.org S390-ccw boot -M: Christian Borntraeger +M: Christian Borntraeger M: Thomas Huth S: Supported F: hw/s390x/ipl.* From b2892a2b9d45d25b909108ca633d19f9d8d673f5 Mon Sep 17 00:00:00 2001 From: Matthew Rosato Date: Fri, 3 Dec 2021 09:27:03 -0500 Subject: [PATCH 187/421] s390x/pci: use a reserved ID for the default PCI group The current default PCI group being used can technically collide with a real group ID passed from a hostdev. Let's instead use a group ID that comes from a special pool (0xF0-0xFF) that is architected to be reserved for simulated devices. Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure") Signed-off-by: Matthew Rosato Reviewed-by: Eric Farman Reviewed-by: Pierre Morel Message-Id: <20211203142706.427279-2-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth --- include/hw/s390x/s390-pci-bus.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/s390x/s390-pci-bus.h b/include/hw/s390x/s390-pci-bus.h index aa891c178d..2727e7bdef 100644 --- a/include/hw/s390x/s390-pci-bus.h +++ b/include/hw/s390x/s390-pci-bus.h @@ -313,7 +313,7 @@ typedef struct ZpciFmb { } ZpciFmb; QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb"); -#define ZPCI_DEFAULT_FN_GRP 0x20 +#define ZPCI_DEFAULT_FN_GRP 0xFF typedef struct S390PCIGroup { ClpRspQueryPciGrp zpci_group; int id; From df7ce0a94d9283f0656b4bc0f21566973ff649a3 Mon Sep 17 00:00:00 2001 From: Matthew Rosato Date: Fri, 3 Dec 2021 09:27:04 -0500 Subject: [PATCH 188/421] s390x/pci: don't use hard-coded dma range in reg_ioat Instead use the values from clp info, they will either be the hard-coded values or what came from the host driver via vfio. Fixes: 9670ee752727 ("s390x/pci: use a PCI Function structure") Signed-off-by: Matthew Rosato Reviewed-by: Eric Farman Reviewed-by: Pierre Morel Message-Id: <20211203142706.427279-3-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth --- hw/s390x/s390-pci-inst.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 1c8ad91175..11b7f6bfa1 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -916,9 +916,10 @@ int pci_dereg_irqs(S390PCIBusDevice *pbdev) return 0; } -static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, +static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib, uintptr_t ra) { + S390PCIIOMMU *iommu = pbdev->iommu; uint64_t pba = ldq_p(&fib.pba); uint64_t pal = ldq_p(&fib.pal); uint64_t g_iota = ldq_p(&fib.iota); @@ -927,7 +928,7 @@ static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, pba &= ~0xfff; pal |= 0xfff; - if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { + if (pba > pal || pba < pbdev->zpci_fn.sdma || pal > pbdev->zpci_fn.edma) { s390_program_interrupt(env, PGM_OPERAND, ra); return -EINVAL; } @@ -1125,7 +1126,7 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, } else if (pbdev->iommu->enabled) { cc = ZPCI_PCI_LS_ERR; s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); - } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { + } else if (reg_ioat(env, pbdev, fib, ra)) { cc = ZPCI_PCI_LS_ERR; s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); } @@ -1150,7 +1151,7 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); } else { pci_dereg_ioat(pbdev->iommu); - if (reg_ioat(env, pbdev->iommu, fib, ra)) { + if (reg_ioat(env, pbdev, fib, ra)) { cc = ZPCI_PCI_LS_ERR; s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); } From cb6d6a3e6aa1226b67fd218953dcb3866c3a6845 Mon Sep 17 00:00:00 2001 From: Matthew Rosato Date: Fri, 3 Dec 2021 09:27:05 -0500 Subject: [PATCH 189/421] s390x/pci: use the passthrough measurement update interval We may have gotten a measurement update interval from the underlying host via vfio -- Use it to set the interval via which we update the function measurement block. Fixes: 28dc86a072 ("s390x/pci: use a PCI Group structure") Signed-off-by: Matthew Rosato Reviewed-by: Eric Farman Reviewed-by: Pierre Morel Message-Id: <20211203142706.427279-4-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth --- hw/s390x/s390-pci-inst.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 11b7f6bfa1..07bab85ce5 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -1046,7 +1046,7 @@ static void fmb_update(void *opaque) sizeof(pbdev->fmb.last_update))) { return; } - timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI); + timer_mod(pbdev->fmb_timer, t + pbdev->pci_group->zpci_group.mui); } int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, @@ -1204,7 +1204,8 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, } pbdev->fmb_addr = fmb_addr; timer_mod(pbdev->fmb_timer, - qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI); + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + pbdev->pci_group->zpci_group.mui); break; } default: From ac6aa30ac47b2abaf142f76de46374da2a98f6e7 Mon Sep 17 00:00:00 2001 From: Matthew Rosato Date: Fri, 3 Dec 2021 09:27:06 -0500 Subject: [PATCH 190/421] s390x/pci: add supported DT information to clp response The DTSM is a mask that specifies which I/O Address Translation designation types are supported. Today QEMU only supports DT=1. Signed-off-by: Matthew Rosato Reviewed-by: Eric Farman Reviewed-by: Pierre Morel Message-Id: <20211203142706.427279-5-mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth --- hw/s390x/s390-pci-bus.c | 1 + hw/s390x/s390-pci-inst.c | 1 + hw/s390x/s390-pci-vfio.c | 1 + include/hw/s390x/s390-pci-bus.h | 1 + include/hw/s390x/s390-pci-clp.h | 3 ++- 5 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 1b51a72838..01b58ebc70 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -782,6 +782,7 @@ static void s390_pci_init_default_group(void) resgrp->i = 128; resgrp->maxstbl = 128; resgrp->version = 0; + resgrp->dtsm = ZPCI_DTSM; } static void set_pbdev_info(S390PCIBusDevice *pbdev) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 07bab85ce5..6d400d4147 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -329,6 +329,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) stw_p(&resgrp->i, group->zpci_group.i); stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl); resgrp->version = group->zpci_group.version; + resgrp->dtsm = group->zpci_group.dtsm; stw_p(&resgrp->hdr.rsp, CLP_RC_OK); break; } diff --git a/hw/s390x/s390-pci-vfio.c b/hw/s390x/s390-pci-vfio.c index 2a153fa8c9..6f80a47e29 100644 --- a/hw/s390x/s390-pci-vfio.c +++ b/hw/s390x/s390-pci-vfio.c @@ -160,6 +160,7 @@ static void s390_pci_read_group(S390PCIBusDevice *pbdev, resgrp->i = cap->noi; resgrp->maxstbl = cap->maxstbl; resgrp->version = cap->version; + resgrp->dtsm = ZPCI_DTSM; } } diff --git a/include/hw/s390x/s390-pci-bus.h b/include/hw/s390x/s390-pci-bus.h index 2727e7bdef..da3cde2bb4 100644 --- a/include/hw/s390x/s390-pci-bus.h +++ b/include/hw/s390x/s390-pci-bus.h @@ -37,6 +37,7 @@ #define ZPCI_MAX_UID 0xffff #define UID_UNDEFINED 0 #define UID_CHECKING_ENABLED 0x01 +#define ZPCI_DTSM 0x40 OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE) OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS) diff --git a/include/hw/s390x/s390-pci-clp.h b/include/hw/s390x/s390-pci-clp.h index 96b8e3f133..cc8c8662b8 100644 --- a/include/hw/s390x/s390-pci-clp.h +++ b/include/hw/s390x/s390-pci-clp.h @@ -163,7 +163,8 @@ typedef struct ClpRspQueryPciGrp { uint8_t fr; uint16_t maxstbl; uint16_t mui; - uint64_t reserved3; + uint8_t dtsm; + uint8_t reserved3[7]; uint64_t dasm; /* dma address space mask */ uint64_t msia; /* MSI address */ uint64_t reserved4; From 9f8e6cad65a66b27e797defe639a4a4fd4330f23 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Thu, 16 Dec 2021 09:22:53 +0100 Subject: [PATCH 191/421] gitlab-ci: Speed up the msys2-64bit job by using --without-default-devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new msys2-64bit job is often running for more than 50 minutes - and if the CI is currently loaded, it times out after 60 minutes. The job has been declared with a bigger timeout, but seems like this is getting ignored on the shared Gitlab-CI Windows runners, so we're currently seeing a lot of failures with this job. Thus we have to reduce the time it takes to finish this job. Since we want to test compiling the WHPX and HAX accelerator code with this job, switching to another target CPU is not really a good option, so let's reduce the amount of code that we have to compile with the --without-default-devices switch instead. Message-Id: <20211216082253.43899-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- .gitlab-ci.d/windows.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml index 309f7e7fb8..62dd9ed832 100644 --- a/.gitlab-ci.d/windows.yml +++ b/.gitlab-ci.d/windows.yml @@ -58,7 +58,7 @@ msys2-64bit: - $env:CHERE_INVOKING = 'yes' # Preserve the current working directory - $env:MSYSTEM = 'MINGW64' # Start a 64 bit Mingw environment - .\msys64\usr\bin\bash -lc './configure --target-list=x86_64-softmmu - --enable-capstone=system' + --enable-capstone=system --without-default-devices' - .\msys64\usr\bin\bash -lc "sed -i '/^ROMS=/d' build/config-host.mak" - .\msys64\usr\bin\bash -lc 'make -j2' - .\msys64\usr\bin\bash -lc 'make check' From 57a93f16e8dad554720edcc5ed1fe613d68bf230 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 9 Nov 2021 15:45:04 +0100 Subject: [PATCH 192/421] configure: Symlink binaries using .exe suffix with MinGW MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When using the MinGW toolchain, we use the .exe suffix for the executable name. We also need to use it for the symlinks in the build directory. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Weil Acked-by: Paolo Bonzini Message-Id: <20211109144504.1541206-1-philmd@redhat.com> Signed-off-by: Laurent Vivier --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 5fae19858d..28e1cf6291 100755 --- a/configure +++ b/configure @@ -3754,7 +3754,7 @@ fi for target in $target_list; do target_dir="$target" - target_name=$(echo $target | cut -d '-' -f 1) + target_name=$(echo $target | cut -d '-' -f 1)$EXESUF mkdir -p $target_dir case $target in *-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" ;; From dc7d6cafce8a7d36d2ebc03be3b6162e0eb98c22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 16 Nov 2021 20:39:55 +0100 Subject: [PATCH 193/421] target/i386/kvm: Replace use of __u32 type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QEMU coding style mandates to not use Linux kernel internal types for scalars types. Replace __u32 by uint32_t. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211116193955.2793171-1-philmd@redhat.com> Signed-off-by: Laurent Vivier --- target/i386/kvm/kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 5a698bde19..13f8e30c2a 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1406,7 +1406,7 @@ static int hyperv_fill_cpuids(CPUState *cs, c->edx = cpu->hyperv_limits[2]; if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { - __u32 function; + uint32_t function; /* Create zeroed 0x40000006..0x40000009 leaves */ for (function = HV_CPUID_IMPLEMENT_LIMITS + 1; From 4455922f7bb8fef2f5aa0a4d3901041bcc4b659d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 17 Nov 2021 18:45:33 +0100 Subject: [PATCH 194/421] qemu-keymap: Add license in generated files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Warner Losh Message-Id: <20211117174533.1900570-1-philmd@redhat.com> Signed-off-by: Laurent Vivier --- qemu-keymap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu-keymap.c b/qemu-keymap.c index 536e8f2385..4095b654a6 100644 --- a/qemu-keymap.c +++ b/qemu-keymap.c @@ -187,6 +187,7 @@ int main(int argc, char *argv[]) } fprintf(outfile, + "# SPDX-License-Identifier: GPL-2.0-or-later\n" "#\n" "# generated by qemu-keymap\n" "# model : %s\n" From 74fb2f4f4c47c966ab54687392e6561b4de4bb8a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 5 Dec 2021 23:41:09 +0100 Subject: [PATCH 195/421] hw/avr: Realize AVRCPU qdev object using qdev_realize() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TYPE_AVR_CPU inherits TYPE_CPU, which itself inherits TYPE_DEVICE. TYPE_DEVICE instances are realized using qdev_realize(), we don't need to access QOM internal values. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael Rolnik Message-Id: <20211205224109.322152-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier --- hw/avr/atmega.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 0608e2d475..a34803e642 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -233,7 +233,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) /* CPU */ object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type); - object_property_set_bool(OBJECT(&s->cpu), "realized", true, &error_abort); + qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev = DEVICE(&s->cpu); /* SRAM */ From f71d31fa811f15d40ab076b350c2067d30ac22b1 Mon Sep 17 00:00:00 2001 From: Leonardo Garcia Date: Tue, 23 Nov 2021 08:48:31 -0300 Subject: [PATCH 196/421] hw/virtio/vhost: Fix typo in comment. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Leonardo Garcia Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Laurent Vivier --- hw/virtio/vhost.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 437347ad01..20913cf8fb 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -313,7 +313,7 @@ static int vhost_dev_has_iommu(struct vhost_dev *dev) * For vhost, VIRTIO_F_IOMMU_PLATFORM means the backend support * incremental memory mapping API via IOTLB API. For platform that * does not have IOMMU, there's no need to enable this feature - * which may cause unnecessary IOTLB miss/update trnasactions. + * which may cause unnecessary IOTLB miss/update transactions. */ return virtio_bus_device_iommu_enabled(vdev) && virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM); From 036ef344b6c51f651a3b5c6ca56868fa3e6554fe Mon Sep 17 00:00:00 2001 From: Zhang Chen Date: Mon, 18 Oct 2021 16:50:44 +0800 Subject: [PATCH 197/421] docs/block-replication.txt: Fix replication top-id command demo This demo not correct, the original childs1 can't pass the the bdrv_is_root_node check in replcation_start(). Keep consistent with docs/COLO-FT.txt Signed-off-by: Zhang Chen Reviewed-by: Laurent Vivier Message-Id: <20211018085044.2788276-1-chen.zhang@intel.com> Signed-off-by: Laurent Vivier --- docs/block-replication.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/block-replication.txt b/docs/block-replication.txt index b0f23761c6..e1b28a6cc1 100644 --- a/docs/block-replication.txt +++ b/docs/block-replication.txt @@ -179,7 +179,7 @@ Primary: Secondary: -drive if=none,driver=raw,file.filename=1.raw,id=colo1 \ - -drive if=none,id=childs1,driver=replication,mode=secondary,top-id=childs1 + -drive if=none,id=childs1,driver=replication,mode=secondary,top-id=top-disk1 file.file.filename=active_disk.qcow2,\ file.driver=qcow2,\ file.backing.file.filename=hidden_disk.qcow2,\ From 2c674fada72079583a3f2cc1790b16a0259c4fa0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 3 Sep 2021 19:44:44 +0200 Subject: [PATCH 198/421] glib-compat: Introduce g_memdup2() wrapper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When experimenting raising GLIB_VERSION_MIN_REQUIRED to 2.68 (Fedora 34 provides GLib 2.68.1) we get: hw/virtio/virtio-crypto.c:245:24: error: 'g_memdup' is deprecated: Use 'g_memdup2' instead [-Werror,-Wdeprecated-declarations] ... g_memdup() has been updated by g_memdup2() to fix eventual security issues (size argument is 32-bit and could be truncated / wrapping). GLib recommends to copy their static inline version of g_memdup2(): https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 Our glib-compat.h provides a comment explaining how to deal with these deprecated declarations (see commit e71e8cc0355 "glib: enforce the minimum required version and warn about old APIs"). Following this comment suggestion, implement the g_memdup2_qemu() wrapper to g_memdup2(), and use the safer equivalent inlined when we are using pre-2.68 GLib. Reported-by: Eric Blake Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Eric Blake Message-Id: <20210903174510.751630-3-philmd@redhat.com> Signed-off-by: Laurent Vivier --- include/glib-compat.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/include/glib-compat.h b/include/glib-compat.h index 9e95c888f5..8d01a8c01f 100644 --- a/include/glib-compat.h +++ b/include/glib-compat.h @@ -68,6 +68,43 @@ * without generating warnings. */ +/* + * g_memdup2_qemu: + * @mem: (nullable): the memory to copy. + * @byte_size: the number of bytes to copy. + * + * Allocates @byte_size bytes of memory, and copies @byte_size bytes into it + * from @mem. If @mem is %NULL it returns %NULL. + * + * This replaces g_memdup(), which was prone to integer overflows when + * converting the argument from a #gsize to a #guint. + * + * This static inline version is a backport of the new public API from + * GLib 2.68, kept internal to GLib for backport to older stable releases. + * See https://gitlab.gnome.org/GNOME/glib/-/issues/2319. + * + * Returns: (nullable): a pointer to the newly-allocated copy of the memory, + * or %NULL if @mem is %NULL. + */ +static inline gpointer g_memdup2_qemu(gconstpointer mem, gsize byte_size) +{ +#if GLIB_CHECK_VERSION(2, 68, 0) + return g_memdup2(mem, byte_size); +#else + gpointer new_mem; + + if (mem && byte_size != 0) { + new_mem = g_malloc(byte_size); + memcpy(new_mem, mem, byte_size); + } else { + new_mem = NULL; + } + + return new_mem; +#endif +} +#define g_memdup2(m, s) g_memdup2_qemu(m, s) + #if defined(G_OS_UNIX) /* * Note: The fallback implementation is not MT-safe, and it returns a copy of From 460056dbe6b2df363de6d8c2a9c9ba862653d6bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 3 Sep 2021 19:45:06 +0200 Subject: [PATCH 199/421] tests/qtest: Replace g_memdup() by g_memdup2() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize to g_memdup(). For large values, that would lead to a silent truncation of the size from 64 to 32 bits, and result in a heap area being returned which is significantly smaller than what the caller expects. This can likely be exploited in various modules to cause a heap buffer overflow. Replace g_memdup() by the safer g_memdup2() wrapper. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Message-Id: <20210903174510.751630-25-philmd@redhat.com> Signed-off-by: Laurent Vivier --- tests/qtest/libqos/ahci.c | 6 +++--- tests/qtest/libqos/qgraph.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index fba3e7a954..eaa2096512 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -639,8 +639,8 @@ void ahci_exec(AHCIQState *ahci, uint8_t port, AHCIOpts *opts; uint64_t buffer_in; - opts = g_memdup((opts_in == NULL ? &default_opts : opts_in), - sizeof(AHCIOpts)); + opts = g_memdup2((opts_in == NULL ? &default_opts : opts_in), + sizeof(AHCIOpts)); buffer_in = opts->buffer; @@ -860,7 +860,7 @@ AHCICommand *ahci_command_create(uint8_t command_name) g_assert(!props->ncq || props->lba48); /* Defaults and book-keeping */ - cmd->props = g_memdup(props, sizeof(AHCICommandProp)); + cmd->props = g_memdup2(props, sizeof(AHCICommandProp)); cmd->name = command_name; cmd->xbytes = props->size; cmd->prd_size = 4096; diff --git a/tests/qtest/libqos/qgraph.c b/tests/qtest/libqos/qgraph.c index d1dc491930..109ff04e1e 100644 --- a/tests/qtest/libqos/qgraph.c +++ b/tests/qtest/libqos/qgraph.c @@ -93,7 +93,7 @@ static void add_edge(const char *source, const char *dest, edge->type = type; edge->dest = g_strdup(dest); edge->edge_name = g_strdup(opts->edge_name ?: dest); - edge->arg = g_memdup(opts->arg, opts->size_arg); + edge->arg = g_memdup2(opts->arg, opts->size_arg); edge->before_cmd_line = opts->before_cmd_line ? g_strconcat(" ", opts->before_cmd_line, NULL) : NULL; From ce2ff9cccf0c5f123f9d1e3d5e4fc07d1c2c159d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 3 Sep 2021 19:45:10 +0200 Subject: [PATCH 200/421] checkpatch: Do not allow deprecated g_memdup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit g_memdup() is insecure and as been deprecated in GLib 2.68. QEMU provides the safely equivalent g_memdup2() wrapper. Do not allow more g_memdup() calls in the repository, provide a hint to use g_memdup2(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Eric Blake Message-Id: <20210903174510.751630-29-philmd@redhat.com> Signed-off-by: Laurent Vivier --- scripts/checkpatch.pl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index cb8eff233e..5caa739db4 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2850,6 +2850,11 @@ sub process { WARN("consider using g_path_get_$1() in preference to g_strdup($1())\n" . $herecurr); } +# enforce g_memdup2() over g_memdup() + if ($line =~ /\bg_memdup\s*\(/) { + ERROR("use g_memdup2() instead of unsafe g_memdup()\n" . $herecurr); + } + # recommend qemu_strto* over strto* for numeric conversions if ($line =~ /\b(strto[^kd].*?)\s*\(/) { ERROR("consider using qemu_$1 in preference to $1\n" . $herecurr); From 83234b8289e64fc359a5bf02d886a333d65b8f8c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 17 Dec 2021 17:57:12 +0100 Subject: [PATCH 201/421] hw/ppc/mac.h: Remove MAX_CPUS macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mac.h header defines a MAX_CPUS macro. This is confusingly named, because it suggests it's a generic setting, but in fact it's used by only the g3beige and mac99 machines. It's also using a single macro for two values which aren't inherently the same -- if one of these two machines was updated to support SMP configurations then it would want a different max_cpus value to the other. Since the macro is used in only two places, just expand it out and get rid of it. If hypothetical future work to support SMP in these boards needs a compile-time-known limit on the number of CPUs, we can give it a suitable name at that point. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-Id: <20211105184216.120972-1-peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater --- hw/ppc/mac.h | 3 --- hw/ppc/mac_newworld.c | 3 ++- hw/ppc/mac_oldworld.c | 3 ++- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 22c8408078..a1fa8f8e41 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -36,9 +36,6 @@ #include "hw/pci-host/uninorth.h" #include "qom/object.h" -/* SMP is not enabled, for now */ -#define MAX_CPUS 1 - #define NVRAM_SIZE 0x2000 #define PROM_FILENAME "openbios-ppc" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 7bb7ac3997..4bddb529c2 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -581,7 +581,8 @@ static void core99_machine_class_init(ObjectClass *oc, void *data) mc->desc = "Mac99 based PowerMAC"; mc->init = ppc_core99_init; mc->block_default_type = IF_IDE; - mc->max_cpus = MAX_CPUS; + /* SMP is not supported currently */ + mc->max_cpus = 1; mc->default_boot_order = "cd"; mc->default_display = "std"; mc->kvm_type = core99_kvm_type; diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index de2be960e6..7016979a7c 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -423,7 +423,8 @@ static void heathrow_class_init(ObjectClass *oc, void *data) mc->desc = "Heathrow based PowerMAC"; mc->init = ppc_heathrow_init; mc->block_default_type = IF_IDE; - mc->max_cpus = MAX_CPUS; + /* SMP is not supported currently */ + mc->max_cpus = 1; #ifndef TARGET_PPC64 mc->is_default = true; #endif From c3a824b0cf23f98353fa91c715fe4918432d7928 Mon Sep 17 00:00:00 2001 From: "Lucas Mateus Castro (alqotel)" Date: Fri, 17 Dec 2021 17:57:12 +0100 Subject: [PATCH 202/421] target/ppc: Fixed call to deferred exception MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status after updating the value of FPSCR, but helper_float_check_status checks fp_status and fp_status isn't updated based on FPSCR and since the value of fp_status is reset earlier in the instruction, it's always 0. Because of this helper_float_check_status would change the FI bit to 0 as this bit checks if the last operation was inexact and float_flag_inexact is always 0. These instructions also don't throw exceptions correctly since helper_float_check_status throw exceptions based on fp_status. This commit created a new helper, helper_fpscr_check_status that checks FPSCR value instead of fp_status and checks for a larger variety of exceptions than do_float_check_status. Since fp_status isn't used, gen_reset_fpstatus() was removed. The hardware used to compare QEMU's behavior to was a Power9. Reviewed-by: Richard Henderson Signed-off-by: Lucas Mateus Castro (alqotel) Message-Id: <20211201163808.440385-2-lucas.araujo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 48 ++++++++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/fp-impl.c.inc | 9 ++---- 3 files changed, 52 insertions(+), 6 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c4896cecc8..bb72715827 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -414,6 +414,54 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles) ppc_store_fpscr(env, val); } +void helper_fpscr_check_status(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong fpscr = env->fpscr; + int error = 0; + + if ((fpscr & FP_OX) && (fpscr & FP_OE)) { + error = POWERPC_EXCP_FP_OX; + } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { + error = POWERPC_EXCP_FP_UX; + } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { + error = POWERPC_EXCP_FP_XX; + } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { + error = POWERPC_EXCP_FP_ZX; + } else if (fpscr & FP_VE) { + if (fpscr & FP_VXSOFT) { + error = POWERPC_EXCP_FP_VXSOFT; + } else if (fpscr & FP_VXSNAN) { + error = POWERPC_EXCP_FP_VXSNAN; + } else if (fpscr & FP_VXISI) { + error = POWERPC_EXCP_FP_VXISI; + } else if (fpscr & FP_VXIDI) { + error = POWERPC_EXCP_FP_VXIDI; + } else if (fpscr & FP_VXZDZ) { + error = POWERPC_EXCP_FP_VXZDZ; + } else if (fpscr & FP_VXIMZ) { + error = POWERPC_EXCP_FP_VXIMZ; + } else if (fpscr & FP_VXVC) { + error = POWERPC_EXCP_FP_VXVC; + } else if (fpscr & FP_VXSQRT) { + error = POWERPC_EXCP_FP_VXSQRT; + } else if (fpscr & FP_VXCVI) { + error = POWERPC_EXCP_FP_VXCVI; + } else { + return; + } + } else { + return; + } + cs->exception_index = POWERPC_EXCP_PROGRAM; + env->error_code = error | POWERPC_EXCP_FP; + /* Deferred floating-point exception after target FPSCR update */ + if (fp_exceptions_enabled(env)) { + raise_exception_err_ra(env, cs->exception_index, + env->error_code, GETPC()); + } +} + static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { CPUState *cs = env_cpu(env); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 627811cefc..632a81c676 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -63,6 +63,7 @@ DEF_HELPER_FLAGS_1(cntlzw32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_1(float_check_status, void, env) +DEF_HELPER_1(fpscr_check_status, void, env) DEF_HELPER_1(reset_fpstatus, void, env) DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index c9e05201d9..8afd6a087d 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -769,7 +769,6 @@ static void gen_mtfsb1(DisasContext *ctx) return; } crb = 31 - crbD(ctx->opcode); - gen_reset_fpstatus(); /* XXX: we pretend we can only do IEEE floating-point computations */ if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { TCGv_i32 t0; @@ -782,7 +781,7 @@ static void gen_mtfsb1(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); } /* mtfsf */ @@ -803,7 +802,6 @@ static void gen_mtfsf(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } - gen_reset_fpstatus(); if (l) { t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); } else { @@ -818,7 +816,7 @@ static void gen_mtfsf(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); tcg_temp_free_i64(t1); } @@ -840,7 +838,6 @@ static void gen_mtfsfi(DisasContext *ctx) return; } sh = (8 * w) + 7 - bf; - gen_reset_fpstatus(); t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); t1 = tcg_const_i32(1 << sh); gen_helper_store_fpscr(cpu_env, t0, t1); @@ -851,7 +848,7 @@ static void gen_mtfsfi(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); } static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) From 00d38802513da6141a732ef7c3619bd0f8f01a8e Mon Sep 17 00:00:00 2001 From: "Lucas Mateus Castro (alqotel)" Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 203/421] test/tcg/ppc64le: test mtfsf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added tests for the mtfsf to check if FI bit of FPSCR is being set and if exception calls are being made correctly. Reviewed-by: Richard Henderson Signed-off-by: Lucas Mateus Castro (alqotel) Message-Id: <20211201163808.440385-3-lucas.araujo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- tests/tcg/ppc64/Makefile.target | 1 + tests/tcg/ppc64le/Makefile.target | 1 + tests/tcg/ppc64le/mtfsf.c | 61 +++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) create mode 100644 tests/tcg/ppc64le/mtfsf.c diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index 6ab7934fdf..8f4c7ac4ed 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -11,6 +11,7 @@ endif bcdsub: CFLAGS += -mpower8-vector PPC64_TESTS += byte_reverse +PPC64_TESTS += mtfsf ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),) run-byte_reverse: QEMU_OPTS+=-cpu POWER10 run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10 diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target index ba2fde5ff1..e031f65adc 100644 --- a/tests/tcg/ppc64le/Makefile.target +++ b/tests/tcg/ppc64le/Makefile.target @@ -16,6 +16,7 @@ byte_reverse: CFLAGS += -mcpu=power10 run-byte_reverse: QEMU_OPTS+=-cpu POWER10 run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10 +PPC64LE_TESTS += mtfsf PPC64LE_TESTS += signal_save_restore_xer TESTS += $(PPC64LE_TESTS) diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c new file mode 100644 index 0000000000..b3d31f3637 --- /dev/null +++ b/tests/tcg/ppc64le/mtfsf.c @@ -0,0 +1,61 @@ +#include +#include +#include +#include + +#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ +#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ +#define FPSCR_FI 17 /* Floating-point fraction inexact */ + +#define FP_VE (1ull << FPSCR_VE) +#define FP_VXSOFT (1ull << FPSCR_VXSOFT) +#define FP_FI (1ull << FPSCR_FI) + +void sigfpe_handler(int sig, siginfo_t *si, void *ucontext) +{ + if (si->si_code == FPE_FLTINV) { + exit(0); + } + exit(1); +} + +int main(void) +{ + union { + double d; + long long ll; + } fpscr; + + struct sigaction sa = { + .sa_sigaction = sigfpe_handler, + .sa_flags = SA_SIGINFO + }; + + /* + * Enable the MSR bits F0 and F1 to enable exceptions. + * This shouldn't be needed in linux-user as these bits are enabled by + * default, but this allows to execute either in a VM or a real machine + * to compare the behaviors. + */ + prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE); + + /* First test if the FI bit is being set correctly */ + fpscr.ll = FP_FI; + __builtin_mtfsf(0b11111111, fpscr.d); + fpscr.d = __builtin_mffs(); + assert((fpscr.ll & FP_FI) != 0); + + /* Then test if the deferred exception is being called correctly */ + sigaction(SIGFPE, &sa, NULL); + + /* + * Although the VXSOFT exception has been chosen, based on test in a Power9 + * any combination of exception bit + its enabling bit should work. + * But if a different exception is chosen si_code check should + * change accordingly. + */ + fpscr.ll = FP_VE | FP_VXSOFT; + __builtin_mtfsf(0b11111111, fpscr.d); + + return 1; +} From 25ee608d79c1890c0f4e8c495ec8629d5712de45 Mon Sep 17 00:00:00 2001 From: "Lucas Mateus Castro (alqotel)" Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 204/421] target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit fixes the difference reported in the bug in the reserved bit 52, it does this by adding this bit to the mask of bits to not be directly altered in the ppc_store_fpscr function (the hardware used to compare to QEMU was a Power9). The bits 0 to 27 were also added to the mask, as they are marked as reserved in the PowerISA and bit 28 is a reserved extension of the DRN field (bits 29:31) but can't be set using mtfsfi, while the other DRN bits may be set using mtfsfi instruction, so bit 28 was also added to the mask. Although this is a difference reported in the bug, since it's a reserved bit it may be a "don't care" case, as put in the bug report. Looking at the ISA it doesn't explicitly mention this bit can't be set, like it does for FEX and VX, so I'm unsure if this is necessary. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 Signed-off-by: Lucas Mateus Castro (alqotel) Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/cpu.c | 2 +- target/ppc/cpu.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index f933d9f2bd..d7b42bae52 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env) void ppc_store_fpscr(CPUPPCState *env, target_ulong val) { - val &= ~(FP_VX | FP_FEX); + val &= FPSCR_MTFS_MASK; if (val & FPSCR_IX) { val |= FP_VX; } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e946da5f3a..441d3dce19 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -759,6 +759,10 @@ enum { FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ FP_VXSQRT | FP_VXCVI) +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ +#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \ + FP_FEX | FP_VX | PPC_BIT(52))) + /*****************************************************************************/ /* Vector status and control register */ #define VSCR_NJ 16 /* Vector non-java */ From 5f1470b091007f24035d6d33149df49a6dd61682 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 205/421] target/ppc: Implement Vector Expand Mask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement the following PowerISA v3.1 instructions: vexpandbm: Vector Expand Byte Mask vexpandhm: Vector Expand Halfword Mask vexpandwm: Vector Expand Word Mask vexpanddm: Vector Expand Doubleword Mask vexpandqm: Vector Expand Quadword Mask Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/insn32.decode | 11 ++++++++++ target/ppc/translate/vmx-impl.c.inc | 34 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e135b8aba4..9a28f1d266 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -56,6 +56,9 @@ &VX_uim4 vrt uim vrb @VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4 +&VX_tb vrt vrb +@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X @@ -408,6 +411,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN +## Vector Mask Manipulation Instructions + +VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb +VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb +VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb +VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb +VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb + # VSX Load/Store Instructions LXV 111101 ..... ..... ............ . 001 @DQ_TSX diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 8eb8d3a067..ebb0484323 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1491,6 +1491,40 @@ static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a) return true; } +static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb), + (8 << vece) - 1, 16, 16); + + return true; +} + +TRANS(VEXPANDBM, do_vexpand, MO_8) +TRANS(VEXPANDHM, do_vexpand, MO_16) +TRANS(VEXPANDWM, do_vexpand, MO_32) +TRANS(VEXPANDDM, do_vexpand, MO_64) + +static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + get_avr64(tmp, a->vrb, true); + tcg_gen_sari_i64(tmp, tmp, 63); + set_avr64(a->vrt, tmp, false); + set_avr64(a->vrt, tmp, true); + + tcg_temp_free_i64(tmp); + return true; +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \ From 17868d81e0074905b2c1e414af6618570e8059eb Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 206/421] target/ppc: Implement Vector Extract Mask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement the following PowerISA v3.1 instructions: vextractbm: Vector Extract Byte Mask vextracthm: Vector Extract Halfword Mask vextractwm: Vector Extract Word Mask vextractdm: Vector Extract Doubleword Mask vextractqm: Vector Extract Quadword Mask Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/insn32.decode | 6 +++ target/ppc/translate/vmx-impl.c.inc | 82 +++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 9a28f1d266..639ac22bf0 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -419,6 +419,12 @@ VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb +VEXTRACTBM 000100 ..... 01000 ..... 11001000010 @VX_tb +VEXTRACTHM 000100 ..... 01001 ..... 11001000010 @VX_tb +VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb +VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb +VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb + # VSX Load/Store Instructions LXV 111101 ..... ..... ............ . 001 @DQ_TSX diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index ebb0484323..96c97bf6e7 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1525,6 +1525,88 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) return true; } +static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece, + mask = dup_const(vece, 1 << (elem_width - 1)); + uint64_t i, j; + TCGv_i64 lo, hi, t0, t1; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = tcg_temp_new_i64(); + lo = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + get_avr64(lo, a->vrb, false); + get_avr64(hi, a->vrb, true); + + tcg_gen_andi_i64(lo, lo, mask); + tcg_gen_andi_i64(hi, hi, mask); + + /* + * Gather the most significant bit of each element in the highest element + * element. E.g. for bytes: + * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX + * & dup(1 << (elem_width - 1)) + * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000 + * << 32 - 4 + * 0000e0000000f0000000g0000000h00000000000000000000000000000000000 + * | + * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000 + * << 16 - 2 + * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000 + * | + * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000 + * << 8 - 1 + * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000 + * | + * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000 + */ + for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) { + tcg_gen_shli_i64(t0, hi, j - i); + tcg_gen_shli_i64(t1, lo, j - i); + tcg_gen_or_i64(hi, hi, t0); + tcg_gen_or_i64(lo, lo, t1); + } + + tcg_gen_shri_i64(hi, hi, 64 - elem_count_half); + tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half); + tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo); + + tcg_temp_free_i64(hi); + tcg_temp_free_i64(lo); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + return true; +} + +TRANS(VEXTRACTBM, do_vextractm, MO_8) +TRANS(VEXTRACTHM, do_vextractm, MO_16) +TRANS(VEXTRACTWM, do_vextractm, MO_32) +TRANS(VEXTRACTDM, do_vextractm, MO_64) + +static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + get_avr64(tmp, a->vrb, true); + tcg_gen_shri_i64(tmp, tmp, 63); + tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp); + + tcg_temp_free_i64(tmp); + + return true; +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \ From 9193eaa901c54dbff4a91ea0b12a99e0135dbca1 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 207/421] target/ppc: Implement Vector Mask Move insns MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement the following PowerISA v3.1 instructions: mtvsrbm: Move to VSR Byte Mask mtvsrhm: Move to VSR Halfword Mask mtvsrwm: Move to VSR Word Mask mtvsrdm: Move to VSR Doubleword Mask mtvsrqm: Move to VSR Quadword Mask mtvsrbmi: Move to VSR Byte Mask Immediate Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/insn32.decode | 11 +++ target/ppc/translate/vmx-impl.c.inc | 115 ++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 639ac22bf0..f68931f4f3 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -40,6 +40,10 @@ %ds_rtp 22:4 !function=times_2 @DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si +&DX_b vrt b +%dx_b 6:10 16:5 0:1 +@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b + &DX rt d %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d @@ -413,6 +417,13 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN ## Vector Mask Manipulation Instructions +MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb +MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb +MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb +MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb +MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb +MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b + VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 96c97bf6e7..d5e02fd7f2 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1607,6 +1607,121 @@ static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a) return true; } +static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece; + uint64_t c; + int i, j; + TCGv_i64 hi, lo, t0, t1; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = tcg_temp_new_i64(); + lo = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]); + tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half); + tcg_gen_extract_i64(lo, t0, 0, elem_count_half); + + /* + * Spread the bits into their respective elements. + * E.g. for bytes: + * 00000000000000000000000000000000000000000000000000000000abcdefgh + * << 32 - 4 + * 0000000000000000000000000000abcdefgh0000000000000000000000000000 + * | + * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh + * << 16 - 2 + * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000 + * | + * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh + * << 8 - 1 + * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000 + * | + * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh + * & dup(1) + * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h + * * 0xff + * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh + */ + for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) { + tcg_gen_shli_i64(t0, hi, j - i); + tcg_gen_shli_i64(t1, lo, j - i); + tcg_gen_or_i64(hi, hi, t0); + tcg_gen_or_i64(lo, lo, t1); + } + + c = dup_const(vece, 1); + tcg_gen_andi_i64(hi, hi, c); + tcg_gen_andi_i64(lo, lo, c); + + c = MAKE_64BIT_MASK(0, elem_width); + tcg_gen_muli_i64(hi, hi, c); + tcg_gen_muli_i64(lo, lo, c); + + set_avr64(a->vrt, lo, false); + set_avr64(a->vrt, hi, true); + + tcg_temp_free_i64(hi); + tcg_temp_free_i64(lo); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + return true; +} + +TRANS(MTVSRBM, do_mtvsrm, MO_8) +TRANS(MTVSRHM, do_mtvsrm, MO_16) +TRANS(MTVSRWM, do_mtvsrm, MO_32) +TRANS(MTVSRDM, do_mtvsrm, MO_64) + +static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]); + tcg_gen_sextract_i64(tmp, tmp, 0, 1); + set_avr64(a->vrt, tmp, false); + set_avr64(a->vrt, tmp, true); + + tcg_temp_free_i64(tmp); + + return true; +} + +static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a) +{ + const uint64_t mask = dup_const(MO_8, 1); + uint64_t hi, lo; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = extract16(a->b, 8, 8); + lo = extract16(a->b, 0, 8); + + for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) { + hi |= hi << (j - i); + lo |= lo << (j - i); + } + + hi = (hi & mask) * 0xFF; + lo = (lo & mask) * 0xFF; + + set_avr64(a->vrt, tcg_constant_i64(hi), true); + set_avr64(a->vrt, tcg_constant_i64(lo), false); + + return true; +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \ From ef80a708b57ddc8f605d9982bfaa0536e720ed9f Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 208/421] ivshmem.c: change endianness to LITTLE_ENDIAN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ivshmem device, as with most PCI devices, uses little endian byte order. However, the endianness of its mmio_ops is marked as DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big endian hosts but also with PowerPC little endian hosts as well, since the Power architecture in QEMU uses big endian hardware (XIVE controller, PCI Host Bridges, etc) even if the host is in little endian byte order. As it is today, the IVPosition of the device will be byte swapped when running in Power BE and LE. This can be seen by changing the existing qtest 'ivshmem-test' to run in ppc64 hosts and printing the IVPOSITION regs in test_ivshmem_server() right after the VM ids assert. For x86_64 the VM id values read are '0' and '1', for ppc64 (tested in a Power8 RHEL 7.9 BE server) and ppc64le (tested in a Power9 RHEL 8.6 LE server) the ids will be '0' and '0x1000000'. Change this device to LITTLE_ENDIAN fixes the issue for Power hosts of both endianness, and every other big-endian architecture that might use this device, without impacting x86 users. Fixes: cb06608e17f8 ("ivshmem: convert to memory API") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/168 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211124092948.335389-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/misc/ivshmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 1ba4a98377..299837e5c1 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -243,7 +243,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, static const MemoryRegionOps ivshmem_mmio_ops = { .read = ivshmem_io_read, .write = ivshmem_io_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, From d04aeb6862a18540b7f72617b05be19846e1b047 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 209/421] ivshmem-test.c: enable test_ivshmem_server for ppc64 arch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This test, if enabled by hand, was failing when the ivhsmem device was being declared as DEVICE_NATIVE_ENDIAN with the following error: /ppc64/ivshmem/pair: OK /ppc64/ivshmem/server: ** ERROR:/home/danielhb/qemu/tests/qtest/ivshmem-test.c:367:test_ivshmem_server: assertion failed (ret != 0): (0 != 0) Aborted After the endianness change done in the previous patch, we can verify in both a a Power 9 little-endian host and in a Power 8 big-endian host that this test is now passing: $ QTEST_QEMU_BINARY=./ppc64-softmmu/qemu-system-ppc64 ./tests/qtest/ivshmem-test -m slow /ppc64/ivshmem/single: OK /ppc64/ivshmem/hotplug: OK /ppc64/ivshmem/memdev: OK /ppc64/ivshmem/pair: OK /ppc64/ivshmem/server: OK Let's keep it that way by officially enabling it for ppc64. Acked-by: Thomas Huth Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211124092948.335389-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- tests/qtest/ivshmem-test.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tests/qtest/ivshmem-test.c b/tests/qtest/ivshmem-test.c index dfa69424ed..fe94dd3b96 100644 --- a/tests/qtest/ivshmem-test.c +++ b/tests/qtest/ivshmem-test.c @@ -463,7 +463,6 @@ static gchar *mktempshm(int size, int *fd) int main(int argc, char **argv) { int ret, fd; - const char *arch = qtest_get_arch(); gchar dir[] = "/tmp/ivshmem-test.XXXXXX"; g_test_init(&argc, &argv, NULL); @@ -488,9 +487,7 @@ int main(int argc, char **argv) qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev); if (g_test_slow()) { qtest_add_func("/ivshmem/pair", test_ivshmem_pair); - if (strcmp(arch, "ppc64") != 0) { - qtest_add_func("/ivshmem/server", test_ivshmem_server); - } + qtest_add_func("/ivshmem/server", test_ivshmem_server); } out: From fa4b5eaaf923731c8667c3aec7b64ccc3c7757bf Mon Sep 17 00:00:00 2001 From: Christophe Lombard Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 210/421] pci-host: Allow extended config space access for PowerNV PHB4 model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PCIe extended configuration space on the device is not currently accessible to the host. if by default, it is still inaccessible for conventional for PCIe buses, add the current flag PCI_BUS_EXTENDED_CONFIG_SPACE on the root bus permits PCI-E extended config space access. Signed-off-by: Christophe Lombard Reviewed-by: Frederic Barrat Reviewed-by: Cédric Le Goater Message-Id: <20211109145053.43524-1-clombard@linux.vnet.ibm.com> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 5c375a9f28..40b793201a 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1205,6 +1205,7 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) &phb->pci_mmio, &phb->pci_io, 0, 4, TYPE_PNV_PHB4_ROOT_BUS); pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); + pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; /* Add a single Root port */ qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id); From 58c49ef5c4c367d13c51e7d488611f884fdd6ac8 Mon Sep 17 00:00:00 2001 From: Leonardo Garcia Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 211/421] docs: Minor updates on the powernv documentation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Leonardo Garcia [ clg: replaced Power9 by POWER9 ] Message-Id: Signed-off-by: Cédric Le Goater --- docs/system/ppc/powernv.rst | 55 +++++++++++++++++++------------------ 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index 86186b7d2c..edd45d1eaa 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -1,7 +1,7 @@ -PowerNV family boards (``powernv8``, ``powernv9``) +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``) ================================================================== -PowerNV (as Non-Virtualized) is the "baremetal" platform using the +PowerNV (as Non-Virtualized) is the "bare metal" platform using the OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can be used as an hypervisor OS, running KVM guests, or simply as a host OS. @@ -16,16 +16,14 @@ Supported devices ----------------- * Multi processor support for POWER8, POWER8NVL and POWER9. - * XSCOM, serial communication sideband bus to configure chiplets - * Simple LPC Controller - * Processor Service Interface (PSI) Controller - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) - * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge - * Simple OCC is an on-chip microcontroller used for power management - tasks - * iBT device to handle BMC communication, with the internal BMC - simulator provided by QEMU or an external BMC such as an Aspeed - QEMU machine. + * XSCOM, serial communication sideband bus to configure chiplets. + * Simple LPC Controller. + * Processor Service Interface (PSI) Controller. + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10). + * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge. + * Simple OCC is an on-chip micro-controller used for power management tasks. + * iBT device to handle BMC communication, with the internal BMC simulator + provided by QEMU or an external BMC such as an Aspeed QEMU machine. * PNOR containing the different firmware partitions. Missing devices @@ -33,27 +31,25 @@ Missing devices A lot is missing, among which : - * POWER10 processor - * XIVE2 (POWER10) interrupt controller - * I2C controllers (yet to be merged) - * NPU/NPU2/NPU3 controllers - * EEH support for PCIe Host bridge controllers - * NX controller - * VAS controller - * chipTOD (Time Of Day) + * I2C controllers (yet to be merged). + * NPU/NPU2/NPU3 controllers. + * EEH support for PCIe Host bridge controllers. + * NX controller. + * VAS controller. + * chipTOD (Time Of Day). * Self Boot Engine (SBE). - * FSI bus + * FSI bus. Firmware -------- The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems includes the runtime services ``skiboot`` and the bootloader kernel and -initramfs ``skiroot``. Source code can be found on GitHub: +initramfs ``skiroot``. Source code can be found on the `OpenPOWER account at +GitHub `_. - https://github.com/open-power. - -Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the `OpenPOWER `__ site. +Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the +`OpenPOWER `__ site. QEMU includes a prebuilt image of ``skiboot`` which is updated when a more recent version is required by the models. @@ -83,6 +79,7 @@ and a SATA disk : Complex PCIe configuration ~~~~~~~~~~~~~~~~~~~~~~~~~~ + Six PHBs are defined per chip (POWER9) but no default PCI layout is provided (to be compatible with libvirt). One PCI device can be added on any of the available PCIe slots using command line options such as: @@ -157,7 +154,7 @@ one on the command line : The files `palmetto-SDR.bin `__ and `palmetto-FRU.bin `__ define a Sensor Data Record repository and a Field Replaceable Unit -inventory for a palmetto BMC. They can be used to extend the QEMU BMC +inventory for a Palmetto BMC. They can be used to extend the QEMU BMC simulator. .. code-block:: bash @@ -189,4 +186,8 @@ CAVEATS ------- * No support for multiple HW threads (SMT=1). Same as pseries. - * CPU can hang when doing intensive I/Os. Use ``-append powersave=off`` in that case. + +Maintainer contact information +------------------------------ + +Cédric Le Goater From ebe6c3fab8614a26130f7c72dd35ecede11a0f71 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 212/421] ppc/pnv.c: add a friendly warning when accel=kvm is used MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If one tries to use -machine powernv9,accel=kvm in a Power9 host, a cryptic error will be shown: qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only "-cpu host" is possible qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid argument Appending '-cpu host' will throw another error: qemu-system-ppc64: invalid chip model 'host' for powernv9 machine The root cause is that in IBM PowerPC we have different specs for the bare-metal and the guests. The bare-metal follows OPAL, the guests follow PAPR. The kernel KVM modules presented in the ppc kernels implements PAPR. This means that we can't use KVM accel when using the powernv machine, which is the emulation of the bare-metal host. All that said, let's give a more informative error in this case. Signed-off-by: Daniel Henrique Barboza Reviewed-by: David Gibson Message-Id: <20211130133153.444601-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 71e45515f1..e5b87e8730 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -742,6 +742,11 @@ static void pnv_init(MachineState *machine) DriveInfo *pnor = drive_get(IF_MTD, 0, 0); DeviceState *dev; + if (kvm_enabled()) { + error_report("The powernv machine does not work with KVM acceleration"); + exit(EXIT_FAILURE); + } + /* allocate RAM */ if (machine->ram_size < mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); From 3e8f7158153f035477d975869d22d07da719f0be Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 213/421] docs/system/ppc/powernv.rst: document KVM support status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Put in a more accessible place the reasoning behind our decision to officially drop KVM support in the powernv machine. Signed-off-by: Daniel Henrique Barboza Message-Id: <20211130133153.444601-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- docs/system/ppc/powernv.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index edd45d1eaa..c8f9762342 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -54,6 +54,19 @@ Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the QEMU includes a prebuilt image of ``skiboot`` which is updated when a more recent version is required by the models. +Current acceleration status +--------------------------- + +KVM acceleration in Linux Power hosts is provided by the kvm-hv and +kvm-pr modules. kvm-hv is adherent to PAPR and it's not compliant with +powernv. kvm-pr in theory could be used as a valid accel option but +this isn't supported by kvm-pr at this moment. + +To spare users from dealing with not so informative errors when attempting +to use accel=kvm, the powernv machine will throw an error informing that +KVM is not supported. This can be revisited in the future if kvm-pr (or +any other KVM alternative) is usable as KVM accel for this machine. + Boot options ------------ From bbfbbff5fc0fb4cee42ed22c4430cc5d68bacc27 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 214/421] ppc/pnv.c: fix "system-id" FDT when -uuid is set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Setting -uuid in the pnv machine does not work: ./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid 7ff61ca1-a4a0-4bc1-944c-abd114a35e80 qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt, "system-id", buf)): FDT_ERR_BADSTATE This happens because we're using fdt_property_string(), which is a sequential write function that is supposed to be used when we're building a new FDT, in a case where read/writing into an existing FDT. Fix it by using fdt_setprop_string() instead. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211207094858.744386-1-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e5b87e8730..44ae41a9cb 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -522,7 +522,7 @@ static void *pnv_dt_create(MachineState *machine) buf = qemu_uuid_unparse_strdup(&qemu_uuid); _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); if (qemu_uuid_set) { - _FDT((fdt_property_string(fdt, "system-id", buf))); + _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); } g_free(buf); From 88581cc43b90f3e3ebf5b2a8d08916c0f2889a17 Mon Sep 17 00:00:00 2001 From: Leonardo Garcia Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 215/421] docs: Introducing pseries documentation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The purpose of this document is to substitute the content currently available in the QEMU wiki at [0]. This initial version does contain some additional content as well. Whenever this documentation gets upstream and is reflected in [1], the QEMU wiki will be edited to point to this documentation, so that we only need to keep it updated in one place. 0. https://wiki.qemu.org/Documentation/Platforms/POWER 1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html Signed-off-by: Leonardo Garcia Reviewed-by: David Gibson Message-Id: <66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater --- docs/system/ppc/pseries.rst | 226 ++++++++++++++++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index 932d4dd17d..0d2e4af94e 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -1,12 +1,238 @@ pSeries family boards (``pseries``) =================================== +The Power machine para-virtualized environment described by the `Linux on Power +Architecture Reference document (LoPAR) +`_ +is called pSeries. This environment is also known as sPAPR, System p guests, or +simply Power Linux guests (although it is capable of running other operating +systems, such as AIX). + +Even though pSeries is designed to behave as a guest environment, it is also +capable of acting as a hypervisor OS, providing, on that role, nested +virtualization capabilities. + Supported devices ----------------- + * Multi processor support for many Power processors generations: POWER7, + POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, + but its state is unknown. + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) + * vPHB PCIe Host bridge. + * vscsi and vnet devices, compatible with the same devices available on a + PowerVM hypervisor with VIOS managing LPARs. + * Virtio based devices. + * PCIe device pass through. + Missing devices --------------- + * SPICE support. Firmware -------- + +`SLOF `_ (Slimline Open Firmware) is an +implementation of the `IEEE 1275-1994, Standard for Boot (Initialization +Configuration) Firmware: Core Requirements and Practices +`_. + +QEMU includes a prebuilt image of SLOF which is updated when a more recent +version is required. + +Build directions +---------------- + +.. code-block:: bash + + ./configure --target-list=ppc64-softmmu && make + +Running instructions +-------------------- + +Someone can select the pSeries machine type by running QEMU with the following +options: + +.. code-block:: bash + + qemu-system-ppc64 -M pseries + +sPAPR devices +------------- + +The sPAPR specification defines a set of para-virtualized devices, which are +also supported by the pSeries machine in QEMU and can be instantiated with the +``-device`` option: + +* ``spapr-vlan`` : a virtual network interface. +* ``spapr-vscsi`` : a virtual SCSI disk interface. +* ``spapr-rng`` : a pseudo-device for passing random number generator data to the + guest (see the `H_RANDOM hypercall feature + `_ for details). +* ``spapr-vty``: a virtual teletype. +* ``spapr-pci-host-bridge``: a PCI host bridge. +* ``tpm-spapr``: a Trusted Platform Module (TPM). +* ``spapr-tpm-proxy``: a TPM proxy. + +These are compatible with the devices historically available for use when +running the IBM PowerVM hypervisor with LPARs. + +However, since these devices have originally been specified with another +hypervisor and non-Linux guests in mind, you should use the virtio counterparts +(virtio-net, virtio-blk/scsi and virtio-rng for instance) if possible instead, +since they will most probably give you better performance with Linux guests in a +QEMU environment. + +The pSeries machine in QEMU is always instantiated with the following devices: + +* A NVRAM device (``spapr-nvram``). +* A virtual teletype (``spapr-vty``). +* A PCI host bridge (``spapr-pci-host-bridge``). + +Hence, it is not needed to add them manually, unless you use the ``-nodefaults`` +command line option in QEMU. + +In the case of the default ``spapr-nvram`` device, if someone wants to make the +contents of the NVRAM device persistent, they will need to specify a PFLASH +device when starting QEMU, i.e. either use +``-drive if=pflash,file=,format=raw`` to set the default PFLASH +device, or specify one with an ID +(``-drive if=none,file=,format=raw,id=pfid``) and pass that ID to the +NVRAM device with ``-global spapr-nvram.drive=pfid``. + +sPAPR specification +^^^^^^^^^^^^^^^^^^^ + +The main source of documentation on the sPAPR standard is the `Linux on Power +Architecture Reference document (LoPAR) +`_. +However, documentation specific to QEMU's implementation of the specification +can also be found in QEMU documentation: + +.. toctree:: + :maxdepth: 1 + + ../../specs/ppc-spapr-numa.rst + ../../specs/ppc-spapr-xive.rst + +Other documentation available in QEMU docs directory: + +* Hypervisor calls (a.k.a. hcalls) (``docs/specs/ppc-spapr-hcalls.txt``). +* Hot plug (``/docs/specs/ppc-spapr-hotplug.txt``). +* Hypervisor calls needed by the Ultravisor + (``/docs/specs/ppc-spapr-uv-hcalls.txt``). + +Switching between the KVM-PR and KVM-HV kernel module +----------------------------------------------------- + +Currently, there are two implementations of KVM on Power, ``kvm_hv.ko`` and +``kvm_pr.ko``. + + +If a host supports both KVM modes, and both KVM kernel modules are loaded, it is +possible to switch between the two modes with the ``kvm-type`` parameter: + +* Use ``qemu-system-ppc64 -M pseries,accel=kvm,kvm-type=PR`` to use the + ``kvm_pr.ko`` kernel module. +* Use ``qemu-system-ppc64 -M pseries,accel=kvm,kvm-type=HV`` to use ``kvm_hv.ko`` + instead. + +KVM-PR +^^^^^^ + +KVM-PR uses the so-called **PR**\ oblem state of the PPC CPUs to run the guests, +i.e. the virtual machine is run in user mode and all privileged instructions +trap and have to be emulated by the host. That means you can run KVM-PR inside +a pSeries guest (or a PowerVM LPAR for that matter), and that is where it has +originated, as historically (prior to POWER7) it was not possible to run Linux +on hypervisor mode on a Power processor (this function was restricted to +PowerVM, the IBM proprietary hypervisor). + +Because all privileged instructions are trapped, guests that use a lot of +privileged instructions run quite slow with KVM-PR. On the other hand, because +of that, this kernel module can run on pretty much every PPC hardware, and is +able to emulate a lot of guests CPUs. This module can even be used to run other +PowerPC guests like an emulated PowerMac. + +As KVM-PR can be run inside a pSeries guest, it can also provide nested +virtualization capabilities (i.e. running a guest from within a guest). + +It is important to notice that, as KVM-HV provides a much better execution +performance, maintenance work has been much more focused on it in the past +years. Maintenance for KVM-PR has been minimal. + +In order to run KVM-PR guests with POWER9 processors, someone will need to start +QEMU with ``kernel_irqchip=off`` command line option. + +KVM-HV +^^^^^^ + +KVM-HV uses the hypervisor mode of more recent Power processors, that allow +access to the bare metal hardware directly. Although POWER7 had this capability, +it was only starting with POWER8 that this was officially supported by IBM. + +Originally, KVM-HV was only available when running on a PowerNV platform (a.k.a. +Power bare metal). Although it runs on a PowerNV platform, it can only be used +to start pSeries guests. As the pSeries guest doesn't have access to the +hypervisor mode of the Power CPU, it wasn't possible to run KVM-HV on a guest. +This limitation has been lifted, and now it is possible to run KVM-HV inside +pSeries guests as well, making nested virtualization possible with KVM-HV. + +As KVM-HV has access to privileged instructions, guests that use a lot of these +can run much faster than with KVM-PR. On the other hand, the guest CPU has to be +of the same type as the host CPU this way, e.g. it is not possible to specify an +embedded PPC CPU for the guest with KVM-HV. However, there is at least the +possibility to run the guest in a backward-compatibility mode of the previous +CPUs generations, e.g. you can run a POWER7 guest on a POWER8 host by using +``-cpu POWER8,compat=power7`` as parameter to QEMU. + +Modules support +--------------- + +As noticed in the sections above, each module can run in a different +environment. The following table shows with which environment each module can +run. As long as you are in a supported environment, you can run KVM-PR or KVM-HV +nested. Combinations not shown in the table are not available. + ++--------------+------------+------+-------------------+----------+--------+ +| Platform | Host type | Bits | Page table format | KVM-HV | KVM-PR | ++==============+============+======+===================+==========+========+ +| PowerNV | bare metal | 32 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | N/A | N/A | +| | +------+-------------------+----------+--------+ +| | | 64 | hash | yes | yes | +| | | +-------------------+----------+--------+ +| | | | radix | yes | no | ++--------------+------------+------+-------------------+----------+--------+ +| pSeries [1]_ | PowerNV | 32 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | N/A | N/A | +| | +------+-------------------+----------+--------+ +| | | 64 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | yes [2]_ | no | +| +------------+------+-------------------+----------+--------+ +| | PowerVM | 32 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | N/A | N/A | +| | +------+-------------------+----------+--------+ +| | | 64 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix [3]_ | no | yes | ++--------------+------------+------+-------------------+----------+--------+ + +.. [1] On POWER9 DD2.1 processors, the page table format on the host and guest + must be the same. + +.. [2] KVM-HV cannot run nested on POWER8 machines. + +.. [3] Introduced on Power10 machines. + +Maintainer contact information +------------------------------ + +Cédric Le Goater + +Daniel Henrique Barboza From d483f2b53a61753a221b85edc498552bb9dfd852 Mon Sep 17 00:00:00 2001 From: Leonardo Garcia Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 216/421] docs: rSTify ppc-spapr-hcalls.txt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Leonardo Garcia Reviewed-by: Daniel Henrique Barboza [ clg: - replaced lingua by terminology - add a new line at EOF ] Message-Id: Signed-off-by: Cédric Le Goater --- docs/specs/ppc-spapr-hcalls.txt | 92 ++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/docs/specs/ppc-spapr-hcalls.txt b/docs/specs/ppc-spapr-hcalls.txt index 93fe3da91b..28daf9734a 100644 --- a/docs/specs/ppc-spapr-hcalls.txt +++ b/docs/specs/ppc-spapr-hcalls.txt @@ -1,9 +1,15 @@ -When used with the "pseries" machine type, QEMU-system-ppc64 implements -a set of hypervisor calls using a subset of the server "PAPR" specification -(IBM internal at this point), which is also what IBM's proprietary hypervisor -adheres too. +sPAPR hypervisor calls +---------------------- -The subset is selected based on the requirements of Linux as a guest. +When used with the ``pseries`` machine type, ``qemu-system-ppc64`` implements +a set of hypervisor calls (a.k.a. hcalls) defined in the `Linux on Power +Architecture Reference document (LoPAR) +`_. +This document is a subset of the Power Architecture Platform Reference (PAPR+) +specification (IBM internal only), which is what PowerVM, the IBM proprietary +hypervisor, adheres to. + +The subset in LoPAR is selected based on the requirements of Linux as a guest. In addition to those calls, we have added our own private hypervisor calls which are mostly used as a private interface between the firmware @@ -12,13 +18,14 @@ running in the guest and QEMU. All those hypercalls start at hcall number 0xf000 which correspond to an implementation specific range in PAPR. -- H_RTAS (0xf000) +H_RTAS (0xf000) +^^^^^^^^^^^^^^^ -RTAS is a set of runtime services generally provided by the firmware -inside the guest to the operating system. It predates the existence -of hypervisors (it was originally an extension to Open Firmware) and -is still used by PAPR to provide various services that aren't performance -sensitive. +RTAS stands for Run-Time Abstraction Sercies and is a set of runtime services +generally provided by the firmware inside the guest to the operating system. It +predates the existence of hypervisors (it was originally an extension to Open +Firmware) and is still used by PAPR and LoPAR to provide various services that +are not performance sensitive. We currently implement the RTAS services in QEMU itself. The actual RTAS "firmware" blob in the guest is a small stub of a few instructions which @@ -26,22 +33,25 @@ calls our private H_RTAS hypervisor call to pass the RTAS calls to QEMU. Arguments: - r3 : H_RTAS (0xf000) - r4 : Guest physical address of RTAS parameter block + ``r3``: ``H_RTAS (0xf000)`` + + ``r4``: Guest physical address of RTAS parameter block. Returns: - H_SUCCESS : Successfully called the RTAS function (RTAS result - will have been stored in the parameter block) - H_PARAMETER : Unknown token + ``H_SUCCESS``: Successfully called the RTAS function (RTAS result will have + been stored in the parameter block). -- H_LOGICAL_MEMOP (0xf001) + ``H_PARAMETER``: Unknown token. -When the guest runs in "real mode" (in powerpc lingua this means -with MMU disabled, ie guest effective == guest physical), it only -has access to a subset of memory and no IOs. +H_LOGICAL_MEMOP (0xf001) +^^^^^^^^^^^^^^^^^^^^^^^^ -PAPR provides a set of hypervisor calls to perform cacheable or +When the guest runs in "real mode" (in powerpc terminology this means with MMU +disabled, i.e. guest effective address equals to guest physical address), it +only has access to a subset of memory and no I/Os. + +PAPR and LoPAR provides a set of hypervisor calls to perform cacheable or non-cacheable accesses to any guest physical addresses that the guest can use in order to access IO devices while in real mode. @@ -58,21 +68,33 @@ is used by our SLOF firmware to invert the screen. Arguments: - r3: H_LOGICAL_MEMOP (0xf001) - r4: Guest physical address of destination - r5: Guest physical address of source - r6: Individual element size - 0 = 1 byte - 1 = 2 bytes - 2 = 4 bytes - 3 = 8 bytes - r7: Number of elements - r8: Operation - 0 = copy - 1 = xor + ``r3 ``: ``H_LOGICAL_MEMOP (0xf001)`` + + ``r4``: Guest physical address of destination. + + ``r5``: Guest physical address of source. + + ``r6``: Individual element size, defined by the binary logarithm of the + desired size. Supported values are: + + ``0`` = 1 byte + + ``1`` = 2 bytes + + ``2`` = 4 bytes + + ``3`` = 8 bytes + + ``r7``: Number of elements. + + ``r8``: Operation. Supported values are: + + ``0``: copy + + ``1``: xor Returns: - H_SUCCESS : Success - H_PARAMETER : Invalid argument + ``H_SUCCESS``: Success. + ``H_PARAMETER``: Invalid argument. From d55b123d141c78cc0d965243c543a7274810da33 Mon Sep 17 00:00:00 2001 From: Leonardo Garcia Date: Fri, 17 Dec 2021 17:57:13 +0100 Subject: [PATCH 217/421] docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Leonardo Garcia Reviewed-by: Daniel Henrique Barboza Message-Id: <7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater --- docs/specs/{ppc-spapr-hcalls.txt => ppc-spapr-hcalls.rst} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename docs/specs/{ppc-spapr-hcalls.txt => ppc-spapr-hcalls.rst} (100%) diff --git a/docs/specs/ppc-spapr-hcalls.txt b/docs/specs/ppc-spapr-hcalls.rst similarity index 100% rename from docs/specs/ppc-spapr-hcalls.txt rename to docs/specs/ppc-spapr-hcalls.rst From 9befbe4f629d5c9b23efc347e90fed8b4d9b74e6 Mon Sep 17 00:00:00 2001 From: Leonardo Garcia Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 218/421] Link new ppc-spapr-hcalls.rst file to pseries.rst. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Leonardo Garcia Reviewed-by: Daniel Henrique Barboza Message-Id: <7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater --- docs/system/ppc/pseries.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index 0d2e4af94e..72e315eff6 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -113,12 +113,12 @@ can also be found in QEMU documentation: .. toctree:: :maxdepth: 1 + ../../specs/ppc-spapr-hcalls.rst ../../specs/ppc-spapr-numa.rst ../../specs/ppc-spapr-xive.rst Other documentation available in QEMU docs directory: -* Hypervisor calls (a.k.a. hcalls) (``docs/specs/ppc-spapr-hcalls.txt``). * Hot plug (``/docs/specs/ppc-spapr-hotplug.txt``). * Hypervisor calls needed by the Ultravisor (``/docs/specs/ppc-spapr-uv-hcalls.txt``). From 149a48f6e6ccedfa01307d45884aa480f5bf77c5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 219/421] softfloat: Extend float_exception_flags to 16 bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We will shortly have more than 8 bits of exceptions. Repack the existing flags into low bits and reformat to hex. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211119160502.17432-2-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- include/fpu/softfloat-types.h | 16 ++++++++-------- include/fpu/softfloat.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 5bcbd041f7..65a43aff59 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -145,13 +145,13 @@ typedef enum __attribute__((__packed__)) { */ enum { - float_flag_invalid = 1, - float_flag_divbyzero = 4, - float_flag_overflow = 8, - float_flag_underflow = 16, - float_flag_inexact = 32, - float_flag_input_denormal = 64, - float_flag_output_denormal = 128 + float_flag_invalid = 0x0001, + float_flag_divbyzero = 0x0002, + float_flag_overflow = 0x0004, + float_flag_underflow = 0x0008, + float_flag_inexact = 0x0010, + float_flag_input_denormal = 0x0020, + float_flag_output_denormal = 0x0040, }; /* @@ -171,8 +171,8 @@ typedef enum __attribute__((__packed__)) { */ typedef struct float_status { + uint16_t float_exception_flags; FloatRoundMode float_rounding_mode; - uint8_t float_exception_flags; FloatX80RoundPrec floatx80_rounding_precision; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a249991e61..0d3b407807 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -100,7 +100,7 @@ typedef enum { | Routine to raise any or all of the software IEC/IEEE floating-point | exception flags. *----------------------------------------------------------------------------*/ -static inline void float_raise(uint8_t flags, float_status *status) +static inline void float_raise(uint16_t flags, float_status *status) { status->float_exception_flags |= flags; } From ba11446c40903b9d97fb75a078d43fee6444d3b6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 220/421] softfloat: Add flag specific to Inf - Inf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat-parts.c.inc | 3 ++- include/fpu/softfloat-types.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 41d4b17e41..eb2b475ca4 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -354,7 +354,7 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b, return a; } /* Inf - Inf */ - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_isi, s); parts_default_nan(a, s); return a; } @@ -494,6 +494,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, if (ab_mask & float_cmask_inf) { if (c->cls == float_class_inf && a->sign != c->sign) { + float_raise(float_flag_invalid | float_flag_invalid_isi, s); goto d_nan; } goto return_inf; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 65a43aff59..eaa12e1e00 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -152,6 +152,7 @@ enum { float_flag_inexact = 0x0010, float_flag_input_denormal = 0x0020, float_flag_output_denormal = 0x0040, + float_flag_invalid_isi = 0x0080, /* inf - inf */ }; /* From bead3c9b0ff8efd652afb27923d8ab4458b3bbd9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 221/421] softfloat: Add flag specific to Inf * 0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat-parts.c.inc | 4 ++-- fpu/softfloat-specialize.c.inc | 12 ++++++------ include/fpu/softfloat-types.h | 1 + 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index eb2b475ca4..3ed793347b 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b, /* Inf * Zero == NaN */ if (unlikely(ab_mask == float_cmask_infzero)) { - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_imz, s); parts_default_nan(a, s); return a; } @@ -489,6 +489,7 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, if (unlikely(ab_mask != float_cmask_normal)) { if (unlikely(ab_mask == float_cmask_infzero)) { + float_raise(float_flag_invalid | float_flag_invalid_imz, s); goto d_nan; } @@ -567,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, goto finish_sign; d_nan: - float_raise(float_flag_invalid, s); parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f2ad0f335e..943e3301d2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the input value 'c' */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 2; } /* Prefer sNaN over qNaN, in the c, a, b order. */ @@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 2; } @@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, #elif defined(TARGET_RISCV) /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); } return 3; /* default NaN */ #elif defined(TARGET_XTENSA) @@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * an input NaN if we have one (ie c). */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 2; } if (status->use_first_nan) { diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index eaa12e1e00..56b4cf7835 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -153,6 +153,7 @@ enum { float_flag_input_denormal = 0x0020, float_flag_output_denormal = 0x0040, float_flag_invalid_isi = 0x0080, /* inf - inf */ + float_flag_invalid_imz = 0x0100, /* inf * 0 */ }; /* From 10cc964030fca459591d9353571f3b1b4e1b5aec Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 222/421] softfloat: Add flags specific to Inf / Inf and 0 / 0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC has these flags, and it's easier to compute them here than after the fact. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat-parts.c.inc | 16 +++++++++++----- include/fpu/softfloat-types.h | 2 ++ 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 3ed793347b..b8563cd2df 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -590,11 +590,13 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, } /* 0/0 or Inf/Inf => NaN */ - if (unlikely(ab_mask == float_cmask_zero) || - unlikely(ab_mask == float_cmask_inf)) { - float_raise(float_flag_invalid, s); - parts_default_nan(a, s); - return a; + if (unlikely(ab_mask == float_cmask_zero)) { + float_raise(float_flag_invalid | float_flag_invalid_zdz, s); + goto d_nan; + } + if (unlikely(ab_mask == float_cmask_inf)) { + float_raise(float_flag_invalid | float_flag_invalid_idi, s); + goto d_nan; } /* All the NaN cases */ @@ -625,6 +627,10 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_divbyzero, s); a->cls = float_class_inf; return a; + + d_nan: + parts_default_nan(a, s); + return a; } /* diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 56b4cf7835..5a9671e564 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -154,6 +154,8 @@ enum { float_flag_output_denormal = 0x0040, float_flag_invalid_isi = 0x0080, /* inf - inf */ float_flag_invalid_imz = 0x0100, /* inf * 0 */ + float_flag_invalid_idi = 0x0200, /* inf / inf */ + float_flag_invalid_zdz = 0x0400, /* 0 / 0 */ }; /* From f8718aab8950c2c88c72b002aa0ba60caabfee36 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 223/421] softfloat: Add flag specific to sqrt(-x) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat-parts.c.inc | 2 +- include/fpu/softfloat-types.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index b8563cd2df..cc8c2c3aee 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -869,7 +869,7 @@ static void partsN(sqrt)(FloatPartsN *a, float_status *status, return; d_nan: - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_sqrt, status); parts_default_nan(a, status); } diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 5a9671e564..33224b5f22 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -156,6 +156,7 @@ enum { float_flag_invalid_imz = 0x0100, /* inf * 0 */ float_flag_invalid_idi = 0x0200, /* inf / inf */ float_flag_invalid_zdz = 0x0400, /* 0 / 0 */ + float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */ }; /* From 81254b02eb2a551d7794d542cbdff03e8349355e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 224/421] softfloat: Add flag specific to convert non-nan to int MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat-parts.c.inc | 14 +++++++------- include/fpu/softfloat-types.h | 1 + 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cc8c2c3aee..ce580347dd 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1055,7 +1055,7 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, break; case float_class_inf: - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = p->sign ? min : max; break; @@ -1077,11 +1077,11 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, if (r <= -(uint64_t)min) { r = -r; } else { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = min; } } else if (r > max) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = max; } break; @@ -1120,7 +1120,7 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, break; case float_class_inf: - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = p->sign ? 0 : max; break; @@ -1138,15 +1138,15 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, } if (p->sign) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = 0; } else if (p->exp > DECOMPOSED_BINARY_POINT) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = max; } else { r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); if (r > max) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = max; } } diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 33224b5f22..9ca50e930b 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -157,6 +157,7 @@ enum { float_flag_invalid_idi = 0x0200, /* inf / inf */ float_flag_invalid_zdz = 0x0400, /* 0 / 0 */ float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */ + float_flag_invalid_cvti = 0x1000, /* non-nan to integer */ }; /* From e706d4455b8d54252b11fc504c56df060151cb89 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 225/421] softfloat: Add flag specific to signaling nans MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PowerPC has this flag, and it's easier to compute it here than after the fact. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat-parts.c.inc | 18 ++++++++++++------ fpu/softfloat.c | 4 +++- include/fpu/softfloat-types.h | 1 + 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index ce580347dd..db3e1f393d 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -19,7 +19,7 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) { switch (a->cls) { case float_class_snan: - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_snan, s); if (s->default_nan_mode) { parts_default_nan(a, s); } else { @@ -40,7 +40,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { if (is_snan(a->cls) || is_snan(b->cls)) { - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_snan, s); } if (s->default_nan_mode) { @@ -68,7 +68,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int which; if (unlikely(abc_mask & float_cmask_snan)) { - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_snan, s); } which = pickNaNMulAdd(a->cls, b->cls, c->cls, @@ -1049,8 +1049,10 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, switch (p->cls) { case float_class_snan: + flags |= float_flag_invalid_snan; + /* fall through */ case float_class_qnan: - flags = float_flag_invalid; + flags |= float_flag_invalid; r = max; break; @@ -1114,8 +1116,10 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, switch (p->cls) { case float_class_snan: + flags |= float_flag_invalid_snan; + /* fall through */ case float_class_qnan: - flags = float_flag_invalid; + flags |= float_flag_invalid; r = max; break; @@ -1341,7 +1345,9 @@ static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b, } if (unlikely(ab_mask & float_cmask_anynan)) { - if (!is_quiet || (ab_mask & float_cmask_snan)) { + if (ab_mask & float_cmask_snan) { + float_raise(float_flag_invalid | float_flag_invalid_snan, s); + } else if (!is_quiet) { float_raise(float_flag_invalid, s); } return float_relation_unordered; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9a28720d82..834ed3a054 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -2543,8 +2543,10 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) static void parts_float_to_ahp(FloatParts64 *a, float_status *s) { switch (a->cls) { - case float_class_qnan: case float_class_snan: + float_raise(float_flag_invalid_snan, s); + /* fall through */ + case float_class_qnan: /* * There is no NaN in the destination format. Raise Invalid * and return a zero with the sign of the input NaN. diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 9ca50e930b..8abd9ab4ec 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -158,6 +158,7 @@ enum { float_flag_invalid_zdz = 0x0400, /* 0 / 0 */ float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */ float_flag_invalid_cvti = 0x1000, /* non-nan to integer */ + float_flag_invalid_snan = 0x2000, /* any operand was snan */ }; /* From 941298ecd7e3103d3789d2dd87dd0f119e81c69e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 226/421] target/ppc: Update float_invalid_op_addsub for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vxisi and vxsnan are computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index bb72715827..d8ad0250bc 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -498,13 +498,12 @@ void helper_reset_fpstatus(CPUPPCState *env) set_float_exception_flags(0, &env->fp_status); } -static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc, - uintptr_t retaddr, int classes) +static void float_invalid_op_addsub(CPUPPCState *env, int flags, + bool set_fpcc, uintptr_t retaddr) { - if ((classes & ~is_neg) == is_inf) { - /* Magnitude subtraction of infinities */ + if (flags & float_flag_invalid_isi) { float_invalid_op_vxisi(env, set_fpcc, retaddr); - } else if (classes & is_snan) { + } else if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -513,12 +512,10 @@ static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc, float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_add(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); } return ret; @@ -528,12 +525,10 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_sub(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); } return ret; @@ -1664,9 +1659,8 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_addsub(env, sfprf, GETPC(), \ - tp##_classify(xa->fld) | \ - tp##_classify(xb->fld)); \ + float_invalid_op_addsub(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ @@ -1708,9 +1702,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); @@ -3326,9 +3318,7 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); From 4edf55698fc2ea30903657c63ed95db0d5548943 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 227/421] target/ppc: Update float_invalid_op_mul for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vximz and vxsnan are computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d8ad0250bc..f02bb3a4af 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -534,13 +534,12 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } -static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc, - uintptr_t retaddr, int classes) +static void float_invalid_op_mul(CPUPPCState *env, int flags, + bool set_fprc, uintptr_t retaddr) { - if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) { - /* Multiplication of zero by infinity */ + if (flags & float_flag_invalid_imz) { float_invalid_op_vximz(env, set_fprc, retaddr); - } else if (classes & is_snan) { + } else if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -549,12 +548,10 @@ static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc, float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_mul(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - float_invalid_op_mul(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_mul(env, flags, 1, GETPC()); } return ret; @@ -1735,9 +1732,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_mul(env, sfprf, GETPC(), \ - tp##_classify(xa->fld) | \ - tp##_classify(xb->fld)); \ + float_invalid_op_mul(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ @@ -1775,9 +1771,7 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_mul(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); From c07f82416cb7973c64d1e21c09957182b4b033dc Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 228/421] target/ppc: Update float_invalid_op_div for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vxidi, vxzdz, and vxsnan are computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 38 ++++++++++++++------------------------ 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index f02bb3a4af..9bcd7abd16 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -557,17 +557,14 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } -static void float_invalid_op_div(CPUPPCState *env, bool set_fprc, - uintptr_t retaddr, int classes) +static void float_invalid_op_div(CPUPPCState *env, int flags, + bool set_fprc, uintptr_t retaddr) { - classes &= ~is_neg; - if (classes == is_inf) { - /* Division of infinity by infinity */ + if (flags & float_flag_invalid_idi) { float_invalid_op_vxidi(env, set_fprc, retaddr); - } else if (classes == is_zero) { - /* Division of zero by zero */ + } else if (flags & float_flag_invalid_zdz) { float_invalid_op_vxzdz(env, set_fprc, retaddr); - } else if (classes & is_snan) { + } else if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -576,17 +573,13 @@ static void float_invalid_op_div(CPUPPCState *env, bool set_fprc, float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_div(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - float_invalid_op_div(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); - } - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, GETPC()); - } + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_div(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); } return ret; @@ -1803,9 +1796,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_div(env, sfprf, GETPC(), \ - tp##_classify(xa->fld) | \ - tp##_classify(xb->fld)); \ + float_invalid_op_div(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \ float_zero_divide_excp(env, GETPC()); \ @@ -1846,9 +1838,7 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_div(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC()); } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { float_zero_divide_excp(env, GETPC()); From f2e25046766ed39e56d8dd5c6de790e430804511 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 229/421] target/ppc: Move float_check_status from FPU_FCTI to translate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a bug in which e.g XE enabled causes inexact to be raised before the writeback to the architectural register. All of the users of GEN_FLOAT_B either set set_fprf, or are one of the convert-to-integer instructions that require this behaviour. Split out the two gen_helper_* calls in gen_compute_fprf_float64 and protect only the first with set_fprf. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-12-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 9 +++------ target/ppc/translate/fp-impl.c.inc | 3 ++- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9bcd7abd16..f453b04751 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -600,12 +600,9 @@ uint64_t helper_##op(CPUPPCState *env, float64 arg) \ uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \ int status = get_float_exception_flags(&env->fp_status); \ \ - if (unlikely(status)) { \ - if (status & float_flag_invalid) { \ - float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \ - ret = nanval; \ - } \ - do_float_check_status(env, GETPC()); \ + if (unlikely(status & float_flag_invalid)) { \ + float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \ + ret = nanval; \ } \ return ret; \ } diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index 8afd6a087d..0767e45d87 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -157,8 +157,9 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_f##name(t1, cpu_env, t0); \ set_fpr(rD(ctx->opcode), t1); \ if (set_fprf) { \ - gen_compute_fprf_float64(t1); \ + gen_helper_compute_fprf_float64(cpu_env, t1); \ } \ + gen_helper_float_check_status(cpu_env); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ From 353464ea16890222fa4661717947043357b1041b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 230/421] target/ppc: Update float_invalid_cvt for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vxsnan is computed directly by softfloat, we don't need to recompute it via classes. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-13-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index f453b04751..be460cc744 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -585,11 +585,11 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } -static void float_invalid_cvt(CPUPPCState *env, bool set_fprc, - uintptr_t retaddr, int class1) +static void float_invalid_cvt(CPUPPCState *env, int flags, + bool set_fprc, uintptr_t retaddr) { float_invalid_op_vxcvi(env, set_fprc, retaddr); - if (class1 & is_snan) { + if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -598,10 +598,10 @@ static void float_invalid_cvt(CPUPPCState *env, bool set_fprc, uint64_t helper_##op(CPUPPCState *env, float64 arg) \ { \ uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \ - int status = get_float_exception_flags(&env->fp_status); \ + int flags = get_float_exception_flags(&env->fp_status); \ \ - if (unlikely(status & float_flag_invalid)) { \ - float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \ + if (unlikely(flags & float_flag_invalid)) { \ + float_invalid_cvt(env, flags, 1, GETPC()); \ ret = nanval; \ } \ return ret; \ @@ -2794,7 +2794,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \ flags = env->fp_status.float_exception_flags; \ if (unlikely(flags & float_flag_invalid)) { \ - float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \ + float_invalid_cvt(env, flags, 0, GETPC()); \ t.tfld = rnan; \ } \ all_flags |= flags; \ @@ -2837,10 +2837,12 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = { }; \ + int flags; \ \ t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \ - if (env->fp_status.float_exception_flags & float_flag_invalid) { \ - float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \ + flags = get_float_exception_flags(&env->fp_status); \ + if (flags & float_flag_invalid) { \ + float_invalid_cvt(env, flags, 0, GETPC()); \ t.tfld = rnan; \ } \ \ From fed12f3b2ddcb2ded39f48d8303c1bfc9b52772d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:14 +0100 Subject: [PATCH 231/421] target/ppc: Fix VXCVI return value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We were returning nanval for any instance of invalid being set, but that is an incorrect for VXCVI. This failure can be seen in the float_convs tests. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index be460cc744..d471a0a1b8 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -585,13 +585,20 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } -static void float_invalid_cvt(CPUPPCState *env, int flags, - bool set_fprc, uintptr_t retaddr) +static uint64_t float_invalid_cvt(CPUPPCState *env, int flags, + uint64_t ret, uint64_t ret_nan, + bool set_fprc, uintptr_t retaddr) { - float_invalid_op_vxcvi(env, set_fprc, retaddr); + /* + * VXCVI is different from most in that it sets two exception bits, + * VXCVI and VXSNAN for an SNaN input. + */ if (flags & float_flag_invalid_snan) { - float_invalid_op_vxsnan(env, retaddr); + env->fpscr |= FP_VXSNAN; } + float_invalid_op_vxcvi(env, set_fprc, retaddr); + + return flags & float_flag_invalid_cvti ? ret : ret_nan; } #define FPU_FCTI(op, cvt, nanval) \ @@ -599,10 +606,8 @@ uint64_t helper_##op(CPUPPCState *env, float64 arg) \ { \ uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \ int flags = get_float_exception_flags(&env->fp_status); \ - \ if (unlikely(flags & float_flag_invalid)) { \ - float_invalid_cvt(env, flags, 1, GETPC()); \ - ret = nanval; \ + ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \ } \ return ret; \ } @@ -2794,8 +2799,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \ flags = env->fp_status.float_exception_flags; \ if (unlikely(flags & float_flag_invalid)) { \ - float_invalid_cvt(env, flags, 0, GETPC()); \ - t.tfld = rnan; \ + t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\ } \ all_flags |= flags; \ } \ @@ -2842,8 +2846,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \ flags = get_float_exception_flags(&env->fp_status); \ if (flags & float_flag_invalid) { \ - float_invalid_cvt(env, flags, 0, GETPC()); \ - t.tfld = rnan; \ + t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \ } \ \ *xt = t; \ From b891757e44b4a06975f0ef59d247046f9659c690 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 232/421] target/ppc: Remove inline from do_fri MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no reason the callers can't tail call to one function. Leave it up to the compiler either way. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211119160502.17432-15-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d471a0a1b8..f81812e5da 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -641,8 +641,8 @@ FPU_FCFI(fcfids, int64_to_float32, 1) FPU_FCFI(fcfidu, uint64_to_float64, 0) FPU_FCFI(fcfidus, uint64_to_float32, 1) -static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, - int rounding_mode) +static uint64_t do_fri(CPUPPCState *env, uint64_t arg, + int rounding_mode) { CPU_DoubleU farg; FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status); From 6bce07777755b86e7ccc27c641c580bbc69bd4eb Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 233/421] target/ppc: Use FloatRoundMode in do_fri MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the proper type for the enumeration. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211119160502.17432-16-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index f81812e5da..c3e0efe7c3 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -642,7 +642,7 @@ FPU_FCFI(fcfidu, uint64_to_float64, 0) FPU_FCFI(fcfidus, uint64_to_float32, 1) static uint64_t do_fri(CPUPPCState *env, uint64_t arg, - int rounding_mode) + FloatRoundMode rounding_mode) { CPU_DoubleU farg; FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status); From 1348d20b168b83f9400cb2bb6fca769a3a7c12ec Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 234/421] target/ppc: Tidy inexact handling in do_fri MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In GEN_FLOAT_B, we called helper_reset_fpstatus immediately before calling helper_fri*. Therefore get_float_exception_flags is known to be zero, and this code can be simplified. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-17-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c3e0efe7c3..d4f72c296f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -654,16 +654,12 @@ static uint64_t do_fri(CPUPPCState *env, uint64_t arg, float_invalid_op_vxsnan(env, GETPC()); farg.ll = arg | 0x0008000000000000ULL; } else { - int inexact = get_float_exception_flags(&env->fp_status) & - float_flag_inexact; set_float_rounding_mode(rounding_mode, &env->fp_status); farg.ll = float64_round_to_int(farg.d, &env->fp_status); set_float_rounding_mode(old_rounding_mode, &env->fp_status); /* fri* does not set FPSCR[XX] */ - if (!inexact) { - env->fp_status.float_exception_flags &= ~float_flag_inexact; - } + env->fp_status.float_exception_flags &= ~float_flag_inexact; } do_float_check_status(env, GETPC()); return farg.ll; From a496352736033c19b530dc02c917fa5509104792 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 235/421] target/ppc: Clean up do_fri MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let float64_round_to_int detect and silence snans. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-18-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d4f72c296f..7716bb15b1 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -644,25 +644,23 @@ FPU_FCFI(fcfidus, uint64_to_float32, 1) static uint64_t do_fri(CPUPPCState *env, uint64_t arg, FloatRoundMode rounding_mode) { - CPU_DoubleU farg; FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status); + int flags; - farg.ll = arg; + set_float_rounding_mode(rounding_mode, &env->fp_status); + arg = float64_round_to_int(arg, &env->fp_status); + set_float_rounding_mode(old_rounding_mode, &env->fp_status); - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN round */ + flags = get_float_exception_flags(&env->fp_status); + if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, GETPC()); - farg.ll = arg | 0x0008000000000000ULL; - } else { - set_float_rounding_mode(rounding_mode, &env->fp_status); - farg.ll = float64_round_to_int(farg.d, &env->fp_status); - set_float_rounding_mode(old_rounding_mode, &env->fp_status); - - /* fri* does not set FPSCR[XX] */ - env->fp_status.float_exception_flags &= ~float_flag_inexact; } + + /* fri* does not set FPSCR[XX] */ + set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status); do_float_check_status(env, GETPC()); - return farg.ll; + + return arg; } uint64_t helper_frin(CPUPPCState *env, uint64_t arg) From e4052bb773cc829a27786d68caa22f28cff19d39 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 236/421] target/ppc: Update fmadd for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vximz, vxisi, and vxsnan are computed directly by softfloat, we don't need to recompute it. This replaces the separate float{32,64}_maddsub_update_excp functions with a single float_invalid_op_madd function. Fix VSX_MADD by passing sfprf to float_invalid_op_madd, whereas the previous *_maddsub_update_excp assumed it true. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 46 ++++++++++------------------------------- 1 file changed, 11 insertions(+), 35 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 7716bb15b1..f5d6bb4eba 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -683,38 +683,15 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg) return do_fri(env, arg, float_round_down); } -#define FPU_MADDSUB_UPDATE(NAME, TP) \ -static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \ - unsigned int madd_flags, uintptr_t retaddr) \ -{ \ - if (TP##_is_signaling_nan(arg1, &env->fp_status) || \ - TP##_is_signaling_nan(arg2, &env->fp_status) || \ - TP##_is_signaling_nan(arg3, &env->fp_status)) { \ - /* sNaN operation */ \ - float_invalid_op_vxsnan(env, retaddr); \ - } \ - if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \ - (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \ - /* Multiplication of zero by infinity */ \ - float_invalid_op_vximz(env, 1, retaddr); \ - } \ - if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \ - TP##_is_infinity(arg3)) { \ - uint8_t aSign, bSign, cSign; \ - \ - aSign = TP##_is_neg(arg1); \ - bSign = TP##_is_neg(arg2); \ - cSign = TP##_is_neg(arg3); \ - if (madd_flags & float_muladd_negate_c) { \ - cSign ^= 1; \ - } \ - if (aSign ^ bSign ^ cSign) { \ - float_invalid_op_vxisi(env, 1, retaddr); \ - } \ - } \ +static void float_invalid_op_madd(CPUPPCState *env, int flags, + bool set_fpcc, uintptr_t retaddr) +{ + if (flags & float_flag_invalid_imz) { + float_invalid_op_vximz(env, set_fpcc, retaddr); + } else { + float_invalid_op_addsub(env, flags, set_fpcc, retaddr); + } } -FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32) -FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64) #define FPU_FMADD(op, madd_flags) \ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ @@ -726,8 +703,7 @@ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ flags = get_float_exception_flags(&env->fp_status); \ if (flags) { \ if (flags & float_flag_invalid) { \ - float64_maddsub_update_excp(env, arg1, arg2, arg3, \ - madd_flags, GETPC()); \ + float_invalid_op_madd(env, flags, 1, GETPC()); \ } \ do_float_check_status(env, GETPC()); \ } \ @@ -2131,8 +2107,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - tp##_maddsub_update_excp(env, xa->fld, b->fld, \ - c->fld, maddflgs, GETPC()); \ + float_invalid_op_madd(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ From ffdaff8e9c698061f57a6b1827570562c5a1c909 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 237/421] target/ppc: Split out do_fmadd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Create a common function for all of the madd helpers. Let the compiler tail call or inline as it chooses. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index f5d6bb4eba..d7e0362e80 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -693,23 +693,26 @@ static void float_invalid_op_madd(CPUPPCState *env, int flags, } } -#define FPU_FMADD(op, madd_flags) \ -uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ - uint64_t arg2, uint64_t arg3) \ -{ \ - uint32_t flags; \ - float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \ - &env->fp_status); \ - flags = get_float_exception_flags(&env->fp_status); \ - if (flags) { \ - if (flags & float_flag_invalid) { \ - float_invalid_op_madd(env, flags, 1, GETPC()); \ - } \ - do_float_check_status(env, GETPC()); \ - } \ - return ret; \ +static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b, + float64 c, int madd_flags, uintptr_t retaddr) +{ + float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (flags) { + if (flags & float_flag_invalid) { + float_invalid_op_madd(env, flags, 1, retaddr); + } + do_float_check_status(env, retaddr); + } + return ret; } +#define FPU_FMADD(op, madd_flags) \ + uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ + uint64_t arg2, uint64_t arg3) \ + { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } + #define MADD_FLGS 0 #define MSUB_FLGS float_muladd_negate_c #define NMADD_FLGS float_muladd_negate_result From 2125ac18bfa3e9568b75906636ec9c69c628c0a0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 238/421] target/ppc: Do not call do_float_check_status from do_fmadd MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We will process flags other than in valid in helper_float_check_status, which is invoked after the writeback to FRT. Fixes a bug in which FRT is not written when OE/UE/XE are enabled. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-21-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d7e0362e80..dd9d40f74b 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -699,11 +699,8 @@ static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b, float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status); int flags = get_float_exception_flags(&env->fp_status); - if (flags) { - if (flags & float_flag_invalid) { - float_invalid_op_madd(env, flags, 1, retaddr); - } - do_float_check_status(env, retaddr); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_madd(env, flags, 1, retaddr); } return ret; } From 7238e55bd6cc494728561e7367b8068182a915c3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 239/421] target/ppc: Split out do_frsp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calling helper_frsp directly from other helpers generates the incorrect retaddr. Split out a helper that takes the retaddr as a parameter. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-22-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index dd9d40f74b..77ab6f9e64 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -721,7 +721,7 @@ FPU_FMADD(fmsub, MSUB_FLGS) FPU_FMADD(fnmsub, NMSUB_FLGS) /* frsp - frsp. */ -uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) +static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr) { CPU_DoubleU farg; float32 f32; @@ -729,7 +729,7 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) farg.ll = arg; if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - float_invalid_op_vxsnan(env, GETPC()); + float_invalid_op_vxsnan(env, retaddr); } f32 = float64_to_float32(farg.d, &env->fp_status); farg.d = float32_to_float64(f32, &env->fp_status); @@ -737,6 +737,11 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) return farg.ll; } +uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) +{ + return do_frsp(env, arg, GETPC()); +} + /* fsqrt - fsqrt. */ float64 helper_fsqrt(CPUPPCState *env, float64 arg) { @@ -1626,7 +1631,7 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1702,7 +1707,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1776,7 +1781,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1844,7 +1849,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1892,7 +1897,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1941,7 +1946,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -2112,7 +2117,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -2851,7 +2856,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ for (i = 0; i < nels; i++) { \ t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \ if (r2sp) { \ - t.tfld = helper_frsp(env, t.tfld); \ + t.tfld = do_frsp(env, t.tfld, GETPC()); \ } \ if (sfprf) { \ helper_compute_fprf_float64(env, t.tfld); \ @@ -2976,7 +2981,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) { helper_reset_fpstatus(env); - uint64_t xt = helper_frsp(env, xb); + uint64_t xt = do_frsp(env, xb, GETPC()); helper_compute_fprf_float64(env, xt); do_float_check_status(env, GETPC()); From 734cfbd84e6951e136aea129b37e6e3d4a58913a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 240/421] target/ppc: Update do_frsp for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vxsnan is computed directly by softfloat, we don't need to recompute it. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-23-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 77ab6f9e64..65acf605b7 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -723,18 +723,13 @@ FPU_FMADD(fnmsub, NMSUB_FLGS) /* frsp - frsp. */ static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr) { - CPU_DoubleU farg; - float32 f32; + float32 f32 = float64_to_float32(arg, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - farg.ll = arg; - - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { + if (unlikely(flags & float_flag_invalid_snan)) { float_invalid_op_vxsnan(env, retaddr); } - f32 = float64_to_float32(farg.d, &env->fp_status); - farg.d = float32_to_float64(f32, &env->fp_status); - - return farg.ll; + return float32_to_float64(f32, &env->fp_status); } uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) From 58c7edef6163dd9a136e64149b08eec3f5778f37 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 241/421] target/ppc: Use helper_todouble in do_frsp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We only needed one ieee arithmetic operation to raise exceptions. To convert back to register form, we can use our simpler non-arithmetic function. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 65acf605b7..870a861e36 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -729,7 +729,7 @@ static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr) if (unlikely(flags & float_flag_invalid_snan)) { float_invalid_op_vxsnan(env, retaddr); } - return float32_to_float64(f32, &env->fp_status); + return helper_todouble(f32); } uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) From 3d3050cc8d12ad4a59c0f0b952f8e85e0212d2b6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 242/421] target/ppc: Update sqrt for new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that vxsqrt and vxsnan are computed directly by softfloat, we don't need to recompute it. Split out float_invalid_op_sqrt to be used in several places. This fixes VSX_SQRT, which did not order its tests correctly to eliminate NaN with sign set. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 72 ++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 47 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 870a861e36..08f7c8837e 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -737,22 +737,24 @@ uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) return do_frsp(env, arg, GETPC()); } +static void float_invalid_op_sqrt(CPUPPCState *env, int flags, + bool set_fpcc, uintptr_t retaddr) +{ + if (unlikely(flags & float_flag_invalid_sqrt)) { + float_invalid_op_vxsqrt(env, set_fpcc, retaddr); + } else if (unlikely(flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, retaddr); + } +} + /* fsqrt - fsqrt. */ float64 helper_fsqrt(CPUPPCState *env, float64 arg) { float64 ret = float64_sqrt(arg, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - if (unlikely(float64_is_any_nan(arg))) { - if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) { - /* sNaN square root */ - float_invalid_op_vxsnan(env, GETPC()); - } - } else { - /* Square root of a negative nonzero number */ - float_invalid_op_vxsqrt(env, 1, GETPC()); - } + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); } return ret; @@ -807,22 +809,14 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg) /* "Estimate" the reciprocal with actual division. */ float64 rets = float64_sqrt(arg, &env->fp_status); float64 retd = float64_div(float64_one, rets, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - if (float64_is_signaling_nan(arg, &env->fp_status)) { - /* sNaN reciprocal */ - float_invalid_op_vxsnan(env, GETPC()); - } else { - /* Square root of a negative nonzero number */ - float_invalid_op_vxsqrt(env, 1, GETPC()); - } - } - if (status & float_flag_divbyzero) { - /* Reciprocal of (square root of) zero. */ - float_zero_divide_excp(env, GETPC()); - } + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + /* Reciprocal of (square root of) zero. */ + float_zero_divide_excp(env, GETPC()); } return retd; @@ -1884,11 +1878,8 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \ - float_invalid_op_vxsqrt(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_sqrt(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ @@ -1931,15 +1922,10 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.fld = tp##_sqrt(xb->fld, &tstat); \ t.fld = tp##_div(tp##_one, t.fld, &tstat); \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ - \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \ - float_invalid_op_vxsqrt(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_sqrt(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ - \ if (r2sp) { \ t.fld = do_frsp(env, t.fld, GETPC()); \ } \ @@ -3240,15 +3226,7 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb->f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - t.f128 = float128_snan_to_qnan(xb->f128); - } else if (float128_is_quiet_nan(xb->f128, &tstat)) { - t.f128 = xb->f128; - } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128)) { - float_invalid_op_vxsqrt(env, 1, GETPC()); - t.f128 = float128_default_nan(&env->fp_status); - } + float_invalid_op_sqrt(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); From 053e23a6942bc3208fff4a097483d4afce79a1ee Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 243/421] target/ppc: Update xsrqpi and xsrqpxp to new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 08f7c8837e..853e0aad1d 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3138,11 +3138,8 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode, t.f128 = float128_round_to_int(xb->f128, &tstat); env->fp_status.float_exception_flags |= tstat.float_exception_flags; - if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb->f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - t.f128 = float128_snan_to_qnan(t.f128); - } + if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); } if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) { @@ -3196,11 +3193,9 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode, t.f128 = floatx80_to_float128(round_res, &tstat); env->fp_status.float_exception_flags |= tstat.float_exception_flags; - if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb->f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - t.f128 = float128_snan_to_qnan(t.f128); - } + if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); + t.f128 = float128_snan_to_qnan(t.f128); } helper_compute_fprf_float128(env, t.f128); From 8ea0b1408e680ecd08a48c51fb1e4d0ec8cbdc15 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 244/421] target/ppc: Update fre to new flags MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 853e0aad1d..aef81a818f 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -765,20 +765,15 @@ float64 helper_fre(CPUPPCState *env, float64 arg) { /* "Estimate" the reciprocal with actual division. */ float64 ret = float64_div(float64_one, arg, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - if (float64_is_signaling_nan(arg, &env->fp_status)) { - /* sNaN reciprocal */ - float_invalid_op_vxsnan(env, GETPC()); - } - } - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, GETPC()); - /* For FPSCR.ZE == 0, the result is 1/2. */ - ret = float64_set_sign(float64_half, float64_is_neg(arg)); - } + if (unlikely(flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE == 0, the result is 1/2. */ + ret = float64_set_sign(float64_half, float64_is_neg(arg)); } return ret; From 42636fb923de0598104858d886c6f0acdbeb21b5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:15 +0100 Subject: [PATCH 245/421] softfloat: Add float64r32 arithmetic routines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These variants take a float64 as input, compute the result to infinite precision (as we do with FloatParts), round the result to the precision and dynamic range of float32, and then return the result in the format of float64. This is the operation PowerPC requires for its float32 operations. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- fpu/softfloat.c | 110 ++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 12 +++++ 2 files changed, 122 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 834ed3a054..7f524d4377 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1693,6 +1693,50 @@ static float64 float64_round_pack_canonical(FloatParts64 *p, return float64_pack_raw(p); } +static float64 float64r32_round_pack_canonical(FloatParts64 *p, + float_status *s) +{ + parts_uncanon(p, s, &float32_params); + + /* + * In parts_uncanon, we placed the fraction for float32 at the lsb. + * We need to adjust the fraction higher so that the least N bits are + * zero, and the fraction is adjacent to the float64 implicit bit. + */ + switch (p->cls) { + case float_class_normal: + if (unlikely(p->exp == 0)) { + /* + * The result is denormal for float32, but can be represented + * in normalized form for float64. Adjust, per canonicalize. + */ + int shift = frac_normalize(p); + p->exp = (float32_params.frac_shift - + float32_params.exp_bias - shift + 1 + + float64_params.exp_bias); + frac_shr(p, float64_params.frac_shift); + } else { + frac_shl(p, float32_params.frac_shift - float64_params.frac_shift); + p->exp += float64_params.exp_bias - float32_params.exp_bias; + } + break; + case float_class_snan: + case float_class_qnan: + frac_shl(p, float32_params.frac_shift - float64_params.frac_shift); + p->exp = float64_params.exp_max; + break; + case float_class_inf: + p->exp = float64_params.exp_max; + break; + case float_class_zero: + break; + default: + g_assert_not_reached(); + } + + return float64_pack_raw(p); +} + static void float128_unpack_canonical(FloatParts128 *p, float128 f, float_status *s) { @@ -1938,6 +1982,28 @@ float64_sub(float64 a, float64 b, float_status *s) return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub); } +static float64 float64r32_addsub(float64 a, float64 b, float_status *status, + bool subtract) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_addsub(&pa, &pb, status, subtract); + + return float64r32_round_pack_canonical(pr, status); +} + +float64 float64r32_add(float64 a, float64 b, float_status *status) +{ + return float64r32_addsub(a, b, status, false); +} + +float64 float64r32_sub(float64 a, float64 b, float_status *status) +{ + return float64r32_addsub(a, b, status, true); +} + static bfloat16 QEMU_FLATTEN bfloat16_addsub(bfloat16 a, bfloat16 b, float_status *status, bool subtract) { @@ -2069,6 +2135,17 @@ float64_mul(float64 a, float64 b, float_status *s) f64_is_zon2, f64_addsubmul_post); } +float64 float64r32_mul(float64 a, float64 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_mul(&pa, &pb, status); + + return float64r32_round_pack_canonical(pr, status); +} + bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) { @@ -2296,6 +2373,19 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s); } +float64 float64r32_muladd(float64 a, float64 b, float64 c, + int flags, float_status *status) +{ + FloatParts64 pa, pb, pc, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + float64_unpack_canonical(&pc, c, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); + + return float64r32_round_pack_canonical(pr, status); +} + bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { @@ -2419,6 +2509,17 @@ float64_div(float64 a, float64 b, float_status *s) f64_div_pre, f64_div_post); } +float64 float64r32_div(float64 a, float64 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_div(&pa, &pb, status); + + return float64r32_round_pack_canonical(pr, status); +} + bfloat16 QEMU_FLATTEN bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { @@ -4285,6 +4386,15 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_status *s) return soft_f64_sqrt(ua.s, s); } +float64 float64r32_sqrt(float64 a, float_status *status) +{ + FloatParts64 p; + + float64_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float64_params); + return float64r32_round_pack_canonical(&p, status); +} + bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { FloatParts64 p; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 0d3b407807..d34b2c44d2 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -908,6 +908,18 @@ static inline bool float64_unordered_quiet(float64 a, float64 b, *----------------------------------------------------------------------------*/ float64 float64_default_nan(float_status *status); +/*---------------------------------------------------------------------------- +| Software IEC/IEEE double-precision operations, rounding to single precision, +| returning a result in double precision, with only one rounding step. +*----------------------------------------------------------------------------*/ + +float64 float64r32_add(float64, float64, float_status *status); +float64 float64r32_sub(float64, float64, float_status *status); +float64 float64r32_mul(float64, float64, float_status *status); +float64 float64r32_div(float64, float64, float_status *status); +float64 float64r32_muladd(float64, float64, float64, int, float_status *status); +float64 float64r32_sqrt(float64, float_status *status); + /*---------------------------------------------------------------------------- | Software IEC/IEEE extended double-precision conversion routines. *----------------------------------------------------------------------------*/ From d04ca895dc7fec3a5d6e5a017093f807d47ce141 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 246/421] target/ppc: Add helpers for fmadds et al MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use float64r32_muladd. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 17 ++++++++++++++++- target/ppc/helper.h | 4 ++++ target/ppc/translate/fp-impl.c.inc | 13 +++++-------- 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index aef81a818f..12dd889fb5 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -705,10 +705,25 @@ static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b, return ret; } +static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b, + float64 c, int madd_flags, uintptr_t retaddr) +{ + float64 ret = float64r32_muladd(a, b, c, madd_flags, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_madd(env, flags, 1, retaddr); + } + return ret; +} + #define FPU_FMADD(op, madd_flags) \ uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ uint64_t arg2, uint64_t arg3) \ - { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } + { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } \ + uint64_t helper_##op##s(CPUPPCState *env, uint64_t arg1, \ + uint64_t arg2, uint64_t arg3) \ + { return do_fmadds(env, arg1, arg2, arg3, madd_flags, GETPC()); } #define MADD_FLGS 0 #define MSUB_FLGS float_muladd_negate_c diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 632a81c676..8a9f2ee7ed 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -101,6 +101,10 @@ DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64) +DEF_HELPER_4(fmadds, i64, env, i64, i64, i64) +DEF_HELPER_4(fmsubs, i64, env, i64, i64, i64) +DEF_HELPER_4(fnmadds, i64, env, i64, i64, i64) +DEF_HELPER_4(fnmsubs, i64, env, i64, i64, i64) DEF_HELPER_2(fsqrt, f64, env, f64) DEF_HELPER_2(fre, i64, env, i64) DEF_HELPER_2(fres, i64, env, i64) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index 0767e45d87..2e3162d3e7 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -31,7 +31,7 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx) #endif /*** Floating-Point arithmetic ***/ -#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ +#define _GEN_FLOAT_ACB(name, op1, op2, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ TCGv_i64 t0; \ @@ -50,10 +50,7 @@ static void gen_f##name(DisasContext *ctx) \ get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \ get_fpr(t2, rB(ctx->opcode)); \ - gen_helper_f##op(t3, cpu_env, t0, t1, t2); \ - if (isfloat) { \ - gen_helper_frsp(t3, cpu_env, t3); \ - } \ + gen_helper_f##name(t3, cpu_env, t0, t1, t2); \ set_fpr(rD(ctx->opcode), t3); \ if (set_fprf) { \ gen_compute_fprf_float64(t3); \ @@ -68,8 +65,8 @@ static void gen_f##name(DisasContext *ctx) \ } #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ -_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ -_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); +_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \ +_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type); #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ @@ -233,7 +230,7 @@ static void gen_frsqrtes(DisasContext *ctx) } /* fsel */ -_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); +_GEN_FLOAT_ACB(sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL); /* fsub - fsubs */ GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); /* Optional: */ From 41ae890d08b2254da02c2b422a85cbb9d38843df Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 247/421] target/ppc: Add helper for fsqrts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use float64r32_sqrt. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 12 ++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/fp-impl.c.inc | 3 +-- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 12dd889fb5..07e1695b07 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -775,6 +775,18 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg) return ret; } +/* fsqrts - fsqrts. */ +float64 helper_fsqrts(CPUPPCState *env, float64 arg) +{ + float64 ret = float64r32_sqrt(arg, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); + } + return ret; +} + /* fre - fre. */ float64 helper_fre(CPUPPCState *env, float64 arg) { diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 8a9f2ee7ed..9d7c9a919a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -106,6 +106,7 @@ DEF_HELPER_4(fmsubs, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadds, i64, env, i64, i64, i64) DEF_HELPER_4(fnmsubs, i64, env, i64, i64, i64) DEF_HELPER_2(fsqrt, f64, env, f64) +DEF_HELPER_2(fsqrts, f64, env, f64) DEF_HELPER_2(fre, i64, env, i64) DEF_HELPER_2(fres, i64, env, i64) DEF_HELPER_2(frsqrte, i64, env, i64) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index 2e3162d3e7..baa31d3431 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -270,8 +270,7 @@ static void gen_fsqrts(DisasContext *ctx) t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); get_fpr(t0, rB(ctx->opcode)); - gen_helper_fsqrt(t1, cpu_env, t0); - gen_helper_frsp(t1, cpu_env, t1); + gen_helper_fsqrts(t1, cpu_env, t0); set_fpr(rD(ctx->opcode), t1); gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { From d9e792a1c17020ea87f281b83d4d79a1fda3856f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 248/421] target/ppc: Add helpers for fadds, fsubs, fdivs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use float64r32_{add,sub,div}. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 40 ++++++++++++++++++++++++++++++ target/ppc/helper.h | 3 +++ target/ppc/translate/fp-impl.c.inc | 11 +++----- 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 07e1695b07..c36cf05d80 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -521,6 +521,18 @@ float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +/* fadds - fadds. */ +float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2) +{ + float64 ret = float64r32_add(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); + } + return ret; +} + /* fsub - fsub. */ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { @@ -534,6 +546,18 @@ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +/* fsubs - fsubs. */ +float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2) +{ + float64 ret = float64r32_sub(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); + } + return ret; +} + static void float_invalid_op_mul(CPUPPCState *env, int flags, bool set_fprc, uintptr_t retaddr) { @@ -585,6 +609,22 @@ float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +/* fdivs - fdivs. */ +float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2) +{ + float64 ret = float64r32_div(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_div(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + } + + return ret; +} + static uint64_t float_invalid_cvt(CPUPPCState *env, int flags, uint64_t ret, uint64_t ret_nan, bool set_fprc, uintptr_t retaddr) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 9d7c9a919a..2b80c2f228 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -94,9 +94,12 @@ DEF_HELPER_2(frip, i64, env, i64) DEF_HELPER_2(frim, i64, env, i64) DEF_HELPER_3(fadd, f64, env, f64, f64) +DEF_HELPER_3(fadds, f64, env, f64, f64) DEF_HELPER_3(fsub, f64, env, f64, f64) +DEF_HELPER_3(fsubs, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64) +DEF_HELPER_3(fdivs, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index baa31d3431..b84097544f 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -68,7 +68,7 @@ static void gen_f##name(DisasContext *ctx) \ _GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \ _GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type); -#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +#define _GEN_FLOAT_AB(name, op1, op2, inval, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ TCGv_i64 t0; \ @@ -84,10 +84,7 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t1, rB(ctx->opcode)); \ - gen_helper_f##op(t2, cpu_env, t0, t1); \ - if (isfloat) { \ - gen_helper_frsp(t2, cpu_env, t2); \ - } \ + gen_helper_f##name(t2, cpu_env, t0, t1); \ set_fpr(rD(ctx->opcode), t2); \ if (set_fprf) { \ gen_compute_fprf_float64(t2); \ @@ -100,8 +97,8 @@ static void gen_f##name(DisasContext *ctx) \ tcg_temp_free_i64(t2); \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ -_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); +_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \ +_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type); #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ From 7f87214e3b9f0d562d75f9c7315bfa53b00d29a6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 249/421] target/ppc: Add helper for fmuls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use float64r32_mul. Fixes a double-rounding issue with performing the compuation in float64 and then rounding afterward. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 12 ++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/fp-impl.c.inc | 11 ++++------- 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c36cf05d80..4acc557c08 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -581,6 +581,18 @@ float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) return ret; } +/* fmuls - fmuls. */ +float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2) +{ + float64 ret = float64r32_mul(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_mul(env, flags, 1, GETPC()); + } + return ret; +} + static void float_invalid_op_div(CPUPPCState *env, int flags, bool set_fprc, uintptr_t retaddr) { diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 2b80c2f228..f70a3aefcb 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -98,6 +98,7 @@ DEF_HELPER_3(fadds, f64, env, f64, f64) DEF_HELPER_3(fsub, f64, env, f64, f64) DEF_HELPER_3(fsubs, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64) +DEF_HELPER_3(fmuls, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_3(fdivs, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index b84097544f..bf56e35cb6 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -100,7 +100,7 @@ static void gen_f##name(DisasContext *ctx) \ _GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \ _GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type); -#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +#define _GEN_FLOAT_AC(name, op1, op2, inval, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ TCGv_i64 t0; \ @@ -116,10 +116,7 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \ - gen_helper_f##op(t2, cpu_env, t0, t1); \ - if (isfloat) { \ - gen_helper_frsp(t2, cpu_env, t2); \ - } \ + gen_helper_f##name(t2, cpu_env, t0, t1); \ set_fpr(rD(ctx->opcode), t2); \ if (set_fprf) { \ gen_compute_fprf_float64(t2); \ @@ -132,8 +129,8 @@ static void gen_f##name(DisasContext *ctx) \ tcg_temp_free_i64(t2); \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ -_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); +_GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); \ +_GEN_FLOAT_AC(name##s, 0x3B, op2, inval, set_fprf, type); #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ From dedbfda765a74c3965c5dd676e64fc3afa15e963 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 250/421] target/ppc: Add helper for frsqrtes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no double-rounding bug here, because the result is merely an estimate to within 1 part in 32, but perform the operation with float64r32_div for consistency. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 19 +++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate/fp-impl.c.inc | 3 +-- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 4acc557c08..83c8f2556c 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -896,6 +896,25 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg) return retd; } +/* frsqrtes - frsqrtes. */ +float64 helper_frsqrtes(CPUPPCState *env, float64 arg) +{ + /* "Estimate" the reciprocal with actual division. */ + float64 rets = float64_sqrt(arg, &env->fp_status); + float64 retd = float64r32_div(float64_one, rets, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + /* Reciprocal of (square root of) zero. */ + float_zero_divide_excp(env, GETPC()); + } + + return retd; +} + /* fsel - fsel. */ uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2, uint64_t arg3) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index f70a3aefcb..48774fab19 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -114,6 +114,7 @@ DEF_HELPER_2(fsqrts, f64, env, f64) DEF_HELPER_2(fre, i64, env, i64) DEF_HELPER_2(fres, i64, env, i64) DEF_HELPER_2(frsqrte, i64, env, i64) +DEF_HELPER_2(frsqrtes, i64, env, i64) DEF_HELPER_4(fsel, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index bf56e35cb6..2baae5988f 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -212,8 +212,7 @@ static void gen_frsqrtes(DisasContext *ctx) t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); get_fpr(t0, rB(ctx->opcode)); - gen_helper_frsqrte(t1, cpu_env, t0); - gen_helper_frsp(t1, cpu_env, t1); + gen_helper_frsqrtes(t1, cpu_env, t0); set_fpr(rD(ctx->opcode), t1); gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { From 7d82ea34840e1d53bb173ad628b0f2371741d138 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 251/421] target/ppc: Update fres to new flags and float64r32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no double-rounding bug here, because the result is merely an estimate to within 1 part in 256, but perform the operation with float64r32_div for consistency. Use float_flag_invalid_snan instead of recomputing the snan-ness of the operand. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 83c8f2556c..c955b20739 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -861,20 +861,20 @@ float64 helper_fre(CPUPPCState *env, float64 arg) /* fres - fres. */ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) { - CPU_DoubleU farg; - float32 f32; + /* "Estimate" the reciprocal with actual division. */ + float64 ret = float64r32_div(float64_one, arg, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - farg.ll = arg; - - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal */ + if (unlikely(flags & float_flag_invalid_snan)) { float_invalid_op_vxsnan(env, GETPC()); } - farg.d = float64_div(float64_one, farg.d, &env->fp_status); - f32 = float64_to_float32(farg.d, &env->fp_status); - farg.d = float32_to_float64(f32, &env->fp_status); + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE == 0, the result is 1/2. */ + ret = float64_set_sign(float64_half, float64_is_neg(arg)); + } - return farg.ll; + return ret; } /* frsqrte - frsqrte. */ From a1f1c731c6515313d81630eff8867f0cba27dec5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 252/421] target/ppc: Use helper_todouble/tosingle in helper_xststdcsp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When computing the predicate "is this value currently formatted for single precision", we do not want to round the value according to the current rounding mode, nor perform a floating-point equality. We want to see if the N bits that make up single-precision are the only ones set within the register, and then a bitwise equality. Fixes a bug in which a single-precision NaN is considered !SP, because float64_eq(nan, nan) is always false. Signed-off-by: Richard Henderson Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c955b20739..1e9a161540 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3163,26 +3163,25 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) { uint32_t dcmx, sign, exp; uint32_t cc, match = 0, not_sp = 0; + float64 arg = xb->VsrD(0); + float64 arg_sp; dcmx = DCMX(opcode); - exp = (xb->VsrD(0) >> 52) & 0x7FF; + exp = (arg >> 52) & 0x7FF; + sign = float64_is_neg(arg); - sign = float64_is_neg(xb->VsrD(0)); - if (float64_is_any_nan(xb->VsrD(0))) { + if (float64_is_any_nan(arg)) { match = extract32(dcmx, 6, 1); - } else if (float64_is_infinity(xb->VsrD(0))) { + } else if (float64_is_infinity(arg)) { match = extract32(dcmx, 4 + !sign, 1); - } else if (float64_is_zero(xb->VsrD(0))) { + } else if (float64_is_zero(arg)) { match = extract32(dcmx, 2 + !sign, 1); - } else if (float64_is_zero_or_denormal(xb->VsrD(0)) || - (exp > 0 && exp < 0x381)) { + } else if (float64_is_zero_or_denormal(arg) || (exp > 0 && exp < 0x381)) { match = extract32(dcmx, 0 + !sign, 1); } - not_sp = !float64_eq(xb->VsrD(0), - float32_to_float64( - float64_to_float32(xb->VsrD(0), &env->fp_status), - &env->fp_status), &env->fp_status); + arg_sp = helper_todouble(helper_tosingle(arg)); + not_sp = arg != arg_sp; cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT; env->fpscr &= ~FP_FPCC; From 1da666cd8e795295e23f6feac7cf8d06f9c64725 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 253/421] target/ppc: Disable software TLB for the 7450 family MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit (Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)* We have since 2011 [1] been unable to run OpenBIOS in the 7450s and have not heard of any other software that is used with those CPUs in QEMU. A current discussion [2] shows that the 7450 software TLB is unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS 3.15. With no known support in firmware or OS, this means that no code for any of the 7450 CPUs is ever ran in QEMU. Since the implementation in QEMU of the 7400 MMU is the same as the 7450, except for the software TLB vs. hardware TLB search, this patch changes all 7450 cpus to the 7400 MMU model. This has the practical effect of disabling the software TLB feature while keeping other aspects of address translation working as expected. This allow us to run software on the 7450 family again. *- note that the 7448 is currently aliased in QEMU for a 7400, so it is unaffected by this change. 1- https://bugs.launchpad.net/qemu/+bug/812398 https://gitlab.com/qemu-project/qemu/-/issues/86 2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html message id: 20211119134431.406753-1-farosas@linux.ibm.com Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6695985e9b..509df35d09 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5932,7 +5932,6 @@ static void init_proc_7440(CPUPPCState *env) 0x00000000); /* Memory management */ register_low_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -5956,7 +5955,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -5976,7 +5975,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6067,7 +6066,6 @@ static void init_proc_7450(CPUPPCState *env) 0x00000000); /* Memory management */ register_low_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6091,7 +6089,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6111,7 +6109,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6205,7 +6203,6 @@ static void init_proc_7445(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6229,7 +6226,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6249,7 +6246,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6345,7 +6342,6 @@ static void init_proc_7455(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6369,7 +6365,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6389,7 +6385,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6509,7 +6505,6 @@ static void init_proc_7457(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6533,7 +6528,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6553,7 +6548,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; From b137fb72d7f41a8c7e4dacbd0394612420db6c5d Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 254/421] target/ppc: Disable unused facilities in the e600 CPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The e600 CPU is a successor of the 7448 and like all the 7450s CPUs, it has an optional software TLB feature. We have determined that there is no OS software support for the 7450 software TLB available these days. See the previous commit for more information. This patch disables the SPRs and instructions related to software TLB from the e600 CPU. No functional change intended. These facilities should be used by the OS in interrupt handlers for interrupts that QEMU never generates. Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 509df35d09..962acf295f 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2537,9 +2537,6 @@ static void init_excp_7450(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; @@ -6643,7 +6640,6 @@ static void init_proc_e600(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6667,7 +6663,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->insns_flags2 = PPC_NONE; From a09410ed1fb80a8d5e624d93b51e46ccdafdea64 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 255/421] target/ppc: Remove the software TLB model of 7450 CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit (Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448) The QEMU-side software TLB implementation for the 7450 family of CPUs is being removed due to lack of known users in the real world. The last users in the code were removed by the two previous commits. A brief history: The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU models in switches...") with the mention that Linux was not able to handle the TLB miss interrupts and the MMU model would be kept disabled. At some point later, commit 8ca3f6c382 ("Allow selection of all defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450 family without further justification. We have since the year 2011 [1] been unable to run OpenBIOS in the 7450s and have not heard of any other software that is used with those CPUs in QEMU. Attempts were made to find a guest OS that implemented the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS 3.15. All CPUs that registered this feature were moved to an MMU model that replaces the software TLB with a QEMU hardware TLB implementation. They can now run the same software as the 7400 CPUs, including the OSes mentioned above. References: - https://bugs.launchpad.net/qemu/+bug/812398 https://gitlab.com/qemu-project/qemu/-/issues/86 - https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html message id: 20211119134431.406753-1-farosas@linux.ibm.com Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 6 +++++- target/ppc/cpu.h | 4 +--- target/ppc/cpu_init.c | 26 -------------------------- target/ppc/excp_helper.c | 29 ----------------------------- target/ppc/helper.h | 2 -- target/ppc/mmu_common.c | 19 ------------------- target/ppc/mmu_helper.c | 31 ------------------------------- target/ppc/translate.c | 26 -------------------------- 8 files changed, 6 insertions(+), 137 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 5800fa324e..ef9e324474 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -45,7 +45,11 @@ enum powerpc_mmu_t { POWERPC_MMU_32B = 0x00000001, /* PowerPC 6xx MMU with software TLB */ POWERPC_MMU_SOFT_6xx = 0x00000002, - /* PowerPC 74xx MMU with software TLB */ + /* + * PowerPC 74xx MMU with software TLB (this has been + * disabled, see git history for more information. + * keywords: tlbld tlbli TLBMISS PTEHI PTELO) + */ POWERPC_MMU_SOFT_74xx = 0x00000003, /* PowerPC 4xx MMU with software TLB */ POWERPC_MMU_SOFT_4xx = 0x00000004, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 441d3dce19..c07a8e9f7d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2142,8 +2142,6 @@ enum { PPC_SEGMENT = 0x0000020000000000ULL, /* PowerPC 6xx TLB management instructions */ PPC_6xx_TLB = 0x0000040000000000ULL, - /* PowerPC 74xx TLB management instructions */ - PPC_74xx_TLB = 0x0000080000000000ULL, /* PowerPC 40x TLB management instructions */ PPC_40x_TLB = 0x0000100000000000ULL, /* segment register access instructions for PowerPC 64 "bridge" */ @@ -2200,7 +2198,7 @@ enum { | PPC_CACHE_DCBZ \ | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ - | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ + | PPC_40x_TLB | PPC_SEGMENT_64B \ | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 962acf295f..ed0e2136d9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -945,31 +945,6 @@ static void register_l3_ctrl(CPUPPCState *env) 0x00000000); } -static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) -{ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = nb_tlbs; - env->nb_ways = nb_ways; - env->id_tlbs = 1; - env->tlb_type = TLB_6XX; - /* XXX : not implemented */ - spr_register(env, SPR_PTEHI, "PTEHI", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_PTELO, "PTELO", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_TLBMISS, "TLBMISS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#endif -} - static void register_usprg3_sprs(CPUPPCState *env) { spr_register(env, SPR_USPRG3, "USPRG3", @@ -9238,7 +9213,6 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) case POWERPC_MMU_32B: case POWERPC_MMU_601: case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 17607adbe4..f1da0e119d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -714,35 +714,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Set way using a LRU mechanism */ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; break; - case POWERPC_EXCP_74xx: -#if defined(DEBUG_SOFTWARE_TLB) - if (qemu_log_enabled()) { - const char *es; - target_ulong *miss, *cmp; - int en; - - if (excp == POWERPC_EXCP_IFTLB) { - es = "I"; - en = 'I'; - miss = &env->spr[SPR_TLBMISS]; - cmp = &env->spr[SPR_PTEHI]; - } else { - if (excp == POWERPC_EXCP_DLTLB) { - es = "DL"; - } else { - es = "DS"; - } - en = 'D'; - miss = &env->spr[SPR_TLBMISS]; - cmp = &env->spr[SPR_PTEHI]; - } - qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " - TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, - env->error_code); - } -#endif - msr |= env->error_code; /* key bit */ - break; default: cpu_abort(cs, "Invalid TLB miss exception\n"); break; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 48774fab19..72b2c70ac1 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -625,8 +625,6 @@ DEF_HELPER_2(booke_set_eplc, void, env, tl) DEF_HELPER_2(booke_set_epsc, void, env, tl) DEF_HELPER_2(6xx_tlbd, void, env, tl) DEF_HELPER_2(6xx_tlbi, void, env, tl) -DEF_HELPER_2(74xx_tlbd, void, env, tl) -DEF_HELPER_2(74xx_tlbi, void, env, tl) DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 754509e556..86795b2814 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1147,7 +1147,6 @@ void dump_mmu(CPUPPCState *env) mmubooke206_dump_mmu(env); break; case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: mmu6xx_dump_mmu(env); break; #if defined(TARGET_PPC64) @@ -1181,7 +1180,6 @@ static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, ret = 0; switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_REAL: case POWERPC_MMU_BOOKE: @@ -1234,7 +1232,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: if (real_mode) { ret = check_physical(env, ctx, eaddr, access_type); } else { @@ -1383,9 +1380,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, env->spr[SPR_IMISS] = eaddr; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; - case POWERPC_MMU_SOFT_74xx: - cs->exception_index = POWERPC_EXCP_IFTLB; - goto tlb_miss_74xx; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_ITLB; @@ -1454,19 +1448,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) + get_pteg_offset32(cpu, ctx.hash[1]); break; - case POWERPC_MMU_SOFT_74xx: - if (access_type == MMU_DATA_STORE) { - cs->exception_index = POWERPC_EXCP_DSTLB; - } else { - cs->exception_index = POWERPC_EXCP_DLTLB; - } - tlb_miss_74xx: - /* Implement LRU algorithm */ - env->error_code = ctx.key << 19; - env->spr[SPR_TLBMISS] = (eaddr & ~((target_ulong)0x3)) | - ((env->last_way + 1) & (env->nb_ways - 1)); - env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; - break; case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_DTLB; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e0c4950dda..f992131c1a 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -385,7 +385,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: ppc6xx_tlb_invalidate_all(env); break; case POWERPC_MMU_SOFT_4xx: @@ -434,7 +433,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: ppc6xx_tlb_invalidate_virt(env, addr, 0); if (env->id_tlbs == 1) { ppc6xx_tlb_invalidate_virt(env, addr, 1); @@ -571,35 +569,6 @@ void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN) do_6xx_tlb(env, EPN, 1); } -/* PowerPC 74xx software TLB load instructions helpers */ -static void do_74xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code) -{ - target_ulong RPN, CMP, EPN; - int way; - - RPN = env->spr[SPR_PTELO]; - CMP = env->spr[SPR_PTEHI]; - EPN = env->spr[SPR_TLBMISS] & ~0x3; - way = env->spr[SPR_TLBMISS] & 0x3; - (void)EPN; /* avoid a compiler warning */ - LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx - " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP, - RPN, way); - /* Store this TLB */ - ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK), - way, is_code, CMP, RPN); -} - -void helper_74xx_tlbd(CPUPPCState *env, target_ulong EPN) -{ - do_74xx_tlb(env, EPN, 0); -} - -void helper_74xx_tlbi(CPUPPCState *env, target_ulong EPN) -{ - do_74xx_tlb(env, EPN, 1); -} - /*****************************************************************************/ /* PowerPC 601 specific instructions (POWER bridge) */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9960df6e18..b3f3b408db 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6252,30 +6252,6 @@ static void gen_tlbli_6xx(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } -/* 74xx TLB management */ - -/* tlbld */ -static void gen_tlbld_74xx(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* tlbli */ -static void gen_tlbli_74xx(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - /* POWER instructions not in PowerPC 601 */ /* clf */ @@ -7735,8 +7711,6 @@ GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), -GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), -GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), From 6328a3bb4bc57f8898eed9192546b6d0380eca73 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 256/421] target/ppc: Fix MPCxxx FPU interrupt address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Floating-point Unavailable and Decrementer interrupts are being registered at the same 0x900 address. The FPU should be at 0x800 instead. Verified on MPC555, MPC860 and MPC885 user manuals. Reported-by: BALATON Zoltan Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20211208123029.2052625-2-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ed0e2136d9..7e61994e35 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2155,7 +2155,7 @@ static void init_excp_MPC5xx(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; @@ -2182,7 +2182,7 @@ static void init_excp_MPC8xx(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; From fd77f75710c30416d501fa316040290e9a82960f Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 257/421] target/ppc: Remove 603e exception model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 603e uses the same exception code as 603 so we don't need a dedicated entry for it. This is only a removal of redundant code, no functional change. Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20211208123029.2052625-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu-qom.h | 2 -- target/ppc/cpu_init.c | 32 ++------------------------------ target/ppc/excp_helper.c | 1 - 3 files changed, 2 insertions(+), 33 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index ef9e324474..7d299f90c7 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -98,8 +98,6 @@ enum powerpc_excp_t { POWERPC_EXCP_602, /* PowerPC 603 exception model */ POWERPC_EXCP_603, - /* PowerPC 603e exception model */ - POWERPC_EXCP_603E, /* PowerPC G2 exception model */ POWERPC_EXCP_G2, /* PowerPC 604 exception model */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7e61994e35..db06568777 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -4721,41 +4721,13 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data) POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; } -static void init_proc_603E(CPUPPCState *env) -{ - register_ne_601_sprs(env); - register_sdr1_sprs(env); - register_603_sprs(env); - /* Time base */ - register_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - register_low_BATs(env); - register_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_603(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); dc->desc = "PowerPC 603e"; - pcc->init_proc = init_proc_603E; + pcc->init_proc = init_proc_603; pcc->check_pow = check_pow_hid0; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | @@ -4781,7 +4753,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_603E; + pcc->excp_model = POWERPC_EXCP_603; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_ec603e; pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f1da0e119d..1612b9b30e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -672,7 +672,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) switch (excp_model) { case POWERPC_EXCP_602: case POWERPC_EXCP_603: - case POWERPC_EXCP_603E: case POWERPC_EXCP_G2: /* Swap temporary saved registers with GPRs */ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { From 84835acbbfa4cb05146e218a7e5228707513d462 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 258/421] target/ppc: Set 601v exception model id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The exception model id for 601v has been removed without mention why. I assume it was inadvertent and restore it here. Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling") Signed-off-by: Fabiano Rosas Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Message-Id: <20211208123029.2052625-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index db06568777..ccdd5c9bad 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -4579,6 +4579,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) (1ull << MSR_IR) | (1ull << MSR_DR); pcc->mmu_model = POWERPC_MMU_601; + pcc->excp_model = POWERPC_EXCP_601; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; From c8f49e6b938e72eba2331cfce0ab20c6994ac74d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:16 +0100 Subject: [PATCH 259/421] target/ppc: remove 401/403 CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They have been there since 2007 without any board using them, most were protected by a TODO define. Drop support. Signed-off-by: Cédric Le Goater Reviewed-by: Richard Henderson Reviewed-by: David Gibson Reviewed-by: Daniel Henrique Barboza Message-Id: <20211202191108.1291515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater --- target/ppc/cpu-models.c | 34 --- target/ppc/cpu-models.h | 19 -- target/ppc/cpu-qom.h | 4 - target/ppc/cpu_init.c | 512 --------------------------------------- target/ppc/excp_helper.c | 1 - target/ppc/mmu_common.c | 41 +--- target/ppc/mmu_helper.c | 1 - 7 files changed, 4 insertions(+), 608 deletions(-) diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 4baa111713..c9fcb6119f 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -67,40 +67,6 @@ POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type) /* Embedded PowerPC */ - /* PowerPC 401 family */ - POWERPC_DEF("401", CPU_POWERPC_401, 401, - "Generic PowerPC 401") - /* PowerPC 401 cores */ - POWERPC_DEF("401a1", CPU_POWERPC_401A1, 401, - "PowerPC 401A1") - POWERPC_DEF("401b2", CPU_POWERPC_401B2, 401x2, - "PowerPC 401B2") - POWERPC_DEF("401c2", CPU_POWERPC_401C2, 401x2, - "PowerPC 401C2") - POWERPC_DEF("401d2", CPU_POWERPC_401D2, 401x2, - "PowerPC 401D2") - POWERPC_DEF("401e2", CPU_POWERPC_401E2, 401x2, - "PowerPC 401E2") - POWERPC_DEF("401f2", CPU_POWERPC_401F2, 401x2, - "PowerPC 401F2") - /* XXX: to be checked */ - POWERPC_DEF("401g2", CPU_POWERPC_401G2, 401x2, - "PowerPC 401G2") - /* PowerPC 401 microcontrollers */ - POWERPC_DEF("iop480", CPU_POWERPC_IOP480, IOP480, - "IOP480 (401 microcontroller)") - POWERPC_DEF("cobra", CPU_POWERPC_COBRA, 401, - "IBM Processor for Network Resources") - /* PowerPC 403 family */ - /* PowerPC 403 microcontrollers */ - POWERPC_DEF("403ga", CPU_POWERPC_403GA, 403, - "PowerPC 403 GA") - POWERPC_DEF("403gb", CPU_POWERPC_403GB, 403, - "PowerPC 403 GB") - POWERPC_DEF("403gc", CPU_POWERPC_403GC, 403, - "PowerPC 403 GC") - POWERPC_DEF("403gcx", CPU_POWERPC_403GCX, 403GCX, - "PowerPC 403 GCX") /* PowerPC 405 family */ /* PowerPC 405 cores */ POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405, diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0952592759..bf1dc7e5ca 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -38,27 +38,8 @@ extern PowerPCCPUAlias ppc_cpu_aliases[]; /*****************************************************************************/ /* PVR definitions for most known PowerPC */ enum { - /* PowerPC 401 family */ - /* Generic PowerPC 401 */ -#define CPU_POWERPC_401 CPU_POWERPC_401G2 - /* PowerPC 401 cores */ - CPU_POWERPC_401A1 = 0x00210000, - CPU_POWERPC_401B2 = 0x00220000, - CPU_POWERPC_401C2 = 0x00230000, - CPU_POWERPC_401D2 = 0x00240000, - CPU_POWERPC_401E2 = 0x00250000, - CPU_POWERPC_401F2 = 0x00260000, - CPU_POWERPC_401G2 = 0x00270000, - /* PowerPC 401 microcontrolers */ -#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2 /* IBM Processor for Network Resources */ CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */ - /* PowerPC 403 family */ - /* PowerPC 403 microcontrollers */ - CPU_POWERPC_403GA = 0x00200011, - CPU_POWERPC_403GB = 0x00200100, - CPU_POWERPC_403GC = 0x00200200, - CPU_POWERPC_403GCX = 0x00201400, /* PowerPC 405 family */ /* PowerPC 405 cores */ CPU_POWERPC_405D2 = 0x20010000, diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 7d299f90c7..99a6b509af 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -53,8 +53,6 @@ enum powerpc_mmu_t { POWERPC_MMU_SOFT_74xx = 0x00000003, /* PowerPC 4xx MMU with software TLB */ POWERPC_MMU_SOFT_4xx = 0x00000004, - /* PowerPC 4xx MMU with software TLB and zones protections */ - POWERPC_MMU_SOFT_4xx_Z = 0x00000005, /* PowerPC MMU in real mode only */ POWERPC_MMU_REAL = 0x00000006, /* Freescale MPC8xx MMU model */ @@ -149,8 +147,6 @@ enum powerpc_input_t { PPC_FLAGS_INPUT_POWER7, /* PowerPC POWER9 bus */ PPC_FLAGS_INPUT_POWER9, - /* PowerPC 401 bus */ - PPC_FLAGS_INPUT_401, /* Freescale RCPU bus */ PPC_FLAGS_INPUT_RCPU, }; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ccdd5c9bad..96034889dd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1553,169 +1553,6 @@ static void register_405_sprs(CPUPPCState *env) register_usprgh_sprs(env); } -/* SPR shared between PowerPC 401 & 403 implementations */ -static void register_401_403_sprs(CPUPPCState *env) -{ - /* Time base */ - spr_register(env, SPR_403_VTBL, "TBL", - &spr_read_tbl, SPR_NOACCESS, - &spr_read_tbl, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_403_TBL, "TBL", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbl, - 0x00000000); - spr_register(env, SPR_403_VTBU, "TBU", - &spr_read_tbu, SPR_NOACCESS, - &spr_read_tbu, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_403_TBU, "TBU", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbu, - 0x00000000); - /* Debug */ - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_403_CDBCR, "CDBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 401 implementation */ -static void register_401_sprs(CPUPPCState *env) -{ - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Storage control */ - /* XXX: TODO: not implemented */ - spr_register(env, SPR_405_SLER, "SLER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_sler, - 0x00000000); - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void register_401x2_sprs(CPUPPCState *env) -{ - register_401_sprs(env); - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 403 implementation */ -static void register_403_sprs(CPUPPCState *env) -{ - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC2, "DAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC2, "IAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void register_403_real_sprs(CPUPPCState *env) -{ - spr_register(env, SPR_403_PBL1, "PBL1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBU1, "PBU1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBL2, "PBL2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBU2, "PBU2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); -} - -static void register_403_mmu_sprs(CPUPPCState *env) -{ - /* MMU */ - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC compression coprocessor extension */ -static void register_compress_sprs(CPUPPCState *env) -{ - /* XXX : not implemented */ - spr_register(env, SPR_401_SKR, "SKR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} static void register_5xx_8xx_sprs(CPUPPCState *env) { @@ -2103,26 +1940,6 @@ static void register_8xx_sprs(CPUPPCState *env) /*****************************************************************************/ /* Exception vectors models */ -static void init_excp_4xx_real(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0xFFFFFFFCUL; -#endif -} - static void init_excp_4xx_softmmu(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -2662,335 +2479,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env) \ static void glue(glue(ppc_, _name), _cpu_family_class_init) -static void init_proc_401(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401_sprs(env); - init_excp_4xx_real(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401"; - pcc->init_proc = init_proc_401; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_WRTEE | PPC_DCR | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_401x2(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401x2_sprs(env); - register_compress_sprs(env); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401x2"; - pcc->init_proc = init_proc_401x2; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_401x3(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401_sprs(env); - register_401x2_sprs(env); - register_compress_sprs(env); - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401x3"; - pcc->init_proc = init_proc_401x3; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_IOP480(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401x2_sprs(env); - register_compress_sprs(env); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "IOP480"; - pcc->init_proc = init_proc_IOP480; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_403(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_403_sprs(env); - register_403_real_sprs(env); - init_excp_4xx_real(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(403)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 403"; - pcc->init_proc = init_proc_403; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_PE) | - (1ull << MSR_PX) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_403GCX(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_403_sprs(env); - register_403_real_sprs(env); - register_403_mmu_sprs(env); - /* Bus access control */ - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 403 GCX"; - pcc->init_proc = init_proc_403GCX; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_PE) | - (1ull << MSR_PX) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | - POWERPC_FLAG_BUS_CLK; -} - static void init_proc_405(CPUPPCState *env) { /* Time base */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 1612b9b30e..cbd88f74c9 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1434,7 +1434,6 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, switch (env->mmu_model) { case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: env->spr[SPR_40x_DEAR] = vaddr; break; case POWERPC_MMU_BOOKE: diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 86795b2814..4e278365ca 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1173,11 +1173,9 @@ void dump_mmu(CPUPPCState *env) static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, MMUAccessType access_type) { - int in_plb, ret; - ctx->raddr = eaddr; ctx->prot = PAGE_READ | PAGE_EXEC; - ret = 0; + switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_4xx: @@ -1186,39 +1184,12 @@ static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, ctx->prot |= PAGE_WRITE; break; - case POWERPC_MMU_SOFT_4xx_Z: - if (unlikely(msr_pe != 0)) { - /* - * 403 family add some particular protections, using - * PBL/PBU registers for accesses with no translation. - */ - in_plb = - /* Check PLB validity */ - (env->pb[0] < env->pb[1] && - /* and address in plb area */ - eaddr >= env->pb[0] && eaddr < env->pb[1]) || - (env->pb[2] < env->pb[3] && - eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; - if (in_plb ^ msr_px) { - /* Access in protected area */ - if (access_type == MMU_DATA_STORE) { - /* Access is not allowed */ - ret = -2; - } - } else { - /* Read-write access is allowed */ - ctx->prot |= PAGE_WRITE; - } - } - break; - default: /* Caller's checks mean we should never get here for other models */ - abort(); - return -1; + g_assert_not_reached(); } - return ret; + return 0; } int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, @@ -1247,7 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, break; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: if (real_mode) { ret = check_physical(env, ctx, eaddr, access_type); } else { @@ -1381,7 +1351,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = eaddr; @@ -1449,7 +1418,6 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, get_pteg_offset32(cpu, ctx.hash[1]); break; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = eaddr; @@ -1482,8 +1450,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, /* Access rights violation */ cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; - if (env->mmu_model == POWERPC_MMU_SOFT_4xx - || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { + if (env->mmu_model == POWERPC_MMU_SOFT_4xx) { env->spr[SPR_40x_DEAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_40x_ESR] |= 0x00800000; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f992131c1a..2ec3d203a0 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -388,7 +388,6 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc6xx_tlb_invalidate_all(env); break; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: From 82f64c2384507477618db75d24c92b7324ff674c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 260/421] ppc/ppc405: Change kernel load address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The default addresses to load the kernel, fdt, initrd of AMCC boards in U-Boot v2015.10 are : "kernel_addr_r=1000000\0" "fdt_addr_r=1800000\0" "ramdisk_addr_r=1900000\0" The taihu is one of these boards, the ref405ep is not but we don't have much information on it and both boards have a very similar address space layout. Also, if loaded at address 0, U-Boot will partially overwrite the uImage because of a bug in get_ram_size() (U-Boot v2015.10) not restoring properly the probed RAM contents and because the exception vectors are installed in the same range. Finally, a gzipped kernel image will be uncompressed at 0x0. These are all good reasons for not mappping a kernel image at this address. Change the kernel load address to match U-Boot expectations and fix loading. Cc: Christophe Leroy Signed-off-by: Cédric Le Goater Reviewed-by: Thomas Huth Message-Id: <20211202191446.1292125-1-clg@kaod.org> Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-2-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 972a7a4a3e..b4249f4626 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -45,7 +45,7 @@ #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2 * MiB) -#define KERNEL_LOAD_ADDR 0x00000000 +#define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 #define USE_FLASH_BIOS From 26e8bed611222c4e2b9408a8d5a405158e491a98 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 261/421] ppc: Mark the 'taihu' machine as deprecated MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar, except for some external periphery. However, the periphery of the 'taihu' machine is hardly emulated at all (e.g. neither the LCD nor the USB part had been implemented), so there is not much value added by this board. The users can use the 'ref405ep' machine to test their PPC405 code instead. Signed-off-by: Thomas Huth Reviewed-by: Daniel Henrique Barboza Message-Id: <20211203164904.290954-2-thuth@redhat.com> Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-3-clg@kaod.org> Signed-off-by: Cédric Le Goater --- docs/about/deprecated.rst | 9 +++++++++ hw/ppc/ppc405_boards.c | 1 + 2 files changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ff7488cb63..5693abb663 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -315,6 +315,15 @@ This machine is deprecated because we have enough AST2500 based OpenPOWER machines. It can be easily replaced by the ``witherspoon-bmc`` or the ``romulus-bmc`` machines. +PPC 405 ``taihu`` machine (since 7.0) +''''''''''''''''''''''''''''''''''''' + +The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar, +except for some external periphery. However, the periphery of the ``taihu`` +machine is hardly emulated at all (e.g. neither the LCD nor the USB part had +been implemented), so there is not much value added by this board. Use the +``ref405ep`` machine instead. + Backend options --------------- diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index b4249f4626..f1623aa622 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -547,6 +547,7 @@ static void taihu_class_init(ObjectClass *oc, void *data) mc->init = taihu_405ep_init; mc->default_ram_size = 0x08000000; mc->default_ram_id = "taihu_405ep.ram"; + mc->deprecation_reason = "incomplete, use 'ref405ep' instead"; } static const TypeInfo taihu_type = { From de82dabeadd0511a3b18c76dc3c666a63798f8ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 262/421] ppc: Add trace-events for DCR accesses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-4-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc.c | 2 ++ hw/ppc/trace-events | 3 +++ 2 files changed, 5 insertions(+) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index e8127599c9..818d757985 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1367,6 +1367,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) if (dcr->dcr_read == NULL) goto error; *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); + trace_ppc_dcr_read(dcrn, *valp); return 0; @@ -1386,6 +1387,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) dcr = &dcr_env->dcrn[dcrn]; if (dcr->dcr_write == NULL) goto error; + trace_ppc_dcr_write(dcrn, val); (*dcr->dcr_write)(dcr->opaque, dcrn, val); return 0; diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 3bf43fa340..602adb8315 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -119,6 +119,9 @@ ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d" ppc_irq_reset(const char *name) "%s" ppc_irq_cpu(const char *action) "%s" +ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" +ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" + # prep_systemio.c prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x" From 09960a5be3ec4b8caddb894ad5b73d4533ead5fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 263/421] ppc/ppc405: Convert printfs to trace-events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit and one error message to a LOG_GUEST_ERROR. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-5-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_uc.c | 159 +++++++++++++++----------------------------- hw/ppc/trace-events | 20 ++++++ 2 files changed, 74 insertions(+), 105 deletions(-) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e632c408bd..e14d61e9b8 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/ppc/ppc.h" #include "hw/i2c/ppc4xx_i2c.h" @@ -38,15 +39,7 @@ #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" #include "qapi/error.h" - -//#define DEBUG_OPBA -//#define DEBUG_SDRAM -//#define DEBUG_GPIO -//#define DEBUG_SERIAL -//#define DEBUG_OCM -//#define DEBUG_GPT -//#define DEBUG_CLOCKS -//#define DEBUG_CLOCKS_LL +#include "trace.h" ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) @@ -287,13 +280,9 @@ struct ppc4xx_opba_t { static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_opba_t *opba; + ppc4xx_opba_t *opba = opaque; uint32_t ret; -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - opba = opaque; switch (addr) { case 0x00: ret = opba->cr; @@ -306,19 +295,17 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) break; } + trace_opba_readb(addr, ret); return ret; } static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_opba_t *opba; + ppc4xx_opba_t *opba = opaque; + + trace_opba_writeb(addr, value); -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba = opaque; switch (addr) { case 0x00: opba->cr = value & 0xF8; @@ -353,10 +340,9 @@ static void ppc4xx_opba_init(hwaddr base) { ppc4xx_opba_t *opba; + trace_opba_init(base); + opba = g_malloc0(sizeof(ppc4xx_opba_t)); -#ifdef DEBUG_OPBA - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); memory_region_add_subregion(get_system_memory(), base, &opba->io); qemu_register_reset(ppc4xx_opba_reset, opba); @@ -707,20 +693,14 @@ struct ppc405_gpio_t { static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); -#endif - + trace_ppc405_gpio_read(addr, size); return 0; } static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", - __func__, addr, size, value); -#endif + trace_ppc405_gpio_write(addr, size, value); } static const MemoryRegionOps ppc405_gpio_ops = { @@ -737,10 +717,9 @@ static void ppc405_gpio_init(hwaddr base) { ppc405_gpio_t *gpio; + trace_ppc405_gpio_init(base); + gpio = g_malloc0(sizeof(ppc405_gpio_t)); -#ifdef DEBUG_GPIO - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); memory_region_add_subregion(get_system_memory(), base, &gpio->io); qemu_register_reset(&ppc405_gpio_reset, gpio); @@ -770,25 +749,19 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl) { -#ifdef DEBUG_OCM - printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 - " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 - " (%08" PRIx32 " %08" PRIx32 ")\n", - isarc, isacntl, dsarc, dsacntl, - ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); -#endif + trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, + ocm->isacntl, ocm->dsarc, ocm->dsacntl); + if (ocm->isarc != isarc || (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { if (ocm->isacntl & 0x80000000) { /* Unmap previously assigned memory region */ - printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); + trace_ocm_unmap("ISA", ocm->isarc); memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); } if (isacntl & 0x80000000) { /* Map new instruction memory region */ -#ifdef DEBUG_OCM - printf("OCM map ISA %08" PRIx32 "\n", isarc); -#endif + trace_ocm_map("ISA", isarc); memory_region_add_subregion(get_system_memory(), isarc, &ocm->isarc_ram); } @@ -799,9 +772,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, /* Beware not to unmap the region we just mapped */ if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { /* Unmap previously assigned memory region */ -#ifdef DEBUG_OCM - printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); -#endif + trace_ocm_unmap("DSA", ocm->dsarc); memory_region_del_subregion(get_system_memory(), &ocm->dsarc_ram); } @@ -810,9 +781,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, /* Beware not to remap the region we just mapped */ if (!(isacntl & 0x80000000) || dsarc != isarc) { /* Map new data memory region */ -#ifdef DEBUG_OCM - printf("OCM map DSA %08" PRIx32 "\n", dsarc); -#endif + trace_ocm_map("DSA", dsarc); memory_region_add_subregion(get_system_memory(), dsarc, &ocm->dsarc_ram); } @@ -988,14 +957,12 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_gpt_t *gpt; + ppc4xx_gpt_t *gpt = opaque; uint32_t ret; int idx; -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - gpt = opaque; + trace_ppc4xx_gpt_read(addr, size); + switch (addr) { case 0x00: /* Time base counter */ @@ -1044,14 +1011,11 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_gpt_t *gpt; + ppc4xx_gpt_t *gpt = opaque; int idx; -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - gpt = opaque; + trace_ppc4xx_gpt_write(addr, size, value); + switch (addr) { case 0x00: /* Time base counter */ @@ -1144,14 +1108,13 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) ppc4xx_gpt_t *gpt; int i; + trace_ppc4xx_gpt_init(base); + gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); for (i = 0; i < 5; i++) { gpt->irqs[i] = irqs[i]; } gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); -#ifdef DEBUG_GPT - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); qemu_register_reset(ppc4xx_gpt_reset, gpt); @@ -1215,17 +1178,14 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) VCO_out = 0; if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ -#ifdef DEBUG_CLOCKS_LL - printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); -#endif + trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ -#ifdef DEBUG_CLOCKS_LL - printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); -#endif + trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); VCO_out = (uint64_t)cpc->sysclk * M * D; if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { /* Error - unlock the PLL */ - printf("VCO out of range %" PRIu64 "\n", VCO_out); + qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", + VCO_out); #if 0 cpc->pllmr[1] &= ~0x80000000; goto pll_bypass; @@ -1246,54 +1206,43 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) } /* Now, compute all other clocks */ D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ -#ifdef DEBUG_CLOCKS_LL - printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); CPU_clk = PLL_out / D; D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ -#ifdef DEBUG_CLOCKS_LL - printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); PLB_clk = CPU_clk / D; D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); OPB_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); EBC_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); MAL_clk = PLB_clk / D; D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); PCI_clk = PLB_clk / D; D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ -#ifdef DEBUG_CLOCKS_LL - printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); -#endif + trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); UART0_clk = PLL_out / D; D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ -#ifdef DEBUG_CLOCKS_LL - printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); -#endif + trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); UART1_clk = PLL_out / D; -#ifdef DEBUG_CLOCKS - printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 - " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); - printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 - " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 - " UART1 %" PRIu32 "\n", - CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, - UART0_clk, UART1_clk); -#endif + + if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { + g_autofree char *trace = g_strdup_printf( + "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 + " PLL out %" PRIu64 " Hz\n" + "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 + " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 + " UART1 %" PRIu32 "\n", + cpc->sysclk, VCO_out, PLL_out, + CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, + UART0_clk, UART1_clk); + trace_ppc405ep_clocks_setup(trace); + } + /* Setup CPU clocks */ clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); /* Setup PLB clock */ diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 602adb8315..ada644652d 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -144,3 +144,23 @@ ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 + +# ppc405_boards.c +opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 +opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64 +opba_init(uint64_t addr) "offet 0x%" PRIx64 + +ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" +ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64 +ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64 + +ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")" +ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32 +ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32 + +ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" +ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64 +ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64 + +ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d" +ppc405ep_clocks_setup(const char *trace) "%s" From af9e361512a39f1b9a6b29a838656dbeb8fa7233 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 264/421] ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was introduced in commit b8d3f5d12642 ("Add flags to support PowerPC 405 bootinfos variations.") but since its value has always been set to '1'. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-6-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 3 +-- hw/ppc/ppc405_boards.c | 2 +- hw/ppc/ppc405_uc.c | 8 +++----- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c58f739886..4cb77aca56 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -56,8 +56,7 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags); +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index f1623aa622..2ac38c86a6 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -261,7 +261,7 @@ static void ref405ep_init(MachineState *machine) bd.bi_plb_busfreq = 33333333; bd.bi_pci_busfreq = 33333333; bd.bi_opbfreq = 33333333; - bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); + bdloc = ppc405_set_bootinfo(env, &bd); env->gpr[3] = bdloc; kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e14d61e9b8..6806d6be31 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -41,8 +41,7 @@ #include "qapi/error.h" #include "trace.h" -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags) +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) { CPUState *cs = env_cpu(env); ram_addr_t bdloc; @@ -81,9 +80,8 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); } n = 0x6A; - if (flags & 0x00000001) { - for (i = 0; i < 6; i++) - stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); + for (i = 0; i < 6; i++) { + stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); } stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); n += 4; From a3e973e1bfffb2cddfc0763fe90414f8ca3bf531 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 265/421] ppc/ppc405: Change ppc405ep_init() return value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I will be useful to rework the boot from Linux. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-7-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 6 +++++- hw/ppc/ppc405_uc.c | 4 ++-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 4cb77aca56..ad5f4026b5 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -61,7 +61,7 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); -CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, +PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 2ac38c86a6..fcdb6d4cf8 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -145,6 +145,7 @@ static void ref405ep_init(MachineState *machine) const char *initrd_filename = machine->initrd_filename; char *filename; ppc4xx_bd_info_t bd; + PowerPCCPU *cpu; CPUPPCState *env; DeviceState *dev; SysBusDevice *s; @@ -180,8 +181,11 @@ static void ref405ep_init(MachineState *machine) memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; - env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, + + cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); + env = &cpu->env; + /* allocate SRAM */ sram_size = 512 * KiB; memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 6806d6be31..4ad81695e8 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1391,7 +1391,7 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], #endif } -CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, +PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], @@ -1490,5 +1490,5 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); - return env; + return cpu; } From f61b99d35e31d98f1799cdfdf14ec96093e903a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 266/421] ppc/ppc405: Add some address space definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-8-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 7 +++++++ hw/ppc/ppc405_boards.c | 16 +++++++--------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ad5f4026b5..ea48c36269 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -27,6 +27,13 @@ #include "hw/ppc/ppc4xx.h" +#define PPC405EP_SDRAM_BASE 0x00000000 +#define PPC405EP_NVRAM_BASE 0xF0000000 +#define PPC405EP_FPGA_BASE 0xF0300000 +#define PPC405EP_SRAM_BASE 0xFFF00000 +#define PPC405EP_SRAM_SIZE (512 * KiB) +#define PPC405EP_FLASH_BASE 0xFFF80000 + /* Bootinfo as set-up by u-boot */ typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; struct ppc4xx_bd_info_t { diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index fcdb6d4cf8..60dc81fa48 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -154,7 +154,6 @@ static void ref405ep_init(MachineState *machine) ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - target_ulong sram_size; long bios_size; //int phy_addr = 0; //static int phy_addr = 1; @@ -187,10 +186,9 @@ static void ref405ep_init(MachineState *machine) env = &cpu->env; /* allocate SRAM */ - sram_size = 512 * KiB; - memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, + memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, &error_fatal); - memory_region_add_subregion(sysmem, 0xFFF00000, sram); + memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); /* allocate and load BIOS */ #ifdef USE_FLASH_BIOS dinfo = drive_get(IF_PFLASH, 0, 0); @@ -230,24 +228,24 @@ static void ref405ep_init(MachineState *machine) } } /* Register FPGA */ - ref405ep_fpga_init(sysmem, 0xF0300000); + ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE); /* Register NVRAM */ dev = qdev_new("sysbus-m48t08"); qdev_prop_set_int32(dev, "base-year", 1968); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, 0xF0000000); + sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); /* Load kernel */ linux_boot = (kernel_filename != NULL); if (linux_boot) { memset(&bd, 0, sizeof(bd)); - bd.bi_memstart = 0x00000000; + bd.bi_memstart = PPC405EP_SDRAM_BASE; bd.bi_memsize = machine->ram_size; bd.bi_flashstart = -bios_size; bd.bi_flashsize = -bios_size; bd.bi_flashoffset = 0; - bd.bi_sramstart = 0xFFF00000; - bd.bi_sramsize = sram_size; + bd.bi_sramstart = PPC405EP_SRAM_BASE; + bd.bi_sramsize = PPC405EP_SRAM_SIZE; bd.bi_bootflags = 0; bd.bi_intfreq = 133333333; bd.bi_busfreq = 33333333; From 9fb100efa169749da9f148440e3b1005345fb6d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 267/421] ppc/ppc405: Remove flash support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is currently impossible to find a "ppc405_rom.bin" firmware file or a full flash image for the PPC405EP evalution board. Even if it should be technically possible to recreate such an image, it's unlikely that anyone will do it since the board is obsolete and support in QEMU has been broken for about 10 years. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-9-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 60dc81fa48..a385e8f150 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -161,7 +161,6 @@ static void ref405ep_init(MachineState *machine) long kernel_size, initrd_size; int linux_boot; int len; - DriveInfo *dinfo; MemoryRegion *sysmem = get_system_memory(); DeviceState *uicdev; @@ -189,19 +188,8 @@ static void ref405ep_init(MachineState *machine) memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, &error_fatal); memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); + /* allocate and load BIOS */ -#ifdef USE_FLASH_BIOS - dinfo = drive_get(IF_PFLASH, 0, 0); - if (dinfo) { - bios_size = 8 * MiB; - pflash_cfi02_register((uint32_t)(-bios_size), - "ef405ep.bios", bios_size, - blk_by_legacy_dinfo(dinfo), - 64 * KiB, 1, - 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, - 1); - } else -#endif { bios = g_new(MemoryRegion, 1); memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, From 13d63de59bf31119f3d47e638a64b27da86e1a5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 268/421] ppc/ppc405: Rework FW load MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QEMU installs a custom U-Boot in-memory descriptor to share board information with Linux, which means that the QEMU machine was initially designed to support booting Linux directly without using the loaded FW. But, it's not that simple because the CPU still starts at address 0xfffffffc where nothing is currently mapped. Support must have been broken these last years. Since we can not find a "ppc405_rom.bin" firmware file, request one to be specified on the command line. A consequence of this change is that the machine can be booted directly from Linux without any FW being loaded. This is still broken and the CPU start address will be fixed in the next changes. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-10-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 45 +++++++++++++++++++----------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index a385e8f150..cfed43dba2 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -139,24 +139,19 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) static void ref405ep_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); - const char *bios_name = machine->firmware ?: BIOS_FILENAME; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - char *filename; ppc4xx_bd_info_t bd; PowerPCCPU *cpu; CPUPPCState *env; DeviceState *dev; SysBusDevice *s; - MemoryRegion *bios; MemoryRegion *sram = g_new(MemoryRegion, 1); ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - long bios_size; - //int phy_addr = 0; - //static int phy_addr = 1; + long bios_size = -1; target_ulong kernel_base, initrd_base; long kernel_size, initrd_size; int linux_boot; @@ -190,31 +185,31 @@ static void ref405ep_init(MachineState *machine) memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); /* allocate and load BIOS */ - { - bios = g_new(MemoryRegion, 1); + if (machine->firmware) { + MemoryRegion *bios = g_new(MemoryRegion, 1); + g_autofree char *filename; + memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, &error_fatal); - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - if (filename) { - bios_size = load_image_size(filename, - memory_region_get_ram_ptr(bios), - BIOS_SIZE); - g_free(filename); - if (bios_size < 0) { - error_report("Could not load PowerPC BIOS '%s'", bios_name); - exit(1); - } - bios_size = (bios_size + 0xfff) & ~0xfff; - memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); - } else if (!qtest_enabled() || kernel_filename != NULL) { - error_report("Could not load PowerPC BIOS '%s'", bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); + if (!filename) { + error_report("Could not find firmware '%s'", machine->firmware); exit(1); - } else { - /* Avoid an uninitialized variable warning */ - bios_size = -1; } + + bios_size = load_image_size(filename, + memory_region_get_ram_ptr(bios), + BIOS_SIZE); + if (bios_size < 0) { + error_report("Could not load PowerPC BIOS '%s'", machine->firmware); + exit(1); + } + + bios_size = (bios_size + 0xfff) & ~0xfff; + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } + /* Register FPGA */ ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE); /* Register NVRAM */ From e3931ecab32d993fa89802b3a8af39f3ea957b3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 269/421] ppc/ppc405: Introduce ppc405_set_default_bootinfo() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This routine is a small helper to cleanup the code. The update of the flash fields were removed because there are not of any use when booting from a Linux kernel image. It should be functionally equivalent. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-11-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 2 +- hw/ppc/ppc405_boards.c | 28 +--------------------------- hw/ppc/ppc405_uc.c | 41 ++++++++++++++++++++++++++++++++++++++++- 3 files changed, 42 insertions(+), 29 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index ea48c36269..6fb8b41bbc 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,7 +63,7 @@ struct ppc4xx_bd_info_t { }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd); +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index cfed43dba2..71a652e2d8 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -142,7 +142,6 @@ static void ref405ep_init(MachineState *machine) const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - ppc4xx_bd_info_t bd; PowerPCCPU *cpu; CPUPPCState *env; DeviceState *dev; @@ -221,32 +220,7 @@ static void ref405ep_init(MachineState *machine) /* Load kernel */ linux_boot = (kernel_filename != NULL); if (linux_boot) { - memset(&bd, 0, sizeof(bd)); - bd.bi_memstart = PPC405EP_SDRAM_BASE; - bd.bi_memsize = machine->ram_size; - bd.bi_flashstart = -bios_size; - bd.bi_flashsize = -bios_size; - bd.bi_flashoffset = 0; - bd.bi_sramstart = PPC405EP_SRAM_BASE; - bd.bi_sramsize = PPC405EP_SRAM_SIZE; - bd.bi_bootflags = 0; - bd.bi_intfreq = 133333333; - bd.bi_busfreq = 33333333; - bd.bi_baudrate = 115200; - bd.bi_s_version[0] = 'Q'; - bd.bi_s_version[1] = 'M'; - bd.bi_s_version[2] = 'U'; - bd.bi_s_version[3] = '\0'; - bd.bi_r_version[0] = 'Q'; - bd.bi_r_version[1] = 'E'; - bd.bi_r_version[2] = 'M'; - bd.bi_r_version[3] = 'U'; - bd.bi_r_version[4] = '\0'; - bd.bi_procfreq = 133333333; - bd.bi_plb_busfreq = 33333333; - bd.bi_pci_busfreq = 33333333; - bd.bi_opbfreq = 33333333; - bdloc = ppc405_set_bootinfo(env, &bd); + bdloc = ppc405_set_bootinfo(env, machine->ram_size); env->gpr[3] = bdloc; kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 4ad81695e8..303af58444 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -41,7 +41,35 @@ #include "qapi/error.h" #include "trace.h" -ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) +static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, + ram_addr_t ram_size) +{ + memset(bd, 0, sizeof(*bd)); + + bd->bi_memstart = PPC405EP_SDRAM_BASE; + bd->bi_memsize = ram_size; + bd->bi_sramstart = PPC405EP_SRAM_BASE; + bd->bi_sramsize = PPC405EP_SRAM_SIZE; + bd->bi_bootflags = 0; + bd->bi_intfreq = 133333333; + bd->bi_busfreq = 33333333; + bd->bi_baudrate = 115200; + bd->bi_s_version[0] = 'Q'; + bd->bi_s_version[1] = 'M'; + bd->bi_s_version[2] = 'U'; + bd->bi_s_version[3] = '\0'; + bd->bi_r_version[0] = 'Q'; + bd->bi_r_version[1] = 'E'; + bd->bi_r_version[2] = 'M'; + bd->bi_r_version[3] = 'U'; + bd->bi_r_version[4] = '\0'; + bd->bi_procfreq = 133333333; + bd->bi_plb_busfreq = 33333333; + bd->bi_pci_busfreq = 33333333; + bd->bi_opbfreq = 33333333; +} + +static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) { CPUState *cs = env_cpu(env); ram_addr_t bdloc; @@ -93,6 +121,17 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) return bdloc; } +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) +{ + ppc4xx_bd_info_t bd; + + memset(&bd, 0, sizeof(bd)); + + ppc405_set_default_bootinfo(&bd, ram_size); + + return __ppc405_set_bootinfo(env, &bd); +} + /*****************************************************************************/ /* Shared peripherals */ From 337270b2a5b7e23fd595aaf22a789bf3194887cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 270/421] ppc/ppc405: Fix boot from kernel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The machine can already boot with kernel and initrd U-boot images if a firmware is loaded first. Adapt and improve the load sequence to let the machine boot directly from a Linux kernel ELF image and a usual initrd image if a firmware image is not provided. For that, install a custom CPU reset handler to setup the registers and to start the CPU from the Linux kernel entry point. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-12-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 145 +++++++++++++++++++++++++++++------------ 1 file changed, 102 insertions(+), 43 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 71a652e2d8..3ae2b36373 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -41,6 +41,7 @@ #include "qemu/error-report.h" #include "hw/loader.h" #include "qemu/cutils.h" +#include "elf.h" #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2 * MiB) @@ -136,25 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) qemu_register_reset(&ref405ep_fpga_reset, fpga); } +/* + * CPU reset handler when booting directly from a loaded kernel + */ +static struct boot_info { + uint32_t entry; + uint32_t bdloc; + uint32_t initrd_base; + uint32_t initrd_size; + uint32_t cmdline_base; + uint32_t cmdline_size; +} boot_info; + +static void main_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + struct boot_info *bi = env->load_info; + + cpu_reset(CPU(cpu)); + + /* stack: top of sram */ + env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8; + + /* Tune our boot state */ + env->gpr[3] = bi->bdloc; + env->gpr[4] = bi->initrd_base; + env->gpr[5] = bi->initrd_base + bi->initrd_size; + env->gpr[6] = bi->cmdline_base; + env->gpr[7] = bi->cmdline_size; + + env->nip = bi->entry; +} + +static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + hwaddr boot_entry; + hwaddr kernel_base; + int kernel_size; + hwaddr initrd_base; + int initrd_size; + ram_addr_t bdloc; + int len; + + bdloc = ppc405_set_bootinfo(env, machine->ram_size); + boot_info.bdloc = bdloc; + + kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL, + &boot_entry, &kernel_base, NULL, NULL, + 1, PPC_ELF_MACHINE, 0, 0); + if (kernel_size < 0) { + error_report("Could not load kernel '%s' : %s", + machine->kernel_filename, load_elf_strerror(kernel_size)); + exit(1); + } + boot_info.entry = boot_entry; + + /* load initrd */ + if (machine->initrd_filename) { + initrd_base = INITRD_LOAD_ADDR; + initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, + machine->ram_size - initrd_base); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + machine->initrd_filename); + exit(1); + } + + boot_info.initrd_base = initrd_base; + boot_info.initrd_size = initrd_size; + } + + if (machine->kernel_cmdline) { + len = strlen(machine->kernel_cmdline); + bdloc -= ((len + 255) & ~255); + cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1); + boot_info.cmdline_base = bdloc; + boot_info.cmdline_size = bdloc + len; + } + + /* Install our custom reset handler to start from Linux */ + qemu_register_reset(main_cpu_reset, cpu); + env->load_info = &boot_info; +} + static void ref405ep_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; - const char *kernel_cmdline = machine->kernel_cmdline; - const char *initrd_filename = machine->initrd_filename; PowerPCCPU *cpu; - CPUPPCState *env; DeviceState *dev; SysBusDevice *s; MemoryRegion *sram = g_new(MemoryRegion, 1); - ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - long bios_size = -1; - target_ulong kernel_base, initrd_base; - long kernel_size, initrd_size; - int linux_boot; - int len; MemoryRegion *sysmem = get_system_memory(); DeviceState *uicdev; @@ -176,7 +253,6 @@ static void ref405ep_init(MachineState *machine) cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); - env = &cpu->env; /* allocate SRAM */ memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, @@ -187,6 +263,7 @@ static void ref405ep_init(MachineState *machine) if (machine->firmware) { MemoryRegion *bios = g_new(MemoryRegion, 1); g_autofree char *filename; + long bios_size; memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, &error_fatal); @@ -217,54 +294,36 @@ static void ref405ep_init(MachineState *machine) s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); - /* Load kernel */ - linux_boot = (kernel_filename != NULL); - if (linux_boot) { - bdloc = ppc405_set_bootinfo(env, machine->ram_size); - env->gpr[3] = bdloc; + + /* Load kernel and initrd using U-Boot images */ + if (kernel_filename && machine->firmware) { + target_ulong kernel_base, initrd_base; + long kernel_size, initrd_size; + kernel_base = KERNEL_LOAD_ADDR; - /* now we can load the kernel */ kernel_size = load_image_targphys(kernel_filename, kernel_base, machine->ram_size - kernel_base); if (kernel_size < 0) { error_report("could not load kernel '%s'", kernel_filename); exit(1); } - printf("Load kernel size %ld at " TARGET_FMT_lx, - kernel_size, kernel_base); + /* load initrd */ - if (initrd_filename) { + if (machine->initrd_filename) { initrd_base = INITRD_LOAD_ADDR; - initrd_size = load_image_targphys(initrd_filename, initrd_base, + initrd_size = load_image_targphys(machine->initrd_filename, + initrd_base, machine->ram_size - initrd_base); if (initrd_size < 0) { error_report("could not load initial ram disk '%s'", - initrd_filename); + machine->initrd_filename); exit(1); } - } else { - initrd_base = 0; - initrd_size = 0; } - env->gpr[4] = initrd_base; - env->gpr[5] = initrd_size; - if (kernel_cmdline != NULL) { - len = strlen(kernel_cmdline); - bdloc -= ((len + 255) & ~255); - cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); - env->gpr[6] = bdloc; - env->gpr[7] = bdloc + len; - } else { - env->gpr[6] = 0; - env->gpr[7] = 0; - } - env->nip = KERNEL_LOAD_ADDR; - } else { - kernel_base = 0; - kernel_size = 0; - initrd_base = 0; - initrd_size = 0; - bdloc = 0; + + /* Load ELF kernel and rootfs.cpio */ + } else if (kernel_filename && !machine->firmware) { + boot_from_kernel(machine, cpu); } } From cada9f30d35ccbd613ade00c4986a74a5446aa21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 271/421] ppc/ppc405: Change default PLL values at reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These values are computed and updated by U-Boot at startup. Use them as defaults to improve direct Linux boot. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-13-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_uc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 303af58444..2a1e2d71b0 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1381,9 +1381,9 @@ static void ppc405ep_cpc_reset (void *opaque) cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ cpc->epctl = 0x00000000; - cpc->pllmr[0] = 0x00011010; - cpc->pllmr[1] = 0x40000000; - cpc->ucr = 0x00000000; + cpc->pllmr[0] = 0x00021002; + cpc->pllmr[1] = 0x80a552be; + cpc->ucr = 0x00004646; cpc->srr = 0x00040000; cpc->pci = 0x00000000; cpc->er = 0x00000000; From e0caa8e64de2c62dfa00afc176e2dd2b3afe7f19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 272/421] ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The board information for the 405EP first appeared in commit 04f20795ac81 ("Move PowerPC 405 specific definitions into a separate file ...") An Ethernet address is a 6 byte number. Fix that. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20211206103712.1866296-14-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 6fb8b41bbc..83f156f585 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -57,7 +57,7 @@ struct ppc4xx_bd_info_t { uint32_t bi_plb_busfreq; uint32_t bi_pci_busfreq; uint8_t bi_pci_enetaddr[6]; - uint32_t bi_pci_enetaddr2[6]; + uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ uint32_t bi_opbfreq; uint32_t bi_iic_fast[2]; }; From 6518c0ede9f8b12c7eb4ab5e843bcacb7198652f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:17 +0100 Subject: [PATCH 273/421] ppc/ppc405: Add update of bi_procfreq field MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt the fields offset in the board information for Linux. Since Linux relies on the CPU frequency value, I wonder how it ever worked. Signed-off-by: Cédric Le Goater Message-Id: <20211206103712.1866296-15-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_uc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 2a1e2d71b0..ec97b22bd0 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -102,12 +102,13 @@ static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) for (i = 0; i < 32; i++) { stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); } - stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); - stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); + stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); + stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); + stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); for (i = 0; i < 6; i++) { - stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); + stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); } - n = 0x6A; + n = 0x70; /* includes 2 bytes hole */ for (i = 0; i < 6; i++) { stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); } From 201fc774e0e1cc76ec23b595968004a7b14fb6e8 Mon Sep 17 00:00:00 2001 From: Victor Colombo Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 274/421] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using vector registers when they should be using VSX ones. This happens because the instructions are using GEN_VSX_HELPER_R3, which adds 32 to the register numbers, effectively making them vector registers. This patch fixes it by changing these instructions to use GEN_VSX_HELPER_X3. Reviewed-by: Richard Henderson Signed-off-by: Victor Colombo Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 4 ++-- target/ppc/helper.h | 8 ++++---- target/ppc/translate/vsx-impl.c.inc | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 1e9a161540..d144f21dc0 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2495,7 +2495,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i)) VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i)) #define VSX_MAX_MINC(name, max) \ -void helper_##name(CPUPPCState *env, uint32_t opcode, \ +void helper_##name(CPUPPCState *env, \ ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = *xt; \ @@ -2530,7 +2530,7 @@ VSX_MAX_MINC(xsmaxcdp, 1); VSX_MAX_MINC(xsmincdp, 0); #define VSX_MAX_MINJ(name, max) \ -void helper_##name(CPUPPCState *env, uint32_t opcode, \ +void helper_##name(CPUPPCState *env, \ ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = *xt; \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 72b2c70ac1..fb946dc974 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -403,10 +403,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr) -DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr) +DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index c0e38060b4..02df75339e 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1098,10 +1098,10 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) +GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) From c5df1898a147c232f0502cda5dac8df6074070fc Mon Sep 17 00:00:00 2001 From: Victor Colombo Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 275/421] target/ppc: Move xs{max,min}[cj]dp to decodetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Richard Henderson Signed-off-by: Victor Colombo Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/insn32.decode | 17 +++++++++++++--- target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++---- target/ppc/translate/vsx-ops.c.inc | 4 ---- 3 files changed, 40 insertions(+), 11 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index f68931f4f3..97b2476ce6 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -130,10 +130,14 @@ &X_vrt_frbp vrt frbp @X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp +%xx_xt 0:1 21:5 +%xx_xb 1:1 11:5 +%xx_xa 2:1 16:5 &XX2 xt xb uim:uint8_t -%xx2_xt 0:1 21:5 -%xx2_xb 1:1 11:5 -@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb +@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb + +&XX3 xt xa xb +@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb &Z22_bf_fra bf fra dm @Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra @@ -455,3 +459,10 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2 ## VSX Vector Load Special Value Instruction LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5 + +## VSX Comparison Instructions + +XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3 +XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3 +XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3 +XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3 diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 02df75339e..e2447750dd 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1098,10 +1098,6 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) @@ -2185,6 +2181,32 @@ TRANS(XXBLENDVH, do_xxblendv, MO_16) TRANS(XXBLENDVW, do_xxblendv, MO_32) TRANS(XXBLENDVD, do_xxblendv, MO_64) +static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a, + void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr xt, xa, xb; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + xt = gen_vsr_ptr(a->xt); + xa = gen_vsr_ptr(a->xa); + xb = gen_vsr_ptr(a->xb); + + helper(cpu_env, xt, xa, xb); + + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xa); + tcg_temp_free_ptr(xb); + + return true; +} + +TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp) +TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp) +TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp) +TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index 152d1e5c3b..f980bc1bae 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -207,10 +207,6 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), -GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300), -GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300), -GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300), -GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300), GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300), GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), From 38d4914c5065e14f0969161274793ded448f067f Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 276/421] target/ppc: fix xscvqpdp register access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This instruction has VRT and VRB fields instead of T/TX and B/BX. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/translate/vsx-impl.c.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index e2447750dd..ab5cb21f13 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -913,8 +913,9 @@ static void gen_xscvqpdp(DisasContext *ctx) return; } opc = tcg_const_i32(ctx->opcode); - xt = gen_vsr_ptr(xT(ctx->opcode)); - xb = gen_vsr_ptr(xB(ctx->opcode)); + + xt = gen_vsr_ptr(rD(ctx->opcode) + 32); + xb = gen_vsr_ptr(rB(ctx->opcode) + 32); gen_helper_xscvqpdp(cpu_env, opc, xt, xb); tcg_temp_free_i32(opc); tcg_temp_free_ptr(xt); From caf6f9b568479bea6f6d97798be670f21641a006 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 277/421] target/ppc: move xscvqpdp to decodetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br> Signed-off-by: Cédric Le Goater --- target/ppc/fpu_helper.c | 10 +++------- target/ppc/helper.h | 2 +- target/ppc/insn32.decode | 4 ++++ target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++----------- target/ppc/translate/vsx-ops.c.inc | 1 - 5 files changed, 21 insertions(+), 20 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index d144f21dc0..700c79156b 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2751,18 +2751,14 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1) VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0) VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0) -/* - * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be - * added to this later. - */ -void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode, - ppc_vsr_t *xt, ppc_vsr_t *xb) +void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt, + ppc_vsr_t *xb) { ppc_vsr_t t = { }; float_status tstat; tstat = env->fp_status; - if (unlikely(Rc(opcode) != 0)) { + if (ro != 0) { tstat.float_rounding_mode = float_round_to_odd; } diff --git a/target/ppc/helper.h b/target/ppc/helper.h index fb946dc974..d166323b64 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -411,7 +411,7 @@ DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpspn, i64, env, i64) -DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) +DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr) DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr) DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr) DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 97b2476ce6..8bdc059a4c 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -466,3 +466,7 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3 XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3 XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3 XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3 + +## VSX Binary Floating-Point Convert Instructions + +XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index ab5cb21f13..c08185e857 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) -static void gen_xscvqpdp(DisasContext *ctx) +static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a) { - TCGv_i32 opc; + TCGv_i32 ro; TCGv_ptr xt, xb; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - opc = tcg_const_i32(ctx->opcode); - xt = gen_vsr_ptr(rD(ctx->opcode) + 32); - xb = gen_vsr_ptr(rB(ctx->opcode) + 32); - gen_helper_xscvqpdp(cpu_env, opc, xt, xb); - tcg_temp_free_i32(opc); + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + ro = tcg_const_i32(a->rc); + + xt = gen_avr_ptr(a->rt); + xb = gen_avr_ptr(a->rb); + gen_helper_XSCVQPDP(cpu_env, ro, xt, xb); + tcg_temp_free_i32(ro); tcg_temp_free_ptr(xt); tcg_temp_free_ptr(xb); + + return true; } #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index f980bc1bae..c974324c4c 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -133,7 +133,6 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001), GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001), GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001), GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0), GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001), GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001), GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001), From 7fc1dc8313219182bc279ad1861d34b3fc27fa25 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 278/421] target/ppc: Fix e6500 boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When Altivec support was added to the e6500 kernel in 2012[1], the QEMU code was not changed, so we don't register the VPU/VPUA exceptions for the e6500: qemu: fatal: Raised an exception without defined vector 73 Note that the error message says 73, instead of 32, which is the IVOR for VPU. This is because QEMU knows only knows about the VPU interrupt for the 7400s. In theory, we should not be raising _that_ VPU interrupt, but instead another one specific for the e6500. We unfortunately cannot register e6500-specific VPU/VPUA interrupts because the SPEU/EFPDI interrupts also use IVOR32/33. These are present only in the e500v1/2 versions. From the user manual: e500v1, e500v2: only SPEU/EFPDI/EFPRI e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA e6500: only VPU/VPUA So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code to convert the VPU #73 to a #32 when we're in the e6500. Since the handling for SPEU and VPU is the same this is the only change that's needed. The EFPDI is not implemented and will cause an abort. I don't think it worth it changing the error message to take VPUA into consideration, so I'm not changing anything there. This bug was discussed in the thread: https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html 1- https://git.kernel.org/torvalds/c/cd66cc2ee52 Reported-by: Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20211213133542.2608540-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 6 ++++++ target/ppc/excp_helper.c | 12 +++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 96034889dd..c8e6868389 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2065,8 +2065,14 @@ static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; + /* + * These two are the same IVOR as POWERPC_EXCP_VPU and + * POWERPC_EXCP_VPUA. We deal with that when dispatching at + * powerpc_excp(). + */ env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; env->ivor_mask = 0x0000FFF7UL; env->ivpr_mask = ivpr_mask; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index cbd88f74c9..feb3fd42e2 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -344,6 +344,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) excp = POWERPC_EXCP_PROGRAM; } +#ifdef TARGET_PPC64 + /* + * SPEU and VPU share the same IVOR but they exist in different + * processors. SPEU is e500v1/2 only and VPU is e6500 only. + */ + if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) { + excp = POWERPC_EXCP_SPEU; + } +#endif + switch (excp) { case POWERPC_EXCP_NONE: /* Should never happen */ @@ -569,7 +579,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) cpu_abort(cs, "Debug exception triggered on unsupported model\n"); } break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */ env->spr[SPR_BOOKE_ESR] = ESR_SPV; break; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ From 29c4a3363bf287bb9a7b0342b1bc2dba3661c96c Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 279/421] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2. It breaks the --disable-tcg build: ../target/ppc/excp_helper.c:463:29: error: implicit declaration of function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration] We should not have TCG code in powerpc_excp because some kvm-only routines use it indirectly to dispatch interrupts. See kvm_handle_debug, spapr_mce_req_event and spapr_do_system_reset_on_cpu. We can re-introduce the change once we have split the interrupt injection code between KVM and TCG. Signed-off-by: Fabiano Rosas Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index feb3fd42e2..6ba0840e99 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -464,15 +464,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ + /* Get rS/rD and rA from faulting opcode */ /* - * Get rS/rD and rA from faulting opcode. - * Note: We will only invoke ALIGN for atomic operations, - * so all instructions are X-form. + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. */ - { - uint32_t insn = cpu_ldl_code(env, env->nip); - env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16; - } + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { @@ -1441,6 +1439,11 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env = cs->env_ptr; + uint32_t insn; + + /* Restore state and reload the insn we executed, for filling in DSISR. */ + cpu_restore_state(cs, retaddr, true); + insn = cpu_ldl_code(env, env->nip); switch (env->mmu_model) { case POWERPC_MMU_SOFT_4xx: @@ -1456,8 +1459,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, } cs->exception_index = POWERPC_EXCP_ALIGN; - env->error_code = 0; - cpu_loop_exit_restore(cs, retaddr); + env->error_code = insn & 0x03FF0000; + cpu_loop_exit(cs); } #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ From 8f2e9d400320d75bb54d693282672cc407d8a128 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 280/421] target/ppc: introduce PMUEventType and PMU overflow timers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch starts an IBM Power8+ compatible PMU implementation by adding the representation of PMU events that we are going to sample, PMUEventType. This enum represents a Perf event that is being sampled by a specific counter 'sprn'. Events that aren't available (i.e. no event was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are inactive due to frozen counter bits state are of type 'PMU_EVENT_INACTIVE'. Other types added in this patch are PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added later on. Let's also add the required PMU cycle overflow timers. They will be used to trigger cycle overflows when cycle events are being sampled. This timer will call cpu_ppc_pmu_timer_cb(), which in turn calls fire_PMC_interrupt(). Both functions are stubs that will be implemented later on when EBB support is added. Two new helper files are created to host this new logic. cpu_ppc_pmu_init() will init all overflow timers during CPU init time. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- hw/ppc/spapr_cpu_core.c | 1 + target/ppc/cpu.h | 15 ++++++++++ target/ppc/cpu_init.c | 24 ++++++++++++++++ target/ppc/meson.build | 1 + target/ppc/power8-pmu.c | 62 +++++++++++++++++++++++++++++++++++++++++ target/ppc/power8-pmu.h | 25 +++++++++++++++++ 6 files changed, 128 insertions(+) create mode 100644 target/ppc/power8-pmu.c create mode 100644 target/ppc/power8-pmu.h diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 58e7341cb7..a57ba70a87 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -20,6 +20,7 @@ #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/power8-pmu.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index c07a8e9f7d..39fadca564 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -296,6 +296,15 @@ typedef struct ppc_v3_pate_t { uint64_t dw1; } ppc_v3_pate_t; +/* PMU related structs and defines */ +#define PMU_COUNTERS_NUM 6 +typedef enum { + PMU_EVENT_INVALID = 0, + PMU_EVENT_INACTIVE, + PMU_EVENT_CYCLES, + PMU_EVENT_INSTRUCTIONS, +} PMUEventType; + /*****************************************************************************/ /* Machine state register bits definition */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */ @@ -1195,6 +1204,12 @@ struct CPUPPCState { uint32_t tm_vscr; uint64_t tm_dscr; uint64_t tm_tar; + + /* + * Timers used to fire performance monitor alerts + * when counting cycles. + */ + QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM]; }; #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c8e6868389..7c47ffd6e1 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,6 +45,7 @@ #include "helper_regs.h" #include "internal.h" #include "spr_tcg.h" +#include "power8-pmu.h" /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ @@ -6810,6 +6811,20 @@ static void register_power9_mmu_sprs(CPUPPCState *env) #endif } +/* + * Initialize PMU counter overflow timers for Power8 and + * newer Power chips when using TCG. + */ +static void init_tcg_pmu_power8(CPUPPCState *env) +{ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + /* Init PMU overflow timers */ + if (!kvm_enabled()) { + cpu_ppc_pmu_init(env); + } +#endif +} + static void init_proc_book3s_common(CPUPPCState *env) { register_ne_601_sprs(env); @@ -7127,6 +7142,9 @@ static void init_proc_POWER8(CPUPPCState *env) register_sdr1_sprs(env); register_book3s_207_dbg_sprs(env); + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_rmor_sprs(env); @@ -7321,6 +7339,9 @@ static void init_proc_POWER9(CPUPPCState *env) init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_amr_sprs(env); @@ -7537,6 +7558,9 @@ static void init_proc_POWER10(CPUPPCState *env) init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_amr_sprs(env); diff --git a/target/ppc/meson.build b/target/ppc/meson.build index b85f295703..a49a8911e0 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -51,6 +51,7 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-book3s-v3.c', 'mmu-hash64.c', 'mmu-radix64.c', + 'power8-pmu.c', )) target_arch += {'ppc': ppc_ss} diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c new file mode 100644 index 0000000000..d443bcb6c6 --- /dev/null +++ b/target/ppc/power8-pmu.c @@ -0,0 +1,62 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "power8-pmu.h" +#include "cpu.h" +#include "helper_regs.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" +#include "hw/ppc/ppc.h" + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static void fire_PMC_interrupt(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { + return; + } + + /* PMC interrupt not implemented yet */ + return; +} + +static void cpu_ppc_pmu_timer_cb(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + fire_PMC_interrupt(cpu); +} + +void cpu_ppc_pmu_init(CPUPPCState *env) +{ + PowerPCCPU *cpu = env_archcpu(env); + int i, sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + if (sprn == SPR_POWER_PMC5) { + continue; + } + + i = sprn - SPR_POWER_PMC1; + + env->pmu_cyc_overflow_timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, + &cpu_ppc_pmu_timer_cb, + cpu); + } +} +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h new file mode 100644 index 0000000000..49a813a443 --- /dev/null +++ b/target/ppc/power8-pmu.h @@ -0,0 +1,25 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef POWER8_PMU +#define POWER8_PMU + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +void cpu_ppc_pmu_init(CPUPPCState *env); + +#endif From c2eff582a32f4251515e041f4919d3fbe4a0048e Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 281/421] target/ppc: PMU basic cycle count for pseries TCG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the barebones of the PMU logic by enabling cycle counting. The overall logic goes as follows: - MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid having to spin the PMU right at system init; - to retrieve the events that are being profiled, pmc_get_event() will check the current MMCR0 and MMCR1 value and return the appropriate PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation dependent value of PMU_EVENT_CYCLES. These events are supported by IBM Power chips since Power8, at least, and the Linux Perf driver makes use of these events until kernel v5.15. For PMC1, event 0xF0 is the architected PowerISA event for cycles. Event 0xFE is the architected PowerISA event for instructions; - if the counter is frozen, either via the global MMCR0_FC bit or its individual frozen counter bits, PMU_EVENT_INACTIVE is returned; - pmu_update_cycles() will go through each counter and update the values of all PMCs that are counting cycles. This function will be called every time a MMCR0 update is done to keep counters values up to date. Upcoming patches will use this function to allow the counters to be properly updated during read/write of the PMCs and MMCR1 writes. Given that the base CPU frequency is fixed at 1Ghz for both powernv and pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU cycle. Cycle value is then calculated by adding the elapsed time, in nanoseconds, of the last cycle update done via pmu_update_cycles(). Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu.h | 20 ++++++ target/ppc/cpu_init.c | 6 +- target/ppc/helper.h | 1 + target/ppc/power8-pmu-regs.c.inc | 23 ++++++- target/ppc/power8-pmu.c | 110 +++++++++++++++++++++++++++++++ target/ppc/spr_tcg.h | 1 + 6 files changed, 157 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 39fadca564..69cfb2e5f9 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -360,6 +360,9 @@ typedef enum { #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */ #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */ +#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ +#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ +#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ @@ -372,6 +375,17 @@ typedef enum { #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \ MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0) +#define MMCR1_EVT_SIZE 8 +/* extract64() does a right shift before extracting */ +#define MMCR1_PMC1SEL_START 32 +#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC2SEL_START 40 +#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC3SEL_START 48 +#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC4SEL_START 56 +#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) @@ -1210,6 +1224,12 @@ struct CPUPPCState { * when counting cycles. */ QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM]; + + /* + * PMU base time value used by the PMU to calculate + * running cycles. + */ + uint64_t pmu_base_time; }; #define SET_FIT_PERIOD(a_, b_, c_, d_) \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7c47ffd6e1..cfa605a76b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6254,8 +6254,8 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) { spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR0, 0x00000000); + &spr_read_generic, &spr_write_MMCR0, + KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -6303,7 +6303,7 @@ static void register_book3s_pmu_user_sprs(CPUPPCState *env) spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, &spr_read_ureg, &spr_write_ureg, - 0x00000000); + 0x80000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index d166323b64..0e6cf2d09d 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -20,6 +20,7 @@ DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_mmcr0, void, env, tl) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index 7391851238..fbb8977641 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -104,6 +104,17 @@ void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) tcg_temp_free(t0); } +static void write_MMCR0_common(DisasContext *ctx, TCGv val) +{ + /* + * helper_store_mmcr0 will make clock based operations that + * will cause 'bad icount read' errors if we do not execute + * gen_icount_io_start() beforehand. + */ + gen_icount_io_start(ctx); + gen_helper_store_mmcr0(cpu_env, val); +} + void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) { TCGv masked_gprn; @@ -119,7 +130,7 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) */ masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0, MMCR0_UREG_MASK); - gen_store_spr(SPR_POWER_MMCR0, masked_gprn); + write_MMCR0_common(ctx, masked_gprn); tcg_temp_free(masked_gprn); } @@ -219,6 +230,11 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) /* The remaining steps are similar to PMCs 1-4 userspace write */ spr_write_PMC14_ureg(ctx, sprn, gprn); } + +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + write_MMCR0_common(ctx, cpu_gpr[gprn]); +} #else void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) { @@ -259,4 +275,9 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) { spr_noaccess(ctx, gprn, sprn); } + +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index d443bcb6c6..5e689144d7 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -23,6 +23,116 @@ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +static bool pmc_is_inactive(CPUPPCState *env, int sprn) +{ + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { + return true; + } + + if (sprn < SPR_POWER_PMC5) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; +} + +/* + * For PMCs 1-4, IBM POWER chips has support for an implementation + * dependent event, 0x1E, that enables cycle counting. The Linux kernel + * makes extensive use of 0x1E, so let's also support it. + * + * Likewise, event 0x2 is an implementation-dependent event that IBM + * POWER chips implement (at least since POWER8) that is equivalent to + * PM_INST_CMPL. Let's support this event on PMCs 1-4 as well. + */ +static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) +{ + uint8_t mmcr1_evt_extr[] = { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR, + MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR }; + PMUEventType evt_type = PMU_EVENT_INVALID; + uint8_t pmcsel; + int i; + + if (pmc_is_inactive(env, sprn)) { + return PMU_EVENT_INACTIVE; + } + + if (sprn == SPR_POWER_PMC5) { + return PMU_EVENT_INSTRUCTIONS; + } + + if (sprn == SPR_POWER_PMC6) { + return PMU_EVENT_CYCLES; + } + + i = sprn - SPR_POWER_PMC1; + pmcsel = extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i], + MMCR1_EVT_SIZE); + + switch (pmcsel) { + case 0x2: + evt_type = PMU_EVENT_INSTRUCTIONS; + break; + case 0x1E: + evt_type = PMU_EVENT_CYCLES; + break; + case 0xF0: + /* + * PMC1SEL = 0xF0 is the architected PowerISA v3.1 + * event that counts cycles using PMC1. + */ + if (sprn == SPR_POWER_PMC1) { + evt_type = PMU_EVENT_CYCLES; + } + break; + case 0xFE: + /* + * PMC1SEL = 0xFE is the architected PowerISA v3.1 + * event to sample instructions using PMC1. + */ + if (sprn == SPR_POWER_PMC1) { + evt_type = PMU_EVENT_INSTRUCTIONS; + } + break; + default: + break; + } + + return evt_type; +} + +static void pmu_update_cycles(CPUPPCState *env) +{ + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t time_delta = now - env->pmu_base_time; + int sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES) { + continue; + } + + /* + * The pseries and powernv clock runs at 1Ghz, meaning + * that 1 nanosec equals 1 cycle. + */ + env->spr[sprn] += time_delta; + } + + /* Update base_time for future calculations */ + env->pmu_base_time = now; +} + +void helper_store_mmcr0(CPUPPCState *env, target_ulong value) +{ + pmu_update_cycles(env); + + env->spr[SPR_POWER_MMCR0] = value; + + /* MMCR0 writes can change HFLAGS_PMCCCLEAR */ + hreg_compute_hflags(env); +} + static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 520f1ef233..eb1d0c2bf0 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -25,6 +25,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); From 308b9fad2a301f3473e920f981d49e2ff0829029 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 282/421] target/ppc: PMU: update counters on PMCs r/w MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Calling pmu_update_cycles() on every PMC read/write operation ensures that the values being fetched are up to date with the current PMU state. In theory we can get away by just trapping PMCs reads, but we're going to trap PMC writes to deal with counter overflow logic later on. Let's put the required wiring for that and make our lives a bit easier in the next patches. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-4-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 12 ++++++------ target/ppc/helper.h | 2 ++ target/ppc/power8-pmu-regs.c.inc | 29 +++++++++++++++++++++++++++-- target/ppc/power8-pmu.c | 14 ++++++++++++++ target/ppc/spr_tcg.h | 2 ++ 5 files changed, 51 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index cfa605a76b..ceb325b311 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6266,27 +6266,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 0e6cf2d09d..984d03181a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,8 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_3(store_pmc, void, env, i32, i64) +DEF_HELPER_2(read_pmc, tl, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index fbb8977641..f0c9cc343b 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -181,13 +181,23 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn) tcg_temp_free(masked_gprn); } +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) +{ + TCGv_i32 t_sprn = tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); + + tcg_temp_free_i32(t_sprn); +} + void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) { if (!spr_groupA_read_allowed(ctx)) { return; } - spr_read_ureg(ctx, gprn, sprn); + spr_read_PMC(ctx, gprn, sprn + 0x10); } void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) @@ -206,13 +216,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) spr_read_PMC14_ureg(ctx, gprn, sprn); } +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t_sprn = tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + + tcg_temp_free_i32(t_sprn); +} + void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) { if (!spr_groupA_write_allowed(ctx)) { return; } - spr_write_ureg(ctx, sprn, gprn); + spr_write_PMC(ctx, sprn + 0x10, gprn); } void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) @@ -280,4 +300,9 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) { spr_write_generic(ctx, sprn, gprn); } + +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 5e689144d7..7131f52ccc 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -133,6 +133,20 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) hreg_compute_hflags(env); } +target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) +{ + pmu_update_cycles(env); + + return env->spr[sprn]; +} + +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[sprn] = value; +} + static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env = &cpu->env; diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index eb1d0c2bf0..1e79a0522a 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); @@ -35,6 +36,7 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gprn); void spr_read_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_tbl(DisasContext *ctx, int gprn, int sprn); From a6f91249e064a2ee935c900529b03f949ad89e6c Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 283/421] target/ppc: PMU: update counters on MMCR1 write MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMCR1 determines the events to be sampled by the PMU. Updating the counters at every MMCR1 write ensures that we're not sampling more or less events by looking only at MMCR0 and the PMCs. It is worth noticing that both the Book3S PowerPC PMU, and this IBM Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to control the PMU. These three registers aren't being handled in this initial implementation, so for now we're controlling all the PMU aspects using MMCR0, MMCR1 and the PMCs. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu_init.c | 2 +- target/ppc/helper.h | 1 + target/ppc/power8-pmu-regs.c.inc | 11 +++++++++++ target/ppc/power8-pmu.c | 7 +++++++ target/ppc/spr_tcg.h | 1 + 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index ceb325b311..e865d368f2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6258,7 +6258,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_MMCR1, KVM_REG_PPC_MMCR1, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 984d03181a..77c85e1292 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) #endif diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index f0c9cc343b..25b13ad564 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -255,6 +255,12 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) { write_MMCR0_common(ctx, cpu_gpr[gprn]); } + +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) +{ + gen_icount_io_start(ctx); + gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]); +} #else void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) { @@ -301,6 +307,11 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) spr_write_generic(ctx, sprn, gprn); } +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} + void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) { spr_write_generic(ctx, sprn, gprn); diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 7131f52ccc..73252529be 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -133,6 +133,13 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) hreg_compute_hflags(env); } +void helper_store_mmcr1(CPUPPCState *env, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[SPR_POWER_MMCR1] = value; +} + target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) { pmu_update_cycles(env); diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 1e79a0522a..1d6521eedc 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -26,6 +26,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); From 1474ba6d100179c248fed6c67756814a6fa89432 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 284/421] target/ppc: enable PMU counter overflow with cycle events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert can trigger an event-based exception (to be implemented in the next patches) if the MMCR0_EBE bit is set. For now, overflowing the counter when the PMC is counting cycles will just trigger a performance monitor alert. This is done by starting the overflow timer to expire in the moment the overflow would be occuring. The timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will trigger the PMU alert and, if the conditions are met, an EBB exception. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu.h | 2 ++ target/ppc/power8-pmu.c | 71 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 69cfb2e5f9..cf637f0f6d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -363,6 +363,8 @@ typedef enum { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 73252529be..399234a2fc 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -23,6 +23,8 @@ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL + static bool pmc_is_inactive(CPUPPCState *env, int sprn) { if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { @@ -36,6 +38,15 @@ static bool pmc_is_inactive(CPUPPCState *env, int sprn) return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; } +static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) +{ + if (sprn == SPR_POWER_PMC1) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; +} + /* * For PMCs 1-4, IBM POWER chips has support for an implementation * dependent event, 0x1E, that enables cycle counting. The Linux kernel @@ -123,6 +134,61 @@ static void pmu_update_cycles(CPUPPCState *env) env->pmu_base_time = now; } +/* + * Helper function to retrieve the cycle overflow timer of the + * 'sprn' counter. + */ +static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn) +{ + return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1]; +} + +static void pmc_update_overflow_timer(CPUPPCState *env, int sprn) +{ + QEMUTimer *pmc_overflow_timer = get_cyc_overflow_timer(env, sprn); + int64_t timeout; + + /* + * PMC5 does not have an overflow timer and this pointer + * will be NULL. + */ + if (!pmc_overflow_timer) { + return; + } + + if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES || + !pmc_has_overflow_enabled(env, sprn)) { + /* Overflow timer is not needed for this counter */ + timer_del(pmc_overflow_timer); + return; + } + + if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) { + timeout = 0; + } else { + timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn]; + } + + /* + * Use timer_mod_anticipate() because an overflow timer might + * be already running for this PMC. + */ + timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout); +} + +static void pmu_update_overflow_timers(CPUPPCState *env) +{ + int sprn; + + /* + * Scroll through all PMCs and start counter overflow timers for + * PM_CYC events, if needed. + */ + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + pmc_update_overflow_timer(env, sprn); + } +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { pmu_update_cycles(env); @@ -131,6 +197,9 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) /* MMCR0 writes can change HFLAGS_PMCCCLEAR */ hreg_compute_hflags(env); + + /* Update cycle overflow timers with the current MMCR0 state */ + pmu_update_overflow_timers(env); } void helper_store_mmcr1(CPUPPCState *env, uint64_t value) @@ -152,6 +221,8 @@ void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) pmu_update_cycles(env); env->spr[sprn] = value; + + pmc_update_overflow_timer(env, sprn); } static void fire_PMC_interrupt(PowerPCCPU *cpu) From 46d396bde988020528445691089711eb27b348b5 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 285/421] target/ppc: enable PMU instruction count MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in each translation block right before exiting it. A new pmu_count_insns() helper in translation.c was added to do that. After verifying that the PMU is counting instructions, call helper_insns_inc(). This new helper from power8-pmu.c will add the instructions to the relevant counters. It'll also be responsible for triggering counter negative overflows as it is already being done with cycles. To verify whether the PMU is counting instructions or now, a new hflags named 'HFLAGS_INSN_CNT' is introduced. This flag will match the internal state of the PMU. We're be using this flag to avoid calling helper_insn_inc() when we do not have a valid instruction event being sampled. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu.h | 1 + target/ppc/helper.h | 1 + target/ppc/helper_regs.c | 7 ++++ target/ppc/power8-pmu-regs.c.inc | 6 +++ target/ppc/power8-pmu.c | 67 +++++++++++++++++++++++++++++++- target/ppc/power8-pmu.h | 1 + target/ppc/translate.c | 64 ++++++++++++++++++++++++++++++ 7 files changed, 146 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cf637f0f6d..313b16f392 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -655,6 +655,7 @@ enum { HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */ HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */ + HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 77c85e1292..13d8305a08 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -24,6 +24,7 @@ DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) +DEF_HELPER_2(insns_inc, void, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 99562edd57..b847928842 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "helper_regs.h" +#include "power8-pmu.h" /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -121,6 +122,12 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) hflags |= 1 << HFLAGS_HV; } +#if defined(TARGET_PPC64) + if (pmu_insn_cnt_enabled(env)) { + hflags |= 1 << HFLAGS_INSN_CNT; + } +#endif + /* * This is our encoding for server processors. The architecture * specifies that there is no such thing as userspace with diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index 25b13ad564..2bab6cece7 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -113,6 +113,12 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val) */ gen_icount_io_start(ctx); gen_helper_store_mmcr0(cpu_env, val); + + /* + * End the translation block because MMCR0 writes can change + * ctx->pmu_insn_cnt. + */ + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 399234a2fc..e163ba5640 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -112,6 +112,54 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) return evt_type; } +bool pmu_insn_cnt_enabled(CPUPPCState *env) +{ + int sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { + if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) { + return true; + } + } + + return false; +} + +static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered = false; + int sprn; + + /* PMC6 never counts instructions */ + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { + if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) { + continue; + } + + env->spr[sprn] += num_insns; + + if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && + pmc_has_overflow_enabled(env, sprn)) { + + overflow_triggered = true; + + /* + * The real PMU will always trigger a counter overflow with + * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to + * do that since we're counting block of instructions at + * the end of each translation block, and we're probably + * passing this value at this point. + * + * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed + * counter to simulate what the real hardware would do. + */ + env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL; + } + } + + return overflow_triggered; +} + static void pmu_update_cycles(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -195,7 +243,7 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) env->spr[SPR_POWER_MMCR0] = value; - /* MMCR0 writes can change HFLAGS_PMCCCLEAR */ + /* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_INSN_CNT */ hreg_compute_hflags(env); /* Update cycle overflow timers with the current MMCR0 state */ @@ -207,6 +255,9 @@ void helper_store_mmcr1(CPUPPCState *env, uint64_t value) pmu_update_cycles(env); env->spr[SPR_POWER_MMCR1] = value; + + /* MMCR1 writes can change HFLAGS_INSN_CNT */ + hreg_compute_hflags(env); } target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) @@ -237,6 +288,20 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) return; } +/* This helper assumes that the PMC is running. */ +void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered; + PowerPCCPU *cpu; + + overflow_triggered = pmu_increment_insns(env, num_insns); + + if (overflow_triggered) { + cpu = env_archcpu(env); + fire_PMC_interrupt(cpu); + } +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu = opaque; diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index 49a813a443..3ee4b4cda5 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -21,5 +21,6 @@ #include "qemu/main-loop.h" void cpu_ppc_pmu_init(CPUPPCState *env); +bool pmu_insn_cnt_enabled(CPUPPCState *env); #endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b3f3b408db..633b907058 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -177,6 +177,7 @@ struct DisasContext { bool hr; bool mmcr0_pmcc0; bool mmcr0_pmcc1; + bool pmu_insn_cnt; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -4170,6 +4171,49 @@ static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) #endif } +#if defined(TARGET_PPC64) +static void pmu_count_insns(DisasContext *ctx) +{ + /* + * Do not bother calling the helper if the PMU isn't counting + * instructions. + */ + if (!ctx->pmu_insn_cnt) { + return; + } + + #if !defined(CONFIG_USER_ONLY) + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +#else + /* + * User mode can read (but not write) PMC5 and start/stop + * the PMU via MMCR0_FC. In this case just increment + * PMC5 with base.num_insns. + */ + TCGv t0 = tcg_temp_new(); + + gen_load_spr(t0, SPR_POWER_PMC5); + tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC5, t0); + + tcg_temp_free(t0); +#endif /* #if !defined(CONFIG_USER_ONLY) */ +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif /* #if defined(TARGET_PPC64) */ + static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -4180,6 +4224,14 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx) if (unlikely(ctx->singlestep_enabled)) { gen_debug_exception(ctx); } else { + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); } } @@ -4191,6 +4243,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) dest = (uint32_t) dest; } if (use_goto_tb(ctx, dest)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_nip, dest & ~3); tcg_gen_exit_tb(ctx->base.tb, n); @@ -8432,6 +8485,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->hr = (hflags >> HFLAGS_HR) & 1; ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; + ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { @@ -8538,6 +8592,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) switch (is_jmp) { case DISAS_TOO_MANY: if (use_goto_tb(ctx, nip)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(0); gen_update_nip(ctx, nip); tcg_gen_exit_tb(ctx->base.tb, 0); @@ -8548,6 +8603,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_CHAIN: + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); break; @@ -8555,6 +8618,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_EXIT: + pmu_count_insns(ctx); tcg_gen_exit_tb(NULL, 0); break; From 7aeac354a6925afcec684e985d56e612f9e81b2d Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: [PATCH 286/421] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR_CTRL is written. A small tweak in pmu_increment_insns() is then needed to only increment this event if the thread has the run latch. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu.h | 4 ++++ target/ppc/cpu_init.c | 2 +- target/ppc/power8-pmu.c | 27 ++++++++++++++++++++++++--- target/ppc/spr_tcg.h | 1 + target/ppc/translate.c | 12 ++++++++++++ 5 files changed, 42 insertions(+), 4 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 313b16f392..b0473526ce 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -303,6 +303,7 @@ typedef enum { PMU_EVENT_INACTIVE, PMU_EVENT_CYCLES, PMU_EVENT_INSTRUCTIONS, + PMU_EVENT_INSN_RUN_LATCH, } PMUEventType; /*****************************************************************************/ @@ -388,6 +389,9 @@ typedef enum { #define MMCR1_PMC4SEL_START 56 #define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) +/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ +#define CTRL_RUN PPC_BIT(63) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e865d368f2..06ef15cd9e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6182,7 +6182,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *env) { spr_register(env, SPR_CTRL, "SPR_CTRL", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, + SPR_NOACCESS, &spr_write_CTRL, 0x00000000); spr_register(env, SPR_UCTRL, "SPR_UCTRL", &spr_read_ureg, SPR_NOACCESS, diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index e163ba5640..08d1902cd5 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -96,6 +96,15 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) evt_type = PMU_EVENT_CYCLES; } break; + case 0xFA: + /* + * PMC4SEL = 0xFA is the "instructions completed + * with run latch set" event. + */ + if (sprn == SPR_POWER_PMC4) { + evt_type = PMU_EVENT_INSN_RUN_LATCH; + } + break; case 0xFE: /* * PMC1SEL = 0xFE is the architected PowerISA v3.1 @@ -117,7 +126,8 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env) int sprn; for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) { + if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS || + pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) { return true; } } @@ -132,11 +142,22 @@ static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) /* PMC6 never counts instructions */ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) { + PMUEventType evt_type = pmc_get_event(env, sprn); + bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS || + evt_type == PMU_EVENT_INSN_RUN_LATCH; + + if (pmc_is_inactive(env, sprn) || !insn_event) { continue; } - env->spr[sprn] += num_insns; + if (evt_type == PMU_EVENT_INSTRUCTIONS) { + env->spr[sprn] += num_insns; + } + + if (evt_type == PMU_EVENT_INSN_RUN_LATCH && + env->spr[SPR_CTRL] & CTRL_RUN) { + env->spr[sprn] += num_insns; + } if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && pmc_has_overflow_enabled(env, sprn)) { diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 1d6521eedc..f98d97c0ba 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 633b907058..68fbbf67ec 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -403,6 +403,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn) spr_store_dump_spr(sprn); } +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); + + /* + * SPR_CTRL writes must force a new translation block, + * allowing the PMU to calculate the run latch events with + * more accuracy. + */ + ctx->base.is_jmp = DISAS_EXIT_UPDATE; +} + #if !defined(CONFIG_USER_ONLY) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { From 1f26c75191178a9c652bc98afbefa00c0d4fb486 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 287/421] PPC64/TCG: Implement 'rfebb' instruction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit An Event-Based Branch (EBB) allows applications to change the NIA when a event-based exception occurs. Event-based exceptions are enabled by setting the Branch Event Status and Control Register (BESCR). If the event-based exception is enabled when the exception occurs, an EBB happens. The following operations happens during an EBB: - Global Enable (GE) bit of BESCR is set to 0; - bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set to the the effective address of the NIA that would have executed if the EBB didn't happen; - Instruction fetch and execution will continue in the effective address contained in the Event-Based Branch Handler Register (EBBHR). The EBB Handler will process the event and then execute the Return From Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then redirects execution to the address pointed in EBBRR. This process is described in the PowerISA v3.1, Book II, Chapter 6 [1]. This patch implements the rfebb instruction. Descriptions of all relevant BESCR bits are also added - this patch is only using BESCR_GE, but the next patches will use the remaining bits. [1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf Reviewed-by: David Gibson Reviewed-by: Matheus Ferst Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/cpu.h | 13 ++++++++++ target/ppc/excp_helper.c | 31 ++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/insn32.decode | 5 ++++ target/ppc/translate.c | 2 ++ target/ppc/translate/branch-impl.c.inc | 33 ++++++++++++++++++++++++++ 6 files changed, 85 insertions(+) create mode 100644 target/ppc/translate/branch-impl.c.inc diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b0473526ce..fc66c3561d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -392,6 +392,19 @@ typedef enum { /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ #define CTRL_RUN PPC_BIT(63) +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 6ba0840e99..f90e616aac 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1228,6 +1228,37 @@ void helper_hrfid(CPUPPCState *env) } #endif +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void helper_rfebb(CPUPPCState *env, target_ulong s) +{ + target_ulong msr = env->msr; + + /* + * Handling of BESCR bits 32:33 according to PowerISA v3.1: + * + * "If BESCR 32:33 != 0b00 the instruction is treated as if + * the instruction form were invalid." + */ + if (env->spr[SPR_BESCR] & BESCR_INVALID) { + raise_exception_err(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } + + env->nip = env->spr[SPR_EBBRR]; + + /* Switching to 32-bit ? Crop the nip */ + if (!msr_is_64bit(env, msr)) { + env->nip = (uint32_t)env->spr[SPR_EBBRR]; + } + + if (s) { + env->spr[SPR_BESCR] |= BESCR_GE; + } else { + env->spr[SPR_BESCR] &= ~BESCR_GE; + } +} +#endif + /*****************************************************************************/ /* Embedded PowerPC specific helpers */ void helper_40x_rfci(CPUPPCState *env) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 13d8305a08..fb6cac38b4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 8bdc059a4c..2a9c91a423 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -470,3 +470,8 @@ XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3 ## VSX Binary Floating-Point Convert Instructions XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc + +### rfebb +&XL_s s:uint8_t +@XL_s ......-------------- s:1 .......... - &XL_s +RFEBB 010011-------------- . 0010010010 - @XL_s diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 68fbbf67ec..114456148c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7461,6 +7461,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) #include "translate/spe-impl.c.inc" +#include "translate/branch-impl.c.inc" + /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc new file mode 100644 index 0000000000..29cfa11854 --- /dev/null +++ b/target/ppc/translate/branch-impl.c.inc @@ -0,0 +1,33 @@ +/* + * Power ISA decode for branch instructions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + + gen_icount_io_start(ctx); + gen_update_cfar(ctx, ctx->cia); + gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + + ctx->base.is_jmp = DISAS_CHAIN; + + return true; +} +#else +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + gen_invalid(ctx); + return true; +} +#endif From 2c4d3a501e55bb90f90577b2e3f0181dc89efd42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 288/421] ppc/pnv: Introduce a "chip" property under PHB3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change will help us move the mapping of XSCOM regions under the PHB3 realize routine, which will be necessary for user created PHB3 devices. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-3-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3.c | 1 + hw/ppc/pnv.c | 2 ++ include/hw/pci-host/pnv_phb3.h | 3 +++ 3 files changed, 6 insertions(+) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a7f9685005..3aa42ef9d4 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, static Property pnv_phb3_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 44ae41a9cb..3e43c53376 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1231,6 +1231,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, &error_fatal); + object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), + &error_fatal); if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index e2a2e36245..e9c13e6bd8 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -16,6 +16,7 @@ #include "qom/object.h" typedef struct PnvPHB3 PnvPHB3; +typedef struct PnvChip PnvChip; /* * PHB3 XICS Source for MSIs @@ -157,6 +158,8 @@ struct PnvPHB3 { PnvPHB3RootPort root; QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; + + PnvChip *chip; }; uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); From a8fa95c7e621d3cd0dddb653b4f894fac65dec19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 289/421] ppc/pnv: Use the chip class to check the index of PHB3 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The maximum number of PHB3 devices per chip can be different depending on the POWER8 processor model. Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20211213132830.108372-4-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 3aa42ef9d4..9c4451ca0d 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -993,7 +993,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; - if (phb->phb_id >= PNV8_CHIP_PHB3_MAX) { + if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; } From 9e59b09ccf7c3cb0ac666a63f4883f1389b68465 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 290/421] ppc/pnv: Drop the "num-phbs" property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is never used. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-5-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3e43c53376..bbebd21d75 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1771,7 +1771,6 @@ static Property pnv_chip_properties[] = { DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), - DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), DEFINE_PROP_END_OF_LIST(), }; From 10841a76eb8900ab5718fe91beb6f73ec365291a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 291/421] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change will help us providing support for user created PHB3 devices. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-6-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb3_pbcq.c | 11 +++++++++++ hw/ppc/pnv.c | 12 ------------ 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c index a0526aa1ec..c7426cd27a 100644 --- a/hw/pci-host/pnv_phb3_pbcq.c +++ b/hw/pci-host/pnv_phb3_pbcq.c @@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev), &pnv_pbcq_spci_xscom_ops, pbcq, name, PNV_XSCOM_PBCQ_SPCI_SIZE); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_nest_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_pci_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, + &pbcq->xscom_spci_regs); } static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index bbebd21d75..c97fe77e88 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1226,7 +1226,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* PHB3 controllers */ for (i = 0; i < chip->num_phbs; i++) { PnvPHB3 *phb = &chip8->phbs[i]; - PnvPBCQState *pbcq = &phb->pbcq; object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, @@ -1236,17 +1235,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_nest_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_pci_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, - &pbcq->xscom_spci_regs); } } From 2ff73dda02d8a467ab56a0e497df7888a15af0c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 292/421] ppc/pnv: Use QOM hierarchy to scan PHB3 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When -nodefaults is supported for PHB3 devices, the phbs array under the chip will be empty. This will break the XICSFabric handlers, and all interrupt delivery, and the 'info pic' HMP command. Do a QOM loop on the chip children and look for PHB3 devices instead. Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20211213132830.108372-7-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 72 +++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 54 insertions(+), 18 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c97fe77e88..e75fc999ee 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -638,16 +638,25 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); } +static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) +{ + Monitor *mon = opaque; + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + pnv_phb3_msi_pic_print_info(&phb3->msis, mon); + ics_pic_print_info(&phb3->lsis, mon); + } + return 0; +} + static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv8Chip *chip8 = PNV8_CHIP(chip); - int i; ics_pic_print_info(&chip8->psi.ics, mon); - for (i = 0; i < chip->num_phbs; i++) { - pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); - ics_pic_print_info(&chip8->phbs[i].lsis, mon); - } + object_child_foreach(OBJECT(chip), + pnv_chip_power8_pic_print_info_child, mon); } static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) @@ -1789,10 +1798,32 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) return NULL; } +typedef struct ForeachPhb3Args { + int irq; + ICSState *ics; +} ForeachPhb3Args; + +static int pnv_ics_get_child(Object *child, void *opaque) +{ + ForeachPhb3Args *args = opaque; + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + if (ics_valid_irq(&phb3->lsis, args->irq)) { + args->ics = &phb3->lsis; + } + if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { + args->ics = ICS(&phb3->msis); + } + } + return args->ics ? 1 : 0; +} + static ICSState *pnv_ics_get(XICSFabric *xi, int irq) { PnvMachineState *pnv = PNV_MACHINE(xi); - int i, j; + ForeachPhb3Args args = { irq, NULL }; + int i; for (i = 0; i < pnv->num_chips; i++) { PnvChip *chip = pnv->chips[i]; @@ -1801,32 +1832,37 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) if (ics_valid_irq(&chip8->psi.ics, irq)) { return &chip8->psi.ics; } - for (j = 0; j < chip->num_phbs; j++) { - if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { - return &chip8->phbs[j].lsis; - } - if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { - return ICS(&chip8->phbs[j].msis); - } + + object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); + if (args.ics) { + return args.ics; } } return NULL; } +static int pnv_ics_resend_child(Object *child, void *opaque) +{ + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + ics_resend(&phb3->lsis); + ics_resend(ICS(&phb3->msis)); + } + return 0; +} + static void pnv_ics_resend(XICSFabric *xi) { PnvMachineState *pnv = PNV_MACHINE(xi); - int i, j; + int i; for (i = 0; i < pnv->num_chips; i++) { PnvChip *chip = pnv->chips[i]; Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); ics_resend(&chip8->psi.ics); - for (j = 0; j < chip->num_phbs; j++) { - ics_resend(&chip8->phbs[j].lsis); - ics_resend(ICS(&chip8->phbs[j].msis)); - } + object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); } } From 422fd92e613ab6b5239538bf2dc1202eb9d3f0f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 293/421] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and each PEC can have several PHBs : * PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5) A num_pecs class attribute represents better the logic units of the POWER9 chip. Use that instead of num_phbs which fits POWER8 chips. This will ease adding support for user created devices. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-8-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 19 ++++++++----------- include/hw/ppc/pnv.h | 2 ++ 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e75fc999ee..2fc2b0dff7 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -667,7 +667,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) pnv_xive_pic_print_info(&chip9->xive, mon); pnv_psi_pic_print_info(&chip9->psi, mon); - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; for (j = 0; j < pec->num_stacks; j++) { pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); @@ -1344,15 +1344,13 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + /* Number of PECs is the chip default */ + chip->num_pecs = pcc->num_pecs; + + for (i = 0; i < chip->num_pecs; i++) { object_initialize_child(obj, "pec[*]", &chip9->pecs[i], TYPE_PNV_PHB4_PEC); } - - /* - * Number of PHBs is the chip default - */ - chip->num_phbs = pcc->num_phbs; } static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) @@ -1388,7 +1386,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) int i, j; int phb_id = 0; - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); uint32_t pec_nest_base; @@ -1416,8 +1414,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; - j++, phb_id++) { + for (j = 0; j < pec->num_stacks; j++, phb_id++) { PnvPhb4PecStack *stack = &pec->stacks[j]; Object *obj = OBJECT(&stack->phb); @@ -1573,7 +1570,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->xscom_core_base = pnv_chip_power9_xscom_core_base; k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; - k->num_phbs = 6; + k->num_pecs = PNV9_CHIP_MAX_PEC; device_class_set_parent_realize(dc, pnv_chip_power9_realize, &k->parent_realize); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index aa08d79d24..c781525277 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -53,6 +53,7 @@ struct PnvChip { PnvCore **cores; uint32_t num_phbs; + uint32_t num_pecs; MemoryRegion xscom_mmio; MemoryRegion xscom; @@ -136,6 +137,7 @@ struct PnvChipClass { uint64_t chip_cfam_id; uint64_t cores_mask; uint32_t num_phbs; + uint32_t num_pecs; DeviceRealize parent_realize; From 12060cbd3fd42e2a263c473829f5872c89dc71d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 294/421] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It prepares ground for PHB5 which has different values. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-9-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 2 ++ hw/ppc/pnv.c | 4 ++-- include/hw/pci-host/pnv_phb4.h | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 741ddc90ed..9f722729ac 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -499,6 +499,8 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->compat_size = sizeof(compat); pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); + pecc->version = PNV_PHB4_VERSION; + pecc->device_id = PNV_PHB4_DEVICE_ID; } static const TypeInfo pnv_pec_type_info = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 2fc2b0dff7..78436a30ac 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1421,9 +1421,9 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) object_property_set_int(obj, "index", phb_id, &error_fatal); object_property_set_int(obj, "chip-id", chip->chip_id, &error_fatal); - object_property_set_int(obj, "version", PNV_PHB4_VERSION, + object_property_set_int(obj, "version", pecc->version, &error_fatal); - object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, + object_property_set_int(obj, "device-id", pecc->device_id, &error_fatal); object_property_set_link(obj, "stack", OBJECT(stack), &error_abort); diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 27556ae534..b286423364 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -219,6 +219,8 @@ struct PnvPhb4PecClass { int compat_size; const char *stk_compat; int stk_compat_size; + uint64_t version; + uint64_t device_id; }; #endif /* PCI_HOST_PNV_PHB4_H */ From 6f43d2551fba2569e67c8c1ac4e8768a566738eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 295/421] ppc/pnv: Introduce a "chip" property under the PHB4 model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit And check the PEC index using the chip class. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-10-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 7 +++++++ hw/ppc/pnv.c | 2 ++ include/hw/pci-host/pnv_phb4.h | 2 ++ 3 files changed, 11 insertions(+) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 9f722729ac..4b32b5ae6e 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -382,6 +382,11 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) assert(pec->system_memory); + if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { + error_setg(errp, "invalid PEC index: %d", pec->index); + return; + } + /* Create stacks */ for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; @@ -462,6 +467,8 @@ static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0), DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, + PnvChip *), DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 78436a30ac..ceee63c4d0 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1402,6 +1402,8 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) &error_fatal); object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, &error_fatal); + object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), + &error_fatal); object_property_set_link(OBJECT(pec), "system-memory", OBJECT(get_system_memory()), &error_abort); if (!qdev_realize(DEVICE(pec), NULL, errp)) { diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index b286423364..8a585c9a42 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -205,6 +205,8 @@ struct PnvPhb4PecState { #define PHB4_PEC_MAX_STACKS 3 uint32_t num_stacks; PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS]; + + PnvChip *chip; }; From cf0ee6955cc2f7f256e44c4f8198f69aae6ea39c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 296/421] ppc/pnv: Introduce a num_stack class attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each PEC device of the POWER9 chip has a predefined number of stacks, equivalent of a root port complex: PEC0 -> 1 stack PEC1 -> 2 stacks PEC2 -> 3 stacks Introduce a class attribute to hold these values and remove the "num-stacks" property. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-11-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 12 +++++++++++- hw/ppc/pnv.c | 7 ------- include/hw/pci-host/pnv_phb4.h | 1 + 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 4b32b5ae6e..293909b5cb 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -377,6 +377,7 @@ static void pnv_pec_instance_init(Object *obj) static void pnv_pec_realize(DeviceState *dev, Error **errp) { PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); char name[64]; int i; @@ -387,6 +388,8 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) return; } + pec->num_stacks = pecc->num_stacks[pec->index]; + /* Create stacks */ for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; @@ -465,7 +468,6 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), - DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0), DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, PnvChip *), @@ -484,6 +486,13 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; } +/* + * PEC0 -> 1 stack + * PEC1 -> 2 stacks + * PEC2 -> 3 stacks + */ +static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 }; + static void pnv_pec_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -508,6 +517,7 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->stk_compat_size = sizeof(stk_compat); pecc->version = PNV_PHB4_VERSION; pecc->device_id = PNV_PHB4_DEVICE_ID; + pecc->num_stacks = pnv_pec_num_stacks; } static const TypeInfo pnv_pec_type_info = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index ceee63c4d0..3957a8c3b1 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1393,13 +1393,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) uint32_t pec_pci_base; object_property_set_int(OBJECT(pec), "index", i, &error_fatal); - /* - * PEC0 -> 1 stack - * PEC1 -> 2 stacks - * PEC2 -> 3 stacks - */ - object_property_set_int(OBJECT(pec), "num-stacks", i + 1, - &error_fatal); object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, &error_fatal); object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 8a585c9a42..60de3031a6 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -223,6 +223,7 @@ struct PnvPhb4PecClass { int stk_compat_size; uint64_t version; uint64_t device_id; + const uint32_t *num_stacks; }; #endif /* PCI_HOST_PNV_PHB4_H */ From aa8cc84d88945088e4588aeaa31573fb4ed3b27a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 297/421] ppc/pnv: Compute the PHB index from the PHB4 PEC model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the num_stacks class attribute to compute the PHB index depending on the PEC index : * PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5) The routine pnv_pec_phb_offset() is a bit complex but it also prepares ground for PHB5 which has a different layout of stacks: 3 per PECs. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-12-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 16 ++++++++++++++++ hw/ppc/pnv.c | 4 +--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 293909b5cb..a7dd4173d5 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -374,6 +374,19 @@ static void pnv_pec_instance_init(Object *obj) } } +static int pnv_pec_phb_offset(PnvPhb4PecState *pec) +{ + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + int index = pec->index; + int offset = 0; + + while (index--) { + offset += pecc->num_stacks[index]; + } + + return offset; +} + static void pnv_pec_realize(DeviceState *dev, Error **errp) { PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); @@ -394,8 +407,10 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; Object *stk_obj = OBJECT(stack); + int phb_id = pnv_pec_phb_offset(pec) + i; object_property_set_int(stk_obj, "stack-no", i, &error_abort); + object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort); if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { return; @@ -538,6 +553,7 @@ static void pnv_pec_stk_instance_init(Object *obj) PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj); object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); + object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index"); } static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3957a8c3b1..712200264b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1384,7 +1384,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) { Pnv9Chip *chip9 = PNV9_CHIP(chip); int i, j; - int phb_id = 0; for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; @@ -1409,11 +1408,10 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - for (j = 0; j < pec->num_stacks; j++, phb_id++) { + for (j = 0; j < pec->num_stacks; j++) { PnvPhb4PecStack *stack = &pec->stacks[j]; Object *obj = OBJECT(&stack->phb); - object_property_set_int(obj, "index", phb_id, &error_fatal); object_property_set_int(obj, "chip-id", chip->chip_id, &error_fatal); object_property_set_int(obj, "version", pecc->version, From 8da4f8f7b7e7ab896834130a139528e4b1c0b446 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 298/421] ppc/pnv: Remove "system-memory" property from PHB4 PEC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is not useful and will be in the way for support of user created PHB4 devices. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frederic Barrat Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-13-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 6 +----- hw/ppc/pnv.c | 2 -- 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index a7dd4173d5..dfed2af0f7 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -124,7 +124,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) { PnvPhb4PecState *pec = stack->pec; - MemoryRegion *sysmem = pec->system_memory; + MemoryRegion *sysmem = get_system_memory(); uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN]; uint64_t bar, mask, size; char name[64]; @@ -394,8 +394,6 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp) char name[64]; int i; - assert(pec->system_memory); - if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { error_setg(errp, "invalid PEC index: %d", pec->index); return; @@ -486,8 +484,6 @@ static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory, - TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 712200264b..57a5180bcc 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1396,8 +1396,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) &error_fatal); object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), &error_fatal); - object_property_set_link(OBJECT(pec), "system-memory", - OBJECT(get_system_memory()), &error_abort); if (!qdev_realize(DEVICE(pec), NULL, errp)) { return; } From 13480fc58a57e5274894cdb87120fd49c9c95ddc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 299/421] ppc/pnv: Move realize of PEC stacks under the PEC model MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change will help us providing support for user created PHB4 devices. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Message-Id: <20211213132830.108372-14-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/pci-host/pnv_phb4_pec.c | 34 ++++++++++++++++++++++++++++++---- hw/ppc/pnv.c | 37 ++++--------------------------------- 2 files changed, 34 insertions(+), 37 deletions(-) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index dfed2af0f7..24a3adcae3 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -556,6 +556,10 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) { PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec = stack->pec; + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + PnvChip *chip = pec->chip; + uint32_t pec_nest_base; + uint32_t pec_pci_base; char name[64]; assert(pec); @@ -579,10 +583,32 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb), &pnv_phb4_xscom_ops, &stack->phb, name, 0x40); - /* - * Let the machine/chip realize the PHB object to customize more - * easily some fields - */ + object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, + &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, + &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "device-id", pecc->device_id, + &error_fatal); + object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { + return; + } + + pec_nest_base = pecc->xscom_nest_base(pec); + pec_pci_base = pecc->xscom_pci_base(pec); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(chip, + pec_nest_base + 0x40 * (stack->stack_no + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + 0x40 * (stack->stack_no + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); } static Property pnv_pec_stk_properties[] = { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 57a5180bcc..c0b47a7d89 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1380,10 +1380,10 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) } } -static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) +static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) { Pnv9Chip *chip9 = PNV9_CHIP(chip); - int i, j; + int i; for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; @@ -1405,35 +1405,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - - for (j = 0; j < pec->num_stacks; j++) { - PnvPhb4PecStack *stack = &pec->stacks[j]; - Object *obj = OBJECT(&stack->phb); - - object_property_set_int(obj, "chip-id", chip->chip_id, - &error_fatal); - object_property_set_int(obj, "version", pecc->version, - &error_fatal); - object_property_set_int(obj, "device-id", pecc->device_id, - &error_fatal); - object_property_set_link(obj, "stack", OBJECT(stack), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { - return; - } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); - } } } @@ -1529,8 +1500,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), &chip9->homer.regs); - /* PHBs */ - pnv_chip_power9_phb_realize(chip, &local_err); + /* PEC PHBs */ + pnv_chip_power9_pec_realize(chip, &local_err); if (local_err) { error_propagate(errp, local_err); return; From 0e6232bc3cb96bdf6fac1b5d7659aa9887afe657 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Fri, 17 Dec 2021 17:57:19 +0100 Subject: [PATCH 300/421] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When -nodefaults is supported for PHB4 devices, the pecs array under the chip will be empty. This will break the 'info pic' HMP command. Do a QOM loop on the chip children and look for PEC PHB4 devices instead. Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza Message-Id: <20211213132830.108372-15-clg@kaod.org> Signed-off-by: Cédric Le Goater --- hw/ppc/pnv.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c0b47a7d89..29ee0d0f08 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -659,20 +659,26 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) pnv_chip_power8_pic_print_info_child, mon); } +static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) +{ + Monitor *mon = opaque; + PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); + + if (phb4) { + pnv_phb4_pic_print_info(phb4, mon); + } + return 0; +} + static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv9Chip *chip9 = PNV9_CHIP(chip); - int i, j; pnv_xive_pic_print_info(&chip9->xive, mon); pnv_psi_pic_print_info(&chip9->psi, mon); - for (i = 0; i < chip->num_pecs; i++) { - PnvPhb4PecState *pec = &chip9->pecs[i]; - for (j = 0; j < pec->num_stacks; j++) { - pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); - } - } + object_child_foreach_recursive(OBJECT(chip), + pnv_chip_power9_pic_print_info_child, mon); } static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, From ba7c60c203eb068cff591e4d0e7dbcc2b5aa013a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Nov 2021 14:47:54 +0100 Subject: [PATCH 301/421] configure: make $targetos lowercase, use windows instead of MINGW32 targetos is already mostly the same as Meson host_machine.system(), just in CamelCase. Adjust Windows, which is different, and switch to lowercase to match Meson. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 58 ++++++++++++++++++++++++------------------------------- 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/configure b/configure index 28e1cf6291..e72e34b684 100755 --- a/configure +++ b/configure @@ -501,30 +501,30 @@ EOF } if check_define __linux__ ; then - targetos="Linux" + targetos=linux elif check_define _WIN32 ; then - targetos='MINGW32' + targetos=windows elif check_define __OpenBSD__ ; then - targetos='OpenBSD' + targetos=openbsd elif check_define __sun__ ; then - targetos='SunOS' + targetos=sunos elif check_define __HAIKU__ ; then - targetos='Haiku' + targetos=haiku elif check_define __FreeBSD__ ; then - targetos='FreeBSD' + targetos=freebsd elif check_define __FreeBSD_kernel__ && check_define __GLIBC__; then - targetos='GNU/kFreeBSD' + targetos=gnu/kfreebsd elif check_define __DragonFly__ ; then - targetos='DragonFly' + targetos=dragonfly elif check_define __NetBSD__; then - targetos='NetBSD' + targetos=netbsd elif check_define __APPLE__; then - targetos='Darwin' + targetos=darwin else # This is a fatal error, but don't report it yet, because we # might be going to just print the --help text, or it might # be the result of a missing compiler. - targetos='bogus' + targetos=bogus fi # Some host OSes need non-standard checks for which CPU to use. @@ -532,7 +532,7 @@ fi # cross-compiling to one of these OSes then you'll need to specify # the correct CPU with the --cpu option. case $targetos in -SunOS) +sunos) # $(uname -m) returns i86pc even on an x86_64 box, so default based on isainfo if test -z "$cpu" && test "$(isainfo -k)" = "amd64"; then cpu="x86_64" @@ -623,40 +623,40 @@ fi # OS specific case $targetos in -MINGW32*) +windows) mingw32="yes" plugins="no" pie="no" ;; -GNU/kFreeBSD) +gnu/kfreebsd) bsd="yes" ;; -FreeBSD) +freebsd) bsd="yes" bsd_user="yes" make="${MAKE-gmake}" # needed for kinfo_getvmmap(3) in libutil.h ;; -DragonFly) +dragonfly) bsd="yes" make="${MAKE-gmake}" ;; -NetBSD) +netbsd) bsd="yes" make="${MAKE-gmake}" ;; -OpenBSD) +openbsd) bsd="yes" make="${MAKE-gmake}" ;; -Darwin) +darwin) bsd="yes" darwin="yes" # Disable attempts to use ObjectiveC features in os/object.h since they # won't work when we're compiling with gcc as a C compiler. QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" ;; -SunOS) +sunos) solaris="yes" make="${MAKE-gmake}" smbd="${SMBD-/usr/sfw/sbin/smbd}" @@ -665,11 +665,11 @@ SunOS) # needed for TIOCWIN* defines in termios.h QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" ;; -Haiku) +haiku) pie="no" QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -D_BSD_SOURCE -fPIC $QEMU_CFLAGS" ;; -Linux) +linux) linux="yes" linux_user="yes" vhost_user=${default_feature:-yes} @@ -3334,8 +3334,8 @@ QEMU_GA_MSI_MINGW_DLL_PATH="$($pkg_config --variable=prefix glib-2.0)/bin" # Mac OS X ships with a broken assembler roms= if { test "$cpu" = "i386" || test "$cpu" = "x86_64"; } && \ - test "$targetos" != "Darwin" && test "$targetos" != "SunOS" && \ - test "$targetos" != "Haiku" && test "$softmmu" = yes ; then + test "$targetos" != "darwin" && test "$targetos" != "sunos" && \ + test "$targetos" != "haiku" && test "$softmmu" = yes ; then # Different host OS linkers have different ideas about the name of the ELF # emulation. Linux and OpenBSD/amd64 use 'elf_i386'; FreeBSD uses the _fbsd # variant; OpenBSD/i386 uses the _obsd variant; and Windows uses i386pe. @@ -3903,15 +3903,7 @@ if test "$skip_meson" = no; then if test "$cross_compile" = "yes"; then cross_arg="--cross-file config-meson.cross" echo "[host_machine]" >> $cross - if test "$mingw32" = "yes" ; then - echo "system = 'windows'" >> $cross - fi - if test "$linux" = "yes" ; then - echo "system = 'linux'" >> $cross - fi - if test "$darwin" = "yes" ; then - echo "system = 'darwin'" >> $cross - fi + echo "system = '$targetos'" >> $cross case "$ARCH" in i386) echo "cpu_family = 'x86'" >> $cross From 65eff01bcf920bcdbdb83dd0546005b522742c47 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Nov 2021 22:52:35 +0100 Subject: [PATCH 302/421] configure: move target detection before CPU detection This makes more sense, since target detection can affect CPU detection on Solaris. Signed-off-by: Paolo Bonzini --- configure | 115 ++++++++++++++++++++++++++---------------------------- 1 file changed, 55 insertions(+), 60 deletions(-) diff --git a/configure b/configure index e72e34b684..f0a82dd8f5 100755 --- a/configure +++ b/configure @@ -527,16 +527,67 @@ else targetos=bogus fi -# Some host OSes need non-standard checks for which CPU to use. -# Note that these checks are broken for cross-compilation: if you're -# cross-compiling to one of these OSes then you'll need to specify -# the correct CPU with the --cpu option. +# OS specific + case $targetos in +windows) + mingw32="yes" + plugins="no" + pie="no" +;; +gnu/kfreebsd) + bsd="yes" +;; +freebsd) + bsd="yes" + bsd_user="yes" + make="${MAKE-gmake}" + # needed for kinfo_getvmmap(3) in libutil.h +;; +dragonfly) + bsd="yes" + make="${MAKE-gmake}" +;; +netbsd) + bsd="yes" + make="${MAKE-gmake}" +;; +openbsd) + bsd="yes" + make="${MAKE-gmake}" +;; +darwin) + bsd="yes" + darwin="yes" + # Disable attempts to use ObjectiveC features in os/object.h since they + # won't work when we're compiling with gcc as a C compiler. + QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" +;; sunos) + solaris="yes" + make="${MAKE-gmake}" + smbd="${SMBD-/usr/sfw/sbin/smbd}" +# needed for CMSG_ macros in sys/socket.h + QEMU_CFLAGS="-D_XOPEN_SOURCE=600 $QEMU_CFLAGS" +# needed for TIOCWIN* defines in termios.h + QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" # $(uname -m) returns i86pc even on an x86_64 box, so default based on isainfo + # Note that this check is broken for cross-compilation: if you're + # cross-compiling to one of these OSes then you'll need to specify + # the correct CPU with the --cpu option. if test -z "$cpu" && test "$(isainfo -k)" = "amd64"; then cpu="x86_64" fi +;; +haiku) + pie="no" + QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -D_BSD_SOURCE -fPIC $QEMU_CFLAGS" +;; +linux) + linux="yes" + linux_user="yes" + vhost_user=${default_feature:-yes} +;; esac if test ! -z "$cpu" ; then @@ -620,62 +671,6 @@ if test -z "$ARCH"; then ARCH="$cpu" fi -# OS specific - -case $targetos in -windows) - mingw32="yes" - plugins="no" - pie="no" -;; -gnu/kfreebsd) - bsd="yes" -;; -freebsd) - bsd="yes" - bsd_user="yes" - make="${MAKE-gmake}" - # needed for kinfo_getvmmap(3) in libutil.h -;; -dragonfly) - bsd="yes" - make="${MAKE-gmake}" -;; -netbsd) - bsd="yes" - make="${MAKE-gmake}" -;; -openbsd) - bsd="yes" - make="${MAKE-gmake}" -;; -darwin) - bsd="yes" - darwin="yes" - # Disable attempts to use ObjectiveC features in os/object.h since they - # won't work when we're compiling with gcc as a C compiler. - QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" -;; -sunos) - solaris="yes" - make="${MAKE-gmake}" - smbd="${SMBD-/usr/sfw/sbin/smbd}" -# needed for CMSG_ macros in sys/socket.h - QEMU_CFLAGS="-D_XOPEN_SOURCE=600 $QEMU_CFLAGS" -# needed for TIOCWIN* defines in termios.h - QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" -;; -haiku) - pie="no" - QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -D_BSD_SOURCE -fPIC $QEMU_CFLAGS" -;; -linux) - linux="yes" - linux_user="yes" - vhost_user=${default_feature:-yes} -;; -esac - : ${make=${MAKE-make}} # We prefer python 3.x. A bare 'python' is traditionally From e4da0e39dfce5366b22b3e28ec63d0470c1df550 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 9 Nov 2021 09:23:56 +0100 Subject: [PATCH 303/421] configure: unify two case statements on $cpu Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 67 ++++++++++++++++++++++++++----------------------------- 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/configure b/configure index f0a82dd8f5..77ccc15b73 100755 --- a/configure +++ b/configure @@ -636,32 +636,47 @@ else fi ARCH= -# Normalise host CPU name and set ARCH. +# Normalise host CPU name, set ARCH and multilib cflags # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv) - ;; - ppc64le) - ARCH="ppc64" - ;; + aarch64|riscv) ;; + armv*b|armv*l|arm) + cpu="arm" ;; + i386|i486|i586|i686|i86pc|BePC) cpu="i386" - ;; + CPU_CFLAGS="-m32" ;; + x32) + CPU_CFLAGS="-mx32" ;; x86_64|amd64) cpu="x86_64" - ;; - armv*b|armv*l|arm) - cpu="arm" - ;; - aarch64) - cpu="aarch64" - ;; + # ??? Only extremely old AMD cpus do not have cmpxchg16b. + # If we truly care, we should simply detect this case at + # runtime and generate the fallback to serial emulation. + CPU_CFLAGS="-m64 -mcx16" ;; + mips*) - cpu="mips" - ;; + cpu="mips" ;; + + ppc) + CPU_CFLAGS="-m32" ;; + ppc64) + CPU_CFLAGS="-m64" ;; + ppc64le) + ARCH="ppc64" ;; + + s390) + CPU_CFLAGS="-m31" + ARCH=unknown ;; + s390x) + CPU_CFLAGS="-m64" ;; + sparc|sun4[cdmuv]) cpu="sparc" - ;; + CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" ;; + sparc64) + CPU_CFLAGS="-m64 -mcpu=ultrasparc" ;; + *) # This will result in either an error or falling back to TCI later ARCH=unknown @@ -1252,24 +1267,6 @@ local_statedir="${local_statedir:-$prefix/var}" firmwarepath="${firmwarepath:-$datadir/qemu-firmware}" localedir="${localedir:-$datadir/locale}" -case "$cpu" in - ppc) CPU_CFLAGS="-m32" ;; - ppc64) CPU_CFLAGS="-m64" ;; - sparc) CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" ;; - sparc64) CPU_CFLAGS="-m64 -mcpu=ultrasparc" ;; - s390) CPU_CFLAGS="-m31" ;; - s390x) CPU_CFLAGS="-m64" ;; - i386) CPU_CFLAGS="-m32" ;; - x32) CPU_CFLAGS="-mx32" ;; - - # ??? Only extremely old AMD cpus do not have cmpxchg16b. - # If we truly care, we should simply detect this case at - # runtime and generate the fallback to serial emulation. - x86_64) CPU_CFLAGS="-m64 -mcx16" ;; - - # No special flags required for other host CPUs -esac - if eval test -z "\${cross_cc_$cpu}"; then eval "cross_cc_${cpu}=\$cc" cross_cc_vars="$cross_cc_vars cross_cc_${cpu}" From d8ff892dc23e9921db49d2053036240675bb50f8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 9 Nov 2021 09:18:20 +0100 Subject: [PATCH 304/421] configure: unify ppc64 and ppc64le MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The only difference between the two, as far as either configure or Meson are concerned, is the default endianness of the compiler. For tests/tcg, specify the endianness explicitly on the command line; for configure, do the same so that it is possible to have --cpu=ppc64le on a bigendian system or vice versa. Apart from this, cpu=ppc64le can be normalized to ppc64 also in configure and not just in the meson cross file. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 10 ++++------ tests/tcg/configure.sh | 4 +++- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/configure b/configure index 77ccc15b73..85caf2e9ef 100755 --- a/configure +++ b/configure @@ -661,9 +661,10 @@ case "$cpu" in ppc) CPU_CFLAGS="-m32" ;; ppc64) - CPU_CFLAGS="-m64" ;; + CPU_CFLAGS="-m64 -mbig" ;; ppc64le) - ARCH="ppc64" ;; + cpu="ppc64" + CPU_CFLAGS="-m64 -mlittle" ;; s390) CPU_CFLAGS="-m31" @@ -3721,7 +3722,7 @@ if test "$linux" = "yes" ; then i386|x86_64|x32) linux_arch=x86 ;; - ppc|ppc64|ppc64le) + ppc|ppc64) linux_arch=powerpc ;; s390x) @@ -3903,9 +3904,6 @@ if test "$skip_meson" = no; then x86_64|x32) echo "cpu_family = 'x86_64'" >> $cross ;; - ppc64le) - echo "cpu_family = 'ppc64'" >> $cross - ;; *) echo "cpu_family = '$ARCH'" >> $cross ;; diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 9b76f58258..9ef913df5b 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -64,7 +64,9 @@ fi : ${cross_cc_ppc="powerpc-linux-gnu-gcc"} : ${cross_cc_cflags_ppc="-m32"} : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"} -: ${cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"} +: ${cross_cc_cflags_ppc64="-m64 -mbig"} +: ${cross_cc_ppc64le="$cross_cc_ppc64"} +: ${cross_cc_cflags_ppc64le="-m64 -mlittle"} : ${cross_cc_riscv64="riscv64-linux-gnu-gcc"} : ${cross_cc_s390x="s390x-linux-gnu-gcc"} : ${cross_cc_sh4="sh4-linux-gnu-gcc"} From 4da270be1c4ac32c0e60a364e3173b57b1f79dba Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 9 Nov 2021 09:36:10 +0100 Subject: [PATCH 305/421] configure: unify x86_64 and x32 The only difference between the two, as far as either configure or Meson are concerned, is in the multilib flags passed to the compiler. For QEMU, this fixes the handling of TYPE_OLDDEVT in include/exec/user/thunk.h and enables testing of dirty ring buffer, because both are using HOST_X86_64. For tests/tcg, this means that on a hypothetical x32 host the cross compiler will not be used to build the tests. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 6 ++---- meson.build | 3 +-- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/configure b/configure index 85caf2e9ef..108b7621e2 100755 --- a/configure +++ b/configure @@ -647,6 +647,7 @@ case "$cpu" in cpu="i386" CPU_CFLAGS="-m32" ;; x32) + cpu="x86_64" CPU_CFLAGS="-mx32" ;; x86_64|amd64) cpu="x86_64" @@ -3719,7 +3720,7 @@ fi if test "$linux" = "yes" ; then mkdir -p linux-headers case "$cpu" in - i386|x86_64|x32) + i386|x86_64) linux_arch=x86 ;; ppc|ppc64) @@ -3901,9 +3902,6 @@ if test "$skip_meson" = no; then i386) echo "cpu_family = 'x86'" >> $cross ;; - x86_64|x32) - echo "cpu_family = 'x86_64'" >> $cross - ;; *) echo "cpu_family = '$ARCH'" >> $cross ;; diff --git a/meson.build b/meson.build index ae67ca28ab..69cca2aa9f 100644 --- a/meson.build +++ b/meson.build @@ -355,7 +355,7 @@ if not get_option('tcg').disabled() tcg_arch = 'tci' elif config_host['ARCH'] == 'sparc64' tcg_arch = 'sparc' - elif config_host['ARCH'] in ['x86_64', 'x32'] + elif config_host['ARCH'] == 'x86_64' tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' tcg_arch = 'ppc' @@ -1806,7 +1806,6 @@ disassemblers = { 'hppa' : ['CONFIG_HPPA_DIS'], 'i386' : ['CONFIG_I386_DIS'], 'x86_64' : ['CONFIG_I386_DIS'], - 'x32' : ['CONFIG_I386_DIS'], 'm68k' : ['CONFIG_M68K_DIS'], 'microblaze' : ['CONFIG_MICROBLAZE_DIS'], 'mips' : ['CONFIG_MIPS_DIS'], From ffb91f68b1c13a1cc36124350eacfe14095d5e1e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Nov 2021 15:44:39 +0100 Subject: [PATCH 306/421] meson: rename "arch" variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid confusion between the ARCH variable of configure/config-host.mak and the same-named variable of meson.build. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- meson.build | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/meson.build b/meson.build index 69cca2aa9f..4fdaa65b05 100644 --- a/meson.build +++ b/meson.build @@ -2850,7 +2850,7 @@ emulators = {} foreach target : target_dirs config_target = config_target_mak[target] target_name = config_target['TARGET_NAME'] - arch = config_target['TARGET_BASE_ARCH'] + target_base_arch = config_target['TARGET_BASE_ARCH'] arch_srcs = [config_target_h[target]] arch_deps = [] c_args = ['-DNEED_CPU_H', @@ -2866,11 +2866,11 @@ foreach target : target_dirs if target.endswith('-softmmu') qemu_target_name = 'qemu-system-' + target_name target_type='system' - t = target_softmmu_arch[arch].apply(config_target, strict: false) + t = target_softmmu_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() - hw_dir = target_name == 'sparc64' ? 'sparc64' : arch + hw_dir = target_name == 'sparc64' ? 'sparc64' : target_base_arch hw = hw_arch[hw_dir].apply(config_target, strict: false) arch_srcs += hw.sources() arch_deps += hw.dependencies() @@ -2881,8 +2881,8 @@ foreach target : target_dirs abi = config_target['TARGET_ABI_DIR'] target_type='user' qemu_target_name = 'qemu-' + target_name - if arch in target_user_arch - t = target_user_arch[arch].apply(config_target, strict: false) + if target_base_arch in target_user_arch + t = target_user_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() endif @@ -2920,7 +2920,7 @@ foreach target : target_dirs arch_srcs += gdbstub_xml endif - t = target_arch[arch].apply(config_target, strict: false) + t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() From 823eb013452e93d34fc0630fea98717d7d8f240a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Nov 2021 14:18:17 +0100 Subject: [PATCH 307/421] configure, meson: move ARCH to meson.build $ARCH and the HOST_* symbols are only used by the QEMU build; configure uses $cpu instead. Remove it from config-host.mak. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 21 ++++----------------- meson.build | 26 +++++++++++++++++--------- 2 files changed, 21 insertions(+), 26 deletions(-) diff --git a/configure b/configure index 108b7621e2..6e06ac6161 100755 --- a/configure +++ b/configure @@ -635,11 +635,9 @@ else cpu=$(uname -m) fi -ARCH= -# Normalise host CPU name, set ARCH and multilib cflags +# Normalise host CPU name, set multilib cflags # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - aarch64|riscv) ;; armv*b|armv*l|arm) cpu="arm" ;; @@ -668,8 +666,7 @@ case "$cpu" in CPU_CFLAGS="-m64 -mlittle" ;; s390) - CPU_CFLAGS="-m31" - ARCH=unknown ;; + CPU_CFLAGS="-m31" ;; s390x) CPU_CFLAGS="-m64" ;; @@ -678,15 +675,7 @@ case "$cpu" in CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" ;; sparc64) CPU_CFLAGS="-m64 -mcpu=ultrasparc" ;; - - *) - # This will result in either an error or falling back to TCI later - ARCH=unknown - ;; esac -if test -z "$ARCH"; then - ARCH="$cpu" -fi : ${make=${MAKE-make}} @@ -3406,8 +3395,6 @@ echo "GIT=$git" >> $config_host_mak echo "GIT_SUBMODULES=$git_submodules" >> $config_host_mak echo "GIT_SUBMODULES_ACTION=$git_submodules_action" >> $config_host_mak -echo "ARCH=$ARCH" >> $config_host_mak - if test "$debug_tcg" = "yes" ; then echo "CONFIG_DEBUG_TCG=y" >> $config_host_mak fi @@ -3898,12 +3885,12 @@ if test "$skip_meson" = no; then cross_arg="--cross-file config-meson.cross" echo "[host_machine]" >> $cross echo "system = '$targetos'" >> $cross - case "$ARCH" in + case "$cpu" in i386) echo "cpu_family = 'x86'" >> $cross ;; *) - echo "cpu_family = '$ARCH'" >> $cross + echo "cpu_family = '$cpu'" >> $cross ;; esac echo "cpu = '$cpu'" >> $cross diff --git a/meson.build b/meson.build index 4fdaa65b05..2495360fd0 100644 --- a/meson.build +++ b/meson.build @@ -67,6 +67,14 @@ endif targetos = host_machine.system() +if cpu not in supported_cpus + host_arch = 'unknown' +elif cpu == 'x86' + host_arch = 'i386' +else + host_arch = cpu +endif + if cpu in ['x86', 'x86_64'] kvm_targets = ['i386-softmmu', 'x86_64-softmmu'] elif cpu == 'aarch64' @@ -335,9 +343,9 @@ if targetos == 'netbsd' endif endif -tcg_arch = config_host['ARCH'] +tcg_arch = host_arch if not get_option('tcg').disabled() - if cpu not in supported_cpus + if host_arch == 'unknown' if get_option('tcg_interpreter') warning('Unsupported CPU @0@, will use TCG with TCI (slow)'.format(cpu)) else @@ -353,11 +361,11 @@ if not get_option('tcg').disabled() endif if get_option('tcg_interpreter') tcg_arch = 'tci' - elif config_host['ARCH'] == 'sparc64' + elif host_arch == 'sparc64' tcg_arch = 'sparc' - elif config_host['ARCH'] == 'x86_64' + elif host_arch == 'x86_64' tcg_arch = 'i386' - elif config_host['ARCH'] == 'ppc64' + elif host_arch == 'ppc64' tcg_arch = 'ppc' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, @@ -1426,6 +1434,8 @@ config_host_data.set_quoted('CONFIG_QEMU_LOCALSTATEDIR', get_option('prefix') / config_host_data.set_quoted('CONFIG_QEMU_MODDIR', get_option('prefix') / qemu_moddir) config_host_data.set_quoted('CONFIG_SYSCONFDIR', get_option('prefix') / get_option('sysconfdir')) +config_host_data.set('HOST_' + host_arch.to_upper(), 1) + config_host_data.set('CONFIG_ATTR', libattr.found()) config_host_data.set('CONFIG_BRLAPI', brlapi.found()) config_host_data.set('CONFIG_COCOA', cocoa.found()) @@ -1775,8 +1785,6 @@ foreach k, v: config_host v = '"' + '", "'.join(v.split()) + '", ' endif config_host_data.set(k, v) - elif k == 'ARCH' - config_host_data.set('HOST_' + v.to_upper(), 1) elif strings.contains(k) config_host_data.set_quoted(k, v) elif k.startswith('CONFIG_') @@ -1919,7 +1927,7 @@ foreach target : target_dirs endif foreach k, v: disassemblers - if config_host['ARCH'].startswith(k) or config_target['TARGET_BASE_ARCH'].startswith(k) + if host_arch.startswith(k) or config_target['TARGET_BASE_ARCH'].startswith(k) foreach sym: v config_target += { sym: 'y' } config_all_disas += { sym: 'y' } @@ -2888,7 +2896,7 @@ foreach target : target_dirs endif if 'CONFIG_LINUX_USER' in config_target base_dir = 'linux-user' - target_inc += include_directories('linux-user/host/' / config_host['ARCH']) + target_inc += include_directories('linux-user/host/' / host_arch) endif if 'CONFIG_BSD_USER' in config_target base_dir = 'bsd-user' From 0f457147f41bd7cbb7fd1193b057af9226a2184a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Nov 2021 10:45:30 +0100 Subject: [PATCH 308/421] configure: remove unnecessary symlinks Make pc-bios/meson.build use the files in the source tree as inputs to bzip2. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- configure | 1 - pc-bios/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configure b/configure index 6e06ac6161..ba85bbb54b 100755 --- a/configure +++ b/configure @@ -3801,7 +3801,6 @@ for bios_file in \ $source_path/pc-bios/*.img \ $source_path/pc-bios/openbios-* \ $source_path/pc-bios/u-boot.* \ - $source_path/pc-bios/edk2-*.fd.bz2 \ $source_path/pc-bios/palcode-* \ $source_path/pc-bios/qemu_vga.ndrv diff --git a/pc-bios/meson.build b/pc-bios/meson.build index b40ff3f2bd..1812a4084f 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -15,7 +15,7 @@ if unpack_edk2_blobs roms += custom_target(f, build_by_default: have_system, output: f, - input: '@0@.bz2'.format(f), + input: files('@0@.bz2'.format(f)), capture: true, install: get_option('install_blobs'), install_dir: qemu_datadir, From 5dce7b8d8ce6f397a2f2e46c236cc102d4e7a585 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 13 Oct 2021 13:56:24 +0200 Subject: [PATCH 309/421] configure: remove DIRS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DIRS is used to create the directory in which the LINKS symbolic links reside, or to create directories for object files. The former can be done directly in the symlinking loop, while the latter is done by Meson already, so DIRS is not necessary. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Tested-by: Alex Bennée Signed-off-by: Paolo Bonzini --- configure | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/configure b/configure index ba85bbb54b..8ccfe51673 100755 --- a/configure +++ b/configure @@ -3762,7 +3762,6 @@ if test "$safe_stack" = "yes"; then fi # If we're using a separate build tree, set it up now. -# DIRS are directories which we simply mkdir in the build tree; # LINKS are things to symlink back into the source tree # (these can be both files and directories). # Caution: do not add files or directories here using wildcards. This @@ -3774,12 +3773,6 @@ fi # UNLINK is used to remove symlinks from older development versions # that might get into the way when doing "git update" without doing # a "make distclean" in between. -DIRS="tests tests/tcg tests/qapi-schema tests/qtest/libqos" -DIRS="$DIRS tests/qtest tests/qemu-iotests tests/vm tests/fp tests/qgraph" -DIRS="$DIRS docs docs/interop fsdev scsi" -DIRS="$DIRS pc-bios/optionrom pc-bios/s390-ccw" -DIRS="$DIRS roms/seabios" -DIRS="$DIRS contrib/plugins/" LINKS="Makefile" LINKS="$LINKS tests/tcg/Makefile.target" LINKS="$LINKS pc-bios/optionrom/Makefile" @@ -3807,9 +3800,9 @@ for bios_file in \ do LINKS="$LINKS pc-bios/$(basename $bios_file)" done -mkdir -p $DIRS for f in $LINKS ; do if [ -e "$source_path/$f" ]; then + mkdir -p `dirname ./$f` symlink "$source_path/$f" "$f" fi done From 7a82413dbd8275303e4df9822c213bca15c34e86 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 13 Oct 2021 11:39:05 +0200 Subject: [PATCH 310/421] meson: reenable test-fdmon-epoll The test was disabled when CONFIG_EPOLL_CREATE1 was moved out of config-host.mak. Fix the condition. Signed-off-by: Paolo Bonzini --- tests/unit/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/unit/meson.build b/tests/unit/meson.build index acac3622ed..90acf5b0da 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -112,7 +112,7 @@ if have_block if nettle.found() or gcrypt.found() tests += {'test-crypto-pbkdf': [io]} endif - if 'CONFIG_EPOLL_CREATE1' in config_host + if config_host_data.get('CONFIG_EPOLL_CREATE1') tests += {'test-fdmon-epoll': [testblock]} endif endif From ad5439bb537a296814e40947dec51f1f96078bec Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 8 Oct 2021 13:33:08 +0200 Subject: [PATCH 311/421] cpu: remove unnecessary #ifdef CONFIG_TCG "if (tcg_enabled())" allows elision of the code inside it; we only need the prototype to exist, so that the code compile even for the --disable-tcg case. Signed-off-by: Paolo Bonzini --- cpu.c | 5 ----- include/exec/cpu-all.h | 2 -- 2 files changed, 7 deletions(-) diff --git a/cpu.c b/cpu.c index 9bce67ef55..945dd3dded 100644 --- a/cpu.c +++ b/cpu.c @@ -137,12 +137,10 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) if (!accel_cpu_realizefn(cpu, errp)) { return; } -#ifdef CONFIG_TCG /* NB: errp parameter is unused currently */ if (tcg_enabled()) { tcg_exec_realizefn(cpu, errp); } -#endif /* CONFIG_TCG */ #ifdef CONFIG_USER_ONLY assert(qdev_get_vmsd(DEVICE(cpu)) == NULL || @@ -169,12 +167,9 @@ void cpu_exec_unrealizefn(CPUState *cpu) vmstate_unregister(NULL, &vmstate_cpu_common, cpu); } #endif -#ifdef CONFIG_TCG - /* NB: errp parameter is unused currently */ if (tcg_enabled()) { tcg_exec_unrealizefn(cpu); } -#endif /* CONFIG_TCG */ cpu_list_remove(cpu); } diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 3c8e24292b..bb37239efa 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -437,12 +437,10 @@ void dump_opcount_info(GString *buf); #endif /* !CONFIG_USER_ONLY */ -#ifdef CONFIG_TCG /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); void tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); -#endif /* CONFIG_TCG */ /* Returns: 0 on success, -1 on error */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, From b20a7ee6f0771b3ec7de9a4c7c7b0e5890b70f3e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 17 Dec 2021 09:52:03 +0100 Subject: [PATCH 312/421] meson: add "check" argument to run_command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Meson is planning to change the default of the "check" argument to run_command (from false to true). Be explicit and include it in all invocations. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- docs/meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/meson.build b/docs/meson.build index 27c6e156ff..57b28a3146 100644 --- a/docs/meson.build +++ b/docs/meson.build @@ -18,12 +18,12 @@ if sphinx_build.found() # This is a bit awkward but works: create a trivial document and # try to run it with our configuration file (which enforces a # version requirement). This will fail if sphinx-build is too old. - run_command('mkdir', ['-p', tmpdir / 'sphinx']) - run_command('touch', [tmpdir / 'sphinx/index.rst']) + run_command('mkdir', ['-p', tmpdir / 'sphinx'], check: true) + run_command('touch', [tmpdir / 'sphinx/index.rst'], check: true) sphinx_build_test_out = run_command(SPHINX_ARGS + [ '-c', meson.current_source_dir(), '-b', 'html', tmpdir / 'sphinx', - tmpdir / 'sphinx/out']) + tmpdir / 'sphinx/out'], check: false) build_docs = (sphinx_build_test_out.returncode() == 0) if not build_docs From 7a3ce79c062117501e89a10a7768051b8b52d562 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 22 Nov 2021 11:47:44 +0100 Subject: [PATCH 313/421] hw/scsi: Fix scsi_bus_init_named() docstring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 739e95f5741 ("scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()") forgot to rename scsi_bus_init() in the function documentation string. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211122104744.1051554-1-f4bug@amsat.org> Reviewed-by: Peter Maydell Signed-off-by: Paolo Bonzini --- include/hw/scsi/scsi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h index a567a5ed86..2ef80af6dc 100644 --- a/include/hw/scsi/scsi.h +++ b/include/hw/scsi/scsi.h @@ -158,7 +158,7 @@ struct SCSIBus { * provided by the caller. It is the caller's responsibility to make * sure that name does not clash with the name of any other bus in the * system. Unless you need the new bus to have a specific name, you - * should use scsi_bus_new() instead. + * should use scsi_bus_init() instead. */ void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, const SCSIBusInfo *info, const char *bus_name); From 97a2b074d150918a7a3a4065b946a52d4d0be8a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 19 Nov 2021 21:11:40 +0100 Subject: [PATCH 314/421] hw/scsi/megasas: Fails command if SGL buffer overflows MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we detect an overflow on the SGL buffer, do not keep processing the command: discard it. TARGET_FAILURE sense code will be returned (MFI_STAT_SCSI_DONE_WITH_ERROR). Reported-by: Alexander Bulekov Resolves: https://gitlab.com/qemu-project/qemu/-/issues/521 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Darren Kenny Message-Id: <20211119201141.532377-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- hw/scsi/megasas.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 4ff51221d4..8f35784100 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -303,6 +303,7 @@ static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl) } if (cmd->iov_size > iov_size) { trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size); + goto unmap; } else if (cmd->iov_size < iov_size) { trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size); } From 08c34c642dbcb5f7d9d94b07b471f80e333541cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 19 Nov 2021 21:11:41 +0100 Subject: [PATCH 315/421] tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without the previous commit, this test triggers: $ make check-qtest-x86_64 [...] Running test qtest-x86_64/fuzz-megasas-test qemu-system-x86_64: softmmu/physmem.c:3229: address_space_unmap: Assertion `mr != NULL' failed. Broken pipe ERROR qtest-x86_64/fuzz-megasas-test - too few tests run (expected 2, got 1) Suggested-by: Alexander Bulekov Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Darren Kenny Message-Id: <20211119201141.532377-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- tests/qtest/fuzz-megasas-test.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tests/qtest/fuzz-megasas-test.c b/tests/qtest/fuzz-megasas-test.c index 940a76bf25..e1141c58a4 100644 --- a/tests/qtest/fuzz-megasas-test.c +++ b/tests/qtest/fuzz-megasas-test.c @@ -34,6 +34,34 @@ static void test_lp1878263_megasas_zero_iov_cnt(void) qtest_quit(s); } +/* + * Overflow SGL buffer. + * https://gitlab.com/qemu-project/qemu/-/issues/521 + */ +static void test_gitlab_issue521_megasas_sgl_ovf(void) +{ + QTestState *s = qtest_init("-display none -m 32M -machine q35 " + "-nodefaults -device megasas " + "-device scsi-cd,drive=null0 " + "-blockdev " + "driver=null-co,read-zeroes=on,node-name=null0"); + qtest_outl(s, 0xcf8, 0x80000818); + qtest_outl(s, 0xcfc, 0xc000); + qtest_outl(s, 0xcf8, 0x80000804); + qtest_outw(s, 0xcfc, 0x05); + qtest_bufwrite(s, 0x0, "\x01", 0x1); + qtest_bufwrite(s, 0x7, "\x01", 0x1); + qtest_bufwrite(s, 0x10, "\x02", 0x1); + qtest_bufwrite(s, 0x16, "\x01", 0x1); + qtest_bufwrite(s, 0x28, "\x01", 0x1); + qtest_bufwrite(s, 0x33, "\x01", 0x1); + qtest_outb(s, 0xc040, 0x0); + qtest_outb(s, 0xc040, 0x20); + qtest_outl(s, 0xc040, 0x20000000); + qtest_outb(s, 0xc040, 0x20); + qtest_quit(s); +} + int main(int argc, char **argv) { const char *arch = qtest_get_arch(); @@ -43,6 +71,8 @@ int main(int argc, char **argv) if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { qtest_add_func("fuzz/test_lp1878263_megasas_zero_iov_cnt", test_lp1878263_megasas_zero_iov_cnt); + qtest_add_func("fuzz/gitlab_issue521_megasas_sgl_ovf", + test_gitlab_issue521_megasas_sgl_ovf); } return g_test_run(); From 5a3a2eb3b1096a52580c1b8c3eb0739714e7d941 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 1 Dec 2021 23:32:53 +0100 Subject: [PATCH 316/421] hw/i386/vmmouse: Require 'i8042' property to be set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the 'i8042' property is not set, mouse events handled by vmmouse_mouse_event() end calling i8042_isa_mouse_fake_event() with a NULL argument, resulting in ps2_mouse_fake_event() being called with invalid PS2MouseState pointer. Fix by requiring the 'i8042' property to be always set: $ qemu-system-x86_64 -device vmmouse qemu-system-x86_64: -device vmmouse: 'i8042' link is not set Fixes: 91c9e09147b ("vmmouse: convert to qdev") Reported-by: Calvin Buckley Resolves: https://gitlab.com/qemu-project/qemu/-/issues/752 Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211201223253.36080-1-f4bug@amsat.org> Signed-off-by: Paolo Bonzini --- hw/i386/vmmouse.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/i386/vmmouse.c b/hw/i386/vmmouse.c index 3d66368286..a56c185f15 100644 --- a/hw/i386/vmmouse.c +++ b/hw/i386/vmmouse.c @@ -286,6 +286,10 @@ static void vmmouse_realizefn(DeviceState *dev, Error **errp) DPRINTF("vmmouse_init\n"); + if (!s->i8042) { + error_setg(errp, "'i8042' link is not set"); + return; + } if (!object_resolve_path_type("", TYPE_VMPORT, NULL)) { error_setg(errp, "vmmouse needs a machine with vmport"); return; From b9d2af3c62c22870c02410d5c9c6d097ee0ddf3f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 23 Nov 2021 11:44:55 +0100 Subject: [PATCH 317/421] linux-user: Untabify all safe-syscall.inc.S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/host/aarch64/safe-syscall.inc.S | 110 +++++++------- linux-user/host/arm/safe-syscall.inc.S | 134 ++++++++--------- linux-user/host/i386/safe-syscall.inc.S | 158 ++++++++++----------- linux-user/host/ppc64/safe-syscall.inc.S | 134 ++++++++--------- linux-user/host/riscv/safe-syscall.inc.S | 114 +++++++-------- linux-user/host/s390x/safe-syscall.inc.S | 140 +++++++++--------- linux-user/host/x86_64/safe-syscall.inc.S | 2 +- 7 files changed, 396 insertions(+), 396 deletions(-) diff --git a/linux-user/host/aarch64/safe-syscall.inc.S b/linux-user/host/aarch64/safe-syscall.inc.S index bc1f5a9792..e2e726ef55 100644 --- a/linux-user/host/aarch64/safe-syscall.inc.S +++ b/linux-user/host/aarch64/safe-syscall.inc.S @@ -10,66 +10,66 @@ * See the COPYING file in the top-level directory. */ - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, #function - .type safe_syscall_start, #function - .type safe_syscall_end, #function + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, #function + .type safe_syscall_start, #function + .type safe_syscall_end, #function - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ safe_syscall_base: - .cfi_startproc - /* The syscall calling convention isn't the same as the - * C one: - * we enter with x0 == *signal_pending - * x1 == syscall number - * x2 ... x7, (stack) == syscall arguments - * and return the result in x0 - * and the syscall instruction needs - * x8 == syscall number - * x0 ... x6 == syscall arguments - * and returns the result in x0 - * Shuffle everything around appropriately. - */ - mov x9, x0 /* signal_pending pointer */ - mov x8, x1 /* syscall number */ - mov x0, x2 /* syscall arguments */ - mov x1, x3 - mov x2, x4 - mov x3, x5 - mov x4, x6 - mov x5, x7 - ldr x6, [sp] + .cfi_startproc + /* The syscall calling convention isn't the same as the + * C one: + * we enter with x0 == *signal_pending + * x1 == syscall number + * x2 ... x7, (stack) == syscall arguments + * and return the result in x0 + * and the syscall instruction needs + * x8 == syscall number + * x0 ... x6 == syscall arguments + * and returns the result in x0 + * Shuffle everything around appropriately. + */ + mov x9, x0 /* signal_pending pointer */ + mov x8, x1 /* syscall number */ + mov x0, x2 /* syscall arguments */ + mov x1, x3 + mov x2, x4 + mov x3, x5 + mov x4, x6 + mov x5, x7 + ldr x6, [sp] - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - ldr w10, [x9] - cbnz w10, 0f - svc 0x0 + /* if signal_pending is non-zero, don't do the call */ + ldr w10, [x9] + cbnz w10, 0f + svc 0x0 safe_syscall_end: - /* code path for having successfully executed the syscall */ - ret + /* code path for having successfully executed the syscall */ + ret 0: - /* code path when we didn't execute the syscall */ - mov x0, #-TARGET_ERESTARTSYS - ret - .cfi_endproc + /* code path when we didn't execute the syscall */ + mov x0, #-TARGET_ERESTARTSYS + ret + .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base + .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/arm/safe-syscall.inc.S b/linux-user/host/arm/safe-syscall.inc.S index 88c4958504..1f1ee8327b 100644 --- a/linux-user/host/arm/safe-syscall.inc.S +++ b/linux-user/host/arm/safe-syscall.inc.S @@ -10,81 +10,81 @@ * See the COPYING file in the top-level directory. */ - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, %function + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, %function - .cfi_sections .debug_frame + .cfi_sections .debug_frame - .text - .syntax unified - .arm - .align 2 + .text + .syntax unified + .arm + .align 2 - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ safe_syscall_base: - .fnstart - .cfi_startproc - mov r12, sp /* save entry stack */ - push { r4, r5, r6, r7, r8, lr } - .save { r4, r5, r6, r7, r8, lr } - .cfi_adjust_cfa_offset 24 - .cfi_rel_offset r4, 0 - .cfi_rel_offset r5, 4 - .cfi_rel_offset r6, 8 - .cfi_rel_offset r7, 12 - .cfi_rel_offset r8, 16 - .cfi_rel_offset lr, 20 + .fnstart + .cfi_startproc + mov r12, sp /* save entry stack */ + push { r4, r5, r6, r7, r8, lr } + .save { r4, r5, r6, r7, r8, lr } + .cfi_adjust_cfa_offset 24 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + .cfi_rel_offset r8, 16 + .cfi_rel_offset lr, 20 - /* The syscall calling convention isn't the same as the C one: - * we enter with r0 == *signal_pending - * r1 == syscall number - * r2, r3, [sp+0] ... [sp+12] == syscall arguments - * and return the result in r0 - * and the syscall instruction needs - * r7 == syscall number - * r0 ... r6 == syscall arguments - * and returns the result in r0 - * Shuffle everything around appropriately. - * Note the 16 bytes that we pushed to save registers. - */ - mov r8, r0 /* copy signal_pending */ - mov r7, r1 /* syscall number */ - mov r0, r2 /* syscall args */ - mov r1, r3 - ldm r12, { r2, r3, r4, r5, r6 } + /* The syscall calling convention isn't the same as the C one: + * we enter with r0 == *signal_pending + * r1 == syscall number + * r2, r3, [sp+0] ... [sp+12] == syscall arguments + * and return the result in r0 + * and the syscall instruction needs + * r7 == syscall number + * r0 ... r6 == syscall arguments + * and returns the result in r0 + * Shuffle everything around appropriately. + * Note the 16 bytes that we pushed to save registers. + */ + mov r8, r0 /* copy signal_pending */ + mov r7, r1 /* syscall number */ + mov r0, r2 /* syscall args */ + mov r1, r3 + ldm r12, { r2, r3, r4, r5, r6 } - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - ldr r12, [r8] /* signal_pending */ - tst r12, r12 - bne 1f - swi 0 + /* if signal_pending is non-zero, don't do the call */ + ldr r12, [r8] /* signal_pending */ + tst r12, r12 + bne 1f + swi 0 safe_syscall_end: - /* code path for having successfully executed the syscall */ - pop { r4, r5, r6, r7, r8, pc } + /* code path for having successfully executed the syscall */ + pop { r4, r5, r6, r7, r8, pc } 1: - /* code path when we didn't execute the syscall */ - ldr r0, =-TARGET_ERESTARTSYS - pop { r4, r5, r6, r7, r8, pc } - .fnend - .cfi_endproc + /* code path when we didn't execute the syscall */ + ldr r0, =-TARGET_ERESTARTSYS + pop { r4, r5, r6, r7, r8, pc } + .fnend + .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base + .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/i386/safe-syscall.inc.S b/linux-user/host/i386/safe-syscall.inc.S index 9e58fc6504..e425aa54d8 100644 --- a/linux-user/host/i386/safe-syscall.inc.S +++ b/linux-user/host/i386/safe-syscall.inc.S @@ -10,91 +10,91 @@ * See the COPYING file in the top-level directory. */ - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ safe_syscall_base: - .cfi_startproc - push %ebp - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset ebp, 0 - push %esi - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset esi, 0 - push %edi - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset edi, 0 - push %ebx - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset ebx, 0 + .cfi_startproc + push %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + push %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + push %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + push %ebx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebx, 0 - /* The syscall calling convention isn't the same as the C one: - * we enter with 0(%esp) == return address - * 4(%esp) == *signal_pending - * 8(%esp) == syscall number - * 12(%esp) ... 32(%esp) == syscall arguments - * and return the result in eax - * and the syscall instruction needs - * eax == syscall number - * ebx, ecx, edx, esi, edi, ebp == syscall arguments - * and returns the result in eax - * Shuffle everything around appropriately. - * Note the 16 bytes that we pushed to save registers. - */ - mov 12+16(%esp), %ebx /* the syscall arguments */ - mov 16+16(%esp), %ecx - mov 20+16(%esp), %edx - mov 24+16(%esp), %esi - mov 28+16(%esp), %edi - mov 32+16(%esp), %ebp + /* The syscall calling convention isn't the same as the C one: + * we enter with 0(%esp) == return address + * 4(%esp) == *signal_pending + * 8(%esp) == syscall number + * 12(%esp) ... 32(%esp) == syscall arguments + * and return the result in eax + * and the syscall instruction needs + * eax == syscall number + * ebx, ecx, edx, esi, edi, ebp == syscall arguments + * and returns the result in eax + * Shuffle everything around appropriately. + * Note the 16 bytes that we pushed to save registers. + */ + mov 12+16(%esp), %ebx /* the syscall arguments */ + mov 16+16(%esp), %ecx + mov 20+16(%esp), %edx + mov 24+16(%esp), %esi + mov 28+16(%esp), %edi + mov 32+16(%esp), %ebp - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - mov 4+16(%esp), %eax /* signal_pending */ - cmpl $0, (%eax) - jnz 1f - mov 8+16(%esp), %eax /* syscall number */ - int $0x80 + /* if signal_pending is non-zero, don't do the call */ + mov 4+16(%esp), %eax /* signal_pending */ + cmpl $0, (%eax) + jnz 1f + mov 8+16(%esp), %eax /* syscall number */ + int $0x80 safe_syscall_end: - /* code path for having successfully executed the syscall */ - pop %ebx - .cfi_remember_state - .cfi_adjust_cfa_offset -4 - .cfi_restore ebx - pop %edi - .cfi_adjust_cfa_offset -4 - .cfi_restore edi - pop %esi - .cfi_adjust_cfa_offset -4 - .cfi_restore esi - pop %ebp - .cfi_adjust_cfa_offset -4 - .cfi_restore ebp - ret + /* code path for having successfully executed the syscall */ + pop %ebx + .cfi_remember_state + .cfi_adjust_cfa_offset -4 + .cfi_restore ebx + pop %edi + .cfi_adjust_cfa_offset -4 + .cfi_restore edi + pop %esi + .cfi_adjust_cfa_offset -4 + .cfi_restore esi + pop %ebp + .cfi_adjust_cfa_offset -4 + .cfi_restore ebp + ret 1: - /* code path when we didn't execute the syscall */ - .cfi_restore_state - mov $-TARGET_ERESTARTSYS, %eax - jmp safe_syscall_end - .cfi_endproc + /* code path when we didn't execute the syscall */ + .cfi_restore_state + mov $-TARGET_ERESTARTSYS, %eax + jmp safe_syscall_end + .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base + .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/ppc64/safe-syscall.inc.S b/linux-user/host/ppc64/safe-syscall.inc.S index 875133173b..4b57440585 100644 --- a/linux-user/host/ppc64/safe-syscall.inc.S +++ b/linux-user/host/ppc64/safe-syscall.inc.S @@ -10,87 +10,87 @@ * See the COPYING file in the top-level directory. */ - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function - .text + .text - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ #if _CALL_ELF == 2 safe_syscall_base: - .cfi_startproc - .localentry safe_syscall_base,0 + .cfi_startproc + .localentry safe_syscall_base,0 #else - .section ".opd","aw" - .align 3 + .section ".opd","aw" + .align 3 safe_syscall_base: - .quad .L.safe_syscall_base,.TOC.@tocbase,0 - .previous + .quad .L.safe_syscall_base,.TOC.@tocbase,0 + .previous .L.safe_syscall_base: - .cfi_startproc + .cfi_startproc #endif - /* We enter with r3 == *signal_pending - * r4 == syscall number - * r5 ... r10 == syscall arguments - * and return the result in r3 - * and the syscall instruction needs - * r0 == syscall number - * r3 ... r8 == syscall arguments - * and returns the result in r3 - * Shuffle everything around appropriately. - */ - std 14, 16(1) /* Preserve r14 in SP+16 */ - .cfi_offset 14, 16 - mr 14, 3 /* signal_pending */ - mr 0, 4 /* syscall number */ - mr 3, 5 /* syscall arguments */ - mr 4, 6 - mr 5, 7 - mr 6, 8 - mr 7, 9 - mr 8, 10 + /* We enter with r3 == *signal_pending + * r4 == syscall number + * r5 ... r10 == syscall arguments + * and return the result in r3 + * and the syscall instruction needs + * r0 == syscall number + * r3 ... r8 == syscall arguments + * and returns the result in r3 + * Shuffle everything around appropriately. + */ + std 14, 16(1) /* Preserve r14 in SP+16 */ + .cfi_offset 14, 16 + mr 14, 3 /* signal_pending */ + mr 0, 4 /* syscall number */ + mr 3, 5 /* syscall arguments */ + mr 4, 6 + mr 5, 7 + mr 6, 8 + mr 7, 9 + mr 8, 10 - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - lwz 12, 0(14) - cmpwi 0, 12, 0 - bne- 0f - sc + /* if signal_pending is non-zero, don't do the call */ + lwz 12, 0(14) + cmpwi 0, 12, 0 + bne- 0f + sc safe_syscall_end: - /* code path when we did execute the syscall */ - ld 14, 16(1) /* restore r14 to its original value */ - bnslr+ + /* code path when we did execute the syscall */ + ld 14, 16(1) /* restore r14 to its original value */ + bnslr+ - /* syscall failed; return negative errno */ - neg 3, 3 - blr + /* syscall failed; return negative errno */ + neg 3, 3 + blr - /* code path when we didn't execute the syscall */ -0: addi 3, 0, -TARGET_ERESTARTSYS - ld 14, 16(1) /* restore r14 to its original value */ - blr - .cfi_endproc + /* code path when we didn't execute the syscall */ +0: addi 3, 0, -TARGET_ERESTARTSYS + ld 14, 16(1) /* restore r14 to its original value */ + blr + .cfi_endproc #if _CALL_ELF == 2 - .size safe_syscall_base, .-safe_syscall_base + .size safe_syscall_base, .-safe_syscall_base #else - .size safe_syscall_base, .-.L.safe_syscall_base - .size .L.safe_syscall_base, .-.L.safe_syscall_base + .size safe_syscall_base, .-.L.safe_syscall_base + .size .L.safe_syscall_base, .-.L.safe_syscall_base #endif diff --git a/linux-user/host/riscv/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S index 9ca3fbfd1e..95c4832de2 100644 --- a/linux-user/host/riscv/safe-syscall.inc.S +++ b/linux-user/host/riscv/safe-syscall.inc.S @@ -10,68 +10,68 @@ * See the COPYING file in the top-level directory. */ - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - .type safe_syscall_start, @function - .type safe_syscall_end, @function + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + .type safe_syscall_start, @function + .type safe_syscall_end, @function - /* - * This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ safe_syscall_base: - .cfi_startproc - /* - * The syscall calling convention is nearly the same as C: - * we enter with a0 == *signal_pending - * a1 == syscall number - * a2 ... a7 == syscall arguments - * and return the result in a0 - * and the syscall instruction needs - * a7 == syscall number - * a0 ... a5 == syscall arguments - * and returns the result in a0 - * Shuffle everything around appropriately. - */ - mv t0, a0 /* signal_pending pointer */ - mv t1, a1 /* syscall number */ - mv a0, a2 /* syscall arguments */ - mv a1, a3 - mv a2, a4 - mv a3, a5 - mv a4, a6 - mv a5, a7 - mv a7, t1 + .cfi_startproc + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == *signal_pending + * a1 == syscall number + * a2 ... a7 == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * a7 == syscall number + * a0 ... a5 == syscall arguments + * and returns the result in a0 + * Shuffle everything around appropriately. + */ + mv t0, a0 /* signal_pending pointer */ + mv t1, a1 /* syscall number */ + mv a0, a2 /* syscall arguments */ + mv a1, a3 + mv a2, a4 + mv a3, a5 + mv a4, a6 + mv a5, a7 + mv a7, t1 - /* - * This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ safe_syscall_start: - /* If signal_pending is non-zero, don't do the call */ - lw t1, 0(t0) - bnez t1, 0f - scall + /* If signal_pending is non-zero, don't do the call */ + lw t1, 0(t0) + bnez t1, 0f + scall safe_syscall_end: - /* code path for having successfully executed the syscall */ - ret + /* code path for having successfully executed the syscall */ + ret 0: - /* code path when we didn't execute the syscall */ - li a0, -TARGET_ERESTARTSYS - ret - .cfi_endproc + /* code path when we didn't execute the syscall */ + li a0, -TARGET_ERESTARTSYS + ret + .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base + .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/s390x/safe-syscall.inc.S b/linux-user/host/s390x/safe-syscall.inc.S index 414b44ad38..d97d27458e 100644 --- a/linux-user/host/s390x/safe-syscall.inc.S +++ b/linux-user/host/s390x/safe-syscall.inc.S @@ -10,81 +10,81 @@ * See the COPYING file in the top-level directory. */ - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ safe_syscall_base: - .cfi_startproc - stmg %r6,%r15,48(%r15) /* save all call-saved registers */ - .cfi_offset %r15,-40 - .cfi_offset %r14,-48 - .cfi_offset %r13,-56 - .cfi_offset %r12,-64 - .cfi_offset %r11,-72 - .cfi_offset %r10,-80 - .cfi_offset %r9,-88 - .cfi_offset %r8,-96 - .cfi_offset %r7,-104 - .cfi_offset %r6,-112 - lgr %r1,%r15 - lg %r0,8(%r15) /* load eos */ - aghi %r15,-160 - .cfi_adjust_cfa_offset 160 - stg %r1,0(%r15) /* store back chain */ - stg %r0,8(%r15) /* store eos */ + .cfi_startproc + stmg %r6,%r15,48(%r15) /* save all call-saved registers */ + .cfi_offset %r15,-40 + .cfi_offset %r14,-48 + .cfi_offset %r13,-56 + .cfi_offset %r12,-64 + .cfi_offset %r11,-72 + .cfi_offset %r10,-80 + .cfi_offset %r9,-88 + .cfi_offset %r8,-96 + .cfi_offset %r7,-104 + .cfi_offset %r6,-112 + lgr %r1,%r15 + lg %r0,8(%r15) /* load eos */ + aghi %r15,-160 + .cfi_adjust_cfa_offset 160 + stg %r1,0(%r15) /* store back chain */ + stg %r0,8(%r15) /* store eos */ - /* The syscall calling convention isn't the same as the - * C one: - * we enter with r2 == *signal_pending - * r3 == syscall number - * r4, r5, r6, (stack) == syscall arguments - * and return the result in r2 - * and the syscall instruction needs - * r1 == syscall number - * r2 ... r7 == syscall arguments - * and returns the result in r2 - * Shuffle everything around appropriately. - */ - lgr %r8,%r2 /* signal_pending pointer */ - lgr %r1,%r3 /* syscall number */ - lgr %r2,%r4 /* syscall args */ - lgr %r3,%r5 - lgr %r4,%r6 - lmg %r5,%r7,320(%r15) + /* The syscall calling convention isn't the same as the + * C one: + * we enter with r2 == *signal_pending + * r3 == syscall number + * r4, r5, r6, (stack) == syscall arguments + * and return the result in r2 + * and the syscall instruction needs + * r1 == syscall number + * r2 ... r7 == syscall arguments + * and returns the result in r2 + * Shuffle everything around appropriately. + */ + lgr %r8,%r2 /* signal_pending pointer */ + lgr %r1,%r3 /* syscall number */ + lgr %r2,%r4 /* syscall args */ + lgr %r3,%r5 + lgr %r4,%r6 + lmg %r5,%r7,320(%r15) - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - icm %r0,15,0(%r8) - jne 2f - svc 0 + /* if signal_pending is non-zero, don't do the call */ + icm %r0,15,0(%r8) + jne 2f + svc 0 safe_syscall_end: -1: lg %r15,0(%r15) /* load back chain */ - .cfi_remember_state - .cfi_adjust_cfa_offset -160 - lmg %r6,%r15,48(%r15) /* load saved registers */ - br %r14 - .cfi_restore_state -2: lghi %r2, -TARGET_ERESTARTSYS - j 1b - .cfi_endproc +1: lg %r15,0(%r15) /* load back chain */ + .cfi_remember_state + .cfi_adjust_cfa_offset -160 + lmg %r6,%r15,48(%r15) /* load saved registers */ + br %r14 + .cfi_restore_state +2: lghi %r2, -TARGET_ERESTARTSYS + j 1b + .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base + .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/x86_64/safe-syscall.inc.S b/linux-user/host/x86_64/safe-syscall.inc.S index f36992daa3..158225553e 100644 --- a/linux-user/host/x86_64/safe-syscall.inc.S +++ b/linux-user/host/x86_64/safe-syscall.inc.S @@ -67,7 +67,7 @@ safe_syscall_base: */ safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ - cmpl $0, (%rbp) + cmpl $0, (%rbp) jnz 1f syscall safe_syscall_end: From a3310c0397e21df8f47cde3e55736104b9584d2d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 15 Nov 2021 14:08:52 +0100 Subject: [PATCH 318/421] linux-user: Move syscall error detection into safe_syscall_base The current api from safe_syscall_base() is to return -errno, which is the interface provided by *some* linux kernel abis. The wrapper macro, safe_syscall(), detects error, stores into errno, and returns -1, to match the api of the system syscall(). For those kernel abis that do not return -errno natively, this leads to double syscall error detection. E.g. Linux ppc64, which sets the SO flag for error. Simplify the usage from C by moving the error detection into assembly, and usage from assembly by providing a C helper with which to set errno. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- linux-user/host/aarch64/safe-syscall.inc.S | 20 ++++++------ linux-user/host/arm/safe-syscall.inc.S | 27 ++++++++++------ linux-user/host/i386/safe-syscall.inc.S | 37 +++++++++++++++------- linux-user/host/ppc64/safe-syscall.inc.S | 24 +++++++------- linux-user/host/riscv/safe-syscall.inc.S | 20 ++++++------ linux-user/host/s390x/safe-syscall.inc.S | 32 ++++++++++++------- linux-user/host/x86_64/safe-syscall.inc.S | 29 +++++++++-------- linux-user/meson.build | 1 + linux-user/safe-syscall-error.c | 28 ++++++++++++++++ linux-user/safe-syscall.h | 16 +++------- 10 files changed, 147 insertions(+), 87 deletions(-) create mode 100644 linux-user/safe-syscall-error.c diff --git a/linux-user/host/aarch64/safe-syscall.inc.S b/linux-user/host/aarch64/safe-syscall.inc.S index e2e726ef55..76a0a18a6c 100644 --- a/linux-user/host/aarch64/safe-syscall.inc.S +++ b/linux-user/host/aarch64/safe-syscall.inc.S @@ -22,15 +22,12 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .cfi_startproc /* The syscall calling convention isn't the same as the * C one: - * we enter with x0 == *signal_pending + * we enter with x0 == &signal_pending * x1 == syscall number * x2 ... x7, (stack) == syscall arguments * and return the result in x0 @@ -60,16 +57,21 @@ safe_syscall_base: safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ ldr w10, [x9] - cbnz w10, 0f + cbnz w10, 2f svc 0x0 safe_syscall_end: /* code path for having successfully executed the syscall */ + cmp x0, #-4096 + b.hi 0f ret -0: + /* code path setting errno */ +0: neg w0, w0 + b safe_syscall_set_errno_tail + /* code path when we didn't execute the syscall */ - mov x0, #-TARGET_ERESTARTSYS - ret - .cfi_endproc +2: mov w0, #TARGET_ERESTARTSYS + b safe_syscall_set_errno_tail + .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/arm/safe-syscall.inc.S b/linux-user/host/arm/safe-syscall.inc.S index 1f1ee8327b..618112c6bf 100644 --- a/linux-user/host/arm/safe-syscall.inc.S +++ b/linux-user/host/arm/safe-syscall.inc.S @@ -27,9 +27,6 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .fnstart @@ -46,7 +43,7 @@ safe_syscall_base: .cfi_rel_offset lr, 20 /* The syscall calling convention isn't the same as the C one: - * we enter with r0 == *signal_pending + * we enter with r0 == &signal_pending * r1 == syscall number * r2, r3, [sp+0] ... [sp+12] == syscall arguments * and return the result in r0 @@ -74,17 +71,29 @@ safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ ldr r12, [r8] /* signal_pending */ tst r12, r12 - bne 1f + bne 2f swi 0 safe_syscall_end: /* code path for having successfully executed the syscall */ + cmp r0, #-4096 + neghi r0, r0 + bhi 1f pop { r4, r5, r6, r7, r8, pc } -1: /* code path when we didn't execute the syscall */ - ldr r0, =-TARGET_ERESTARTSYS - pop { r4, r5, r6, r7, r8, pc } +2: mov r0, #TARGET_ERESTARTSYS + + /* code path setting errno */ +1: pop { r4, r5, r6, r7, r8, lr } + .cfi_adjust_cfa_offset -24 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + .cfi_restore r8 + .cfi_restore lr + b safe_syscall_set_errno_tail + .fnend .cfi_endproc - .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/i386/safe-syscall.inc.S b/linux-user/host/i386/safe-syscall.inc.S index e425aa54d8..f5883234bb 100644 --- a/linux-user/host/i386/safe-syscall.inc.S +++ b/linux-user/host/i386/safe-syscall.inc.S @@ -20,9 +20,6 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .cfi_startproc @@ -41,7 +38,7 @@ safe_syscall_base: /* The syscall calling convention isn't the same as the C one: * we enter with 0(%esp) == return address - * 4(%esp) == *signal_pending + * 4(%esp) == &signal_pending * 8(%esp) == syscall number * 12(%esp) ... 32(%esp) == syscall arguments * and return the result in eax @@ -70,11 +67,13 @@ safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ mov 4+16(%esp), %eax /* signal_pending */ cmpl $0, (%eax) - jnz 1f + jnz 2f mov 8+16(%esp), %eax /* syscall number */ int $0x80 safe_syscall_end: /* code path for having successfully executed the syscall */ + cmp $-4095, %eax + jae 0f pop %ebx .cfi_remember_state .cfi_adjust_cfa_offset -4 @@ -89,12 +88,28 @@ safe_syscall_end: .cfi_adjust_cfa_offset -4 .cfi_restore ebp ret - -1: - /* code path when we didn't execute the syscall */ .cfi_restore_state - mov $-TARGET_ERESTARTSYS, %eax - jmp safe_syscall_end - .cfi_endproc +0: neg %eax + jmp 1f + + /* code path when we didn't execute the syscall */ +2: mov $TARGET_ERESTARTSYS, %eax + + /* code path setting errno */ +1: pop %ebx + .cfi_adjust_cfa_offset -4 + .cfi_restore ebx + pop %edi + .cfi_adjust_cfa_offset -4 + .cfi_restore edi + pop %esi + .cfi_adjust_cfa_offset -4 + .cfi_restore esi + pop %ebp + .cfi_adjust_cfa_offset -4 + .cfi_restore ebp + jmp safe_syscall_set_errno_tail + + .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/ppc64/safe-syscall.inc.S b/linux-user/host/ppc64/safe-syscall.inc.S index 4b57440585..3a640cfc04 100644 --- a/linux-user/host/ppc64/safe-syscall.inc.S +++ b/linux-user/host/ppc64/safe-syscall.inc.S @@ -22,9 +22,6 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ #if _CALL_ELF == 2 safe_syscall_base: @@ -39,7 +36,7 @@ safe_syscall_base: .L.safe_syscall_base: .cfi_startproc #endif - /* We enter with r3 == *signal_pending + /* We enter with r3 == &signal_pending * r4 == syscall number * r5 ... r10 == syscall arguments * and return the result in r3 @@ -71,21 +68,22 @@ safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ lwz 12, 0(14) cmpwi 0, 12, 0 - bne- 0f + bne- 2f sc safe_syscall_end: /* code path when we did execute the syscall */ - ld 14, 16(1) /* restore r14 to its original value */ - bnslr+ - - /* syscall failed; return negative errno */ - neg 3, 3 + ld 14, 16(1) /* restore r14 */ + bso- 1f blr /* code path when we didn't execute the syscall */ -0: addi 3, 0, -TARGET_ERESTARTSYS - ld 14, 16(1) /* restore r14 to its original value */ - blr +2: ld 14, 16(1) /* restore r14 */ + addi 3, 0, TARGET_ERESTARTSYS + + /* code path setting errno */ +1: b safe_syscall_set_errno_tail + nop /* per abi, for the linker to modify */ + .cfi_endproc #if _CALL_ELF == 2 diff --git a/linux-user/host/riscv/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S index 95c4832de2..54c2e23f75 100644 --- a/linux-user/host/riscv/safe-syscall.inc.S +++ b/linux-user/host/riscv/safe-syscall.inc.S @@ -23,15 +23,12 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .cfi_startproc /* * The syscall calling convention is nearly the same as C: - * we enter with a0 == *signal_pending + * we enter with a0 == &signal_pending * a1 == syscall number * a2 ... a7 == syscall arguments * and return the result in a0 @@ -62,16 +59,21 @@ safe_syscall_base: safe_syscall_start: /* If signal_pending is non-zero, don't do the call */ lw t1, 0(t0) - bnez t1, 0f + bnez t1, 2f scall safe_syscall_end: /* code path for having successfully executed the syscall */ + li t2, -4096 + bgtu a0, t2, 0f ret -0: + /* code path setting errno */ +0: neg a0, a0 + j safe_syscall_set_errno_tail + /* code path when we didn't execute the syscall */ - li a0, -TARGET_ERESTARTSYS - ret - .cfi_endproc +2: li a0, TARGET_ERESTARTSYS + j safe_syscall_set_errno_tail + .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/s390x/safe-syscall.inc.S b/linux-user/host/s390x/safe-syscall.inc.S index d97d27458e..899dab39e9 100644 --- a/linux-user/host/s390x/safe-syscall.inc.S +++ b/linux-user/host/s390x/safe-syscall.inc.S @@ -20,9 +20,6 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .cfi_startproc @@ -44,9 +41,9 @@ safe_syscall_base: stg %r1,0(%r15) /* store back chain */ stg %r0,8(%r15) /* store eos */ - /* The syscall calling convention isn't the same as the - * C one: - * we enter with r2 == *signal_pending + /* + * The syscall calling convention isn't the same as the C one: + * we enter with r2 == &signal_pending * r3 == syscall number * r4, r5, r6, (stack) == syscall arguments * and return the result in r2 @@ -77,14 +74,25 @@ safe_syscall_start: svc 0 safe_syscall_end: -1: lg %r15,0(%r15) /* load back chain */ + /* code path for having successfully executed the syscall */ + lg %r15,0(%r15) /* load back chain */ .cfi_remember_state .cfi_adjust_cfa_offset -160 lmg %r6,%r15,48(%r15) /* load saved registers */ - br %r14 - .cfi_restore_state -2: lghi %r2, -TARGET_ERESTARTSYS - j 1b - .cfi_endproc + lghi %r0, -4095 /* check for syscall error */ + clgr %r2, %r0 + blr %r14 /* return on success */ + lcr %r2, %r2 /* create positive errno */ + jg safe_syscall_set_errno_tail + .cfi_restore_state + + /* code path when we didn't execute the syscall */ +2: lg %r15,0(%r15) /* load back chain */ + .cfi_adjust_cfa_offset -160 + lmg %r6,%r15,48(%r15) /* load saved registers */ + lghi %r2, TARGET_ERESTARTSYS + jg safe_syscall_set_errno_tail + + .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/x86_64/safe-syscall.inc.S b/linux-user/host/x86_64/safe-syscall.inc.S index 158225553e..39b64250c3 100644 --- a/linux-user/host/x86_64/safe-syscall.inc.S +++ b/linux-user/host/x86_64/safe-syscall.inc.S @@ -19,9 +19,6 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .cfi_startproc @@ -35,9 +32,9 @@ safe_syscall_base: .cfi_adjust_cfa_offset 8 .cfi_rel_offset rbp, 0 - /* The syscall calling convention isn't the same as the - * C one: - * we enter with rdi == *signal_pending + /* + * The syscall calling convention isn't the same as the C one: + * we enter with rdi == &signal_pending * rsi == syscall number * rdx, rcx, r8, r9, (stack), (stack) == syscall arguments * and return the result in rax @@ -68,24 +65,30 @@ safe_syscall_base: safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ cmpl $0, (%rbp) - jnz 1f + jnz 2f syscall safe_syscall_end: /* code path for having successfully executed the syscall */ + cmp $-4095, %rax + jae 0f pop %rbp .cfi_remember_state .cfi_def_cfa_offset 8 .cfi_restore rbp ret - -1: - /* code path when we didn't execute the syscall */ .cfi_restore_state - mov $-TARGET_ERESTARTSYS, %rax - pop %rbp + +0: neg %eax + jmp 1f + + /* code path when we didn't execute the syscall */ +2: mov $TARGET_ERESTARTSYS, %eax + + /* code path setting errno */ +1: pop %rbp .cfi_def_cfa_offset 8 .cfi_restore rbp - ret + jmp safe_syscall_set_errno_tail .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/meson.build b/linux-user/meson.build index bf62c13e37..94ac3c58ce 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -10,6 +10,7 @@ linux_user_ss.add(files( 'main.c', 'mmap.c', 'safe-syscall.S', + 'safe-syscall-error.c', 'signal.c', 'strace.c', 'syscall.c', diff --git a/linux-user/safe-syscall-error.c b/linux-user/safe-syscall-error.c new file mode 100644 index 0000000000..d7e2700f81 --- /dev/null +++ b/linux-user/safe-syscall-error.c @@ -0,0 +1,28 @@ +/* + * safe-syscall-error.c: errno setting fragment + * This is intended to be invoked by safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2021 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hostdep.h" +#include "safe-syscall.h" + +#ifdef HAVE_SAFE_SYSCALL +/* + * This is intended to be invoked via tail-call on the error path + * from the assembly in host/arch/safe-syscall.inc.S. This takes + * care of the host specific addressing of errno. + * Return -1 to finalize the return value for safe_syscall_base. + */ +long safe_syscall_set_errno_tail(int value) +{ + errno = value; + return -1; +} +#endif diff --git a/linux-user/safe-syscall.h b/linux-user/safe-syscall.h index aaa9ffc0e2..97837faddb 100644 --- a/linux-user/safe-syscall.h +++ b/linux-user/safe-syscall.h @@ -127,21 +127,15 @@ #ifdef HAVE_SAFE_SYSCALL /* The core part of this function is implemented in assembly */ extern long safe_syscall_base(int *pending, long number, ...); +extern long safe_syscall_set_errno_tail(int value); + /* These are defined by the safe-syscall.inc.S file */ extern char safe_syscall_start[]; extern char safe_syscall_end[]; -#define safe_syscall(...) \ - ({ \ - long ret_; \ - int *psp_ = &((TaskState *)thread_cpu->opaque)->signal_pending; \ - ret_ = safe_syscall_base(psp_, __VA_ARGS__); \ - if (is_error(ret_)) { \ - errno = -ret_; \ - ret_ = -1; \ - } \ - ret_; \ - }) +#define safe_syscall(...) \ + safe_syscall_base(&((TaskState *)thread_cpu->opaque)->signal_pending, \ + __VA_ARGS__) #else From 4542adef5b93c13f61ce7b3045d3b028e8b20af0 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 22 Nov 2021 17:38:34 +0100 Subject: [PATCH 319/421] linux-user/host/mips: Add safe-syscall.inc.S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/mips/hostdep.h | 3 + linux-user/host/mips/safe-syscall.inc.S | 148 ++++++++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 linux-user/host/mips/safe-syscall.inc.S diff --git a/linux-user/host/mips/hostdep.h b/linux-user/host/mips/hostdep.h index ba111d75c3..d9e90a096b 100644 --- a/linux-user/host/mips/hostdep.h +++ b/linux-user/host/mips/hostdep.h @@ -12,4 +12,7 @@ #ifndef MIPS_HOSTDEP_H #define MIPS_HOSTDEP_H +/* We have a safe-syscall.inc.S */ +#define HAVE_SAFE_SYSCALL + #endif diff --git a/linux-user/host/mips/safe-syscall.inc.S b/linux-user/host/mips/safe-syscall.inc.S new file mode 100644 index 0000000000..041d1a6e65 --- /dev/null +++ b/linux-user/host/mips/safe-syscall.inc.S @@ -0,0 +1,148 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by linux-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2021 Linaro, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "sys/regdef.h" +#include "sys/asm.h" + + .text + .set nomips16 + .set reorder + + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_start, @function + .type safe_syscall_end, @function + + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ + +#if _MIPS_SIM == _ABIO32 +/* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */ +#define FRAME 40 +#define OFS_S0 32 +#else +/* 1 * 8 for s0 save; 1 * 8 for align. */ +#define FRAME 16 +#define OFS_S0 0 +#endif + + +NESTED(safe_syscall_base, FRAME, ra) + .cfi_startproc + PTR_ADDIU sp, sp, -FRAME + .cfi_adjust_cfa_offset FRAME + REG_S s0, OFS_S0(sp) + .cfi_rel_offset s0, OFS_S0 +#if _MIPS_SIM == _ABIO32 + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == &signal_pending + * a1 == syscall number + * a2, a3, stack == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * v0 == syscall number + * a0 ... a3, stack == syscall arguments + * and returns the result in v0 + * Shuffle everything around appropriately. + */ + move s0, a0 /* signal_pending pointer */ + move v0, a1 /* syscall number */ + move a0, a2 /* syscall arguments */ + move a1, a3 + lw a2, FRAME+16(sp) + lw a3, FRAME+20(sp) + lw t4, FRAME+24(sp) + lw t5, FRAME+28(sp) + lw t6, FRAME+32(sp) + lw t7, FRAME+40(sp) + sw t4, 16(sp) + sw t5, 20(sp) + sw t6, 24(sp) + sw t7, 28(sp) +#else + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == &signal_pending + * a1 == syscall number + * a2 ... a7 == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * v0 == syscall number + * a0 ... a5 == syscall arguments + * and returns the result in v0 + * Shuffle everything around appropriately. + */ + move s0, a0 /* signal_pending pointer */ + move v0, a1 /* syscall number */ + move a0, a2 /* syscall arguments */ + move a1, a3 + move a2, a4 + move a3, a5 + move a4, a6 + move a5, a7 +#endif + + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* If signal_pending is non-zero, don't do the call */ + lw t1, 0(s0) + bnez t1, 2f + syscall +safe_syscall_end: + + /* code path for having successfully executed the syscall */ + REG_L s0, OFS_S0(sp) + PTR_ADDIU sp, sp, FRAME + .cfi_remember_state + .cfi_adjust_cfa_offset -FRAME + .cfi_restore s0 + bnez a3, 1f + jr ra + .cfi_restore_state + + /* code path when we didn't execute the syscall */ +2: REG_L s0, OFS_S0(sp) + PTR_ADDIU sp, sp, FRAME + .cfi_adjust_cfa_offset -FRAME + .cfi_restore s0 + li v0, TARGET_ERESTARTSYS + + /* code path setting errno */ + /* + * We didn't setup GP on entry, optimistic of the syscall success. + * We must do so now to load the address of the helper, as required + * by the ABI, into t9. + * + * Note that SETUP_GPX and SETUP_GPX64 are themselves conditional, + * so we can simply let the one that's not empty succeed. + */ +1: USE_ALT_CP(t0) + SETUP_GPX(t1) + SETUP_GPX64(t0, t1) + PTR_LA t9, safe_syscall_set_errno_tail + jr t9 + + .cfi_endproc +END(safe_syscall_base) From 95c021dac8358b9dffe4a2c05dea4ccce589ac47 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 15 Nov 2021 22:03:28 +0300 Subject: [PATCH 320/421] linux-user/host/sparc64: Add safe-syscall.inc.S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/sparc64/hostdep.h | 3 + linux-user/host/sparc64/safe-syscall.inc.S | 89 ++++++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 linux-user/host/sparc64/safe-syscall.inc.S diff --git a/linux-user/host/sparc64/hostdep.h b/linux-user/host/sparc64/hostdep.h index ce3968fca0..d832868cb1 100644 --- a/linux-user/host/sparc64/hostdep.h +++ b/linux-user/host/sparc64/hostdep.h @@ -12,4 +12,7 @@ #ifndef SPARC64_HOSTDEP_H #define SPARC64_HOSTDEP_H +/* We have a safe-syscall.inc.S */ +#define HAVE_SAFE_SYSCALL + #endif diff --git a/linux-user/host/sparc64/safe-syscall.inc.S b/linux-user/host/sparc64/safe-syscall.inc.S new file mode 100644 index 0000000000..901db15959 --- /dev/null +++ b/linux-user/host/sparc64/safe-syscall.inc.S @@ -0,0 +1,89 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by linux-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2021 Linaro, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .text + .balign 4 + + .register %g2, #scratch + .register %g3, #scratch + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + .type safe_syscall_start, @function + .type safe_syscall_end, @function + +#define STACK_BIAS 2047 +#define PARAM(N) STACK_BIAS + N*8 + + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .cfi_startproc + /* + * The syscall calling convention isn't the same as the C one: + * we enter with o0 == &signal_pending + * o1 == syscall number + * o2 ... o5, (stack) == syscall arguments + * and return the result in x0 + * and the syscall instruction needs + * g1 == syscall number + * o0 ... o5 == syscall arguments + * and returns the result in o0 + * Shuffle everything around appropriately. + */ + mov %o0, %g2 /* signal_pending pointer */ + mov %o1, %g1 /* syscall number */ + mov %o2, %o0 /* syscall arguments */ + mov %o3, %o1 + mov %o4, %o2 + mov %o5, %o3 + ldx [%sp + PARAM(6)], %o4 + ldx [%sp + PARAM(7)], %o5 + + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + lduw [%g2], %g3 + brnz,pn %g3, 2f + nop + ta 0x6d +safe_syscall_end: + /* code path for having successfully executed the syscall */ + bcs,pn %xcc, 1f + nop + ret + nop + + /* code path when we didn't execute the syscall */ +2: set TARGET_ERESTARTSYS, %o0 + + /* code path setting errno */ +1: mov %o7, %g1 + call safe_syscall_set_errno_tail + mov %g1, %o7 + + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base From 0a7e01904d407baa73c1baddbdfc9ccf2ace8356 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 15 Nov 2021 22:08:23 +0300 Subject: [PATCH 321/421] linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All supported hosts now define HAVE_SAFE_SYSCALL, so remove the ifdefs. This leaves hostdep.h empty, so remove it. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/host/aarch64/hostdep.h | 18 ------------------ linux-user/host/arm/hostdep.h | 18 ------------------ linux-user/host/i386/hostdep.h | 18 ------------------ linux-user/host/ia64/hostdep.h | 15 --------------- linux-user/host/mips/hostdep.h | 18 ------------------ linux-user/host/ppc/hostdep.h | 15 --------------- linux-user/host/ppc64/hostdep.h | 18 ------------------ linux-user/host/riscv/hostdep.h | 14 -------------- linux-user/host/s390/hostdep.h | 15 --------------- linux-user/host/s390x/hostdep.h | 18 ------------------ linux-user/host/sparc/hostdep.h | 15 --------------- linux-user/host/sparc64/hostdep.h | 18 ------------------ linux-user/host/x32/hostdep.h | 15 --------------- linux-user/host/x86_64/hostdep.h | 18 ------------------ linux-user/safe-syscall-error.c | 3 --- linux-user/safe-syscall.S | 3 --- linux-user/safe-syscall.h | 13 +------------ linux-user/signal.c | 2 -- linux-user/user-internals.h | 1 - 19 files changed, 1 insertion(+), 254 deletions(-) delete mode 100644 linux-user/host/aarch64/hostdep.h delete mode 100644 linux-user/host/arm/hostdep.h delete mode 100644 linux-user/host/i386/hostdep.h delete mode 100644 linux-user/host/ia64/hostdep.h delete mode 100644 linux-user/host/mips/hostdep.h delete mode 100644 linux-user/host/ppc/hostdep.h delete mode 100644 linux-user/host/ppc64/hostdep.h delete mode 100644 linux-user/host/riscv/hostdep.h delete mode 100644 linux-user/host/s390/hostdep.h delete mode 100644 linux-user/host/s390x/hostdep.h delete mode 100644 linux-user/host/sparc/hostdep.h delete mode 100644 linux-user/host/sparc64/hostdep.h delete mode 100644 linux-user/host/x32/hostdep.h delete mode 100644 linux-user/host/x86_64/hostdep.h diff --git a/linux-user/host/aarch64/hostdep.h b/linux-user/host/aarch64/hostdep.h deleted file mode 100644 index 39299d798a..0000000000 --- a/linux-user/host/aarch64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef AARCH64_HOSTDEP_H -#define AARCH64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/arm/hostdep.h b/linux-user/host/arm/hostdep.h deleted file mode 100644 index 86b137875a..0000000000 --- a/linux-user/host/arm/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef ARM_HOSTDEP_H -#define ARM_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/i386/hostdep.h b/linux-user/host/i386/hostdep.h deleted file mode 100644 index ce7136501f..0000000000 --- a/linux-user/host/i386/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef I386_HOSTDEP_H -#define I386_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/ia64/hostdep.h b/linux-user/host/ia64/hostdep.h deleted file mode 100644 index 263bf7658e..0000000000 --- a/linux-user/host/ia64/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef IA64_HOSTDEP_H -#define IA64_HOSTDEP_H - -#endif diff --git a/linux-user/host/mips/hostdep.h b/linux-user/host/mips/hostdep.h deleted file mode 100644 index d9e90a096b..0000000000 --- a/linux-user/host/mips/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef MIPS_HOSTDEP_H -#define MIPS_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/ppc/hostdep.h b/linux-user/host/ppc/hostdep.h deleted file mode 100644 index 23d8bd9d47..0000000000 --- a/linux-user/host/ppc/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef PPC_HOSTDEP_H -#define PPC_HOSTDEP_H - -#endif diff --git a/linux-user/host/ppc64/hostdep.h b/linux-user/host/ppc64/hostdep.h deleted file mode 100644 index 0c290dd904..0000000000 --- a/linux-user/host/ppc64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef PPC64_HOSTDEP_H -#define PPC64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/riscv/hostdep.h b/linux-user/host/riscv/hostdep.h deleted file mode 100644 index 7f67c22868..0000000000 --- a/linux-user/host/riscv/hostdep.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV_HOSTDEP_H -#define RISCV_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/s390/hostdep.h b/linux-user/host/s390/hostdep.h deleted file mode 100644 index afcba5a16a..0000000000 --- a/linux-user/host/s390/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef S390_HOSTDEP_H -#define S390_HOSTDEP_H - -#endif diff --git a/linux-user/host/s390x/hostdep.h b/linux-user/host/s390x/hostdep.h deleted file mode 100644 index d801145854..0000000000 --- a/linux-user/host/s390x/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef S390X_HOSTDEP_H -#define S390X_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/sparc/hostdep.h b/linux-user/host/sparc/hostdep.h deleted file mode 100644 index 391ad923cf..0000000000 --- a/linux-user/host/sparc/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef SPARC_HOSTDEP_H -#define SPARC_HOSTDEP_H - -#endif diff --git a/linux-user/host/sparc64/hostdep.h b/linux-user/host/sparc64/hostdep.h deleted file mode 100644 index d832868cb1..0000000000 --- a/linux-user/host/sparc64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef SPARC64_HOSTDEP_H -#define SPARC64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/x32/hostdep.h b/linux-user/host/x32/hostdep.h deleted file mode 100644 index 2c2d6d37da..0000000000 --- a/linux-user/host/x32/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef X32_HOSTDEP_H -#define X32_HOSTDEP_H - -#endif diff --git a/linux-user/host/x86_64/hostdep.h b/linux-user/host/x86_64/hostdep.h deleted file mode 100644 index 9c62bd26bd..0000000000 --- a/linux-user/host/x86_64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef X86_64_HOSTDEP_H -#define X86_64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/safe-syscall-error.c b/linux-user/safe-syscall-error.c index d7e2700f81..55d95ac39a 100644 --- a/linux-user/safe-syscall-error.c +++ b/linux-user/safe-syscall-error.c @@ -10,10 +10,8 @@ */ #include "qemu/osdep.h" -#include "hostdep.h" #include "safe-syscall.h" -#ifdef HAVE_SAFE_SYSCALL /* * This is intended to be invoked via tail-call on the error path * from the assembly in host/arch/safe-syscall.inc.S. This takes @@ -25,4 +23,3 @@ long safe_syscall_set_errno_tail(int value) errno = value; return -1; } -#endif diff --git a/linux-user/safe-syscall.S b/linux-user/safe-syscall.S index 42ea7c40ba..7ddc997801 100644 --- a/linux-user/safe-syscall.S +++ b/linux-user/safe-syscall.S @@ -10,15 +10,12 @@ * See the COPYING file in the top-level directory. */ -#include "hostdep.h" #include "target_errno_defs.h" /* We have the correct host directory on our include path * so that this will pull in the right fragment for the architecture. */ -#ifdef HAVE_SAFE_SYSCALL #include "safe-syscall.inc.S" -#endif /* We must specifically say that we're happy for the stack to not be * executable, otherwise the toolchain will default to assuming our diff --git a/linux-user/safe-syscall.h b/linux-user/safe-syscall.h index 97837faddb..f43267a8fc 100644 --- a/linux-user/safe-syscall.h +++ b/linux-user/safe-syscall.h @@ -124,7 +124,7 @@ * need to check SA_RESTART flags in QEMU or distinguish the various * kinds of restartability. */ -#ifdef HAVE_SAFE_SYSCALL + /* The core part of this function is implemented in assembly */ extern long safe_syscall_base(int *pending, long number, ...); extern long safe_syscall_set_errno_tail(int value); @@ -137,15 +137,4 @@ extern char safe_syscall_end[]; safe_syscall_base(&((TaskState *)thread_cpu->opaque)->signal_pending, \ __VA_ARGS__) -#else - -/* - * Fallback for architectures which don't yet provide a safe-syscall assembly - * fragment; note that this is racy! - * This should go away when all host architectures have been updated. - */ -#define safe_syscall syscall - -#endif - #endif diff --git a/linux-user/signal.c b/linux-user/signal.c index 6d5e5b698c..ca8f24b9ec 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -798,7 +798,6 @@ int queue_signal(CPUArchState *env, int sig, int si_type, /* Adjust the signal context to rewind out of safe-syscall if we're in it */ static inline void rewind_if_in_safe_syscall(void *puc) { -#ifdef HAVE_SAFE_SYSCALL ucontext_t *uc = (ucontext_t *)puc; uintptr_t pcreg = host_signal_pc(uc); @@ -806,7 +805,6 @@ static inline void rewind_if_in_safe_syscall(void *puc) && pcreg < (uintptr_t)safe_syscall_end) { host_signal_set_pc(uc, (uintptr_t)safe_syscall_start); } -#endif } static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index 661612a088..f71f372829 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -18,7 +18,6 @@ #ifndef LINUX_USER_USER_INTERNALS_H #define LINUX_USER_USER_INTERNALS_H -#include "hostdep.h" #include "exec/user/thunk.h" #include "exec/exec-all.h" #include "qemu/log.h" From af254a279255bd753c2b0b3a70fc39f09c724aab Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 22 Nov 2021 19:47:33 +0100 Subject: [PATCH 322/421] linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This value is fully internal to qemu, and so is not a TARGET define. We use this as an extra marker for both host and target errno. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 2 +- linux-user/alpha/cpu_loop.c | 2 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/cris/cpu_loop.c | 2 +- linux-user/generic/target_errno_defs.h | 2 +- linux-user/hexagon/cpu_loop.c | 2 +- linux-user/host/aarch64/safe-syscall.inc.S | 3 +-- linux-user/host/arm/safe-syscall.inc.S | 2 +- linux-user/host/i386/safe-syscall.inc.S | 2 +- linux-user/host/mips/safe-syscall.inc.S | 2 +- linux-user/host/ppc64/safe-syscall.inc.S | 2 +- linux-user/host/riscv/safe-syscall.inc.S | 2 +- linux-user/host/s390x/safe-syscall.inc.S | 2 +- linux-user/host/sparc64/safe-syscall.inc.S | 2 +- linux-user/host/x86_64/safe-syscall.inc.S | 2 +- linux-user/hppa/cpu_loop.c | 2 +- linux-user/i386/cpu_loop.c | 6 +++--- linux-user/m68k/cpu_loop.c | 2 +- linux-user/microblaze/cpu_loop.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- linux-user/openrisc/cpu_loop.c | 2 +- linux-user/ppc/cpu_loop.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- linux-user/s390x/cpu_loop.c | 2 +- linux-user/safe-syscall.h | 8 ++++---- linux-user/sh4/cpu_loop.c | 2 +- linux-user/signal-common.h | 2 +- linux-user/signal.c | 6 +++--- linux-user/sparc/cpu_loop.c | 2 +- linux-user/syscall.c | 16 ++++++++-------- linux-user/xtensa/cpu_loop.c | 2 +- 31 files changed, 45 insertions(+), 46 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index f9f3473288..ad9a8fdc25 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -99,7 +99,7 @@ void cpu_loop(CPUARMState *env) env->xregs[4], env->xregs[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->xregs[0] = ret; diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4029849d5c..ce9b251ce3 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -98,7 +98,7 @@ void cpu_loop(CPUAlphaState *env) env->ir[IR_A2], env->ir[IR_A3], env->ir[IR_A4], env->ir[IR_A5], 0, 0); - if (sysret == -TARGET_ERESTARTSYS) { + if (sysret == -QEMU_ERESTARTSYS) { env->pc -= 4; break; } diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 01cb6eb534..1fcf19750e 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -407,7 +407,7 @@ void cpu_loop(CPUARMState *env) env->regs[4], env->regs[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->regs[15] -= env->thumb ? 2 : 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[0] = ret; diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index 0d5d268609..f3e5b13f89 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -50,7 +50,7 @@ void cpu_loop(CPUCRISState *env) env->pregs[7], env->pregs[11], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[10] = ret; diff --git a/linux-user/generic/target_errno_defs.h b/linux-user/generic/target_errno_defs.h index 17d85e0b61..58a06a10d6 100644 --- a/linux-user/generic/target_errno_defs.h +++ b/linux-user/generic/target_errno_defs.h @@ -153,7 +153,7 @@ * after handling any pending signals. They match with the ones the guest * kernel uses for the same purpose. */ -#define TARGET_ERESTARTSYS 512 /* Restart system call (if SA_RESTART) */ +#define QEMU_ERESTARTSYS 512 /* Restart system call (if SA_RESTART) */ /* QEMU internal, not visible to the guest. This is returned by the * do_sigreturn() code after a successful sigreturn syscall, to indicate diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index e47f8348d5..108d755ce0 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -55,7 +55,7 @@ void cpu_loop(CPUHexagonState *env) env->gpr[4], env->gpr[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->gpr[HEX_REG_PC] -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->gpr[0] = ret; diff --git a/linux-user/host/aarch64/safe-syscall.inc.S b/linux-user/host/aarch64/safe-syscall.inc.S index 76a0a18a6c..87c9580faa 100644 --- a/linux-user/host/aarch64/safe-syscall.inc.S +++ b/linux-user/host/aarch64/safe-syscall.inc.S @@ -70,8 +70,7 @@ safe_syscall_end: b safe_syscall_set_errno_tail /* code path when we didn't execute the syscall */ -2: mov w0, #TARGET_ERESTARTSYS +2: mov w0, #QEMU_ERESTARTSYS b safe_syscall_set_errno_tail - .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/arm/safe-syscall.inc.S b/linux-user/host/arm/safe-syscall.inc.S index 618112c6bf..f1a6aabfd3 100644 --- a/linux-user/host/arm/safe-syscall.inc.S +++ b/linux-user/host/arm/safe-syscall.inc.S @@ -81,7 +81,7 @@ safe_syscall_end: pop { r4, r5, r6, r7, r8, pc } /* code path when we didn't execute the syscall */ -2: mov r0, #TARGET_ERESTARTSYS +2: mov r0, #QEMU_ERESTARTSYS /* code path setting errno */ 1: pop { r4, r5, r6, r7, r8, lr } diff --git a/linux-user/host/i386/safe-syscall.inc.S b/linux-user/host/i386/safe-syscall.inc.S index f5883234bb..1fb031d228 100644 --- a/linux-user/host/i386/safe-syscall.inc.S +++ b/linux-user/host/i386/safe-syscall.inc.S @@ -94,7 +94,7 @@ safe_syscall_end: jmp 1f /* code path when we didn't execute the syscall */ -2: mov $TARGET_ERESTARTSYS, %eax +2: mov $QEMU_ERESTARTSYS, %eax /* code path setting errno */ 1: pop %ebx diff --git a/linux-user/host/mips/safe-syscall.inc.S b/linux-user/host/mips/safe-syscall.inc.S index 041d1a6e65..e9362e774d 100644 --- a/linux-user/host/mips/safe-syscall.inc.S +++ b/linux-user/host/mips/safe-syscall.inc.S @@ -127,7 +127,7 @@ safe_syscall_end: PTR_ADDIU sp, sp, FRAME .cfi_adjust_cfa_offset -FRAME .cfi_restore s0 - li v0, TARGET_ERESTARTSYS + li v0, QEMU_ERESTARTSYS /* code path setting errno */ /* diff --git a/linux-user/host/ppc64/safe-syscall.inc.S b/linux-user/host/ppc64/safe-syscall.inc.S index 3a640cfc04..69d3c70094 100644 --- a/linux-user/host/ppc64/safe-syscall.inc.S +++ b/linux-user/host/ppc64/safe-syscall.inc.S @@ -78,7 +78,7 @@ safe_syscall_end: /* code path when we didn't execute the syscall */ 2: ld 14, 16(1) /* restore r14 */ - addi 3, 0, TARGET_ERESTARTSYS + addi 3, 0, QEMU_ERESTARTSYS /* code path setting errno */ 1: b safe_syscall_set_errno_tail diff --git a/linux-user/host/riscv/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S index 54c2e23f75..ca456d8a46 100644 --- a/linux-user/host/riscv/safe-syscall.inc.S +++ b/linux-user/host/riscv/safe-syscall.inc.S @@ -72,7 +72,7 @@ safe_syscall_end: j safe_syscall_set_errno_tail /* code path when we didn't execute the syscall */ -2: li a0, TARGET_ERESTARTSYS +2: li a0, QEMU_ERESTARTSYS j safe_syscall_set_errno_tail .cfi_endproc diff --git a/linux-user/host/s390x/safe-syscall.inc.S b/linux-user/host/s390x/safe-syscall.inc.S index 899dab39e9..66f84385a2 100644 --- a/linux-user/host/s390x/safe-syscall.inc.S +++ b/linux-user/host/s390x/safe-syscall.inc.S @@ -91,7 +91,7 @@ safe_syscall_end: 2: lg %r15,0(%r15) /* load back chain */ .cfi_adjust_cfa_offset -160 lmg %r6,%r15,48(%r15) /* load saved registers */ - lghi %r2, TARGET_ERESTARTSYS + lghi %r2, QEMU_ERESTARTSYS jg safe_syscall_set_errno_tail .cfi_endproc diff --git a/linux-user/host/sparc64/safe-syscall.inc.S b/linux-user/host/sparc64/safe-syscall.inc.S index 901db15959..f4b3c0f9ae 100644 --- a/linux-user/host/sparc64/safe-syscall.inc.S +++ b/linux-user/host/sparc64/safe-syscall.inc.S @@ -78,7 +78,7 @@ safe_syscall_end: nop /* code path when we didn't execute the syscall */ -2: set TARGET_ERESTARTSYS, %o0 +2: set QEMU_ERESTARTSYS, %o0 /* code path setting errno */ 1: mov %o7, %g1 diff --git a/linux-user/host/x86_64/safe-syscall.inc.S b/linux-user/host/x86_64/safe-syscall.inc.S index 39b64250c3..f88cbe1347 100644 --- a/linux-user/host/x86_64/safe-syscall.inc.S +++ b/linux-user/host/x86_64/safe-syscall.inc.S @@ -82,7 +82,7 @@ safe_syscall_end: jmp 1f /* code path when we didn't execute the syscall */ -2: mov $TARGET_ERESTARTSYS, %eax +2: mov $QEMU_ERESTARTSYS, %eax /* code path setting errno */ 1: pop %rbp diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 375576c8f0..5315224d12 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -133,7 +133,7 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case -TARGET_ERESTARTSYS: + case -QEMU_ERESTARTSYS: case -TARGET_QEMU_ESIGRETURN: break; } diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index f6a1cc632b..fbd9a353e5 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -180,7 +180,7 @@ static void emulate_vsyscall(CPUX86State *env) ret = do_syscall(env, syscall, env->regs[R_EDI], env->regs[R_ESI], env->regs[R_EDX], env->regs[10], env->regs[8], env->regs[9], 0, 0); - g_assert(ret != -TARGET_ERESTARTSYS); + g_assert(ret != -QEMU_ERESTARTSYS); g_assert(ret != -TARGET_QEMU_ESIGRETURN); if (ret == -TARGET_EFAULT) { goto sigsegv; @@ -223,7 +223,7 @@ void cpu_loop(CPUX86State *env) env->regs[R_EDI], env->regs[R_EBP], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->eip -= 2; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[R_EAX] = ret; @@ -241,7 +241,7 @@ void cpu_loop(CPUX86State *env) env->regs[8], env->regs[9], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->eip -= 2; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[R_EAX] = ret; diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 790bd558c3..b03c21a3dc 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -80,7 +80,7 @@ void cpu_loop(CPUM68KState *env) env->dregs[5], env->aregs[0], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->dregs[0] = ret; diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index a94467dd2d..6e368f986e 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -53,7 +53,7 @@ void cpu_loop(CPUMBState *env) env->regs[9], env->regs[10], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { /* Wind back to before the syscall. */ env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index b735c99a24..64f308c6ad 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -141,7 +141,7 @@ done_syscall: env->active_tc.gpr[8], env->active_tc.gpr[9], env->active_tc.gpr[10], env->active_tc.gpr[11]); # endif /* O32 */ - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->active_tc.PC -= 4; break; } diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index 3cfdbbf037..3147ab2b62 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -48,7 +48,7 @@ void cpu_loop(CPUOpenRISCState *env) cpu_get_gpr(env, 6), cpu_get_gpr(env, 7), cpu_get_gpr(env, 8), 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { cpu_set_gpr(env, 11, ret); diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 483e669300..5348641e9e 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -428,7 +428,7 @@ void cpu_loop(CPUPPCState *env) ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6], env->gpr[7], env->gpr[8], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->nip -= 4; break; } diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index b301dac802..20f8c48b1d 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -69,7 +69,7 @@ void cpu_loop(CPURISCVState *env) env->gpr[xA5], 0, 0); } - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->gpr[xA0] = ret; diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index d089c8417e..043582ca7c 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -83,7 +83,7 @@ void cpu_loop(CPUS390XState *env) ret = do_syscall(env, n, env->regs[2], env->regs[3], env->regs[4], env->regs[5], env->regs[6], env->regs[7], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->psw.addr -= env->int_svc_ilen; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->regs[2] = ret; diff --git a/linux-user/safe-syscall.h b/linux-user/safe-syscall.h index f43267a8fc..61a04e2b5a 100644 --- a/linux-user/safe-syscall.h +++ b/linux-user/safe-syscall.h @@ -25,10 +25,10 @@ * * Call a system call if guest signal not pending. * This has the same API as the libc syscall() function, except that it - * may return -1 with errno == TARGET_ERESTARTSYS if a signal was pending. + * may return -1 with errno == QEMU_ERESTARTSYS if a signal was pending. * * Returns: the system call result, or -1 with an error code in errno - * (Errnos are host errnos; we rely on TARGET_ERESTARTSYS not clashing + * (Errnos are host errnos; we rely on QEMU_ERESTARTSYS not clashing * with any of the host errno values.) */ @@ -81,7 +81,7 @@ * which are only technically blocking (ie which we know in practice won't * stay in the host kernel indefinitely) it's OK to use libc if necessary. * You must be able to cope with backing out correctly if some safe_syscall - * you make in the implementation returns either -TARGET_ERESTARTSYS or + * you make in the implementation returns either -QEMU_ERESTARTSYS or * EINTR though.) * * block_signals() cannot be used for interruptible syscalls. @@ -94,7 +94,7 @@ * handler checks the interrupted host PC against the addresse of that * known section. If the PC is before or at the address of the syscall * instruction then we change the PC to point at a "return - * -TARGET_ERESTARTSYS" code path instead, and then exit the signal handler + * -QEMU_ERESTARTSYS" code path instead, and then exit the signal handler * (causing the safe_syscall() call to immediately return that value). * Then in the main.c loop if we see this magic return value we adjust * the guest PC to wind it back to before the system call, and invoke diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index ac9b01840c..6c4ebfa969 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -50,7 +50,7 @@ void cpu_loop(CPUSH4State *env) env->gregs[0], env->gregs[1], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; } else if (ret != -TARGET_QEMU_ESIGRETURN) { env->gregs[0] = ret; diff --git a/linux-user/signal-common.h b/linux-user/signal-common.h index 7457f8025c..b9f33bb44f 100644 --- a/linux-user/signal-common.h +++ b/linux-user/signal-common.h @@ -76,7 +76,7 @@ abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx, * Block all signals, and arrange that the signal mask is returned to * its correct value for the guest before we resume execution of guest code. * If this function returns non-zero, then the caller should immediately - * return -TARGET_ERESTARTSYS to the main loop, which will take the pending + * return -QEMU_ERESTARTSYS to the main loop, which will take the pending * signal and restart execution of the syscall. * If block_signals() returns zero, then the caller can continue with * emulation of the system call knowing that no signals can be taken diff --git a/linux-user/signal.c b/linux-user/signal.c index ca8f24b9ec..12b1705287 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -213,7 +213,7 @@ int block_signals(void) /* Wrapper for sigprocmask function * Emulates a sigprocmask in a safe way for the guest. Note that set and oldset - * are host signal set, not guest ones. Returns -TARGET_ERESTARTSYS if + * are host signal set, not guest ones. Returns -QEMU_ERESTARTSYS if * a signal was already pending and the syscall must be restarted, or * 0 on success. * If set is NULL, this is guaranteed not to fail. @@ -230,7 +230,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) int i; if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } switch (how) { @@ -985,7 +985,7 @@ int do_sigaction(int sig, const struct target_sigaction *act, } if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } k = &sigact_table[sig - 1]; diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 0ba65e431c..529337c5e0 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -181,7 +181,7 @@ void cpu_loop (CPUSPARCState *env) env->regwptr[2], env->regwptr[3], env->regwptr[4], env->regwptr[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { + if (ret == -QEMU_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { break; } if ((abi_ulong)ret >= (abi_ulong)(-515)) { diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f1cfcc8104..23fb45e0f1 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -547,7 +547,7 @@ static inline abi_long get_errno(abi_long ret) const char *target_strerror(int err) { - if (err == TARGET_ERESTARTSYS) { + if (err == QEMU_ERESTARTSYS) { return "To be restarted"; } if (err == TARGET_QEMU_ESIGRETURN) { @@ -6458,7 +6458,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, } if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } fork_start(); @@ -8328,7 +8328,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, Do thread termination if we have more then one thread. */ if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } pthread_mutex_lock(&clone_lock); @@ -9317,7 +9317,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, #endif ret = get_errno(safe_rt_sigsuspend(&ts->sigsuspend_mask, SIGSET_T_SIZE)); - if (ret != -TARGET_ERESTARTSYS) { + if (ret != -QEMU_ERESTARTSYS) { ts->in_sigsuspend = 1; } } @@ -9336,7 +9336,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, unlock_user(p, arg1, 0); ret = get_errno(safe_rt_sigsuspend(&ts->sigsuspend_mask, SIGSET_T_SIZE)); - if (ret != -TARGET_ERESTARTSYS) { + if (ret != -QEMU_ERESTARTSYS) { ts->in_sigsuspend = 1; } } @@ -9452,13 +9452,13 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, #ifdef TARGET_NR_sigreturn case TARGET_NR_sigreturn: if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } return do_sigreturn(cpu_env); #endif case TARGET_NR_rt_sigreturn: if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } return do_rt_sigreturn(cpu_env); case TARGET_NR_sethostname: @@ -13145,7 +13145,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, static bool flag; flag = !flag; if (flag) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } } #endif diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index a83490ab35..29cc6f3830 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -184,7 +184,7 @@ void cpu_loop(CPUXtensaState *env) env->regs[2] = ret; break; - case -TARGET_ERESTARTSYS: + case -QEMU_ERESTARTSYS: env->pc -= 3; break; From ea8ee3ee933c40e01be0d0cb95c444182c52cd25 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 22 Nov 2021 19:49:02 +0100 Subject: [PATCH 323/421] bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This value is fully internal to qemu, and so is not a TARGET define. We use this as an extra marker for both host and target errno. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- bsd-user/errno_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsd-user/errno_defs.h b/bsd-user/errno_defs.h index 832671354f..141e08456c 100644 --- a/bsd-user/errno_defs.h +++ b/bsd-user/errno_defs.h @@ -151,6 +151,6 @@ /* Internal errors: */ #define TARGET_EJUSTRETURN 254 /* Just return without modifing regs */ #define TARGET_ERESTART 255 /* Restart syscall */ -#define TARGET_ERESTARTSYS TARGET_ERESTART /* Linux compat */ +#define QEMU_ERESTARTSYS TARGET_ERESTART #endif /* ! _ERRNO_DEFS_H_ */ From 57a0c9384c12b7cc13d168fe5bff1db244c72151 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 05:14:52 -0800 Subject: [PATCH 324/421] linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This value is fully internal to qemu, and so is not a TARGET define. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 2 +- linux-user/aarch64/signal.c | 4 ++-- linux-user/alpha/cpu_loop.c | 2 +- linux-user/alpha/signal.c | 8 ++++---- linux-user/arm/cpu_loop.c | 2 +- linux-user/arm/signal.c | 8 ++++---- linux-user/cris/cpu_loop.c | 2 +- linux-user/cris/signal.c | 4 ++-- linux-user/generic/target_errno_defs.h | 2 +- linux-user/hexagon/cpu_loop.c | 2 +- linux-user/hexagon/signal.c | 2 +- linux-user/hppa/cpu_loop.c | 2 +- linux-user/hppa/signal.c | 4 ++-- linux-user/i386/cpu_loop.c | 6 +++--- linux-user/i386/signal.c | 8 ++++---- linux-user/m68k/cpu_loop.c | 2 +- linux-user/m68k/signal.c | 8 ++++---- linux-user/microblaze/cpu_loop.c | 2 +- linux-user/microblaze/signal.c | 4 ++-- linux-user/mips/cpu_loop.c | 2 +- linux-user/mips/signal.c | 8 ++++---- linux-user/openrisc/cpu_loop.c | 2 +- linux-user/ppc/cpu_loop.c | 2 +- linux-user/ppc/signal.c | 10 +++++----- linux-user/riscv/cpu_loop.c | 2 +- linux-user/riscv/signal.c | 2 +- linux-user/s390x/cpu_loop.c | 2 +- linux-user/s390x/signal.c | 8 ++++---- linux-user/sh4/cpu_loop.c | 2 +- linux-user/sh4/signal.c | 8 ++++---- linux-user/sparc/cpu_loop.c | 2 +- linux-user/sparc/signal.c | 8 ++++---- linux-user/syscall.c | 2 +- linux-user/xtensa/cpu_loop.c | 2 +- linux-user/xtensa/signal.c | 4 ++-- 35 files changed, 70 insertions(+), 70 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index ad9a8fdc25..1737e2ea65 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -101,7 +101,7 @@ void cpu_loop(CPUARMState *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->xregs[0] = ret; } break; diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 29c52db3f1..df9e39a4ba 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -556,12 +556,12 @@ long do_rt_sigreturn(CPUARMState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_sigreturn(CPUARMState *env) diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index ce9b251ce3..37c33f0ccd 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -102,7 +102,7 @@ void cpu_loop(CPUAlphaState *env) env->pc -= 4; break; } - if (sysret == -TARGET_QEMU_ESIGRETURN) { + if (sysret == -QEMU_ESIGRETURN) { break; } /* Syscall writes 0 to V0 to bypass error check, similar diff --git a/linux-user/alpha/signal.c b/linux-user/alpha/signal.c index bbe3dd175a..4ec42994d4 100644 --- a/linux-user/alpha/signal.c +++ b/linux-user/alpha/signal.c @@ -225,11 +225,11 @@ long do_sigreturn(CPUAlphaState *env) restore_sigcontext(env, sc); unlock_user_struct(sc, sc_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUAlphaState *env) @@ -249,13 +249,13 @@ long do_rt_sigreturn(CPUAlphaState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 1fcf19750e..f153ab503a 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -409,7 +409,7 @@ void cpu_loop(CPUARMState *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->regs[15] -= env->thumb ? 2 : 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[0] = ret; } } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index df9f8e8eb2..cf99fd7b8a 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -511,12 +511,12 @@ long do_sigreturn(CPUARMState *env) } unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUARMState *env) @@ -546,12 +546,12 @@ long do_rt_sigreturn(CPUARMState *env) } unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } /* diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index f3e5b13f89..5213aebf55 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -52,7 +52,7 @@ void cpu_loop(CPUCRISState *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[10] = ret; } break; diff --git a/linux-user/cris/signal.c b/linux-user/cris/signal.c index 7f6aca934e..4f532b2903 100644 --- a/linux-user/cris/signal.c +++ b/linux-user/cris/signal.c @@ -177,10 +177,10 @@ long do_sigreturn(CPUCRISState *env) restore_sigcontext(&frame->sc, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUCRISState *env) diff --git a/linux-user/generic/target_errno_defs.h b/linux-user/generic/target_errno_defs.h index 58a06a10d6..bb37d88be9 100644 --- a/linux-user/generic/target_errno_defs.h +++ b/linux-user/generic/target_errno_defs.h @@ -162,6 +162,6 @@ * ERESTART_NOINTR (which is kernel internal) to guarantee that we won't * clash with a valid guest errno now or in the future. */ -#define TARGET_QEMU_ESIGRETURN 513 /* Return from signal */ +#define QEMU_ESIGRETURN 513 /* Return from signal */ #endif diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 108d755ce0..0d73934d31 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -57,7 +57,7 @@ void cpu_loop(CPUHexagonState *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->gpr[HEX_REG_PC] -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->gpr[0] = ret; } break; diff --git a/linux-user/hexagon/signal.c b/linux-user/hexagon/signal.c index 74e61739a0..ad4e3822d5 100644 --- a/linux-user/hexagon/signal.c +++ b/linux-user/hexagon/signal.c @@ -268,7 +268,7 @@ long do_rt_sigreturn(CPUHexagonState *env) target_restore_altstack(&frame->uc.uc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 5315224d12..a47a63176b 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -134,7 +134,7 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_b = env->gr[31] + 4; break; case -QEMU_ERESTARTSYS: - case -TARGET_QEMU_ESIGRETURN: + case -QEMU_ESIGRETURN: break; } break; diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index c2fbc26ebb..962f551c04 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -191,9 +191,9 @@ long do_rt_sigreturn(CPUArchState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index fbd9a353e5..9aaae93e2f 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -181,7 +181,7 @@ static void emulate_vsyscall(CPUX86State *env) env->regs[R_EDX], env->regs[10], env->regs[8], env->regs[9], 0, 0); g_assert(ret != -QEMU_ERESTARTSYS); - g_assert(ret != -TARGET_QEMU_ESIGRETURN); + g_assert(ret != -QEMU_ESIGRETURN); if (ret == -TARGET_EFAULT) { goto sigsegv; } @@ -225,7 +225,7 @@ void cpu_loop(CPUX86State *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->eip -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[R_EAX] = ret; } break; @@ -243,7 +243,7 @@ void cpu_loop(CPUX86State *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->eip -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[R_EAX] = ret; } break; diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 433efa3d69..4372621a4d 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -559,12 +559,12 @@ long do_sigreturn(CPUX86State *env) if (restore_sigcontext(env, &frame->sc)) goto badframe; unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #endif @@ -588,12 +588,12 @@ long do_rt_sigreturn(CPUX86State *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #ifndef TARGET_X86_64 diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index b03c21a3dc..3181594414 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -82,7 +82,7 @@ void cpu_loop(CPUM68KState *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->dregs[0] = ret; } } diff --git a/linux-user/m68k/signal.c b/linux-user/m68k/signal.c index ec33482e14..5f35354487 100644 --- a/linux-user/m68k/signal.c +++ b/linux-user/m68k/signal.c @@ -353,11 +353,11 @@ long do_sigreturn(CPUM68KState *env) restore_sigcontext(env, &frame->sc); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUM68KState *env) @@ -381,12 +381,12 @@ long do_rt_sigreturn(CPUM68KState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 6e368f986e..ff1fb26c8b 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -56,7 +56,7 @@ void cpu_loop(CPUMBState *env) if (ret == -QEMU_ERESTARTSYS) { /* Wind back to before the syscall. */ env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[3] = ret; } /* All syscall exits result in guest r14 being equal to the diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c index 8ebb6a1b7d..5188d74025 100644 --- a/linux-user/microblaze/signal.c +++ b/linux-user/microblaze/signal.c @@ -207,12 +207,12 @@ long do_rt_sigreturn(CPUMBState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 64f308c6ad..32f9fc1c1c 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -145,7 +145,7 @@ done_syscall: env->active_tc.PC -= 4; break; } - if (ret == -TARGET_QEMU_ESIGRETURN) { + if (ret == -QEMU_ESIGRETURN) { /* Returning from a successful sigreturn syscall. Avoid clobbering register state. */ break; diff --git a/linux-user/mips/signal.c b/linux-user/mips/signal.c index 8f79e405ec..58a9d7a8a3 100644 --- a/linux-user/mips/signal.c +++ b/linux-user/mips/signal.c @@ -281,11 +281,11 @@ long do_sigreturn(CPUMIPSState *regs) /* I am not sure this is right, but it seems to work * maybe a problem with nested signals ? */ regs->CP0_EPC = 0; - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } # endif /* O32 */ @@ -371,11 +371,11 @@ long do_rt_sigreturn(CPUMIPSState *env) /* I am not sure this is right, but it seems to work * maybe a problem with nested signals ? */ env->CP0_EPC = 0; - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index 3147ab2b62..592901a68b 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -50,7 +50,7 @@ void cpu_loop(CPUOpenRISCState *env) cpu_get_gpr(env, 8), 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { cpu_set_gpr(env, 11, ret); } break; diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 5348641e9e..30c82f2354 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -432,7 +432,7 @@ void cpu_loop(CPUPPCState *env) env->nip -= 4; break; } - if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { + if (ret == (target_ulong)(-QEMU_ESIGRETURN)) { /* Returning from a successful sigreturn syscall. Avoid corrupting register state. */ break; diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 90a0369632..176c9d8503 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -591,13 +591,13 @@ long do_sigreturn(CPUPPCState *env) unlock_user_struct(sr, sr_addr, 1); unlock_user_struct(sc, sc_addr, 1); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; sigsegv: unlock_user_struct(sr, sr_addr, 1); unlock_user_struct(sc, sc_addr, 1); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #endif /* !defined(TARGET_PPC64) */ @@ -646,12 +646,12 @@ long do_rt_sigreturn(CPUPPCState *env) target_restore_altstack(&rt_sf->uc.tuc_stack, env); unlock_user_struct(rt_sf, rt_sf_addr, 1); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; sigsegv: unlock_user_struct(rt_sf, rt_sf_addr, 1); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } /* This syscall implements {get,set,swap}context for userland. */ @@ -704,7 +704,7 @@ abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx, /* We cannot return to a partially updated context. */ force_sig(TARGET_SIGSEGV); } - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } return 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 20f8c48b1d..0cd8985cb8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -71,7 +71,7 @@ void cpu_loop(CPURISCVState *env) } if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->gpr[xA0] = ret; } if (cs->singlestep_enabled) { diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index a0f9542ce3..296e39fbf0 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -188,7 +188,7 @@ long do_rt_sigreturn(CPURISCVState *env) target_restore_altstack(&frame->uc.uc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index 043582ca7c..ad0c3cd263 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -85,7 +85,7 @@ void cpu_loop(CPUS390XState *env) env->regs[6], env->regs[7], 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->psw.addr -= env->int_svc_ilen; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[2] = ret; } break; diff --git a/linux-user/s390x/signal.c b/linux-user/s390x/signal.c index 676b948147..f47713e04a 100644 --- a/linux-user/s390x/signal.c +++ b/linux-user/s390x/signal.c @@ -359,7 +359,7 @@ long do_sigreturn(CPUS390XState *env) trace_user_do_sigreturn(env, frame_addr); if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } /* Make sure that we're initializing all of target_set. */ @@ -373,7 +373,7 @@ long do_sigreturn(CPUS390XState *env) restore_sigregs_ext(env, &frame->sregs_ext); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUS390XState *env) @@ -385,7 +385,7 @@ long do_rt_sigreturn(CPUS390XState *env) trace_user_do_rt_sigreturn(env, frame_addr); if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } target_to_host_sigset(&set, &frame->uc.tuc_sigmask); @@ -397,7 +397,7 @@ long do_rt_sigreturn(CPUS390XState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 6c4ebfa969..3290f6445c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -52,7 +52,7 @@ void cpu_loop(CPUSH4State *env) 0, 0); if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->gregs[0] = ret; } break; diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c index faa869fb19..f6a18bc6b5 100644 --- a/linux-user/sh4/signal.c +++ b/linux-user/sh4/signal.c @@ -286,12 +286,12 @@ long do_sigreturn(CPUSH4State *regs) restore_sigcontext(regs, &frame->sc); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUSH4State *regs) @@ -313,12 +313,12 @@ long do_rt_sigreturn(CPUSH4State *regs) target_restore_altstack(&frame->uc.tuc_stack, regs); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 529337c5e0..8765ab6020 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -181,7 +181,7 @@ void cpu_loop (CPUSPARCState *env) env->regwptr[2], env->regwptr[3], env->regwptr[4], env->regwptr[5], 0, 0); - if (ret == -QEMU_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { + if (ret == -QEMU_ERESTARTSYS || ret == -QEMU_ESIGRETURN) { break; } if ((abi_ulong)ret >= (abi_ulong)(-515)) { diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index 23e1e761de..b501750fe0 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -431,12 +431,12 @@ long do_sigreturn(CPUSPARCState *env) set_sigmask(&host_set); unlock_user_struct(sf, sf_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; segv_and_exit: unlock_user_struct(sf, sf_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; #else return -TARGET_ENOSYS; #endif @@ -495,12 +495,12 @@ long do_rt_sigreturn(CPUSPARCState *env) env->npc = tnpc; unlock_user_struct(sf, sf_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; segv_and_exit: unlock_user_struct(sf, sf_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 23fb45e0f1..2867be4cd3 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -550,7 +550,7 @@ const char *target_strerror(int err) if (err == QEMU_ERESTARTSYS) { return "To be restarted"; } - if (err == TARGET_QEMU_ESIGRETURN) { + if (err == QEMU_ESIGRETURN) { return "Successful exit from sigreturn"; } diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index 29cc6f3830..6bc6d6dee6 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -188,7 +188,7 @@ void cpu_loop(CPUXtensaState *env) env->pc -= 3; break; - case -TARGET_QEMU_ESIGRETURN: + case -QEMU_ESIGRETURN: break; } break; diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c index 81572a5fc7..06d91a37ec 100644 --- a/linux-user/xtensa/signal.c +++ b/linux-user/xtensa/signal.c @@ -263,12 +263,12 @@ long do_rt_sigreturn(CPUXtensaState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) From 5da4063f647348b1a607f39a9ae1adeec39419c9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 15:46:05 +0100 Subject: [PATCH 325/421] linux-user: Create special-errno.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull the two internal errno used by qemu internally into their own header file. This includes the one define required by safe-syscall.S. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/cpu_loop-common.h | 1 + linux-user/generic/target_errno_defs.h | 17 -------------- linux-user/safe-syscall.S | 2 +- linux-user/signal-common.h | 2 ++ linux-user/special-errno.h | 32 ++++++++++++++++++++++++++ linux-user/syscall.c | 1 + 6 files changed, 37 insertions(+), 18 deletions(-) create mode 100644 linux-user/special-errno.h diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h index 8828af28a4..dc0042e4de 100644 --- a/linux-user/cpu_loop-common.h +++ b/linux-user/cpu_loop-common.h @@ -21,6 +21,7 @@ #define CPU_LOOP_COMMON_H #include "exec/log.h" +#include "special-errno.h" #define EXCP_DUMP(env, fmt, ...) \ do { \ diff --git a/linux-user/generic/target_errno_defs.h b/linux-user/generic/target_errno_defs.h index bb37d88be9..c2f9d403e7 100644 --- a/linux-user/generic/target_errno_defs.h +++ b/linux-user/generic/target_errno_defs.h @@ -147,21 +147,4 @@ #define TARGET_ERFKILL 132 /* Operation not possible due to RF-kill */ #define TARGET_EHWPOISON 133 /* Memory page has hardware error */ -/* QEMU internal, not visible to the guest. This is returned when a - * system call should be restarted, to tell the main loop that it - * should wind the guest PC backwards so it will re-execute the syscall - * after handling any pending signals. They match with the ones the guest - * kernel uses for the same purpose. - */ -#define QEMU_ERESTARTSYS 512 /* Restart system call (if SA_RESTART) */ - -/* QEMU internal, not visible to the guest. This is returned by the - * do_sigreturn() code after a successful sigreturn syscall, to indicate - * that it has correctly set the guest registers and so the main loop - * should not touch them. We use the value the guest would use for - * ERESTART_NOINTR (which is kernel internal) to guarantee that we won't - * clash with a valid guest errno now or in the future. - */ -#define QEMU_ESIGRETURN 513 /* Return from signal */ - #endif diff --git a/linux-user/safe-syscall.S b/linux-user/safe-syscall.S index 7ddc997801..74f7e35694 100644 --- a/linux-user/safe-syscall.S +++ b/linux-user/safe-syscall.S @@ -10,7 +10,7 @@ * See the COPYING file in the top-level directory. */ -#include "target_errno_defs.h" +#include "special-errno.h" /* We have the correct host directory on our include path * so that this will pull in the right fragment for the architecture. diff --git a/linux-user/signal-common.h b/linux-user/signal-common.h index b9f33bb44f..42aa479080 100644 --- a/linux-user/signal-common.h +++ b/linux-user/signal-common.h @@ -20,6 +20,8 @@ #ifndef SIGNAL_COMMON_H #define SIGNAL_COMMON_H +#include "special-errno.h" + /* Fallback addresses into sigtramp page. */ extern abi_ulong default_sigreturn; extern abi_ulong default_rt_sigreturn; diff --git a/linux-user/special-errno.h b/linux-user/special-errno.h new file mode 100644 index 0000000000..4120455baa --- /dev/null +++ b/linux-user/special-errno.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU internal errno values for implementing user-only POSIX. + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2021 Linaro, Ltd. + */ + +#ifndef SPECIAL_ERRNO_H +#define SPECIAL_ERRNO_H + +/* + * All of these are QEMU internal, not visible to the guest. + * They should be chosen so as to not overlap with any host + * or guest errno. + */ + +/* + * This is returned when a system call should be restarted, to tell the + * main loop that it should wind the guest PC backwards so it will + * re-execute the syscall after handling any pending signals. + */ +#define QEMU_ERESTARTSYS 512 + +/* + * This is returned after a successful sigreturn syscall, to indicate + * that it has correctly set the guest registers and so the main loop + * should not touch them. + */ +#define QEMU_ESIGRETURN 513 + +#endif /* SPECIAL_ERRNO_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 2867be4cd3..f5bf6d155c 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -136,6 +136,7 @@ #include "qemu/guest-random.h" #include "qemu/selfmap.h" #include "user/syscall-trace.h" +#include "special-errno.h" #include "qapi/error.h" #include "fd-trans.h" #include "tcg/tcg.h" From 2ac16d01e371ba9fb268f04249eaca9fafceb00b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 05:32:17 -0800 Subject: [PATCH 326/421] bsd-user: Create special-errno.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull the internal errno used by qemu internally its own header file, for use by safe-syscall.S. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- bsd-user/errno_defs.h | 6 +++++- bsd-user/special-errno.h | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 bsd-user/special-errno.h diff --git a/bsd-user/errno_defs.h b/bsd-user/errno_defs.h index 141e08456c..73cfa24b7f 100644 --- a/bsd-user/errno_defs.h +++ b/bsd-user/errno_defs.h @@ -151,6 +151,10 @@ /* Internal errors: */ #define TARGET_EJUSTRETURN 254 /* Just return without modifing regs */ #define TARGET_ERESTART 255 /* Restart syscall */ -#define QEMU_ERESTARTSYS TARGET_ERESTART + +#include "special-errno.h" + +_Static_assert(TARGET_ERESTART == QEMU_ERESTARTSYS, + "TARGET_ERESTART and QEMU_ERESTARTSYS expected to match"); #endif /* ! _ERRNO_DEFS_H_ */ diff --git a/bsd-user/special-errno.h b/bsd-user/special-errno.h new file mode 100644 index 0000000000..03599d9b5a --- /dev/null +++ b/bsd-user/special-errno.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * QEMU internal errno values for implementing user-only POSIX. + * + * Copyright (c) 2021 Linaro, Ltd. + */ + +#ifndef SPECIAL_ERRNO_H +#define SPECIAL_ERRNO_H + +/* + * All of these are QEMU internal, not visible to the guest. + * They should be chosen so as to not overlap with any host + * or guest errno. + */ + +/* + * This is returned when a system call should be restarted, to tell the + * main loop that it should wind the guest PC backwards so it will + * re-execute the syscall after handling any pending signals. + */ +#define QEMU_ERESTARTSYS 255 + +#endif /* SPECIAL_ERRNO_H */ From 915f77b2119952fc6d05ab64db4d749e6b5c196e Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 10 Dec 2021 15:43:20 +0800 Subject: [PATCH 327/421] target/riscv: zfh: half-precision load and store Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-id: 20211210074329.5775-2-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 65 +++++++++++++++++++++++ target/riscv/translate.c | 8 +++ 4 files changed, 78 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..570c49f365 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -312,6 +312,7 @@ struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_zfh; char *priv_spec; char *user_spec; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2f251dac1b..b36a3d8dbf 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -726,3 +726,7 @@ binv 0110100 .......... 001 ..... 0110011 @r binvi 01101. ........... 001 ..... 0010011 @sh bset 0010100 .......... 001 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh + +# *** RV32 Zfh Extension *** +flh ............ ..... 001 ..... 0000111 @i +fsh ....... ..... ..... 001 ..... 0100111 @s diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc new file mode 100644 index 0000000000..dad1d703d7 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -0,0 +1,65 @@ +/* + * RISC-V translation routines for the RV64Zfh Standard Extension. + * + * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_ZFH(ctx) do { \ + if (!ctx->ext_zfh) { \ + return false; \ + } \ +} while (0) + +static bool trans_flh(DisasContext *ctx, arg_flh *a) +{ + TCGv_i64 dest; + TCGv t0; + + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + t0 = get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp = temp_new(ctx); + tcg_gen_addi_tl(temp, t0, a->imm); + t0 = temp; + } + + dest = cpu_fpr[a->rd]; + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW); + gen_nanbox_h(dest, dest); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsh(DisasContext *ctx, arg_fsh *a) +{ + TCGv t0; + + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + t0 = get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, t0, a->imm); + t0 = temp; + } + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW); + + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..bea87b31b5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -73,6 +73,7 @@ typedef struct DisasContext { RISCVMXL ol; bool virt_enabled; bool ext_ifencei; + bool ext_zfh; bool hlsx; /* vector extension */ bool vill; @@ -134,6 +135,11 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); +} + /* * A narrow n-bit operation, where n < FLEN, checks that input operands * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. @@ -574,6 +580,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvh.c.inc" #include "insn_trans/trans_rvv.c.inc" #include "insn_trans/trans_rvb.c.inc" +#include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" /* Include the auto-generated decoder for 16 bit insn */ @@ -626,6 +633,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; + ctx->ext_zfh = cpu->cfg.ext_zfh; ctx->vlen = cpu->cfg.vlen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); From 00c1899f123713bb0629d3994fd4be26d64aeb69 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 10 Dec 2021 15:43:21 +0800 Subject: [PATCH 328/421] target/riscv: zfh: half-precision computational Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-3-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 86 +++++++++++++++ target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 11 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 129 ++++++++++++++++++++++ target/riscv/internals.h | 16 +++ 5 files changed, 255 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index d62f470900..20bb89ad14 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,15 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, + uint64_t rs3, int flags) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + float16 frs3 = check_nanbox_h(rs3); + return nanbox_h(float16_muladd(frs1, frs2, frs3, flags, &env->fp_status)); +} + static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { @@ -102,6 +111,12 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status); } +uint64_t helper_fmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, 0); +} + uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { @@ -115,6 +130,12 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, &env->fp_status); } +uint64_t helper_fmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_c); +} + uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { @@ -128,6 +149,12 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, &env->fp_status); } +uint64_t helper_fnmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_product); +} + uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { @@ -142,6 +169,13 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, float_muladd_negate_product, &env->fp_status); } +uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, + float_muladd_negate_c | float_muladd_negate_product); +} + uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float32 frs1 = check_nanbox_s(rs1); @@ -374,3 +408,55 @@ target_ulong helper_fclass_d(uint64_t frs1) { return fclass_d(frs1); } + +uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_add(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fsub_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_sub(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fmul_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_mul(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fdiv_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_div(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? + float16_minnum(frs1, frs2, &env->fp_status) : + float16_minimum_number(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? + float16_maxnum(frs1, frs2, &env->fp_status) : + float16_maximum_number(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return nanbox_h(float16_sqrt(frs1, &env->fp_status)); +} diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c7a5376227..c6c0323faf 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -7,12 +7,16 @@ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) /* Floating Point - Single Precision */ DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -62,6 +66,15 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) +/* Floating Point - Half Precision */ +DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmul_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64) + /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b36a3d8dbf..66c231a301 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -730,3 +730,14 @@ bseti 00101. ........... 001 ..... 0010011 @sh # *** RV32 Zfh Extension *** flh ............ ..... 001 ..... 0000111 @i fsh ....... ..... ..... 001 ..... 0100111 @s +fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm +fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm +fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm +fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm +fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm +fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm +fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm +fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm +fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm +fmin_h 0010110 ..... ..... 000 ..... 1010011 @r +fmax_h 0010110 ..... ..... 001 ..... 1010011 @r diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index dad1d703d7..9764d76f8b 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -63,3 +63,132 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) return true; } + +static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsub_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmadd_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_helper_fmin_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_helper_fmax_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b15ad394bb..bce91da11a 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -58,4 +58,20 @@ static inline float32 check_nanbox_s(uint64_t f) } } +static inline uint64_t nanbox_h(float16 f) +{ + return f | MAKE_64BIT_MASK(16, 48); +} + +static inline float16 check_nanbox_h(uint64_t f) +{ + uint64_t mask = MAKE_64BIT_MASK(16, 48); + + if (likely((f & mask) == mask)) { + return (uint16_t)f; + } else { + return 0x7E00u; /* default qnan */ + } +} + #endif From 7b03c8e5b5a07bc2d357438b4ee92b116afe8914 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 10 Dec 2021 15:43:22 +0800 Subject: [PATCH 329/421] target/riscv: zfh: half-precision convert and move Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-id: 20211210074329.5775-4-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 67 +++++ target/riscv/helper.h | 12 + target/riscv/insn32.decode | 19 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 288 ++++++++++++++++++++++ target/riscv/translate.c | 10 + 5 files changed, 396 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 20bb89ad14..2ed9b03193 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -460,3 +460,70 @@ uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) float16 frs1 = check_nanbox_h(rs1); return nanbox_h(float16_sqrt(frs1, &env->fp_status)); } + +target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_int32(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return (int32_t)float16_to_uint32(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_int64(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_uint64(frs1, &env->fp_status); +} + +uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(int32_to_float16((int32_t)rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_wu(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(uint32_to_float16((uint32_t)rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_l(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(int64_to_float16(rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(uint64_to_float16(rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1) +{ + float32 frs1 = check_nanbox_s(rs1); + return nanbox_h(float32_to_float16(frs1, true, &env->fp_status)); +} + +uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return nanbox_s(float16_to_float32(frs1, true, &env->fp_status)); +} + +uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1) +{ + return nanbox_h(float64_to_float16(rs1, true, &env->fp_status)); +} + +uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_float64(frs1, true, &env->fp_status); +} diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c6c0323faf..b50672d168 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -74,6 +74,18 @@ DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_d_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_h_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_w_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_wu_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_l_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl) /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 66c231a301..ba40f3e7f8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -739,5 +739,24 @@ fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm +fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r +fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r +fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r fmin_h 0010110 ..... ..... 000 ..... 1010011 @r fmax_h 0010110 ..... ..... 001 ..... 1010011 @r +fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm +fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm +fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm +fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm +fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 +fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm +fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm +fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 + +# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** +fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm +fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm +fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 9764d76f8b..d125025766 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -171,6 +171,93 @@ static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a) return true; } +static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + if (a->rs1 == a->rs2) { /* FMOV */ + gen_check_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { + TCGv_i64 rs1 = tcg_temp_new_i64(); + TCGv_i64 rs2 = tcg_temp_new_i64(); + + gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]); + gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]); + + /* This formulation retains the nanboxing of rs2. */ + tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 15); + tcg_temp_free_i64(rs1); + tcg_temp_free_i64(rs2); + } + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a) +{ + TCGv_i64 rs1, rs2, mask; + + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]); + + if (a->rs1 == a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(15, 1)); + } else { + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]); + + /* + * Replace bit 15 in rs1 with inverse in rs2. + * This formulation retains the nanboxing of rs1. + */ + mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1)); + tcg_gen_not_i64(rs2, rs2); + tcg_gen_andc_i64(rs2, rs2, mask); + tcg_gen_and_i64(rs1, mask, rs1); + tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(mask); + tcg_temp_free_i64(rs2); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnjx_h *a) +{ + TCGv_i64 rs1, rs2; + + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + + if (a->rs1 == a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(15, 1)); + } else { + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* + * Xor bit 15 in rs1 with that in rs2. + * This formulation retains the nanboxing of rs1. + */ + tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(15, 1)); + tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(rs2); + } + + mark_fs_dirty(ctx); + return true; +} + static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a) { REQUIRE_FPU; @@ -192,3 +279,204 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) mark_fs_dirty(ctx); return true; } + +static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + return true; +} + +static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + + return true; +} + +static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + return true; +} + +static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + return true; +} + +static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt_wu_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_h_w *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_w(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_wu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + +#if defined(TARGET_RISCV64) + /* 16 bits -> 64 bits */ + tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]); +#else + /* 16 bits -> 32 bits */ + tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); + tcg_gen_ext16s_tl(dest, dest); +#endif + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO); + + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); + gen_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rd]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcvt_l_h *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fcvt_lu_h *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcvt_h_l *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_l(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fcvt_h_lu *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_lu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index bea87b31b5..93f9ec0c8b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -148,6 +148,16 @@ static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) * * Here, the result is always nan-boxed, even the canonical nan. */ +static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) +{ + TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); + TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); + + tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); + tcg_temp_free_i64(t_max); + tcg_temp_free_i64(t_nan); +} + static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) { TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); From 11f9c450a6772c095c5f9c40f5a08c2f8d15a9a1 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 10 Dec 2021 15:43:23 +0800 Subject: [PATCH 330/421] target/riscv: zfh: half-precision floating-point compare Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-5-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 21 +++++++++++++ target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 37 +++++++++++++++++++++++ 4 files changed, 64 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 2ed9b03193..ec2009ee65 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -461,6 +461,27 @@ uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) return nanbox_h(float16_sqrt(frs1, &env->fp_status)); } +target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return float16_le(frs1, frs2, &env->fp_status); +} + +target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return float16_lt(frs1, frs2, &env->fp_status); +} + +target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return float16_eq_quiet(frs1, frs2, &env->fp_status); +} + target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 = check_nanbox_h(rs1); diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b50672d168..9c89521d4a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -74,6 +74,9 @@ DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_3(fle_h, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(flt_h, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(feq_h, TCG_CALL_NO_RWG, tl, env, i64, i64) DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64) DEF_HELPER_FLAGS_2(fcvt_d_h, TCG_CALL_NO_RWG, i64, env, i64) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ba40f3e7f8..3906c9fb20 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -751,6 +751,9 @@ fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 +feq_h 1010010 ..... ..... 010 ..... 1010011 @r +flt_h 1010010 ..... ..... 001 ..... 1010011 @r +fle_h 1010010 ..... ..... 000 ..... 1010011 @r fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index d125025766..8d0959a667 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -335,6 +335,43 @@ static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) return true; } +static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_feq_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_flt_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_fle_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a) { REQUIRE_FPU; From 6bc6fc96d1c9628c4c3514d277e541429e5b0b80 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Fri, 10 Dec 2021 15:43:24 +0800 Subject: [PATCH 331/421] target/riscv: zfh: half-precision floating-point classify Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-6-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 6 ++++++ target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++++++++++++ 4 files changed, 20 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index ec2009ee65..388e23ca67 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -482,6 +482,12 @@ target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) return float16_eq_quiet(frs1, frs2, &env->fp_status); } +target_ulong helper_fclass_h(uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return fclass_h(frs1); +} + target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 = check_nanbox_h(rs1); diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9c89521d4a..d25cf725c5 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -89,6 +89,7 @@ DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_1(fclass_h, TCG_CALL_NO_RWG_SE, tl, i64) /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3906c9fb20..6c4cde216b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -754,6 +754,7 @@ fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 feq_h 1010010 ..... ..... 010 ..... 1010011 @r flt_h 1010010 ..... ..... 001 ..... 1010011 @r fle_h 1010010 ..... ..... 000 ..... 1010011 @r +fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 8d0959a667..0549e25fb4 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -372,6 +372,18 @@ static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a) return true; } +static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_fclass_h(dest, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a) { REQUIRE_FPU; From 13fb8c7b4252872c1b07fac5f0ea9231480c8463 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:43:25 +0800 Subject: [PATCH 332/421] target/riscv: zfh: add Zfh cpu property Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-7-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..0f808a5bee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -629,6 +629,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), From 2d258b428b4f61b71be823fe2a67e7a174078501 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:43:26 +0800 Subject: [PATCH 333/421] target/riscv: zfh: implement zfhmin extension Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h, fcvt.h.d Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-8-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_rvzfh.c.inc | 22 ++++++++++++++-------- target/riscv/translate.c | 2 ++ 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 570c49f365..ef677f9092 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -313,6 +313,7 @@ struct RISCVCPU { bool ext_ifencei; bool ext_icsr; bool ext_zfh; + bool ext_zfhmin; char *priv_spec; char *user_spec; diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 0549e25fb4..5a7cac8958 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -22,13 +22,19 @@ } \ } while (0) +#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ + if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \ + return false; \ + } \ +} while (0) + static bool trans_flh(DisasContext *ctx, arg_flh *a) { TCGv_i64 dest; TCGv t0; REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -50,7 +56,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) TCGv t0; REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { @@ -283,7 +289,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); gen_set_rm(ctx, a->rm); gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); @@ -296,7 +302,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); REQUIRE_EXT(ctx, RVD); gen_set_rm(ctx, a->rm); @@ -311,7 +317,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); gen_set_rm(ctx, a->rm); gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); @@ -324,7 +330,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); REQUIRE_EXT(ctx, RVD); gen_set_rm(ctx, a->rm); @@ -441,7 +447,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); TCGv dest = dest_gpr(ctx, a->rd); @@ -461,7 +467,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZFH_OR_ZFHMIN(ctx); TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 93f9ec0c8b..d445954dc7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -74,6 +74,7 @@ typedef struct DisasContext { bool virt_enabled; bool ext_ifencei; bool ext_zfh; + bool ext_zfhmin; bool hlsx; /* vector extension */ bool vill; @@ -644,6 +645,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->ext_zfh = cpu->cfg.ext_zfh; + ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; ctx->vlen = cpu->cfg.vlen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); From e523773040ed914b60c8b68c25a96c88b2bb112a Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:43:27 +0800 Subject: [PATCH 334/421] target/riscv: zfh: add Zfhmin cpu property Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20211210074329.5775-9-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f808a5bee..9835829588 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,6 +630,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), From 9ec6622db30df1c00d863c1ffc33341f9e0a534d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:47 +0800 Subject: [PATCH 335/421] target/riscv: drop vector 0.7.1 and add 1.0 support Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20211210075704.23951-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++-------- target/riscv/cpu.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9835829588..728092f78c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -523,7 +523,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) ext |= RVH; } if (cpu->cfg.ext_v) { - int vext_version = VEXT_VERSION_0_07_1; + int vext_version = VEXT_VERSION_1_00_0; ext |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, @@ -548,8 +548,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version = VEXT_VERSION_0_07_1; + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; } else { error_setg(errp, "Unsupported vector spec version '%s'", @@ -558,7 +558,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } else { qemu_log("vector version is not specified, " - "use the default value v0.7.1\n"); + "use the default value v1.0\n"); } set_vext_version(env, vext_version); } @@ -626,6 +626,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -635,6 +636,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), @@ -643,10 +647,6 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), - DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef677f9092..5ea2004ae0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,7 +81,7 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 -#define VEXT_VERSION_0_07_1 0x00000701 +#define VEXT_VERSION_1_00_0 0x00010000 enum { TRANSLATE_SUCCESS, From 52561f2a808a16bde80c9a165f54e07df2e527a7 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:48 +0800 Subject: [PATCH 336/421] target/riscv: Use FIELD_EX32() to extract wd field Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..70f589813e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc) static uint32_t vext_wd(uint32_t desc) { - return (simd_data(desc) >> 11) & 0x1; + return FIELD_EX32(simd_data(desc), VDATA, WD); } /* From 61b4b69d122c055fbf6310e629f3f2d1e70c2599 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 10 Dec 2021 15:55:49 +0800 Subject: [PATCH 337/421] target/riscv: rvv-1.0: add mstatus VS field Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 20 +++++++++++++++++++- target/riscv/csr.c | 12 +++++++++++- 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5ea2004ae0..48b8f61210 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -352,6 +352,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); @@ -395,6 +396,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77..72a716c999 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -375,6 +375,7 @@ #define MSTATUS_UBE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..8803fe0b14 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -90,12 +90,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY flags |= TB_FLAGS_MSTATUS_FS; + flags |= TB_FLAGS_MSTATUS_VS; #else flags |= cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { flags |= env->mstatus & MSTATUS_FS; } + if (riscv_cpu_vector_enabled(env)) { + flags |= env->mstatus & MSTATUS_VS; + } + if (riscv_has_ext(env, RVH)) { if (env->priv == PRV_M || (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || @@ -189,11 +194,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { + return false; + } + return true; + } + + return false; +} + void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL; + MSTATUS64_UXL | MSTATUS_VS; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..9b5bd5d7b4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -273,6 +273,7 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, { #if !defined(CONFIG_USER_ONLY) env->mstatus |= MSTATUS_FS; + env->mstatus |= MSTATUS_VS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; if (vs(env, csrno) >= 0) { @@ -307,6 +308,9 @@ static RISCVException read_vxrm(CPURISCVState *env, int csrno, static RISCVException write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vxrm = val; return RISCV_EXCP_NONE; } @@ -321,6 +325,9 @@ static RISCVException read_vxsat(CPURISCVState *env, int csrno, static RISCVException write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vxsat = val; return RISCV_EXCP_NONE; } @@ -335,6 +342,9 @@ static RISCVException read_vstart(CPURISCVState *env, int csrno, static RISCVException write_vstart(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vstart = val; return RISCV_EXCP_NONE; } @@ -535,7 +545,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS_VS; if (riscv_cpu_mxl(env) != MXL_RV32) { /* From c36b2f1a4d036dc105018c1af3f127a4d3333789 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:50 +0800 Subject: [PATCH 338/421] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9b5bd5d7b4..bb500afdeb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -502,6 +502,7 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno, static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) { if ((status & MSTATUS_FS) == MSTATUS_FS || + (status & MSTATUS_VS) == MSTATUS_VS || (status & MSTATUS_XS) == MSTATUS_XS) { switch (xl) { case MXL_RV32: From 89a81e376a53c17b554d213302e678027c3ad60e Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 10 Dec 2021 15:55:51 +0800 Subject: [PATCH 339/421] target/riscv: rvv-1.0: add sstatus VS field Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 72a716c999..bb62da7549 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -409,6 +409,7 @@ typedef enum { #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bb500afdeb..83f4dbd824 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -463,7 +463,7 @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; From 7b07a37c2caad9252c6c5eec11ab9776826328ff Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:52 +0800 Subject: [PATCH 340/421] target/riscv: rvv-1.0: introduce writable misa.v field Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-7-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 83f4dbd824..bc149add6c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -643,7 +643,7 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ if ((val & RVD) && !(val & RVF)) { From 8e1ee1fb571cbfa7d6897560fed3cd9f367058a1 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:53 +0800 Subject: [PATCH 341/421] target/riscv: rvv-1.0: add translation-time vector context status Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-8-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +- target/riscv/cpu_helper.c | 3 + target/riscv/insn_trans/trans_rvv.c.inc | 75 +++++++++++++++++++++---- target/riscv/translate.c | 40 +++++++++++++ 4 files changed, 109 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 48b8f61210..eee2a2b19e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -410,10 +410,11 @@ FIELD(TB_FLAGS, VILL, 9, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 10, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) +FIELD(TB_FLAGS, MSTATUS_HS_VS, 13, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 13, 2) +FIELD(TB_FLAGS, XL, 15, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_ENABLED, 17, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8803fe0b14..1b31d0ad47 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -111,6 +111,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, get_field(env->mstatus_hs, MSTATUS_FS)); + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, + get_field(env->mstatus_hs, MSTATUS_VS)); } if (riscv_has_ext(env, RVJ)) { int priv = flags & TB_FLAGS_PRIV_MMU_MASK; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 17ee3babef..bc1d4a5f23 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -39,6 +39,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) } gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(ctx, a->rd, dst); + mark_vs_dirty(ctx); tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); @@ -66,6 +67,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) } gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(ctx, a->rd, dst); + mark_vs_dirty(ctx); gen_goto_tb(ctx, 0, ctx->pc_succ_insn); ctx->base.is_jmp = DISAS_NORETURN; @@ -154,7 +156,8 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, TCGv_env, TCGv_i32); static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s) + gen_helper_ldst_us *fn, DisasContext *s, + bool is_store) { TCGv_ptr dest, mask; TCGv base; @@ -183,6 +186,11 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } @@ -233,7 +241,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) @@ -286,7 +294,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } static bool st_us_check(DisasContext *s, arg_r2nfvm* a) @@ -309,7 +317,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask; TCGv base, stride; @@ -331,6 +339,11 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } @@ -365,7 +378,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) @@ -409,7 +422,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return false; } - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } static bool st_stride_check(DisasContext *s, arg_rnfvm* a) @@ -432,7 +445,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t data, gen_helper_ldst_index *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask, index; TCGv base; @@ -456,6 +469,11 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } @@ -490,7 +508,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } /* @@ -542,7 +560,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } static bool st_index_check(DisasContext *s, arg_rnfvm* a) @@ -583,6 +601,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -659,6 +678,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -810,6 +830,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -861,6 +882,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -892,6 +914,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, src1, MAXSZ(s), MAXSZ(s)); tcg_temp_free_i64(src1); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1003,6 +1026,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1026,10 +1050,10 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); } - } else { - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + mark_vs_dirty(s); + return true; } - return true; + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); } /* OPIVI with GVEC IR */ @@ -1089,6 +1113,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1176,6 +1201,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1255,6 +1281,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1383,6 +1410,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, src1, MAXSZ(s), MAXSZ(s)); tcg_temp_free_i32(src1); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1442,6 +1470,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1626,6 +1655,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) fns[s->sew]); gen_set_label(over); } + mark_vs_dirty(s); return true; } return false; @@ -1665,6 +1695,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) tcg_temp_free_i64(s1_i64); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1680,6 +1711,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); + mark_vs_dirty(s); } else { TCGv_i32 desc; TCGv_i64 s1; @@ -1699,6 +1731,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) fns[s->sew](dest, s1, cpu_env, desc); tcg_temp_free_ptr(dest); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -1804,6 +1837,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1838,6 +1872,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1916,6 +1951,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1991,6 +2027,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2106,6 +2143,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2178,6 +2216,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); + mark_vs_dirty(s); } else { TCGv_ptr dest; TCGv_i32 desc; @@ -2196,6 +2235,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); tcg_temp_free_ptr(dest); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -2246,6 +2286,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2295,6 +2336,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2357,6 +2399,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2451,6 +2494,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, s->vlen / 8, s->vlen / 8, \ data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2482,6 +2526,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2508,6 +2553,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2681,6 +2727,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); done: gen_set_label(over); return true; @@ -2731,6 +2778,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) } vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2797,6 +2845,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), dest); tcg_temp_free_i64(dest); + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] = { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2823,6 +2872,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) endian_ofs(s, a->rs2, a->rs1), MAXSZ(s), MAXSZ(s)); } + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] = { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2860,6 +2910,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d445954dc7..8051090d2f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -62,7 +62,9 @@ typedef struct DisasContext { uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; + uint32_t mstatus_vs; uint32_t mstatus_hs_fs; + uint32_t mstatus_hs_vs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -348,6 +350,42 @@ static void mark_fs_dirty(DisasContext *ctx) static inline void mark_fs_dirty(DisasContext *ctx) { } #endif +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_vs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_vs_dirty(DisasContext *ctx) +{ + TCGv tmp; + + if (ctx->mstatus_vs != MSTATUS_VS) { + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_vs = MSTATUS_VS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); + } + + if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { + /* Remember the stage change for the rest of the TB. */ + ctx->mstatus_hs_vs = MSTATUS_VS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_temp_free(tmp); + } +} +#else +static inline void mark_vs_dirty(DisasContext *ctx) { } +#endif + static void gen_set_rm(DisasContext *ctx, int rm) { if (ctx->frm == rm) { @@ -631,6 +669,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver = env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { @@ -648,6 +687,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; ctx->vlen = cpu->cfg.vlen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); + ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); From 9bd291f6e3f8cccca73b58039744f926eb4ac457 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:54 +0800 Subject: [PATCH 342/421] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers * Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. * Remove RVV loose check in fs() predicate function. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-9-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bc149add6c..c522260986 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -38,10 +38,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - /* loose check condition for fcsr in vector extension */ - if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { - return RISCV_EXCP_NONE; - } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -261,10 +257,6 @@ static RISCVException read_fcsr(CPURISCVState *env, int csrno, { *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); - if (vs(env, csrno) >= 0) { - *val |= (env->vxrm << FSR_VXRM_SHIFT) - | (env->vxsat << FSR_VXSAT_SHIFT); - } return RISCV_EXCP_NONE; } @@ -273,13 +265,8 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, { #if !defined(CONFIG_USER_ONLY) env->mstatus |= MSTATUS_FS; - env->mstatus |= MSTATUS_VS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; - if (vs(env, csrno) >= 0) { - env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; - env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; - } riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); return RISCV_EXCP_NONE; } From 4594fa5a96d07a5087df4437aed68dbe0136ca08 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 10 Dec 2021 15:55:55 +0800 Subject: [PATCH 343/421] target/riscv: rvv-1.0: add vcsr register Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-10-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 7 +++++++ target/riscv/csr.c | 17 +++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bb62da7549..8dc6aa62c6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -60,9 +60,16 @@ #define CSR_VSTART 0x008 #define CSR_VXSAT 0x009 #define CSR_VXRM 0x00a +#define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +/* VCSR fields */ +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) + /* User Timers and Counters */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c522260986..832ccdcf33 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -336,6 +336,22 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); + return RISCV_EXCP_NONE; +} + +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif + env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; + env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; + return RISCV_EXCP_NONE; +} + /* User Timers and Counters */ static RISCVException read_instret(CPURISCVState *env, int csrno, target_ulong *val) @@ -1816,6 +1832,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, [CSR_VL] = { "vl", vs, read_vl }, [CSR_VTYPE] = { "vtype", vs, read_vtype }, /* User Timers and Counters */ From 2e56505475cba574ff041cd9d57d417c7d705d24 Mon Sep 17 00:00:00 2001 From: Greentime Hu Date: Fri, 10 Dec 2021 15:55:56 +0800 Subject: [PATCH 344/421] target/riscv: rvv-1.0: add vlenb register Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-11-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8dc6aa62c6..1e31f4d35f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -63,6 +63,7 @@ #define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 /* VCSR fields */ #define VCSR_VXSAT_SHIFT 0 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 832ccdcf33..5d1eec1ea0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -285,6 +285,12 @@ static RISCVException read_vl(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env_archcpu(env)->cfg.vlen >> 3; + return RISCV_EXCP_NONE; +} + static RISCVException read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1835,6 +1841,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, [CSR_VL] = { "vl", vs, read_vl }, [CSR_VTYPE] = { "vtype", vs, read_vtype }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_instret }, [CSR_INSTRET] = { "instret", ctr, read_instret }, From 6bc3dfa96de4173b12929824eaf80fc95d22ac28 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:57 +0800 Subject: [PATCH 345/421] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-12-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5d1eec1ea0..3dfbc17738 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -48,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { if (env->misa_ext & RVV) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } +#endif return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; From f9298de51432148163d8ed9c2b15bc0096546c07 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:58 +0800 Subject: [PATCH 346/421] target/riscv: rvv-1.0: remove MLEN calculations As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-13-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 35 +--- target/riscv/internals.h | 9 +- target/riscv/translate.c | 2 - target/riscv/vector_helper.c | 252 ++++++++++-------------- 4 files changed, 111 insertions(+), 187 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bc1d4a5f23..ecd4b89c6b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -237,7 +237,6 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -290,7 +289,6 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -374,7 +372,6 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -413,7 +410,6 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) gen_helper_vsse_v_w, gen_helper_vsse_v_d } }; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -504,7 +500,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -556,7 +551,6 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -632,7 +626,6 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); @@ -740,7 +733,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) g_assert_not_reached(); } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, WD, a->wd); @@ -823,7 +815,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, } else { uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -868,7 +859,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, src2 = tcg_temp_new_ptr(); src1 = get_gpr(s, rs1, EXT_NONE); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); @@ -1012,7 +1002,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, } else { src1 = tcg_constant_tl(sextract64(imm, 0, 5)); } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); @@ -1105,7 +1094,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -1194,7 +1182,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -1273,7 +1260,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1462,7 +1448,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1829,7 +1814,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1902,7 +1886,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_d, \ }; \ gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -1943,7 +1926,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1982,7 +1964,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2019,7 +2000,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2056,7 +2036,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2136,7 +2115,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2279,7 +2257,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2329,7 +2306,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_set_rm(s, 7); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -2393,7 +2369,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ @@ -2423,7 +2398,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) TCGv dst; TCGv_i32 desc; uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -2453,7 +2427,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) TCGv dst; TCGv_i32 desc; uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -2487,7 +2460,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ @@ -2516,7 +2488,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_3_ptr * const fns[4] = { @@ -2543,7 +2514,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_2_ptr * const fns[4] = { @@ -2833,7 +2803,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) } if (a->vm && s->vl_eq_vlmax) { - int vlmax = s->vlen / s->mlen; + int vlmax = s->vlen; TCGv_i64 dest = tcg_temp_new_i64(); if (a->rs1 == 0) { @@ -2864,7 +2834,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) } if (a->vm && s->vl_eq_vlmax) { - if (a->rs1 >= s->vlen / s->mlen) { + if (a->rs1 >= s->vlen) { tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); } else { @@ -2904,7 +2874,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), diff --git a/target/riscv/internals.h b/target/riscv/internals.h index bce91da11a..81f5dfa477 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -22,11 +22,10 @@ #include "hw/registerfields.h" /* share data between vector helpers and decode code */ -FIELD(VDATA, MLEN, 0, 8) -FIELD(VDATA, VM, 8, 1) -FIELD(VDATA, LMUL, 9, 2) -FIELD(VDATA, NF, 11, 4) -FIELD(VDATA, WD, 11, 1) +FIELD(VDATA, VM, 0, 1) +FIELD(VDATA, LMUL, 1, 3) +FIELD(VDATA, NF, 4, 4) +FIELD(VDATA, WD, 4, 1) /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8051090d2f..17101d854b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -83,7 +83,6 @@ typedef struct DisasContext { uint8_t lmul; uint8_t sew; uint16_t vlen; - uint16_t mlen; bool vl_eq_vlmax; uint8_t ntemp; CPUState *cs; @@ -692,7 +691,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); - ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 70f589813e..ac6c7298bc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -81,11 +81,6 @@ static inline uint32_t vext_nf(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, NF); } -static inline uint32_t vext_mlen(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, MLEN); -} - static inline uint32_t vext_vm(uint32_t desc) { return FIELD_EX32(simd_data(desc), VDATA, VM); @@ -188,19 +183,24 @@ static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) vext_clear(cur, cnt, tot); } -static inline void vext_set_elem_mask(void *v0, int mlen, int index, - uint8_t value) +static inline void vext_set_elem_mask(void *v0, int index, + uint8_t value) { - int idx = (index * mlen) / 64; - int pos = (index * mlen) % 64; + int idx = index / 64; + int pos = index % 64; uint64_t old = ((uint64_t *)v0)[idx]; - ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value); + ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value); } -static inline int vext_elem_mask(void *v0, int mlen, int index) +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) { - int idx = (index * mlen) / 64; - int pos = (index * mlen) % 64; + int idx = index / 64; + int pos = index % 64; return (((uint64_t *)v0)[idx] >> pos) & 1; } @@ -277,12 +277,11 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t mlen = vext_mlen(desc); uint32_t vlmax = vext_maxsz(desc) / esz; /* probe every access*/ for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } probe_pages(env, base + stride * i, nf * msz, ra, access_type); @@ -290,7 +289,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, /* do real access */ for (i = 0; i < env->vl; i++) { k = 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { @@ -506,12 +505,11 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t mlen = vext_mlen(desc); uint32_t vlmax = vext_maxsz(desc) / esz; /* probe every access*/ for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, @@ -520,7 +518,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, /* load bytes from guest memory */ for (i = 0; i < env->vl; i++) { k = 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { @@ -604,7 +602,6 @@ vext_ldff(void *vd, void *v0, target_ulong base, { void *host; uint32_t i, k, vl = 0; - uint32_t mlen = vext_mlen(desc); uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); uint32_t vlmax = vext_maxsz(desc) / esz; @@ -612,7 +609,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, /* probe every access*/ for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } addr = base + nf * i * msz; @@ -653,7 +650,7 @@ ProbeSuccess: } for (i = 0; i < env->vl; i++) { k = 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { @@ -782,18 +779,17 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base, target_long addr; uint32_t wd = vext_wd(desc); uint32_t vm = vext_vm(desc); - uint32_t mlen = vext_mlen(desc); uint32_t vlmax = vext_maxsz(desc) / esz; for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD); probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE); } for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } addr = get_index_addr(base, i, vs2); @@ -907,13 +903,12 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, opivv2_fn *fn, clear_fn *clearfn) { uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; for (i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i); @@ -972,13 +967,12 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, opivx2_fn fn, clear_fn *clearfn) { uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; for (i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i); @@ -1168,7 +1162,6 @@ GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ uint32_t vlmax = vext_maxsz(desc) / esz; \ @@ -1177,7 +1170,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ + uint8_t carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ } \ @@ -1198,7 +1191,6 @@ GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ uint32_t vlmax = vext_maxsz(desc) / esz; \ @@ -1206,7 +1198,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ + uint8_t carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ } \ @@ -1231,7 +1223,6 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ @@ -1239,12 +1230,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ + uint8_t carry = vext_elem_mask(v0, i); \ \ - vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\ + vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -1262,20 +1253,19 @@ GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ + uint8_t carry = vext_elem_mask(v0, i); \ \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -1349,7 +1339,6 @@ GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(TS1); \ @@ -1357,7 +1346,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ TS1 s1 = *((TS1 *)vs1 + HS1(i)); \ @@ -1387,7 +1376,6 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(TD); \ @@ -1395,7 +1383,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ @@ -1444,7 +1432,6 @@ GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ @@ -1453,13 +1440,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \ + vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -1497,7 +1484,6 @@ GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ @@ -1505,14 +1491,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -2074,14 +2060,13 @@ GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \ + ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) = *(vt + H(i)); \ } \ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ @@ -2096,7 +2081,6 @@ GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ uint32_t vlmax = vext_maxsz(desc) / esz; \ @@ -2104,7 +2088,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \ + ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \ (ETYPE)(target_long)s1); \ *((ETYPE *)vd + H(i)) = d; \ } \ @@ -2142,11 +2126,11 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \ static inline void vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm, + uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn) { for (uint32_t i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i, env, vxrm); @@ -2160,26 +2144,25 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, opivv2_rm_fn *fn, clear_fn *clearfn) { uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 0, fn); + env, vl, vm, 0, fn); break; case 1: /* rne */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 1, fn); + env, vl, vm, 1, fn); break; case 2: /* rdn */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 2, fn); + env, vl, vm, 2, fn); break; default: /* rod */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 3, fn); + env, vl, vm, 3, fn); break; } @@ -2262,11 +2245,11 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \ static inline void vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm, + uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn) { for (uint32_t i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i, env, vxrm); @@ -2280,26 +2263,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2, opivx2_rm_fn *fn, clear_fn *clearfn) { uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 0, fn); + env, vl, vm, 0, fn); break; case 1: /* rne */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 1, fn); + env, vl, vm, 1, fn); break; case 2: /* rdn */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 2, fn); + env, vl, vm, 2, fn); break; default: /* rod */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 3, fn); + env, vl, vm, 3, fn); break; } @@ -3184,13 +3166,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t desc) \ { \ uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ @@ -3219,13 +3200,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ uint32_t desc) \ { \ uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ @@ -3790,7 +3770,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -3799,7 +3778,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ return; \ } \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ @@ -3931,7 +3910,6 @@ GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ @@ -3940,14 +3918,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, s1, &env->fp_status)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -3959,7 +3937,6 @@ GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ @@ -3967,14 +3944,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -4088,13 +4065,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i); \ @@ -4171,7 +4147,6 @@ GEN_VEXT_V(vfclass_v_d, 8, 8, clearq) void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ @@ -4181,7 +4156,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ *((ETYPE *)vd + H(i)) \ - = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \ + = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } @@ -4312,7 +4287,6 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -4321,7 +4295,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ \ for (i = 0; i < vl; i++) { \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ s1 = OP(s1, (TD)s2); \ @@ -4395,7 +4369,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -4404,7 +4377,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ \ for (i = 0; i < vl; i++) { \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ s1 = OP(s1, (TD)s2, &env->fp_status); \ @@ -4433,7 +4406,6 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq) void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; @@ -4442,7 +4414,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, for (i = 0; i < vl; i++) { uint16_t s2 = *((uint16_t *)vs2 + H2(i)); - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status), @@ -4455,7 +4427,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; @@ -4464,7 +4435,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, for (i = 0; i < vl; i++) { uint32_t s2 = *((uint32_t *)vs2 + H4(i)); - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status), @@ -4483,19 +4454,18 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vl = env->vl; \ uint32_t i; \ int a, b; \ \ for (i = 0; i < vl; i++) { \ - a = vext_elem_mask(vs1, mlen, i); \ - b = vext_elem_mask(vs2, mlen, i); \ - vext_set_elem_mask(vd, mlen, i, OP(b, a)); \ + a = vext_elem_mask(vs1, i); \ + b = vext_elem_mask(vs2, i); \ + vext_set_elem_mask(vd, i, OP(b, a)); \ } \ for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, 0); \ } \ } @@ -4519,14 +4489,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t desc) { target_ulong cnt = 0; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; for (i = 0; i < vl; i++) { - if (vm || vext_elem_mask(v0, mlen, i)) { - if (vext_elem_mask(vs2, mlen, i)) { + if (vm || vext_elem_mask(v0, i)) { + if (vext_elem_mask(vs2, i)) { cnt++; } } @@ -4538,14 +4507,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; for (i = 0; i < vl; i++) { - if (vm || vext_elem_mask(v0, mlen, i)) { - if (vext_elem_mask(vs2, mlen, i)) { + if (vm || vext_elem_mask(v0, i)) { + if (vext_elem_mask(vs2, i)) { return i; } } @@ -4562,39 +4530,38 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t mlen = vext_mlen(desc); - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; + uint32_t vlmax = env_archcpu(env)->cfg.vlen; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; bool first_mask_bit = false; for (i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } /* write a zero to all following active elements */ if (first_mask_bit) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); continue; } - if (vext_elem_mask(vs2, mlen, i)) { + if (vext_elem_mask(vs2, i)) { first_mask_bit = true; if (type == BEFORE_FIRST) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } else { - vext_set_elem_mask(vd, mlen, i, 1); + vext_set_elem_mask(vd, i, 1); } } else { if (type == ONLY_FIRST) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } else { - vext_set_elem_mask(vd, mlen, i, 1); + vext_set_elem_mask(vd, i, 1); } } } for (; i < vlmax; i++) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } } @@ -4621,19 +4588,18 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t sum = 0; \ int i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = sum; \ - if (vext_elem_mask(vs2, mlen, i)) { \ + if (vext_elem_mask(vs2, i)) { \ sum++; \ } \ } \ @@ -4649,14 +4615,13 @@ GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq) #define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ int i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = i; \ @@ -4678,14 +4643,13 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ target_ulong offset = s1, i; \ \ for (i = offset; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \ @@ -4703,15 +4667,14 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ target_ulong offset = s1, i; \ \ for (i = 0; i < vl; ++i) { \ target_ulong j = i + offset; \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \ @@ -4729,14 +4692,13 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (i == 0) { \ @@ -4758,14 +4720,13 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (i == vl - 1) { \ @@ -4788,15 +4749,14 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ index = *((ETYPE *)vs1 + H(i)); \ @@ -4819,15 +4779,14 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index = s1; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (index >= vlmax) { \ @@ -4850,13 +4809,12 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vl = env->vl; \ uint32_t num = 0, i; \ \ for (i = 0; i < vl; i++) { \ - if (!vext_elem_mask(vs1, mlen, i)) { \ + if (!vext_elem_mask(vs1, i)) { \ continue; \ } \ *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ From 33f1beaf12ebb835cd11a8be0bad229b2af166e2 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:55:59 +0800 Subject: [PATCH 347/421] target/riscv: rvv-1.0: add fractional LMUL Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600) and MSTATUS_FS (0x6000) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-14-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 26 ++++++++++++++------------ target/riscv/translate.c | 16 ++++++++++++++-- target/riscv/vector_helper.c | 16 ++++++++++++++-- 3 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eee2a2b19e..17414bfff7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -102,10 +102,10 @@ typedef struct CPURISCVState CPURISCVState; #define RV_VLEN_MAX 256 -FIELD(VTYPE, VLMUL, 0, 2) -FIELD(VTYPE, VSEW, 2, 3) -FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, VLMUL, 0, 3) +FIELD(VTYPE, VSEW, 3, 3) +FIELD(VTYPE, VEDIV, 8, 2) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { @@ -403,18 +403,20 @@ typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) -FIELD(TB_FLAGS, LMUL, 4, 2) +FIELD(TB_FLAGS, LMUL, 3, 3) FIELD(TB_FLAGS, SEW, 6, 3) -FIELD(TB_FLAGS, VILL, 9, 1) +/* Skip MSTATUS_VS (0x600) bits */ +FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) +FIELD(TB_FLAGS, VILL, 12, 1) +/* Skip MSTATUS_FS (0x6000) bits */ /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 10, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) -FIELD(TB_FLAGS, MSTATUS_HS_VS, 13, 2) +FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) +FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 15, 2) +FIELD(TB_FLAGS, XL, 20, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 17, 1) +FIELD(TB_FLAGS, PM_ENABLED, 22, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 17101d854b..3688e80d03 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -80,7 +80,19 @@ typedef struct DisasContext { bool hlsx; /* vector extension */ bool vill; - uint8_t lmul; + /* + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ + int8_t lmul; uint8_t sew; uint16_t vlen; bool vl_eq_vlmax; @@ -690,7 +702,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); - ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); + ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ac6c7298bc..866bfb3571 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VM); } -static inline uint32_t vext_lmul(uint32_t desc) +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) { - return FIELD_EX32(simd_data(desc), VDATA, LMUL); + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); } static uint32_t vext_wd(uint32_t desc) From 3479a814e4e61509dc48e7012b41ef4528ae42c5 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:00 +0800 Subject: [PATCH 348/421] target/riscv: rvv-1.0: add VMA and VTA Introduce vma and vta fields in vtype register. According to RVV 1.0 spec (section 3.3.3): When a set is marked agnostic, the corresponding set of destination elements in any vector or mask destination operand can either retain the value they previously held, or are overwritten with 1s. So, either vta/vma is set to undisturbed or agnostic, it's legal to retain the inactive masked-off elements and tail elements' original values unchanged. Therefore, besides declaring vta/vma fields in vtype register, also remove all the tail elements clean functions in this commit. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-15-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv/vector_helper.c | 1915 ++++++++++++++++------------------ 2 files changed, 885 insertions(+), 1032 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 17414bfff7..709b7c3abb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -104,6 +104,8 @@ typedef struct CPURISCVState CPURISCVState; FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) +FIELD(VTYPE, VTA, 6, 1) +FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 866bfb3571..db1a40a3db 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -146,55 +146,6 @@ static void probe_pages(CPURISCVState *env, target_ulong addr, } } -#ifdef HOST_WORDS_BIGENDIAN -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) -{ - /* - * Split the remaining range to two parts. - * The first part is in the last uint64_t unit. - * The second part start from the next uint64_t unit. - */ - int part1 = 0, part2 = tot - cnt; - if (cnt % 8) { - part1 = 8 - (cnt % 8); - part2 = tot - cnt - part1; - memset(QEMU_ALIGN_PTR_DOWN(tail, 8), 0, part1); - memset(QEMU_ALIGN_PTR_UP(tail, 8), 0, part2); - } else { - memset(tail, 0, part2); - } -} -#else -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) -{ - memset(tail, 0, tot - cnt); -} -#endif - -static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int8_t *cur = ((int8_t *)vd + H1(idx)); - vext_clear(cur, cnt, tot); -} - -static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int16_t *cur = ((int16_t *)vd + H2(idx)); - vext_clear(cur, cnt, tot); -} - -static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int32_t *cur = ((int32_t *)vd + H4(idx)); - vext_clear(cur, cnt, tot); -} - -static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int64_t *cur = (int64_t *)vd + idx; - vext_clear(cur, cnt, tot); -} - static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { @@ -219,7 +170,6 @@ static inline int vext_elem_mask(void *v0, int index) /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); -typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot); #define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ @@ -283,7 +233,7 @@ static void vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, - vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t msz, uintptr_t ra, MMUAccessType access_type) { @@ -310,47 +260,41 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, k++; } } - /* clear tail elements */ - if (clear_elem) { - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } - } } -#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN) \ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + sizeof(ETYPE), sizeof(MTYPE), \ GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq) +GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b) +GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h) +GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w) +GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d) +GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h) +GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w) +GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d) +GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w) +GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d) +GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b) +GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h) +GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w) +GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d) +GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b) +GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h) +GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w) +GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d) +GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h) +GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w) +GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d) +GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w) +GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d) #define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ @@ -359,7 +303,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ - NULL, sizeof(ETYPE), sizeof(MTYPE), \ + sizeof(ETYPE), sizeof(MTYPE), \ GETPC(), MMU_DATA_STORE); \ } @@ -384,9 +328,8 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) /* unmasked unit-stride load and store operation*/ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t msz, + uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); @@ -403,12 +346,6 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, k++; } } - /* clear tail elements */ - if (clear_elem) { - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } - } } /* @@ -416,45 +353,45 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, * stride = NF * sizeof (MTYPE) */ -#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + sizeof(ETYPE), sizeof(MTYPE), \ GETPC(), MMU_DATA_LOAD); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \ + vext_ldst_us(vd, base, env, desc, LOAD_FN, \ sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq) +GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b) +GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h) +GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w) +GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d) +GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h) +GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w) +GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d) +GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w) +GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d) +GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b) +GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h) +GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w) +GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d) +GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b) +GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h) +GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w) +GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d) +GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h) +GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w) +GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d) +GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w) +GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d) #define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ @@ -462,14 +399,14 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ { \ uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - NULL, sizeof(ETYPE), sizeof(MTYPE), \ + sizeof(ETYPE), sizeof(MTYPE), \ GETPC(), MMU_DATA_STORE); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \ + vext_ldst_us(vd, base, env, desc, STORE_FN, \ sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\ } @@ -510,7 +447,6 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_ldst_elem_fn *ldst_elem, - clear_fn *clear_elem, uint32_t esz, uint32_t msz, uintptr_t ra, MMUAccessType access_type) { @@ -539,52 +475,46 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, k++; } } - /* clear tail elements */ - if (clear_elem) { - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } - } } -#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \ GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb) -GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh) -GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl) -GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq) -GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh) -GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl) -GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq) -GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl) -GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq) -GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb) -GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh) -GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl) -GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq) -GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb) -GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh) -GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl) -GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq) -GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh) -GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl) -GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq) -GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl) -GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq) +GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b) +GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h) +GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w) +GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d) +GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h) +GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w) +GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d) +GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w) +GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d) +GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b) +GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h) +GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w) +GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d) +GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b) +GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h) +GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w) +GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d) +GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h) +GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w) +GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d) +GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w) +GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d) #define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\ + STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \ GETPC(), MMU_DATA_STORE); \ } @@ -609,7 +539,6 @@ static inline void vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc, vext_ldst_elem_fn *ldst_elem, - clear_fn *clear_elem, uint32_t esz, uint32_t msz, uintptr_t ra) { void *host; @@ -671,45 +600,38 @@ ProbeSuccess: k++; } } - /* clear tail elements */ - if (vl != 0) { - return; - } - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } } -#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \ + vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ } -GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq) +GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b) +GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h) +GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w) +GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d) +GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h) +GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w) +GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d) +GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w) +GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d) +GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b) +GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h) +GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w) +GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d) +GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b) +GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h) +GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w) +GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d) +GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h) +GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w) +GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d) +GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w) +GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d) /* *** Vector AMO Operations (Zvamo) @@ -784,14 +706,12 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_amo_noatomic_fn *noatomic_op, - clear_fn *clear_elem, uint32_t esz, uint32_t msz, uintptr_t ra) { uint32_t i; target_long addr; uint32_t wd = vext_wd(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; for (i = 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { @@ -807,46 +727,45 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base, addr = get_index_addr(base, i, vs2); noatomic_op(vs3, addr, wd, i, env, ra); } - clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); } -#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \ +#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN) \ void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \ INDEX_FN, vext_##NAME##_noatomic_op, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ + sizeof(ETYPE), sizeof(MTYPE), \ GETPC()); \ } -GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl) -GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) +GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d) +GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d) +GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d) +GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d) +GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d) +GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d) +GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w) +GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w) +GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w) /* *** Vector Integer Arithmetic Instructions @@ -912,9 +831,8 @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivv2_fn *fn, clear_fn *clearfn) + opivv2_fn *fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; @@ -925,27 +843,26 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, } fn(vd, vs1, vs2, i); } - clearfn(vd, vl, vl * dsz, vlmax * dsz); } /* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VV(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } -GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vadd_vv_b, 1, 1) +GEN_VEXT_VV(vadd_vv_h, 2, 2) +GEN_VEXT_VV(vadd_vv_w, 4, 4) +GEN_VEXT_VV(vadd_vv_d, 8, 8) +GEN_VEXT_VV(vsub_vv_b, 1, 1) +GEN_VEXT_VV(vsub_vv_h, 2, 2) +GEN_VEXT_VV(vsub_vv_w, 4, 4) +GEN_VEXT_VV(vsub_vv_d, 8, 8) typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); @@ -976,9 +893,8 @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivx2_fn fn, clear_fn *clearfn) + opivx2_fn fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; @@ -989,31 +905,30 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, } fn(vd, s1, vs2, i); } - clearfn(vd, vl, vl * dsz, vlmax * dsz); } /* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VX(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } -GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vadd_vx_b, 1, 1) +GEN_VEXT_VX(vadd_vx_h, 2, 2) +GEN_VEXT_VX(vadd_vx_w, 4, 4) +GEN_VEXT_VX(vadd_vx_d, 8, 8) +GEN_VEXT_VX(vsub_vx_b, 1, 1) +GEN_VEXT_VX(vsub_vx_h, 2, 2) +GEN_VEXT_VX(vsub_vx_w, 4, 4) +GEN_VEXT_VX(vsub_vx_d, 8, 8) +GEN_VEXT_VX(vrsub_vx_b, 1, 1) +GEN_VEXT_VX(vrsub_vx_h, 2, 2) +GEN_VEXT_VX(vrsub_vx_w, 4, 4) +GEN_VEXT_VX(vrsub_vx_d, 8, 8) void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc) { @@ -1092,30 +1007,30 @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD) RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB) RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB) RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB) -GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq) -GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq) +GEN_VEXT_VV(vwaddu_vv_b, 1, 2) +GEN_VEXT_VV(vwaddu_vv_h, 2, 4) +GEN_VEXT_VV(vwaddu_vv_w, 4, 8) +GEN_VEXT_VV(vwsubu_vv_b, 1, 2) +GEN_VEXT_VV(vwsubu_vv_h, 2, 4) +GEN_VEXT_VV(vwsubu_vv_w, 4, 8) +GEN_VEXT_VV(vwadd_vv_b, 1, 2) +GEN_VEXT_VV(vwadd_vv_h, 2, 4) +GEN_VEXT_VV(vwadd_vv_w, 4, 8) +GEN_VEXT_VV(vwsub_vv_b, 1, 2) +GEN_VEXT_VV(vwsub_vv_h, 2, 4) +GEN_VEXT_VV(vwsub_vv_w, 4, 8) +GEN_VEXT_VV(vwaddu_wv_b, 1, 2) +GEN_VEXT_VV(vwaddu_wv_h, 2, 4) +GEN_VEXT_VV(vwaddu_wv_w, 4, 8) +GEN_VEXT_VV(vwsubu_wv_b, 1, 2) +GEN_VEXT_VV(vwsubu_wv_h, 2, 4) +GEN_VEXT_VV(vwsubu_wv_w, 4, 8) +GEN_VEXT_VV(vwadd_wv_b, 1, 2) +GEN_VEXT_VV(vwadd_wv_h, 2, 4) +GEN_VEXT_VV(vwadd_wv_w, 4, 8) +GEN_VEXT_VV(vwsub_wv_b, 1, 2) +GEN_VEXT_VV(vwsub_wv_h, 2, 4) +GEN_VEXT_VV(vwsub_wv_w, 4, 8) RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD) RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD) @@ -1141,42 +1056,40 @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD) RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB) RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB) RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB) -GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq) -GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq) +GEN_VEXT_VX(vwaddu_vx_b, 1, 2) +GEN_VEXT_VX(vwaddu_vx_h, 2, 4) +GEN_VEXT_VX(vwaddu_vx_w, 4, 8) +GEN_VEXT_VX(vwsubu_vx_b, 1, 2) +GEN_VEXT_VX(vwsubu_vx_h, 2, 4) +GEN_VEXT_VX(vwsubu_vx_w, 4, 8) +GEN_VEXT_VX(vwadd_vx_b, 1, 2) +GEN_VEXT_VX(vwadd_vx_h, 2, 4) +GEN_VEXT_VX(vwadd_vx_w, 4, 8) +GEN_VEXT_VX(vwsub_vx_b, 1, 2) +GEN_VEXT_VX(vwsub_vx_h, 2, 4) +GEN_VEXT_VX(vwsub_vx_w, 4, 8) +GEN_VEXT_VX(vwaddu_wx_b, 1, 2) +GEN_VEXT_VX(vwaddu_wx_h, 2, 4) +GEN_VEXT_VX(vwaddu_wx_w, 4, 8) +GEN_VEXT_VX(vwsubu_wx_b, 1, 2) +GEN_VEXT_VX(vwsubu_wx_h, 2, 4) +GEN_VEXT_VX(vwsubu_wx_w, 4, 8) +GEN_VEXT_VX(vwadd_wx_b, 1, 2) +GEN_VEXT_VX(vwadd_wx_h, 2, 4) +GEN_VEXT_VX(vwadd_wx_w, 4, 8) +GEN_VEXT_VX(vwsub_wx_b, 1, 2) +GEN_VEXT_VX(vwsub_wx_h, 2, 4) +GEN_VEXT_VX(vwsub_wx_w, 4, 8) /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ #define DO_VADC(N, M, C) (N + M + C) #define DO_VSBC(N, M, C) (N - M - C) -#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \ +#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1186,26 +1099,23 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb) -GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh) -GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl) -GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq) +GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC) +GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC) +GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC) +GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC) -GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb) -GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh) -GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl) -GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq) +GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC) +GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC) +GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC) +GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC) -#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \ +#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1214,18 +1124,17 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb) -GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh) -GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl) -GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq) +GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC) +GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC) +GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC) +GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC) -GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb) -GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh) -GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl) -GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq) +GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC) +GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC) +GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC) +GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC) #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \ (__typeof(N))(N + M) < N) @@ -1304,18 +1213,18 @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR) RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR) RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR) RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR) -GEN_VEXT_VV(vand_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vand_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vand_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vand_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vor_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vor_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vor_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vor_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vand_vv_b, 1, 1) +GEN_VEXT_VV(vand_vv_h, 2, 2) +GEN_VEXT_VV(vand_vv_w, 4, 4) +GEN_VEXT_VV(vand_vv_d, 8, 8) +GEN_VEXT_VV(vor_vv_b, 1, 1) +GEN_VEXT_VV(vor_vv_h, 2, 2) +GEN_VEXT_VV(vor_vv_w, 4, 4) +GEN_VEXT_VV(vor_vv_d, 8, 8) +GEN_VEXT_VV(vxor_vv_b, 1, 1) +GEN_VEXT_VV(vxor_vv_h, 2, 2) +GEN_VEXT_VV(vxor_vv_w, 4, 4) +GEN_VEXT_VV(vxor_vv_d, 8, 8) RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND) RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND) @@ -1329,32 +1238,30 @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR) RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR) RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR) RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR) -GEN_VEXT_VX(vand_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vand_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vand_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vand_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vor_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vor_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vor_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vor_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vand_vx_b, 1, 1) +GEN_VEXT_VX(vand_vx_h, 2, 2) +GEN_VEXT_VX(vand_vx_w, 4, 4) +GEN_VEXT_VX(vand_vx_d, 8, 8) +GEN_VEXT_VX(vor_vx_b, 1, 1) +GEN_VEXT_VX(vor_vx_h, 2, 2) +GEN_VEXT_VX(vor_vx_w, 4, 4) +GEN_VEXT_VX(vor_vx_d, 8, 8) +GEN_VEXT_VX(vxor_vx_b, 1, 1) +GEN_VEXT_VX(vxor_vx_h, 2, 2) +GEN_VEXT_VX(vxor_vx_w, 4, 4) +GEN_VEXT_VX(vxor_vx_d, 8, 8) /* Vector Single-Width Bit Shift Instructions */ #define DO_SLL(N, M) (N << (M)) #define DO_SRL(N, M) (N >> (M)) /* generate the helpers for shift instructions with two vector operators */ -#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \ +#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(TS1); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1365,73 +1272,69 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb) -GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh) -GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl) -GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq) +GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7) +GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf) +GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f) +GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f) -GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f) /* generate the helpers for shift instructions with one vector and one scalar */ -#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t esz = sizeof(TD); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ - } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ + } \ } -GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb) -GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh) -GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl) -GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq) +GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7) +GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf) +GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f) +GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f) -GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f) /* Vector Narrowing Integer Right Shift Instructions */ -GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl) -GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) -GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl) -GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) +GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) /* Vector Integer Comparison Instructions */ #define DO_MSEQ(N, M) (N == M) @@ -1571,22 +1474,22 @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX) RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX) RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX) RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX) -GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vminu_vv_b, 1, 1) +GEN_VEXT_VV(vminu_vv_h, 2, 2) +GEN_VEXT_VV(vminu_vv_w, 4, 4) +GEN_VEXT_VV(vminu_vv_d, 8, 8) +GEN_VEXT_VV(vmin_vv_b, 1, 1) +GEN_VEXT_VV(vmin_vv_h, 2, 2) +GEN_VEXT_VV(vmin_vv_w, 4, 4) +GEN_VEXT_VV(vmin_vv_d, 8, 8) +GEN_VEXT_VV(vmaxu_vv_b, 1, 1) +GEN_VEXT_VV(vmaxu_vv_h, 2, 2) +GEN_VEXT_VV(vmaxu_vv_w, 4, 4) +GEN_VEXT_VV(vmaxu_vv_d, 8, 8) +GEN_VEXT_VV(vmax_vv_b, 1, 1) +GEN_VEXT_VV(vmax_vv_h, 2, 2) +GEN_VEXT_VV(vmax_vv_w, 4, 4) +GEN_VEXT_VV(vmax_vv_d, 8, 8) RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN) RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN) @@ -1604,22 +1507,22 @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX) RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX) RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX) RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX) -GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vminu_vx_b, 1, 1) +GEN_VEXT_VX(vminu_vx_h, 2, 2) +GEN_VEXT_VX(vminu_vx_w, 4, 4) +GEN_VEXT_VX(vminu_vx_d, 8, 8) +GEN_VEXT_VX(vmin_vx_b, 1, 1) +GEN_VEXT_VX(vmin_vx_h, 2, 2) +GEN_VEXT_VX(vmin_vx_w, 4, 4) +GEN_VEXT_VX(vmin_vx_d, 8, 8) +GEN_VEXT_VX(vmaxu_vx_b, 1, 1) +GEN_VEXT_VX(vmaxu_vx_h, 2, 2) +GEN_VEXT_VX(vmaxu_vx_w, 4, 4) +GEN_VEXT_VX(vmaxu_vx_d, 8, 8) +GEN_VEXT_VX(vmax_vx_b, 1, 1) +GEN_VEXT_VX(vmax_vx_h, 2, 2) +GEN_VEXT_VX(vmax_vx_w, 4, 4) +GEN_VEXT_VX(vmax_vx_d, 8, 8) /* Vector Single-Width Integer Multiply Instructions */ #define DO_MUL(N, M) (N * M) @@ -1627,10 +1530,10 @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL) RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL) RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL) RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL) -GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmul_vv_b, 1, 1) +GEN_VEXT_VV(vmul_vv_h, 2, 2) +GEN_VEXT_VV(vmul_vv_w, 4, 4) +GEN_VEXT_VV(vmul_vv_d, 8, 8) static int8_t do_mulh_b(int8_t s2, int8_t s1) { @@ -1734,18 +1637,18 @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b) RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h) RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w) RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d) -GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmulh_vv_b, 1, 1) +GEN_VEXT_VV(vmulh_vv_h, 2, 2) +GEN_VEXT_VV(vmulh_vv_w, 4, 4) +GEN_VEXT_VV(vmulh_vv_d, 8, 8) +GEN_VEXT_VV(vmulhu_vv_b, 1, 1) +GEN_VEXT_VV(vmulhu_vv_h, 2, 2) +GEN_VEXT_VV(vmulhu_vv_w, 4, 4) +GEN_VEXT_VV(vmulhu_vv_d, 8, 8) +GEN_VEXT_VV(vmulhsu_vv_b, 1, 1) +GEN_VEXT_VV(vmulhsu_vv_h, 2, 2) +GEN_VEXT_VV(vmulhsu_vv_w, 4, 4) +GEN_VEXT_VV(vmulhsu_vv_d, 8, 8) RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL) RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL) @@ -1763,22 +1666,22 @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b) RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h) RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w) RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d) -GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmul_vx_b, 1, 1) +GEN_VEXT_VX(vmul_vx_h, 2, 2) +GEN_VEXT_VX(vmul_vx_w, 4, 4) +GEN_VEXT_VX(vmul_vx_d, 8, 8) +GEN_VEXT_VX(vmulh_vx_b, 1, 1) +GEN_VEXT_VX(vmulh_vx_h, 2, 2) +GEN_VEXT_VX(vmulh_vx_w, 4, 4) +GEN_VEXT_VX(vmulh_vx_d, 8, 8) +GEN_VEXT_VX(vmulhu_vx_b, 1, 1) +GEN_VEXT_VX(vmulhu_vx_h, 2, 2) +GEN_VEXT_VX(vmulhu_vx_w, 4, 4) +GEN_VEXT_VX(vmulhu_vx_d, 8, 8) +GEN_VEXT_VX(vmulhsu_vx_b, 1, 1) +GEN_VEXT_VX(vmulhsu_vx_h, 2, 2) +GEN_VEXT_VX(vmulhsu_vx_w, 4, 4) +GEN_VEXT_VX(vmulhsu_vx_d, 8, 8) /* Vector Integer Divide Instructions */ #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M) @@ -1804,22 +1707,22 @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM) RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM) RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM) RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM) -GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vdivu_vv_b, 1, 1) +GEN_VEXT_VV(vdivu_vv_h, 2, 2) +GEN_VEXT_VV(vdivu_vv_w, 4, 4) +GEN_VEXT_VV(vdivu_vv_d, 8, 8) +GEN_VEXT_VV(vdiv_vv_b, 1, 1) +GEN_VEXT_VV(vdiv_vv_h, 2, 2) +GEN_VEXT_VV(vdiv_vv_w, 4, 4) +GEN_VEXT_VV(vdiv_vv_d, 8, 8) +GEN_VEXT_VV(vremu_vv_b, 1, 1) +GEN_VEXT_VV(vremu_vv_h, 2, 2) +GEN_VEXT_VV(vremu_vv_w, 4, 4) +GEN_VEXT_VV(vremu_vv_d, 8, 8) +GEN_VEXT_VV(vrem_vv_b, 1, 1) +GEN_VEXT_VV(vrem_vv_h, 2, 2) +GEN_VEXT_VV(vrem_vv_w, 4, 4) +GEN_VEXT_VV(vrem_vv_d, 8, 8) RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU) RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU) @@ -1837,22 +1740,22 @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM) RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM) RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM) RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM) -GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vdivu_vx_b, 1, 1) +GEN_VEXT_VX(vdivu_vx_h, 2, 2) +GEN_VEXT_VX(vdivu_vx_w, 4, 4) +GEN_VEXT_VX(vdivu_vx_d, 8, 8) +GEN_VEXT_VX(vdiv_vx_b, 1, 1) +GEN_VEXT_VX(vdiv_vx_h, 2, 2) +GEN_VEXT_VX(vdiv_vx_w, 4, 4) +GEN_VEXT_VX(vdiv_vx_d, 8, 8) +GEN_VEXT_VX(vremu_vx_b, 1, 1) +GEN_VEXT_VX(vremu_vx_h, 2, 2) +GEN_VEXT_VX(vremu_vx_w, 4, 4) +GEN_VEXT_VX(vremu_vx_d, 8, 8) +GEN_VEXT_VX(vrem_vx_b, 1, 1) +GEN_VEXT_VX(vrem_vx_h, 2, 2) +GEN_VEXT_VX(vrem_vx_w, 4, 4) +GEN_VEXT_VX(vrem_vx_d, 8, 8) /* Vector Widening Integer Multiply Instructions */ RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL) @@ -1864,15 +1767,15 @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL) RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL) RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL) RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL) -GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmul_vv_b, 1, 2) +GEN_VEXT_VV(vwmul_vv_h, 2, 4) +GEN_VEXT_VV(vwmul_vv_w, 4, 8) +GEN_VEXT_VV(vwmulu_vv_b, 1, 2) +GEN_VEXT_VV(vwmulu_vv_h, 2, 4) +GEN_VEXT_VV(vwmulu_vv_w, 4, 8) +GEN_VEXT_VV(vwmulsu_vv_b, 1, 2) +GEN_VEXT_VV(vwmulsu_vv_h, 2, 4) +GEN_VEXT_VV(vwmulsu_vv_w, 4, 8) RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL) RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL) @@ -1883,15 +1786,15 @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL) RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL) RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL) RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL) -GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmul_vx_b, 1, 2) +GEN_VEXT_VX(vwmul_vx_h, 2, 4) +GEN_VEXT_VX(vwmul_vx_w, 4, 8) +GEN_VEXT_VX(vwmulu_vx_b, 1, 2) +GEN_VEXT_VX(vwmulu_vx_h, 2, 4) +GEN_VEXT_VX(vwmulu_vx_w, 4, 8) +GEN_VEXT_VX(vwmulsu_vx_b, 1, 2) +GEN_VEXT_VX(vwmulsu_vx_h, 2, 4) +GEN_VEXT_VX(vwmulsu_vx_w, 4, 8) /* Vector Single-Width Integer Multiply-Add Instructions */ #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ @@ -1923,22 +1826,22 @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB) RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB) RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB) RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB) -GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmacc_vv_b, 1, 1) +GEN_VEXT_VV(vmacc_vv_h, 2, 2) +GEN_VEXT_VV(vmacc_vv_w, 4, 4) +GEN_VEXT_VV(vmacc_vv_d, 8, 8) +GEN_VEXT_VV(vnmsac_vv_b, 1, 1) +GEN_VEXT_VV(vnmsac_vv_h, 2, 2) +GEN_VEXT_VV(vnmsac_vv_w, 4, 4) +GEN_VEXT_VV(vnmsac_vv_d, 8, 8) +GEN_VEXT_VV(vmadd_vv_b, 1, 1) +GEN_VEXT_VV(vmadd_vv_h, 2, 2) +GEN_VEXT_VV(vmadd_vv_w, 4, 4) +GEN_VEXT_VV(vmadd_vv_d, 8, 8) +GEN_VEXT_VV(vnmsub_vv_b, 1, 1) +GEN_VEXT_VV(vnmsub_vv_h, 2, 2) +GEN_VEXT_VV(vnmsub_vv_w, 4, 4) +GEN_VEXT_VV(vnmsub_vv_d, 8, 8) #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ @@ -1964,22 +1867,22 @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB) RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB) RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB) RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB) -GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmacc_vx_b, 1, 1) +GEN_VEXT_VX(vmacc_vx_h, 2, 2) +GEN_VEXT_VX(vmacc_vx_w, 4, 4) +GEN_VEXT_VX(vmacc_vx_d, 8, 8) +GEN_VEXT_VX(vnmsac_vx_b, 1, 1) +GEN_VEXT_VX(vnmsac_vx_h, 2, 2) +GEN_VEXT_VX(vnmsac_vx_w, 4, 4) +GEN_VEXT_VX(vnmsac_vx_d, 8, 8) +GEN_VEXT_VX(vmadd_vx_b, 1, 1) +GEN_VEXT_VX(vmadd_vx_h, 2, 2) +GEN_VEXT_VX(vmadd_vx_w, 4, 4) +GEN_VEXT_VX(vmadd_vx_d, 8, 8) +GEN_VEXT_VX(vnmsub_vx_b, 1, 1) +GEN_VEXT_VX(vnmsub_vx_h, 2, 2) +GEN_VEXT_VX(vnmsub_vx_w, 4, 4) +GEN_VEXT_VX(vnmsub_vx_d, 8, 8) /* Vector Widening Integer Multiply-Add Instructions */ RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC) @@ -1991,15 +1894,15 @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC) RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC) RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC) RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC) -GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmaccu_vv_b, 1, 2) +GEN_VEXT_VV(vwmaccu_vv_h, 2, 4) +GEN_VEXT_VV(vwmaccu_vv_w, 4, 8) +GEN_VEXT_VV(vwmacc_vv_b, 1, 2) +GEN_VEXT_VV(vwmacc_vv_h, 2, 4) +GEN_VEXT_VV(vwmacc_vv_w, 4, 8) +GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2) +GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4) +GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8) RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC) RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC) @@ -2013,89 +1916,78 @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC) RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC) RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC) RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC) -GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmaccu_vx_b, 1, 2) +GEN_VEXT_VX(vwmaccu_vx_h, 2, 4) +GEN_VEXT_VX(vwmaccu_vx_w, 4, 8) +GEN_VEXT_VX(vwmacc_vx_b, 1, 2) +GEN_VEXT_VX(vwmacc_vx_h, 2, 4) +GEN_VEXT_VX(vwmacc_vx_w, 4, 8) +GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2) +GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4) +GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8) +GEN_VEXT_VX(vwmaccus_vx_b, 1, 2) +GEN_VEXT_VX(vwmaccus_vx_h, 2, 4) +GEN_VEXT_VX(vwmaccus_vx_w, 4, 8) /* Vector Integer Merge and Move Instructions */ -#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMV_VV(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ *((ETYPE *)vd + H(i)) = s1; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb) -GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2, clearh) -GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4, clearl) -GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8, clearq) +GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1) +GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2) +GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4) +GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8) -#define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMV_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ *((ETYPE *)vd + H(i)) = (ETYPE)s1; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb) -GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2, clearh) -GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4, clearl) -GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq) +GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1) +GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2) +GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4) +GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8) -#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) = *(vt + H(i)); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb) -GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2, clearh) -GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4, clearl) -GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq) +GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1) +GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2) +GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4) +GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8) -#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -2104,13 +1996,12 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ (ETYPE)(target_long)s1); \ *((ETYPE *)vd + H(i)) = d; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb) -GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh) -GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl) -GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq) +GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) +GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2) +GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4) +GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8) /* *** Vector Fixed-Point Arithmetic Instructions @@ -2153,9 +2044,8 @@ static inline void vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivv2_rm_fn *fn, clear_fn *clearfn) + opivv2_rm_fn *fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; @@ -2177,17 +2067,15 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, env, vl, vm, 3, fn); break; } - - clearfn(vd, vl, vl * dsz, vlmax * dsz); } /* generate helpers for fixed point instructions with OPIVV format */ -#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) @@ -2237,10 +2125,10 @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8) RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16) RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32) RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64) -GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8) typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i, CPURISCVState *env, int vxrm); @@ -2272,9 +2160,8 @@ static inline void vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivx2_rm_fn *fn, clear_fn *clearfn) + opivx2_rm_fn *fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; @@ -2296,27 +2183,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2, env, vl, vm, 3, fn); break; } - - clearfn(vd, vl, vl * dsz, vlmax * dsz); } /* generate helpers for fixed point instructions with OPIVX format */ -#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8) RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16) RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32) RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64) -GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8) static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { @@ -2362,19 +2247,19 @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8) RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16) RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32) RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64) -GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1) +GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2) +GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4) +GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8) RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16) RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32) RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64) -GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1) +GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2) +GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4) +GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8) static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) { @@ -2423,19 +2308,19 @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8) RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16) RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32) RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64) -GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8) RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16) RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32) RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64) -GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8) static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { @@ -2481,19 +2366,19 @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8) RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16) RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32) RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64) -GEN_VEXT_VV_RM(vssub_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssub_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssub_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssub_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssub_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8) RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16) RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32) RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64) -GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssub_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssub_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssub_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssub_vx_d, 8, 8) /* Vector Single-Width Averaging Add and Subtract */ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) @@ -2545,19 +2430,19 @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32) RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32) RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32) RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64) -GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1) +GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2) +GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4) +GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32) RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32) RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32) RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64) -GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1) +GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2) +GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4) +GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8) static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) { @@ -2581,19 +2466,19 @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32) RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32) RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32) RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64) -GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vasub_vv_b, 1, 1) +GEN_VEXT_VV_RM(vasub_vv_h, 2, 2) +GEN_VEXT_VV_RM(vasub_vv_w, 4, 4) +GEN_VEXT_VV_RM(vasub_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32) RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32) RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32) RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64) -GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vasub_vx_b, 1, 1) +GEN_VEXT_VX_RM(vasub_vx_h, 2, 2) +GEN_VEXT_VX_RM(vasub_vx_w, 4, 4) +GEN_VEXT_VX_RM(vasub_vx_d, 8, 8) /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) @@ -2688,19 +2573,19 @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) -GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1) +GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2) +GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4) +GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) -GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1) +GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2) +GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4) +GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8) /* Vector Widening Saturating Scaled Multiply-Add */ static inline uint16_t @@ -2753,9 +2638,9 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \ RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8) RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16) RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32) -GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq) +GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2) +GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4) +GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8) #define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static inline void \ @@ -2770,9 +2655,9 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \ RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8) RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16) RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32) -GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq) +GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2) +GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4) +GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8) static inline int16_t vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c) @@ -2811,15 +2696,15 @@ vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c) RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8) RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16) RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32) -GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq) +GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2) +GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4) +GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8) RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8) RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16) RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32) -GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq) +GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2) +GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4) +GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8) static inline int16_t vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c) @@ -2857,15 +2742,15 @@ vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c) RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8) RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16) RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32) -GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq) +GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2) +GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4) +GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8) RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8) RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16) RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32) -GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq) +GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2) +GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4) +GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8) static inline int16_t vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c) @@ -2903,9 +2788,9 @@ vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c) RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8) RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16) RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32) -GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq) +GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2) +GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4) +GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8) /* Vector Single-Width Scaling Shift Instructions */ static inline uint8_t @@ -2952,19 +2837,19 @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8) RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16) RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32) RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64) -GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8) RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16) RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32) RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64) -GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8) static inline int8_t vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) @@ -3011,19 +2896,19 @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8) RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16) RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32) RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64) -GEN_VEXT_VV_RM(vssra_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssra_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssra_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssra_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssra_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssra_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssra_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssra_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8) RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16) RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32) RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64) -GEN_VEXT_VX_RM(vssra_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssra_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssra_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssra_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssra_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssra_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssra_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssra_vx_d, 8, 8) /* Vector Narrowing Fixed-Point Clip Instructions */ static inline int8_t @@ -3086,16 +2971,16 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b) RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8) RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16) RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32) -GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl) +GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1) +GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2) +GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4) RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8) RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16) RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32) -GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl) +GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1) +GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2) +GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4) static inline uint8_t vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b) @@ -3148,16 +3033,16 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) -GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl) +GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4) RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8) RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16) RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32) -GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl) +GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4) /* *** Vector Float Point Arithmetic Instructions @@ -3172,12 +3057,11 @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \ } -#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -3188,15 +3072,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ } \ do_##NAME(vd, vs1, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ } RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add) RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add) -GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8) #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ @@ -3206,12 +3089,11 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\ } -#define GEN_VEXT_VF(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VF(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -3222,28 +3104,27 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ } \ do_##NAME(vd, s1, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ } RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add) RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add) -GEN_VEXT_VF(vfadd_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfadd_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfadd_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfadd_vf_h, 2, 2) +GEN_VEXT_VF(vfadd_vf_w, 4, 4) +GEN_VEXT_VF(vfadd_vf_d, 8, 8) RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub) RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub) RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub) -GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8) RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub) RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub) RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub) -GEN_VEXT_VF(vfsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsub_vf_h, 2, 2) +GEN_VEXT_VF(vfsub_vf_w, 4, 4) +GEN_VEXT_VF(vfsub_vf_d, 8, 8) static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s) { @@ -3263,9 +3144,9 @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub) RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub) RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub) -GEN_VEXT_VF(vfrsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfrsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfrsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfrsub_vf_h, 2, 2) +GEN_VEXT_VF(vfrsub_vf_w, 4, 4) +GEN_VEXT_VF(vfrsub_vf_d, 8, 8) /* Vector Widening Floating-Point Add/Subtract Instructions */ static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s) @@ -3283,12 +3164,12 @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16) RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32) -GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8) RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16) RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32) -GEN_VEXT_VF(vfwadd_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwadd_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwadd_vf_h, 2, 4) +GEN_VEXT_VF(vfwadd_vf_w, 4, 8) static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s) { @@ -3305,12 +3186,12 @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16) RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32) -GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8) RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16) RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32) -GEN_VEXT_VF(vfwsub_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwsub_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwsub_vf_h, 2, 4) +GEN_VEXT_VF(vfwsub_vf_w, 4, 8) static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s) { @@ -3324,12 +3205,12 @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16) RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32) -GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8) RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16) RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32) -GEN_VEXT_VF(vfwadd_wf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwadd_wf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwadd_wf_h, 2, 4) +GEN_VEXT_VF(vfwadd_wf_w, 4, 8) static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s) { @@ -3343,39 +3224,39 @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16) RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32) -GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8) RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16) RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) -GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwsub_wf_h, 2, 4) +GEN_VEXT_VF(vfwsub_wf_w, 4, 8) /* Vector Single-Width Floating-Point Multiply/Divide Instructions */ RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) -GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8) RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) -GEN_VEXT_VF(vfmul_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmul_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmul_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmul_vf_h, 2, 2) +GEN_VEXT_VF(vfmul_vf_w, 4, 4) +GEN_VEXT_VF(vfmul_vf_d, 8, 8) RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div) RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div) RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div) -GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8) RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div) RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div) RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div) -GEN_VEXT_VF(vfdiv_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfdiv_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfdiv_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfdiv_vf_h, 2, 2) +GEN_VEXT_VF(vfdiv_vf_w, 4, 4) +GEN_VEXT_VF(vfdiv_vf_d, 8, 8) static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s) { @@ -3395,9 +3276,9 @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv) RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv) RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv) -GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfrdiv_vf_h, 2, 2) +GEN_VEXT_VF(vfrdiv_vf_w, 4, 4) +GEN_VEXT_VF(vfrdiv_vf_d, 8, 8) /* Vector Widening Floating-Point Multiply */ static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s) @@ -3414,12 +3295,12 @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s) } RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16) RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32) -GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8) RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16) RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32) -GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwmul_vf_h, 2, 4) +GEN_VEXT_VF(vfwmul_vf_w, 4, 8) /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ @@ -3450,9 +3331,9 @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16) RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32) RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64) -GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8) #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ @@ -3466,9 +3347,9 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16) RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32) RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64) -GEN_VEXT_VF(vfmacc_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmacc_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmacc_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmacc_vf_h, 2, 2) +GEN_VEXT_VF(vfmacc_vf_w, 4, 4) +GEN_VEXT_VF(vfmacc_vf_d, 8, 8) static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3491,15 +3372,15 @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32) RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64) -GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16) RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32) RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64) -GEN_VEXT_VF(vfnmacc_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmacc_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmacc_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmacc_vf_h, 2, 2) +GEN_VEXT_VF(vfnmacc_vf_w, 4, 4) +GEN_VEXT_VF(vfnmacc_vf_d, 8, 8) static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3519,15 +3400,15 @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16) RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32) RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64) -GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8) RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16) RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32) RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64) -GEN_VEXT_VF(vfmsac_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmsac_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmsac_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmsac_vf_h, 2, 2) +GEN_VEXT_VF(vfmsac_vf_w, 4, 4) +GEN_VEXT_VF(vfmsac_vf_d, 8, 8) static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3547,15 +3428,15 @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16) RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32) RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64) -GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16) RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32) RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64) -GEN_VEXT_VF(vfnmsac_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmsac_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmsac_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmsac_vf_h, 2, 2) +GEN_VEXT_VF(vfnmsac_vf_w, 4, 4) +GEN_VEXT_VF(vfnmsac_vf_d, 8, 8) static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3575,15 +3456,15 @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16) RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32) RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64) -GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8) RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16) RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32) RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64) -GEN_VEXT_VF(vfmadd_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmadd_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmadd_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmadd_vf_h, 2, 2) +GEN_VEXT_VF(vfmadd_vf_w, 4, 4) +GEN_VEXT_VF(vfmadd_vf_d, 8, 8) static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3606,15 +3487,15 @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32) RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64) -GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16) RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32) RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64) -GEN_VEXT_VF(vfnmadd_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmadd_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmadd_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmadd_vf_h, 2, 2) +GEN_VEXT_VF(vfnmadd_vf_w, 4, 4) +GEN_VEXT_VF(vfnmadd_vf_d, 8, 8) static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3634,15 +3515,15 @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16) RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32) RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64) -GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8) RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16) RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32) RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64) -GEN_VEXT_VF(vfmsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmsub_vf_h, 2, 2) +GEN_VEXT_VF(vfmsub_vf_w, 4, 4) +GEN_VEXT_VF(vfmsub_vf_d, 8, 8) static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3662,15 +3543,15 @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16) RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32) RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64) -GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16) RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32) RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64) -GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmsub_vf_h, 2, 2) +GEN_VEXT_VF(vfnmsub_vf_w, 4, 4) +GEN_VEXT_VF(vfnmsub_vf_d, 8, 8) /* Vector Widening Floating-Point Fused Multiply-Add Instructions */ static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) @@ -3687,12 +3568,12 @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16) RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32) -GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8) RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16) RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32) -GEN_VEXT_VF(vfwmacc_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwmacc_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwmacc_vf_h, 2, 4) +GEN_VEXT_VF(vfwmacc_vf_w, 4, 8) static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) { @@ -3710,12 +3591,12 @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32) -GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8) RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16) RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32) -GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4) +GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8) static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) { @@ -3733,12 +3614,12 @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32) -GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8) RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16) RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32) -GEN_VEXT_VF(vfwmsac_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwmsac_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwmsac_vf_h, 2, 4) +GEN_VEXT_VF(vfwmsac_vf_w, 4, 8) static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) { @@ -3756,12 +3637,12 @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32) -GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8) RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16) RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) -GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4) +GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8) /* Vector Floating-Point Square-Root Instruction */ /* (TD, T2, TX2) */ @@ -3777,11 +3658,10 @@ static void do_##NAME(void *vd, void *vs2, int i, \ *((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \ } -#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -3795,42 +3675,41 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ } \ do_##NAME(vd, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ } RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt) RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) -GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2) +GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) +GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) /* Vector Floating-Point MIN/MAX Instructions */ RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) -GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8) RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) -GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmin_vf_h, 2, 2) +GEN_VEXT_VF(vfmin_vf_w, 4, 4) +GEN_VEXT_VF(vfmin_vf_d, 8, 8) RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) -GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8) RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) -GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmax_vf_h, 2, 2) +GEN_VEXT_VF(vfmax_vf_w, 4, 4) +GEN_VEXT_VF(vfmax_vf_d, 8, 8) /* Vector Floating-Point Sign-Injection Instructions */ static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s) @@ -3851,15 +3730,15 @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16) RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32) RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64) -GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8) RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16) RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32) RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64) -GEN_VEXT_VF(vfsgnj_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsgnj_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsgnj_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsgnj_vf_h, 2, 2) +GEN_VEXT_VF(vfsgnj_vf_w, 4, 4) +GEN_VEXT_VF(vfsgnj_vf_d, 8, 8) static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s) { @@ -3879,15 +3758,15 @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16) RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32) RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64) -GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8) RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16) RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32) RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64) -GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2) +GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4) +GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8) static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s) { @@ -3907,15 +3786,15 @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16) RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32) RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64) -GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8) RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16) RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32) RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64) -GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2) +GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4) +GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8) /* Vector Floating-Point Compare Instructions */ #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ @@ -4072,11 +3951,10 @@ static void do_##NAME(void *vd, void *vs2, int i) \ *((TD *)vd + HD(i)) = OP(s2); \ } -#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_V(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -4087,7 +3965,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ } \ do_##NAME(vd, vs2, i); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ } target_ulong fclass_h(uint64_t frs1) @@ -4150,19 +4027,17 @@ target_ulong fclass_d(uint64_t frs1) RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h) RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s) RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) -GEN_VEXT_V(vfclass_v_h, 2, 2, clearh) -GEN_VEXT_V(vfclass_v_w, 4, 4, clearl) -GEN_VEXT_V(vfclass_v_d, 8, 8, clearq) +GEN_VEXT_V(vfclass_v_h, 2, 2) +GEN_VEXT_V(vfclass_v_w, 4, 4) +GEN_VEXT_V(vfclass_v_d, 8, 8) /* Vector Floating-Point Merge Instruction */ -#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VFMERGE_VF(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -4170,45 +4045,44 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ *((ETYPE *)vd + H(i)) \ = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ } -GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh) -GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl) -GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq) +GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2) +GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4) +GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8) /* Single-Width Floating-Point/Integer Type-Convert Instructions */ /* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16) RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32) RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64) -GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8) /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */ RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16) RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32) RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64) -GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8) /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */ RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16) RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32) RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64) -GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8) /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */ RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16) RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32) RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64) -GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8) /* Widening Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ @@ -4217,26 +4091,26 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq) /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/ RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32) RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64) -GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8) /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */ RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32) RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64) -GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8) /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */ RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8) /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) -GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8) /* * vfwcvt.f.f.v vd, vs2, vm # @@ -4249,8 +4123,8 @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16) RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64) -GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8) /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ @@ -4259,26 +4133,26 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq) /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4) /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */ RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) -GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4) /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */ RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4) /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4) /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */ static uint16_t vfncvtffv16(uint32_t a, float_status *s) @@ -4288,21 +4162,20 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s) RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4) /* *** Vector Reduction Operations */ /* Vector Single-Width Integer Reduction Instructions */ -#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ +#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \ TD s1 = *((TD *)vs1 + HD(0)); \ \ for (i = 0; i < vl; i++) { \ @@ -4313,70 +4186,69 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ s1 = OP(s1, (TD)s2); \ } \ *((TD *)vd + HD(0)) = s1; \ - CLEAR_FN(vd, 1, sizeof(TD), tot); \ } /* vd[0] = sum(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb) -GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh) -GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl) -GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq) +GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD) +GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD) +GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD) +GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD) /* vd[0] = maxu(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb) -GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh) -GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl) -GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq) +GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX) /* vd[0] = max(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb) -GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh) -GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl) -GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq) +GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX) +GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX) +GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX) +GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX) /* vd[0] = minu(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb) -GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh) -GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl) -GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq) +GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN) +GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN) +GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN) +GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN) /* vd[0] = min(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb) -GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh) -GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl) -GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq) +GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN) +GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN) +GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN) +GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN) /* vd[0] = and(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb) -GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh) -GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl) -GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq) +GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND) +GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND) +GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND) +GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND) /* vd[0] = or(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb) -GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh) -GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl) -GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq) +GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR) +GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR) +GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR) +GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR) /* vd[0] = xor(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb) -GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) -GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) -GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq) +GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR) +GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR) +GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR) +GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR) /* Vector Widening Integer Reduction Instructions */ /* signed sum reduction into double-width accumulator */ -GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh) -GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl) -GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) +GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD) +GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD) +GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD) /* Unsigned sum reduction into double-width accumulator */ -GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) -GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) -GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) +GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD) +GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD) +GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD) /* Vector Single-Width Floating-Point Reduction Instructions */ -#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ +#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ @@ -4384,7 +4256,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \ TD s1 = *((TD *)vs1 + HD(0)); \ \ for (i = 0; i < vl; i++) { \ @@ -4395,23 +4266,22 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ s1 = OP(s1, (TD)s2, &env->fp_status); \ } \ *((TD *)vd + HD(0)) = s1; \ - CLEAR_FN(vd, 1, sizeof(TD), tot); \ } /* Unordered sum */ -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh) -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl) -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq) +GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) +GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) +GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) /* Maximum value */ -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh) -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl) -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq) +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum) +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum) +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum) /* Minimum value */ -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh) -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl) -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq) +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum) +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum) +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum) /* Vector Widening Floating-Point Reduction Instructions */ /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ @@ -4421,7 +4291,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; uint32_t s1 = *((uint32_t *)vs1 + H4(0)); for (i = 0; i < vl; i++) { @@ -4433,7 +4302,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, &env->fp_status); } *((uint32_t *)vd + H4(0)) = s1; - clearl(vd, 1, sizeof(uint32_t), tot); } void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, @@ -4442,7 +4310,6 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; uint64_t s1 = *((uint64_t *)vs1); for (i = 0; i < vl; i++) { @@ -4454,7 +4321,6 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, &env->fp_status); } *((uint64_t *)vd) = s1; - clearq(vd, 1, sizeof(uint64_t), tot); } /* @@ -4596,11 +4462,10 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, } /* Vector Iota Instruction */ -#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t sum = 0; \ @@ -4615,19 +4480,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ sum++; \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } -GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb) -GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh) -GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl) -GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq) +GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1) +GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2) +GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4) +GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8) /* Vector Element Index Instruction */ -#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VID_V(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ int i; \ @@ -4638,24 +4501,22 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ } \ *((ETYPE *)vd + H(i)) = i; \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } -GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb) -GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh) -GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl) -GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) +GEN_VEXT_VID_V(vid_v_b, uint8_t, H1) +GEN_VEXT_VID_V(vid_v_h, uint16_t, H2) +GEN_VEXT_VID_V(vid_v_w, uint32_t, H4) +GEN_VEXT_VID_V(vid_v_d, uint64_t, H8) /* *** Vector Permutation Instructions */ /* Vector Slide Instructions */ -#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ target_ulong offset = s1, i; \ @@ -4666,16 +4527,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ } \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */ -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8) -#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ @@ -4691,20 +4551,18 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ } \ *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */ -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) -#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -4719,20 +4577,18 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */ -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8) -#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -4747,17 +4603,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */ -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) /* Vector Register Gather Instruction */ -#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ @@ -4778,16 +4633,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */ -GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1, clearb) -GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2, clearh) -GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4, clearl) -GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq) +GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1) +GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2) +GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4) +GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8) -#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ @@ -4807,21 +4661,19 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ -GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1) +GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2) +GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4) +GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8) /* Vector Compress Instruction */ -#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vl = env->vl; \ uint32_t num = 0, i; \ \ @@ -4832,11 +4684,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ num++; \ } \ - CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* Compress into vd elements of vs2 where vs1 is enabled */ -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb) -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh) -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl) -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) From f31dacd720032419531589488020a61da2d58931 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:01 +0800 Subject: [PATCH 349/421] target/riscv: rvv-1.0: update check functions Update check functions with RVV 1.0 rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-16-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 715 +++++++++++++++++------- 1 file changed, 507 insertions(+), 208 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ecd4b89c6b..bef37dd888 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -19,11 +19,112 @@ #include "tcg/tcg-gvec-desc.h" #include "internals.h" +static inline bool is_overlapped(const int8_t astart, int8_t asize, + const int8_t bstart, int8_t bsize) +{ + const int8_t aend = astart + asize; + const int8_t bend = bstart + bsize; + + return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize; +} + +static bool require_rvv(DisasContext *s) +{ + return s->mstatus_vs != 0; +} + +static bool require_rvf(DisasContext *s) +{ + if (s->mstatus_fs == 0) { + return false; + } + + switch (s->sew) { + case MO_16: + case MO_32: + return has_ext(s, RVF); + case MO_64: + return has_ext(s, RVD); + default: + return false; + } +} + +static bool require_scale_rvf(DisasContext *s) +{ + if (s->mstatus_fs == 0) { + return false; + } + + switch (s->sew) { + case MO_8: + case MO_16: + return has_ext(s, RVF); + case MO_32: + return has_ext(s, RVD); + default: + return false; + } +} + +/* Destination vector register group cannot overlap source mask register. */ +static bool require_vm(int vm, int vd) +{ + return (vm != 0 || vd != 0); +} + +/* + * Vector register should aligned with the passed-in LMUL (EMUL). + * If LMUL < 0, i.e. fractional LMUL, any vector register is allowed. + */ +static bool require_align(const int8_t val, const int8_t lmul) +{ + return lmul <= 0 || extract32(val, 0, lmul) == 0; +} + +/* + * A destination vector register group can overlap a source vector + * register group only if one of the following holds: + * 1. The destination EEW equals the source EEW. + * 2. The destination EEW is smaller than the source EEW and the overlap + * is in the lowest-numbered part of the source register group. + * 3. The destination EEW is greater than the source EEW, the source EMUL + * is at least 1, and the overlap is in the highest-numbered part of + * the destination register group. + * (Section 5.2) + * + * This function returns true if one of the following holds: + * * Destination vector register group does not overlap a source vector + * register group. + * * Rule 3 met. + * For rule 1, overlap is allowed so this function doesn't need to be called. + * For rule 2, (vd == vs). Caller has to check whether: (vd != vs) before + * calling this function. + */ +static bool require_noover(const int8_t dst, const int8_t dst_lmul, + const int8_t src, const int8_t src_lmul) +{ + int8_t dst_size = dst_lmul <= 0 ? 1 : 1 << dst_lmul; + int8_t src_size = src_lmul <= 0 ? 1 : 1 << src_lmul; + + /* Destination EEW is greater than the source EEW, check rule 3. */ + if (dst_size > src_size) { + if (dst < src && + src_lmul >= 0 && + is_overlapped(dst, dst_size, src, src_size) && + !is_overlapped(dst, dst_size, src + src_size, src_size)) { + return true; + } + } + + return !is_overlapped(dst, dst_size, src, src_size); +} + static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) { TCGv s1, s2, dst; - if (!has_ext(ctx, RVV)) { + if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { return false; } @@ -51,7 +152,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) { TCGv s1, s2, dst; - if (!has_ext(ctx, RVV)) { + if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { return false; } @@ -82,6 +183,237 @@ static uint32_t vreg_ofs(DisasContext *s, int reg) /* check functions */ +static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) +{ + return require_vm(vm, vd) && + require_align(vd, s->lmul) && + require_align(vs, s->lmul); +} + +/* + * Check function for vector instruction with format: + * single-width result and single-width sources (SEW = SEW op SEW) + * + * Rules to be checked here: + * 1. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 2. Destination vector register number is multiples of LMUL. + * (Section 3.4.2) + * 3. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.4.2) + */ +static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_ss(s, vd, vs2, vm) && + require_align(vs1, s->lmul); +} + +static bool vext_check_ms(DisasContext *s, int vd, int vs) +{ + bool ret = require_align(vs, s->lmul); + if (vd != vs) { + ret &= require_noover(vd, 0, vs, s->lmul); + } + return ret; +} + +/* + * Check function for maskable vector instruction with format: + * single-width result and single-width sources (SEW = SEW op SEW) + * + * Rules to be checked here: + * 1. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.4.2) + * 2. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) + * 3. The destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0), + * unless the destination vector register is being written + * with a mask value (e.g., comparisons) or the scalar result + * of a reduction. (Section 5.3) + */ +static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) +{ + bool ret = vext_check_ms(s, vd, vs2) && + require_align(vs1, s->lmul); + if (vd != vs1) { + ret &= require_noover(vd, 0, vs1, s->lmul); + } + return ret; +} + +/* + * Common check function for vector widening instructions + * of double-width result (2*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * => LMUL < 8. + * => SEW < 64. + * 2. Destination vector register number is multiples of 2 * LMUL. + * (Section 3.4.2) + * 3. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_wide_check_common(DisasContext *s, int vd, int vm) +{ + return (s->lmul <= 2) && + (s->sew < MO_64) && + require_align(vd, s->lmul + 1) && + require_vm(vm, vd); +} + +/* + * Common check function for vector narrowing instructions + * of single-width result (SEW) and double-width source (2*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * => LMUL < 8. + * => SEW < 64. + * 2. Source vector register number is multiples of 2 * LMUL. + * (Section 3.4.2) + * 3. Destination vector register number is multiples of LMUL. + * (Section 3.4.2) + * 4. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, + int vm) +{ + return (s->lmul <= 2) && + (s->sew < MO_64) && + require_align(vs2, s->lmul + 1) && + require_align(vd, s->lmul) && + require_vm(vm, vd); +} + +static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm) +{ + return vext_wide_check_common(s, vd, vm) && + require_align(vs, s->lmul) && + require_noover(vd, s->lmul + 1, vs, s->lmul); +} + +static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) +{ + return vext_wide_check_common(s, vd, vm) && + require_align(vs, s->lmul + 1); +} + +/* + * Check function for vector instruction with format: + * double-width result and single-width sources (2*SEW = SEW op SEW) + * + * Rules to be checked here: + * 1. All rules in defined in widen common rules are applied. + * 2. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.4.2) + * 3. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) + */ +static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_ds(s, vd, vs2, vm) && + require_align(vs1, s->lmul) && + require_noover(vd, s->lmul + 1, vs1, s->lmul); +} + +/* + * Check function for vector instruction with format: + * double-width result and double-width source1 and single-width + * source2 (2*SEW = 2*SEW op SEW) + * + * Rules to be checked here: + * 1. All rules in defined in widen common rules are applied. + * 2. Source 1 (vs2) vector register number is multiples of 2 * LMUL. + * (Section 3.4.2) + * 3. Source 2 (vs1) vector register number is multiples of LMUL. + * (Section 3.4.2) + * 4. Destination vector register cannot overlap a source vector + * register (vs1) group. + * (Section 5.2) + */ +static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_ds(s, vd, vs1, vm) && + require_align(vs2, s->lmul + 1); +} + +static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) +{ + bool ret = vext_narrow_check_common(s, vd, vs, vm); + if (vd != vs) { + ret &= require_noover(vd, s->lmul, vs, s->lmul + 1); + } + return ret; +} + +/* + * Check function for vector instruction with format: + * single-width result and double-width source 1 and single-width + * source 2 (SEW = 2*SEW op SEW) + * + * Rules to be checked here: + * 1. All rules in defined in narrow common rules are applied. + * 2. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + * 3. Source 2 (vs1) vector register number is multiples of LMUL. + * (Section 3.4.2) + */ +static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_sd(s, vd, vs2, vm) && + require_align(vs1, s->lmul); +} + +/* + * Check function for vector reduction instructions. + * + * Rules to be checked here: + * 1. Source 1 (vs2) vector register number is multiples of LMUL. + * (Section 3.4.2) + */ +static bool vext_check_reduction(DisasContext *s, int vs2) +{ + return require_align(vs2, s->lmul); +} + +/* + * Check function for vector slide instructions. + * + * Rules to be checked here: + * 1. Source 1 (vs2) vector register number is multiples of LMUL. + * (Section 3.4.2) + * 2. Destination vector register number is multiples of LMUL. + * (Section 3.4.2) + * 3. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 4. The destination vector register group for vslideup, vslide1up, + * vfslide1up, cannot overlap the source vector register (vs2) group. + * (Section 5.2, 16.3.1, 16.3.3) + */ +static bool vext_check_slide(DisasContext *s, int vd, int vs2, + int vm, bool is_over) +{ + bool ret = require_align(vs2, s->lmul) && + require_align(vd, s->lmul) && + require_vm(vm, vd); + if (is_over) { + ret &= (vd != vs2); + } + return ret; +} + /* * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. * So RVV is also be checked in this function. @@ -139,6 +471,7 @@ static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen) { return ((rd >= rs + slen) || (rs >= rd + dlen)); } + /* common translation macro */ #define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ @@ -787,11 +1120,9 @@ GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64) static bool opivv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, @@ -879,10 +1210,9 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, static bool opivx_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); } typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, @@ -1073,16 +1403,9 @@ GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) /* OPIVV with WIDEN */ static bool opivv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, @@ -1127,13 +1450,9 @@ GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check) /* OPIVX with WIDEN */ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ds(s, a->rd, a->rs2, a->vm); } static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, @@ -1164,14 +1483,9 @@ GEN_OPIVX_WIDEN_TRANS(vwsub_vx) /* WIDEN OPIVV with WIDEN */ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, @@ -1214,11 +1528,9 @@ GEN_OPIWV_WIDEN_TRANS(vwsub_wv) /* WIDEN OPIVX with WIDEN */ static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dd(s, a->rd, a->rs2, a->vm); } static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a, @@ -1280,11 +1592,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((a->rd != 0) || (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd != 0) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check) @@ -1296,11 +1607,9 @@ GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check) */ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2); } GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check) @@ -1308,10 +1617,10 @@ GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check) static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((a->rd != 0) || (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd != 0) && + vext_check_ss(s, a->rd, a->rs2, a->vm); } /* OPIVX without GVEC IR */ @@ -1334,9 +1643,9 @@ GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check) static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ms(s, a->rd, a->rs2); } GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) @@ -1424,14 +1733,9 @@ GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sds(s, a->rd, a->rs1, a->rs2, a->vm); } /* OPIVV with NARROW */ @@ -1466,13 +1770,9 @@ GEN_OPIVV_NARROW_TRANS(vnsrl_vv) static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sd(s, a->rd, a->rs2, a->vm); } /* OPIVX with NARROW */ @@ -1520,13 +1820,11 @@ GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) */ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2); } + GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check) GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check) GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check) @@ -1536,10 +1834,9 @@ GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check) static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ms(s, a->rd, a->rs2); } GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check) @@ -1618,10 +1915,10 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.v has rs2 = 0 and vm = 1 */ + vext_check_sss(s, a->rd, a->rs1, 0, 1)) { if (s->vl_eq_vlmax) { tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), @@ -1649,9 +1946,10 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32); static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.x has rs2 = 0 and vm = 1 */ + vext_check_ss(s, a->rd, 0, 1)) { TCGv s1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -1689,9 +1987,10 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.i has rs2 = 0 and vm = 1 */ + vext_check_ss(s, a->rd, 0, 1)) { int64_t simm = sextract64(a->rs1, 0, 5); if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), @@ -1791,12 +2090,10 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) */ static bool opfvv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } /* OPFVV without GVEC IR */ @@ -1861,17 +2158,16 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, return true; } -static bool opfvf_check(DisasContext *s, arg_rmrr *a) -{ /* * If the current SEW does not correspond to a supported IEEE floating-point * type, an illegal instruction exception is raised */ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0)); +static bool opfvf_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); } /* OPFVF without GVEC IR */ @@ -1901,16 +2197,10 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) /* Vector Widening Floating-Point Add/Subtract Instructions */ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } /* OPFVV with WIDEN */ @@ -1945,13 +2235,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_ds(s, a->rd, a->rs2, a->vm); } /* OPFVF with WIDEN */ @@ -1977,14 +2264,10 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } /* WIDEN OPFVV with WIDEN */ @@ -2019,11 +2302,10 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_dd(s, a->rd, a->rs2, a->vm); } /* WIDEN OPFVF with WIDEN */ @@ -2094,11 +2376,11 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) */ static bool opfv_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + /* OPFV instructions ignore vs1 check */ + vext_check_ss(s, a->rd, a->rs2, a->vm); } #define GEN_OPFV_TRANS(NAME, CHECK) \ @@ -2147,13 +2429,10 @@ GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) /* Vector Floating-Point Compare Instructions */ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew != 0) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul == 0))); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2); } GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) @@ -2164,11 +2443,10 @@ GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul == 0))); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_ms(s, a->rd, a->rs2); } GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) @@ -2187,10 +2465,10 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - (s->sew != 0)) { - + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul)) { if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); @@ -2235,13 +2513,11 @@ GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) */ static bool opfv_widen_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && + vext_check_isa_ill(s) && + vext_check_ds(s, a->rd, a->rs2, a->vm); } #define GEN_OPFV_WIDEN_TRANS(NAME) \ @@ -2284,13 +2560,12 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) */ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + (s->sew != MO_64) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sd(s, a->rd, a->rs2, a->vm); } #define GEN_OPFV_NARROW_TRANS(NAME) \ @@ -2331,7 +2606,9 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) /* Vector Single-Width Integer Reduction Instructions */ static bool reduction_check(DisasContext *s, arg_rmrr *a) { - return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_reduction(s, a->rs2); } GEN_OPIVV_TRANS(vredsum_vs, reduction_check) @@ -2344,8 +2621,13 @@ GEN_OPIVV_TRANS(vredor_vs, reduction_check) GEN_OPIVV_TRANS(vredxor_vs, reduction_check) /* Vector Widening Integer Reduction Instructions */ -GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) -GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) +static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_check(s, a) && (s->sew < MO_64); +} + +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check) /* Vector Single-Width Floating-Point Reduction Instructions */ GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) @@ -2393,7 +2675,8 @@ GEN_MM_TRANS(vmxnor_mm) /* Vector mask population count vmpopc */ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -2422,7 +2705,8 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) /* vmfirst find-first-set mask bit */ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -2480,10 +2764,11 @@ GEN_M_TRANS(vmsof_m) /* Vector Iota Instruction */ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && - (a->vm != 0 || a->rd != 0)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + require_noover(a->rd, s->lmul, a->rs2, 0) && + require_vm(a->vm, a->rd) && + require_align(a->rd, s->lmul)) { uint32_t data = 0; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2507,9 +2792,10 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) /* Vector Element Index Instruction */ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_mask(s, a->rd, a->vm, false)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_vm(a->vm, a->rd)) { uint32_t data = 0; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2758,41 +3044,48 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) /* Vector Slide Instructions */ static bool slideup_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_slide(s, a->rd, a->rs2, a->vm, true); } GEN_OPIVX_TRANS(vslideup_vx, slideup_check) GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) -GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) -GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) +static bool slidedown_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_slide(s, a->rd, a->rs2, a->vm, false); +} + +GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) +GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) +GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check) /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2) && (a->rd != a->rs1)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs1, s->lmul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2 && a->rd != a->rs1) && + require_vm(a->vm, a->rd); } GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check) static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2) && + require_vm(a->vm, a->rd); } /* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ @@ -2853,14 +3146,20 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) return true; } -/* Vector Compress Instruction */ +/* + * Vector Compress Instruction + * + * The destination vector register group cannot overlap the + * source vector register group or the source mask register. + */ static bool vcompress_vm_check(DisasContext *s, arg_r *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && - (a->rd != a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1); } static bool trans_vcompress_vm(DisasContext *s, arg_r *a) From ff64fc91d1fdf8fe71394d81ba35f33410731d8e Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:02 +0800 Subject: [PATCH 350/421] target/riscv: introduce more imm value modes in translator functions Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW) bit * IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-17-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 115 ++++++++++++++---------- 1 file changed, 66 insertions(+), 49 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index bef37dd888..66273afb53 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1313,8 +1313,32 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs, GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs) +typedef enum { + IMM_ZX, /* Zero-extended */ + IMM_SX, /* Sign-extended */ + IMM_TRUNC_SEW, /* Truncate to log(SEW) bits */ + IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */ +} imm_mode_t; + +static int64_t extract_imm(DisasContext *s, uint32_t imm, imm_mode_t imm_mode) +{ + switch (imm_mode) { + case IMM_ZX: + return extract64(imm, 0, 5); + case IMM_SX: + return sextract64(imm, 0, 5); + case IMM_TRUNC_SEW: + return extract64(imm, 0, s->sew + 3); + case IMM_TRUNC_2SEW: + return extract64(imm, 0, s->sew + 4); + default: + g_assert_not_reached(); + } +} + static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, - gen_helper_opivx *fn, DisasContext *s, int zx) + gen_helper_opivx *fn, DisasContext *s, + imm_mode_t imm_mode) { TCGv_ptr dest, src2, mask; TCGv src1; @@ -1327,11 +1351,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr(); - if (zx) { - src1 = tcg_constant_tl(imm); - } else { - src1 = tcg_constant_tl(sextract64(imm, 0, 5)); - } + src1 = tcg_constant_tl(extract_imm(s, imm, imm_mode)); + data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); @@ -1355,28 +1376,23 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, - gen_helper_opivx *fn, int zx) + gen_helper_opivx *fn, imm_mode_t imm_mode) { if (!opivx_check(s, a)) { return false; } if (a->vm && s->vl_eq_vlmax) { - if (zx) { - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } else { - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); mark_vs_dirty(s); return true; } - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode); } /* OPIVI with GVEC IR */ -#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \ +#define GEN_OPIVI_GVEC_TRANS(NAME, IMM_MODE, OPIVX, SUF) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ static gen_helper_opivx * const fns[4] = { \ @@ -1384,10 +1400,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ - fns[s->sew], ZX); \ + fns[s->sew], IMM_MODE); \ } -GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi) +GEN_OPIVI_GVEC_TRANS(vadd_vi, IMM_SX, vadd_vx, addi) static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) @@ -1396,7 +1412,7 @@ static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz); } -GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) +GEN_OPIVI_GVEC_TRANS(vrsub_vi, IMM_SX, vrsub_vx, rsubi) /* Vector Widening Integer Add/Subtract */ @@ -1652,7 +1668,7 @@ GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check) /* OPIVI without GVEC IR */ -#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \ +#define GEN_OPIVI_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ if (CHECK(s, a)) { \ @@ -1661,13 +1677,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ + fns[s->sew], s, IMM_MODE); \ } \ return false; \ } -GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) +GEN_OPIVI_TRANS(vadc_vim, IMM_SX, vadc_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmadc_vim, IMM_SX, vmadc_vxm, opivx_vmadc_check) /* Vector Bitwise Logical Instructions */ GEN_OPIVV_GVEC_TRANS(vand_vv, and) @@ -1676,9 +1692,9 @@ GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) GEN_OPIVX_GVEC_TRANS(vand_vx, ands) GEN_OPIVX_GVEC_TRANS(vor_vx, ors) GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) -GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) -GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) -GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) +GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi) +GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx, ori) +GEN_OPIVI_GVEC_TRANS(vxor_vi, IMM_SX, vxor_vx, xori) /* Vector Single-Width Bit Shift Instructions */ GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv) @@ -1726,9 +1742,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) -GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) @@ -1794,7 +1810,7 @@ GEN_OPIVX_NARROW_TRANS(vnsra_vx) GEN_OPIVX_NARROW_TRANS(vnsrl_vx) /* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \ +#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ if (opivx_narrow_check(s, a)) { \ @@ -1804,13 +1820,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##OPIVX##_w, \ }; \ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ + fns[s->sew], s, IMM_MODE); \ } \ return false; \ } -GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) +GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx) +GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx) /* Vector Integer Comparison Instructions */ /* @@ -1848,12 +1864,12 @@ GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check) GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check) GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check) /* Vector Integer Min/Max Instructions */ GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) @@ -2025,7 +2041,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmerge_vim, IMM_SX, vmerge_vxm, opivx_vadc_check) /* *** Vector Fixed-Point Arithmetic Instructions @@ -2040,8 +2056,8 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) GEN_OPIVX_TRANS(vsadd_vx, opivx_check) GEN_OPIVX_TRANS(vssubu_vx, opivx_check) GEN_OPIVX_TRANS(vssub_vx, opivx_check) -GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) -GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check) /* Vector Single-Width Averaging Add and Subtract */ GEN_OPIVV_TRANS(vaadd_vv, opivv_check) @@ -2068,16 +2084,16 @@ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) GEN_OPIVV_TRANS(vssra_vv, opivv_check) GEN_OPIVX_TRANS(vssrl_vx, opivx_check) GEN_OPIVX_TRANS(vssra_vx, opivx_check) -GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check) -GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check) +GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check) +GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) /* Vector Narrowing Fixed-Point Clip Instructions */ GEN_OPIVV_NARROW_TRANS(vnclipu_vv) GEN_OPIVV_NARROW_TRANS(vnclip_vv) GEN_OPIVX_NARROW_TRANS(vnclipu_vx) GEN_OPIVX_NARROW_TRANS(vnclip_vx) -GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx) -GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) +GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx) +GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) /* *** Vector Float Point Arithmetic Instructions @@ -3051,7 +3067,7 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a) GEN_OPIVX_TRANS(vslideup_vx, slideup_check) GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) -GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) +GEN_OPIVI_TRANS(vslideup_vi, IMM_ZX, vslideup_vx, slideup_check) static bool slidedown_check(DisasContext *s, arg_rmrr *a) { @@ -3062,7 +3078,7 @@ static bool slidedown_check(DisasContext *s, arg_rmrr *a) GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) -GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check) +GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) @@ -3141,7 +3157,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d }; - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1); + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], + s, IMM_ZX); } return true; } From 9b4a40a78603956344404c53cc355c2ea1ee70c3 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:03 +0800 Subject: [PATCH 351/421] target/riscv: rvv:1.0: add translation-time nan-box helper function * Add fp16 nan-box check generator function, if a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting. * Apply nanbox helper in opfvf_trans(). Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-18-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 35 ++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 66273afb53..f9ace6ae41 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2098,6 +2098,33 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) /* *** Vector Float Point Arithmetic Instructions */ + +/* + * As RVF-only cpus always have values NaN-boxed to 64-bits, + * RVF and RVD can be treated equally. + * We don't have to deal with the cases of: SEW > FLEN. + * + * If SEW < FLEN, check whether input fp register is a valid + * NaN-boxed value, in which case the least-significant SEW bits + * of the f regsiter are used, else the canonical NaN value is used. + */ +static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in) +{ + switch (s->sew) { + case 1: + gen_check_nanbox_h(out, in); + break; + case 2: + gen_check_nanbox_s(out, in); + break; + case 3: + tcg_gen_mov_i64(out, in); + break; + default: + g_assert_not_reached(); + } +} + /* Vector Single-Width Floating-Point Add/Subtract Instructions */ /* @@ -2151,6 +2178,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, { TCGv_ptr dest, src2, mask; TCGv_i32 desc; + TCGv_i64 t1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -2164,11 +2192,16 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + /* NaN-box f[rs1] */ + t1 = tcg_temp_new_i64(); + do_nanbox(s, t1, cpu_fpr[rs1]); + + fn(dest, mask, t1, src2, cpu_env, desc); tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + tcg_temp_free_i64(t1); mark_vs_dirty(s); gen_set_label(over); return true; From 57a2d89a82be6167a5200b5efa66b89686ce3141 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:04 +0800 Subject: [PATCH 352/421] target/riscv: rvv-1.0: remove amo operations instructions Vector AMOs are removed from standard vector extensions. Will be added later as separate Zvamo extension, but will need a different encoding from earlier proposal. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-19-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 27 ----- target/riscv/insn32.decode | 24 ---- target/riscv/insn_trans/trans_rvv.c.inc | 140 ------------------------ target/riscv/vector_helper.c | 125 --------------------- 4 files changed, 316 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index d25cf725c5..ecb6af6cd9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -274,33 +274,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6c4cde216b..3d57255fff 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -49,7 +49,6 @@ &atomic aq rl rs2 rs1 rd &rmrr vm rd rs1 rs2 &rmr vm rd rs2 -&rwdvm vm wd rd rs1 rs2 &r2nfvm vm rd rs1 nf &rnfvm vm rd rs1 rs2 nf @@ -79,7 +78,6 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd -@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -340,17 +338,6 @@ vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm -#*** Vector AMO operations are encoded under the standard AMO major opcode *** -vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm - # *** new major opcode OP-V *** vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm @@ -649,17 +636,6 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r -#*** Vector AMO operations (in addition to Zvamo) *** -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm - # *** RV32 Zba Standard Extension *** sh1add 0010000 .......... 010 ..... 0110011 @r sh2add 0010000 .......... 100 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f9ace6ae41..afec187333 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -973,146 +973,6 @@ GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) -/* - *** vector atomic operation - */ -typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr, - TCGv_env, TCGv_i32); - -static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, - uint32_t data, gen_helper_amo *fn, DisasContext *s) -{ - TCGv_ptr dest, mask, index; - TCGv base; - TCGv_i32 desc; - - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - - dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - index = tcg_temp_new_ptr(); - base = get_gpr(s, rs1, EXT_NONE); - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); - - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - - fn(dest, mask, base, index, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(index); - mark_vs_dirty(s); - gen_set_label(over); - return true; -} - -static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_amo *fn; - static gen_helper_amo *const fnsw[9] = { - /* no atomic operation */ - gen_helper_vamoswapw_v_w, - gen_helper_vamoaddw_v_w, - gen_helper_vamoxorw_v_w, - gen_helper_vamoandw_v_w, - gen_helper_vamoorw_v_w, - gen_helper_vamominw_v_w, - gen_helper_vamomaxw_v_w, - gen_helper_vamominuw_v_w, - gen_helper_vamomaxuw_v_w - }; - static gen_helper_amo *const fnsd[18] = { - gen_helper_vamoswapw_v_d, - gen_helper_vamoaddw_v_d, - gen_helper_vamoxorw_v_d, - gen_helper_vamoandw_v_d, - gen_helper_vamoorw_v_d, - gen_helper_vamominw_v_d, - gen_helper_vamomaxw_v_d, - gen_helper_vamominuw_v_d, - gen_helper_vamomaxuw_v_d, - gen_helper_vamoswapd_v_d, - gen_helper_vamoaddd_v_d, - gen_helper_vamoxord_v_d, - gen_helper_vamoandd_v_d, - gen_helper_vamoord_v_d, - gen_helper_vamomind_v_d, - gen_helper_vamomaxd_v_d, - gen_helper_vamominud_v_d, - gen_helper_vamomaxud_v_d - }; - - if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp = DISAS_NORETURN; - return true; - } - - switch (s->sew) { - case 0 ... 2: - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - break; - case 3: - /* XLEN check done in amo_check(). */ - assert(seq < ARRAY_SIZE(fnsd)); - fn = fnsd[seq]; - break; - default: - g_assert_not_reached(); - } - - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, WD, a->wd); - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} -/* - * There are two rules check here. - * - * 1. SEW must be at least as wide as the AMO memory element size. - * - * 2. If SEW is greater than XLEN, an illegal instruction exception is raised. - */ -static bool amo_check(DisasContext *s, arg_rwdvm* a) -{ - return (!s->vill && has_ext(s, RVA) && - (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <= sizeof(target_ulong)) && - ((1 << s->sew) >= 4)); -} - -static bool amo_check64(DisasContext *s, arg_rwdvm* a) -{ - REQUIRE_64BIT(s); - return amo_check(s, a); -} - -GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64) - /* *** Vector Integer Arithmetic Instructions */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index db1a40a3db..bf976d364f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -103,11 +103,6 @@ static inline int32_t vext_lmul(uint32_t desc) return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); } -static uint32_t vext_wd(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, WD); -} - /* * Get vector group length in bytes. Its range is [64, 2048]. * @@ -633,38 +628,12 @@ GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d) GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w) GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d) -/* - *** Vector AMO Operations (Zvamo) - */ -typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, - uint32_t wd, uint32_t idx, CPURISCVState *env, - uintptr_t retaddr); - -/* no atomic opreation for vector atomic insructions */ #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) #define DO_XOR(N, M) (N ^ M) #define DO_OR(N, M) (N | M) #define DO_ADD(N, M) (N + M) -#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \ -static void \ -vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \ - uint32_t wd, uint32_t idx, \ - CPURISCVState *env, uintptr_t retaddr)\ -{ \ - typedef int##ESZ##_t ETYPE; \ - typedef int##MSZ##_t MTYPE; \ - typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \ - ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \ - MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \ - \ - cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \ - if (wd) { \ - *pe3 = a; \ - } \ -} - /* Signed min/max */ #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) @@ -673,100 +642,6 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \ #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) - -static inline void -vext_amo_noatomic(void *vs3, void *v0, target_ulong base, - void *vs2, CPURISCVState *env, uint32_t desc, - vext_get_index_addr get_index_addr, - vext_amo_noatomic_fn *noatomic_op, - uint32_t esz, uint32_t msz, uintptr_t ra) -{ - uint32_t i; - target_long addr; - uint32_t wd = vext_wd(desc); - uint32_t vm = vext_vm(desc); - - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD); - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE); - } - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } - addr = get_index_addr(base, i, vs2); - noatomic_op(vs3, addr, wd, i, env, ra); - } -} - -#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN) \ -void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ -{ \ - vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \ - INDEX_FN, vext_##NAME##_noatomic_op, \ - sizeof(ETYPE), sizeof(MTYPE), \ - GETPC()); \ -} - -GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d) -GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d) -GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d) -GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d) -GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d) -GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d) -GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w) -GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w) -GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w) - /* *** Vector Integer Arithmetic Instructions */ From d9b7609a1fb237dd05fac4cfe5163429115c9c6d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:05 +0800 Subject: [PATCH 353/421] target/riscv: rvv-1.0: configure instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-20-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 64 +++++++++++-------------- target/riscv/vector_helper.c | 14 +++++- 2 files changed, 41 insertions(+), 37 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index afec187333..049688d83a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -120,59 +120,51 @@ static bool require_noover(const int8_t dst, const int8_t dst_lmul, return !is_overlapped(dst, dst_size, src, src_size); } -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) +static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) { - TCGv s1, s2, dst; + TCGv s1, dst; - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { + if (!require_rvv(s) || !has_ext(s, RVV)) { return false; } - s2 = get_gpr(ctx, a->rs2, EXT_ZERO); - dst = dest_gpr(ctx, a->rd); + dst = dest_gpr(s, rd); - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 == 0) { + if (rd == 0 && rs1 == 0) { + s1 = tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (rs1 == 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ s1 = tcg_constant_tl(RV_VLEN_MAX); } else { - s1 = get_gpr(ctx, a->rs1, EXT_ZERO); + s1 = get_gpr(s, rs1, EXT_ZERO); } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - mark_vs_dirty(ctx); - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(s, rd, dst); + mark_vs_dirty(s); + + tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; + + if (rd == 0 && rs1 == 0) { + tcg_temp_free(s1); + } + return true; } -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) { - TCGv s1, s2, dst; + TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO); + return do_vsetvl(s, a->rd, a->rs1, s2); +} - if (!require_rvv(ctx) || !has_ext(ctx, RVV)) { - return false; - } - - s2 = tcg_constant_tl(a->zimm); - dst = dest_gpr(ctx, a->rd); - - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 == 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ - s1 = tcg_constant_tl(RV_VLEN_MAX); - } else { - s1 = get_gpr(ctx, a->rs1, EXT_ZERO); - } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - mark_vs_dirty(ctx); - - gen_goto_tb(ctx, 0, ctx->pc_succ_insn); - ctx->base.is_jmp = DISAS_NORETURN; - return true; +static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a) +{ + TCGv s2 = tcg_constant_tl(a->zimm); + return do_vsetvl(s, a->rd, a->rs1, s2); } /* vector register offset from env */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bf976d364f..78fae78284 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, { int vlmax, vl; RISCVCPU *cpu = env_archcpu(env); + uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL); uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); bool vill = FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED); - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { + if (lmul & 4) { + /* Fractional LMUL. */ + if (lmul == 4 || + cpu->cfg.elen >> (8 - lmul) < sew) { + vill = true; + } + } + + if ((sew > cpu->cfg.elen) + || vill + || (ediv != 0) + || (reserved != 0)) { /* only set vill bit. */ env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); env->vl = 0; From 79556fb6fa067922fb11d2a1209852900109c7ae Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:06 +0800 Subject: [PATCH 354/421] target/riscv: rvv-1.0: stride load and store instructions Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-21-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 129 ++------ target/riscv/insn32.decode | 43 ++- target/riscv/insn_trans/trans_rvv.c.inc | 376 ++++++++++++------------ target/riscv/vector_helper.c | 179 ++++------- 4 files changed, 290 insertions(+), 437 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index ecb6af6cd9..5a760fa4a3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -112,111 +112,30 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) /* Vector functions */ DEF_HELPER_3(vsetvl, tl, env, tl, tl) -DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3d57255fff..2d8f0cbe7c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -294,13 +294,26 @@ hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm -vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm -vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm -vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm -vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm +# Vector unit-stride load/store insns. +vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm +vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm +vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm +vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm +vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm +vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm +vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm +vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm + +# Vector strided insns. +vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm +vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm +vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm +vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm +vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm +vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm +vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm +vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm + vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm @@ -308,22 +321,6 @@ vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm -vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm -vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm -vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm - -vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm -vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm -vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm -vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm -vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm -vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm -vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm -vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm -vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm -vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm -vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 049688d83a..8a4f75f724 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -73,6 +73,12 @@ static bool require_vm(int vm, int vd) return (vm != 0 || vd != 0); } +static bool require_nf(int vd, int nf, int lmul) +{ + int size = nf << MAX(lmul, 0); + return size <= 8 && vd + size <= 32; +} + /* * Vector register should aligned with the passed-in LMUL (EMUL). * If LMUL < 0, i.e. fractional LMUL, any vector register is allowed. @@ -175,6 +181,115 @@ static uint32_t vreg_ofs(DisasContext *s, int reg) /* check functions */ +/* + * Vector unit-stride, strided, unit-stride segment, strided segment + * store check function. + * + * Rules to be checked here: + * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3) + * 2. Destination vector register number is multiples of EMUL. + * (Section 3.4.2, 7.3) + * 3. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8) + * 4. Vector register numbers accessed by the segment load or store + * cannot increment past 31. (Section 7.8) + */ +static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew) +{ + int8_t emul = eew - s->sew + s->lmul; + return (emul >= -3 && emul <= 3) && + require_align(vd, emul) && + require_nf(vd, nf, emul); +} + +/* + * Vector unit-stride, strided, unit-stride segment, strided segment + * load check function. + * + * Rules to be checked here: + * 1. All rules applies to store instructions are applies + * to load instructions. + * 2. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_check_load(DisasContext *s, int vd, int nf, int vm, + uint8_t eew) +{ + return vext_check_store(s, vd, nf, eew) && require_vm(vm, vd); +} + +/* + * Vector indexed, indexed segment store check function. + * + * Rules to be checked here: + * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3) + * 2. Index vector register number is multiples of EMUL. + * (Section 3.4.2, 7.3) + * 3. Destination vector register number is multiples of LMUL. + * (Section 3.4.2, 7.3) + * 4. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8) + * 5. Vector register numbers accessed by the segment load or store + * cannot increment past 31. (Section 7.8) + */ +static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, + uint8_t eew) +{ + int8_t emul = eew - s->sew + s->lmul; + return (emul >= -3 && emul <= 3) && + require_align(vs2, emul) && + require_align(vd, s->lmul) && + require_nf(vd, nf, s->lmul); +} + +/* + * Vector indexed, indexed segment load check function. + * + * Rules to be checked here: + * 1. All rules applies to store instructions are applies + * to load instructions. + * 2. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 3. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + * 4. Destination vector register groups cannot overlap + * the source vector register (vs2) group for + * indexed segment load instructions. (Section 7.8.3) + */ +static bool vext_check_ld_index(DisasContext *s, int vd, int vs2, + int nf, int vm, uint8_t eew) +{ + int8_t seg_vd; + int8_t emul = eew - s->sew + s->lmul; + bool ret = vext_check_st_index(s, vd, vs2, nf, eew) && + require_vm(vm, vd); + + /* Each segment register group has to follow overlap rules. */ + for (int i = 0; i < nf; ++i) { + seg_vd = vd + (1 << MAX(s->lmul, 0)) * i; + + if (eew > s->sew) { + if (seg_vd != vs2) { + ret &= require_noover(seg_vd, s->lmul, vs2, emul); + } + } else if (eew < s->sew) { + ret &= require_noover(seg_vd, s->lmul, vs2, emul); + } + + /* + * Destination vector register groups cannot overlap + * the source vector register (vs2) group for + * indexed segment load instructions. + */ + if (nf > 1) { + ret &= !is_overlapped(seg_vd, 1 << MAX(s->lmul, 0), + vs2, 1 << MAX(emul, 0)); + } + } + return ret; +} + static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) { return require_vm(vm, vd) && @@ -415,63 +530,14 @@ static bool vext_check_isa_ill(DisasContext *s) return !s->vill; } -/* - * There are two rules check here. - * - * 1. Vector register numbers are multiples of LMUL. (Section 3.2) - * - * 2. For all widening instructions, the destination LMUL value must also be - * a supported LMUL value. (Section 11.2) - */ -static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen) -{ - /* - * The destination vector register group results are arranged as if both - * SEW and LMUL were at twice their current settings. (Section 11.2). - */ - int legal = widen ? 2 << s->lmul : 1 << s->lmul; - - return !((s->lmul == 0x3 && widen) || (reg % legal)); -} - -/* - * There are two rules check here. - * - * 1. The destination vector register group for a masked vector instruction can - * only overlap the source mask register (v0) when LMUL=1. (Section 5.3) - * - * 2. In widen instructions and some other insturctions, like vslideup.vx, - * there is no need to check whether LMUL=1. - */ -static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm, - bool force) -{ - return (vm != 0 || vd != 0) || (!force && (s->lmul == 0)); -} - -/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */ -static bool vext_check_nf(DisasContext *s, uint32_t nf) -{ - return (1 << s->lmul) * nf <= 8; -} - -/* - * The destination vector register group cannot overlap a source vector register - * group of a different element width. (Section 11.2) - */ -static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen) -{ - return ((rd >= rs + slen) || (rs >= rd + dlen)); -} - /* common translation macro */ -#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ -{ \ - if (CHECK(s, a)) { \ - return OP(s, a, SEQ); \ - } \ - return false; \ +#define GEN_VEXT_TRANS(NAME, EEW, ARGTYPE, OP, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \ +{ \ + if (CHECK(s, a, EEW)) { \ + return OP(s, a, EEW); \ + } \ + return false; \ } /* @@ -520,44 +586,20 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, return true; } -static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][7][4] = { + static gen_helper_ldst_us * const fns[2][4] = { /* masked unit stride load */ - { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask, - gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask }, - { NULL, gen_helper_vlh_v_h_mask, - gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask }, - { NULL, NULL, - gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask }, - { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask, - gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask }, - { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask, - gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask }, - { NULL, gen_helper_vlhu_v_h_mask, - gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask }, - { NULL, NULL, - gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } }, + { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask, + gen_helper_vle32_v_mask, gen_helper_vle64_v_mask }, /* unmasked unit stride load */ - { { gen_helper_vlb_v_b, gen_helper_vlb_v_h, - gen_helper_vlb_v_w, gen_helper_vlb_v_d }, - { NULL, gen_helper_vlh_v_h, - gen_helper_vlh_v_w, gen_helper_vlh_v_d }, - { NULL, NULL, - gen_helper_vlw_v_w, gen_helper_vlw_v_d }, - { gen_helper_vle_v_b, gen_helper_vle_v_h, - gen_helper_vle_v_w, gen_helper_vle_v_d }, - { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h, - gen_helper_vlbu_v_w, gen_helper_vlbu_v_d }, - { NULL, gen_helper_vlhu_v_h, - gen_helper_vlhu_v_w, gen_helper_vlhu_v_d }, - { NULL, NULL, - gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } } + { gen_helper_vle8_v, gen_helper_vle16_v, + gen_helper_vle32_v, gen_helper_vle64_v } }; - fn = fns[a->vm][seq][s->sew]; + fn = fns[a->vm][eew]; if (fn == NULL) { return false; } @@ -568,48 +610,32 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } -static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) +static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_load(s, a->rd, a->nf, a->vm, eew); } -GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle8_v, MO_8, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle16_v, MO_16, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle32_v, MO_32, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle64_v, MO_64, r2nfvm, ld_us_op, ld_us_check) -static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][4][4] = { - /* masked unit stride load and store */ - { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask, - gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask }, - { NULL, gen_helper_vsh_v_h_mask, - gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask }, - { NULL, NULL, - gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask }, - { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask, - gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } }, + static gen_helper_ldst_us * const fns[2][4] = { + /* masked unit stride store */ + { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask, + gen_helper_vse32_v_mask, gen_helper_vse64_v_mask }, /* unmasked unit stride store */ - { { gen_helper_vsb_v_b, gen_helper_vsb_v_h, - gen_helper_vsb_v_w, gen_helper_vsb_v_d }, - { NULL, gen_helper_vsh_v_h, - gen_helper_vsh_v_w, gen_helper_vsh_v_d }, - { NULL, NULL, - gen_helper_vsw_v_w, gen_helper_vsw_v_d }, - { gen_helper_vse_v_b, gen_helper_vse_v_h, - gen_helper_vse_v_w, gen_helper_vse_v_d } } + { gen_helper_vse8_v, gen_helper_vse16_v, + gen_helper_vse32_v, gen_helper_vse64_v } }; - fn = fns[a->vm][seq][s->sew]; + fn = fns[a->vm][eew]; if (fn == NULL) { return false; } @@ -620,17 +646,17 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } -static bool st_us_check(DisasContext *s, arg_r2nfvm* a) +static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_store(s, a->rd, a->nf, eew); } -GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse8_v, MO_8, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check) /* *** stride load and store @@ -671,28 +697,16 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, return true; } -static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[7][4] = { - { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h, - gen_helper_vlsb_v_w, gen_helper_vlsb_v_d }, - { NULL, gen_helper_vlsh_v_h, - gen_helper_vlsh_v_w, gen_helper_vlsh_v_d }, - { NULL, NULL, - gen_helper_vlsw_v_w, gen_helper_vlsw_v_d }, - { gen_helper_vlse_v_b, gen_helper_vlse_v_h, - gen_helper_vlse_v_w, gen_helper_vlse_v_d }, - { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h, - gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d }, - { NULL, gen_helper_vlshu_v_h, - gen_helper_vlshu_v_w, gen_helper_vlshu_v_d }, - { NULL, NULL, - gen_helper_vlswu_v_w, gen_helper_vlswu_v_d }, + static gen_helper_ldst_stride * const fns[4] = { + gen_helper_vlse8_v, gen_helper_vlse16_v, + gen_helper_vlse32_v, gen_helper_vlse64_v }; - fn = fns[seq][s->sew]; + fn = fns[eew]; if (fn == NULL) { return false; } @@ -703,42 +717,32 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } -static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) +static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_load(s, a->rd, a->nf, a->vm, eew); } -GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse8_v, MO_8, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse16_v, MO_16, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse32_v, MO_32, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check) -static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[4][4] = { + static gen_helper_ldst_stride * const fns[4] = { /* masked stride store */ - { gen_helper_vssb_v_b, gen_helper_vssb_v_h, - gen_helper_vssb_v_w, gen_helper_vssb_v_d }, - { NULL, gen_helper_vssh_v_h, - gen_helper_vssh_v_w, gen_helper_vssh_v_d }, - { NULL, NULL, - gen_helper_vssw_v_w, gen_helper_vssw_v_d }, - { gen_helper_vsse_v_b, gen_helper_vsse_v_h, - gen_helper_vsse_v_w, gen_helper_vsse_v_d } + gen_helper_vsse8_v, gen_helper_vsse16_v, + gen_helper_vsse32_v, gen_helper_vsse64_v }; data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - fn = fns[seq][s->sew]; + fn = fns[eew]; if (fn == NULL) { return false; } @@ -746,17 +750,17 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } -static bool st_stride_check(DisasContext *s, arg_rnfvm* a) +static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_store(s, a->rd, a->nf, eew); } -GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse8_v, MO_8, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse16_v, MO_16, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse32_v, MO_32, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse64_v, MO_64, rnfvm, st_stride_op, st_stride_check) /* *** index load and store @@ -836,16 +840,11 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) * groups cannot overlap the source vector register group (specified by * `vs2`), else an illegal instruction exception is raised. */ -static bool ld_index_check(DisasContext *s, arg_rnfvm* a) +static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf) && - ((a->nf == 1) || - vext_check_overlap_group(a->rd, a->nf << s->lmul, - a->rs2, 1 << s->lmul))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew); } GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) @@ -882,12 +881,11 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } -static bool st_index_check(DisasContext *s, arg_rnfvm* a) +static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_st_index(s, a->rd, a->rs2, a->nf, eew); } GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 78fae78284..9141292994 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -178,38 +178,36 @@ static inline int vext_elem_mask(void *v0, int index) typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); -#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \ +#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr)\ { \ - MTYPE data; \ ETYPE *cur = ((ETYPE *)vd + H(idx)); \ - data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ - *cur = data; \ + *cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ } \ -GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb) -GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb) -GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb) -GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw) -GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw) -GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl) -GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq) -GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub) -GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub) -GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub) -GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw) -GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw) -GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl) +GEN_VEXT_LD_ELEM(ldb_b, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(ldb_h, int16_t, H2, ldsb) +GEN_VEXT_LD_ELEM(ldb_w, int32_t, H4, ldsb) +GEN_VEXT_LD_ELEM(ldb_d, int64_t, H8, ldsb) +GEN_VEXT_LD_ELEM(ldh_h, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(ldh_w, int32_t, H4, ldsw) +GEN_VEXT_LD_ELEM(ldh_d, int64_t, H8, ldsw) +GEN_VEXT_LD_ELEM(ldw_w, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(ldw_d, int64_t, H8, ldl) +GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) +GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, H1, ldub) +GEN_VEXT_LD_ELEM(ldbu_h, uint16_t, H2, ldub) +GEN_VEXT_LD_ELEM(ldbu_w, uint32_t, H4, ldub) +GEN_VEXT_LD_ELEM(ldbu_d, uint64_t, H8, ldub) +GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, H2, lduw) +GEN_VEXT_LD_ELEM(ldhu_w, uint32_t, H4, lduw) +GEN_VEXT_LD_ELEM(ldhu_d, uint64_t, H8, lduw) +GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, H4, ldl) +GEN_VEXT_LD_ELEM(ldwu_d, uint64_t, H8, ldl) #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ @@ -241,8 +239,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, vext_ldst_elem_fn *ldst_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); @@ -253,7 +250,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, base + stride * i, nf * msz, ra, access_type); + probe_pages(env, base + stride * i, nf * esz, ra, access_type); } /* do real access */ for (i = 0; i < env->vl; i++) { @@ -262,71 +259,42 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - target_ulong addr = base + stride * i + k * msz; + target_ulong addr = base + stride * i + k * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } } } -#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN) \ +#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ - sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_LOAD); \ + sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b) -GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h) -GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w) -GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d) -GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h) -GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w) -GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d) -GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w) -GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d) -GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b) -GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h) -GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w) -GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d) -GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b) -GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h) -GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w) -GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d) -GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h) -GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w) -GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d) -GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w) -GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d) +GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b) +GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h) +GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w) +GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d) -#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \ +#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ - sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_STORE); \ + sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ } -GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b) -GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h) -GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w) -GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d) -GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h) -GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w) -GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d) -GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w) -GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d) -GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b) -GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h) -GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w) -GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) +GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) +GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h) +GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) +GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) /* *** unit-stride: access elements stored contiguously in memory @@ -335,20 +303,20 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) /* unmasked unit-stride load and store operation*/ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t msz, - uintptr_t ra, MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t vlmax = vext_maxsz(desc) / esz; /* probe every access */ - probe_pages(env, base, env->vl * nf * msz, ra, access_type); + probe_pages(env, base, env->vl * nf * esz, ra, access_type); /* load bytes from guest memory */ for (i = 0; i < env->vl; i++) { k = 0; while (k < nf) { - target_ulong addr = base + (i * nf + k) * msz; + target_ulong addr = base + (i * nf + k) * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } @@ -360,76 +328,47 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, * stride = NF * sizeof (MTYPE) */ -#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN) \ +#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ + uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_LOAD); \ + sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, LOAD_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \ + sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b) -GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h) -GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w) -GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d) -GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h) -GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w) -GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d) -GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w) -GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d) -GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b) -GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h) -GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w) -GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d) -GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b) -GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h) -GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w) -GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d) -GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h) -GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w) -GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d) -GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w) -GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d) +GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) +GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) +GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) +GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) -#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \ +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ + uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_STORE); \ + sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, STORE_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\ + sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ } -GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b) -GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h) -GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w) -GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d) -GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h) -GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w) -GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d) -GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w) -GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d) -GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b) -GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h) -GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w) -GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d) +GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) +GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) +GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) +GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) /* *** index: access vector element from indexed memory From 08b9d0ed4aaff095a940280eba1321e3414dd5ac Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:07 +0800 Subject: [PATCH 355/421] target/riscv: rvv-1.0: index load and store instructions Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-22-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 67 +++++++-------- target/riscv/insn32.decode | 21 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 110 +++++++++++++----------- target/riscv/vector_helper.c | 92 +++++++++----------- 4 files changed, 142 insertions(+), 148 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5a760fa4a3..1beca6dc0d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -136,41 +136,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2d8f0cbe7c..f34194d31c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -322,18 +322,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm -vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm -vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm -vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm -vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm -vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm -vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm +# Vector ordered-indexed and unordered-indexed load insns. +vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm +vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm +vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm +vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm + # Vector ordered-indexed and unordered-indexed store insns. -vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm -vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm -vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm -vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm +vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm +vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm +vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm +vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm # *** new major opcode OP-V *** vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 8a4f75f724..6946d03340 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -803,31 +803,38 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, return true; } -static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_index *fn; - static gen_helper_ldst_index * const fns[7][4] = { - { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h, - gen_helper_vlxb_v_w, gen_helper_vlxb_v_d }, - { NULL, gen_helper_vlxh_v_h, - gen_helper_vlxh_v_w, gen_helper_vlxh_v_d }, - { NULL, NULL, - gen_helper_vlxw_v_w, gen_helper_vlxw_v_d }, - { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h, - gen_helper_vlxe_v_w, gen_helper_vlxe_v_d }, - { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h, - gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d }, - { NULL, gen_helper_vlxhu_v_h, - gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d }, - { NULL, NULL, - gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d }, + static gen_helper_ldst_index * const fns[4][4] = { + /* + * offset vector register group EEW = 8, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v, + gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v }, + /* + * offset vector register group EEW = 16, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v, + gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v }, + /* + * offset vector register group EEW = 32, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v, + gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v }, + /* + * offset vector register group EEW = 64, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v, + gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v } }; - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } + fn = fns[eew][s->sew]; data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -835,11 +842,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } -/* - * For vector indexed segment loads, the destination vector register - * groups cannot overlap the source vector register group (specified by - * `vs2`), else an illegal instruction exception is raised. - */ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { return require_rvv(s) && @@ -847,33 +849,43 @@ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew); } -GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei8_v, MO_8, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei16_v, MO_16, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei32_v, MO_32, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check) -static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_index *fn; static gen_helper_ldst_index * const fns[4][4] = { - { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h, - gen_helper_vsxb_v_w, gen_helper_vsxb_v_d }, - { NULL, gen_helper_vsxh_v_h, - gen_helper_vsxh_v_w, gen_helper_vsxh_v_d }, - { NULL, NULL, - gen_helper_vsxw_v_w, gen_helper_vsxw_v_d }, - { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h, - gen_helper_vsxe_v_w, gen_helper_vsxe_v_d } + /* + * offset vector register group EEW = 8, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v, + gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v }, + /* + * offset vector register group EEW = 16, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v, + gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v }, + /* + * offset vector register group EEW = 32, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v, + gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v }, + /* + * offset vector register group EEW = 64, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v, + gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v } }; - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } + fn = fns[eew][s->sew]; data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -888,10 +900,10 @@ static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) vext_check_st_index(s, a->rd, a->rs2, a->nf, eew); } -GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei8_v, MO_8, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei16_v, MO_16, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei32_v, MO_32, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check) /* *** unit stride fault-only-first load diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9141292994..df45c1620c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -217,15 +217,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \ cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ } -GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb) -GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb) -GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb) -GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb) -GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw) -GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw) -GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw) -GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl) -GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl) GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) @@ -393,8 +384,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_ldst_elem_fn *ldst_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); @@ -406,7 +396,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, + probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra, access_type); } /* load bytes from guest memory */ @@ -416,67 +406,63 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - abi_ptr addr = get_index_addr(base, i, vs2) + k * msz; + abi_ptr addr = get_index_addr(base, i, vs2) + k * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } } } -#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \ +#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_LOAD); \ + LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b) -GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h) -GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w) -GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d) -GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h) -GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w) -GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d) -GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w) -GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d) -GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b) -GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h) -GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w) -GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d) -GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b) -GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h) -GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w) -GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d) -GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h) -GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w) -GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d) -GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w) -GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d) +GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b) +GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h) +GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w) +GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d) +GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b) +GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h) +GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w) +GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d) +GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b) +GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h) +GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w) +GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d) +GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b) +GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h) +GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w) +GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d) -#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\ +#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \ + STORE_FN, sizeof(ETYPE), \ GETPC(), MMU_DATA_STORE); \ } -GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b) -GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h) -GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w) -GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d) -GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h) -GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w) -GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d) -GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w) -GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d) -GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b) -GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h) -GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w) -GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d) +GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b) +GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h) +GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w) +GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d) +GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b) +GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h) +GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w) +GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d) +GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b) +GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h) +GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w) +GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d) +GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b) +GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h) +GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w) +GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) /* *** unit-stride fault-only-fisrt load instructions From 83fcd573b121939e850d9a9836e24298d189aa79 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:08 +0800 Subject: [PATCH 356/421] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-23-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index df45c1620c..3da4f3b1e6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -374,10 +374,10 @@ static target_ulong NAME(target_ulong base, \ return (base + *((ETYPE *)vs2 + H(idx))); \ } -GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1) -GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2) -GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4) -GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8) +GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1) +GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2) +GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4) +GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8) static inline void vext_ldst_index(void *vd, void *v0, target_ulong base, From d3e5e2ff4fefde240120afaf86b032de19b0c722 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:09 +0800 Subject: [PATCH 357/421] target/riscv: rvv-1.0: fault-only-first unit stride load Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-24-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 26 ++------- target/riscv/insn32.decode | 14 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 33 ++++-------- target/riscv/vector_helper.c | 70 ++++++------------------- 4 files changed, 36 insertions(+), 107 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1beca6dc0d..57560b8c04 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -168,28 +168,10 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f34194d31c..180d97ecba 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -314,14 +314,6 @@ vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm -vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm -vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm -vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm -vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm -vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm -vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm - # Vector ordered-indexed and unordered-indexed load insns. vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm @@ -334,6 +326,12 @@ vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm +# Vector unit-stride fault-only-first load insns. +vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm +vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm +vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm +vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm + # *** new major opcode OP-V *** vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 6946d03340..5b5285b33f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -935,28 +935,16 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, return true; } -static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[7][4] = { - { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h, - gen_helper_vlbff_v_w, gen_helper_vlbff_v_d }, - { NULL, gen_helper_vlhff_v_h, - gen_helper_vlhff_v_w, gen_helper_vlhff_v_d }, - { NULL, NULL, - gen_helper_vlwff_v_w, gen_helper_vlwff_v_d }, - { gen_helper_vleff_v_b, gen_helper_vleff_v_h, - gen_helper_vleff_v_w, gen_helper_vleff_v_d }, - { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h, - gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d }, - { NULL, gen_helper_vlhuff_v_h, - gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d }, - { NULL, NULL, - gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d } + static gen_helper_ldst_us * const fns[4] = { + gen_helper_vle8ff_v, gen_helper_vle16ff_v, + gen_helper_vle32ff_v, gen_helper_vle64ff_v }; - fn = fns[seq][s->sew]; + fn = fns[eew]; if (fn == NULL) { return false; } @@ -967,13 +955,10 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) return ldff_trans(a->rd, a->rs1, data, fn, s); } -GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle8ff_v, MO_8, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check) /* *** Vector Integer Arithmetic Instructions diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 3da4f3b1e6..0e7bf5d27f 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -186,28 +186,10 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \ *cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ } \ -GEN_VEXT_LD_ELEM(ldb_b, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(ldb_h, int16_t, H2, ldsb) -GEN_VEXT_LD_ELEM(ldb_w, int32_t, H4, ldsb) -GEN_VEXT_LD_ELEM(ldb_d, int64_t, H8, ldsb) -GEN_VEXT_LD_ELEM(ldh_h, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(ldh_w, int32_t, H4, ldsw) -GEN_VEXT_LD_ELEM(ldh_d, int64_t, H8, ldsw) -GEN_VEXT_LD_ELEM(ldw_w, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldw_d, int64_t, H8, ldl) GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) -GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(ldbu_h, uint16_t, H2, ldub) -GEN_VEXT_LD_ELEM(ldbu_w, uint32_t, H4, ldub) -GEN_VEXT_LD_ELEM(ldbu_d, uint64_t, H8, ldub) -GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(ldhu_w, uint32_t, H4, lduw) -GEN_VEXT_LD_ELEM(ldhu_d, uint64_t, H8, lduw) -GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldwu_d, uint64_t, H8, ldl) #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ @@ -471,7 +453,7 @@ static inline void vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc, vext_ldst_elem_fn *ldst_elem, - uint32_t esz, uint32_t msz, uintptr_t ra) + uint32_t esz, uintptr_t ra) { void *host; uint32_t i, k, vl = 0; @@ -485,24 +467,24 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - addr = base + nf * i * msz; + addr = base + nf * i * esz; if (i == 0) { - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD); } else { /* if it triggers an exception, no need to check watchpoint */ - remain = nf * msz; + remain = nf * esz; while (remain > 0) { offset = -(addr | TARGET_PAGE_MASK); host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + if (page_check_range(addr, nf * esz, PAGE_READ) < 0) { vl = i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD); #endif } else { vl = i; @@ -527,43 +509,25 @@ ProbeSuccess: continue; } while (k < nf) { - target_ulong addr = base + (i * nf + k) * msz; + target_ulong addr = base + (i * nf + k) * esz; ldst_elem(env, addr, i + k * vlmax, vd, ra); k++; } } } -#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ +#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ + sizeof(ETYPE), GETPC()); \ } -GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b) -GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h) -GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w) -GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d) -GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h) -GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w) -GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d) -GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w) -GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d) -GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b) -GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h) -GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w) -GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d) -GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b) -GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h) -GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w) -GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d) -GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h) -GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w) -GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d) -GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w) -GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d) +GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b) +GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h) +GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w) +GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) From 30206bd8421d6ca17ba762ec18b039b12fcf6c9d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:10 +0800 Subject: [PATCH 358/421] target/riscv: rvv-1.0: load/store whole register instructions Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-25-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 21 ++++++++ target/riscv/insn32.decode | 22 ++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 68 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 65 +++++++++++++++++++++++ 4 files changed, 176 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 57560b8c04..b8894d6151 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -173,6 +173,27 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_4(vl1re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl1re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl1re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl1re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs2r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs4r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs8r_v, void, ptr, tl, env, i32) + DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 180d97ecba..7d8441d1f2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -332,6 +332,28 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm +# Vector whole register insns +vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 +vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 +vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 +vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 +vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 +vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 +vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 +vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 +vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 +vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 +vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 +vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 +vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 +vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 +vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 +vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 +vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 +vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 +vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 +vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 + # *** new major opcode OP-V *** vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5b5285b33f..5e8e49d43f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -960,6 +960,74 @@ GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check) GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check) +/* + * load and store whole register instructions + */ +typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); + +static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, + gen_helper_ldst_whole *fn, DisasContext *s, + bool is_store) +{ + TCGv_ptr dest; + TCGv base; + TCGv_i32 desc; + + uint32_t data = FIELD_DP32(0, VDATA, NF, nf); + dest = tcg_temp_new_ptr(); + desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + + base = get_gpr(s, rs1, EXT_NONE); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + + fn(dest, base, cpu_env, desc); + + tcg_temp_free_ptr(dest); + + if (!is_store) { + mark_vs_dirty(s); + } + + return true; +} + +/* + * load and store whole register instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 7.9) + */ +#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \ + return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \ + s, IS_STORE); \ + } \ + return false; \ +} + +GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, false) +GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false) +GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false) +GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false) + +GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true) +GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true) +GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true) +GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) + /* *** Vector Integer Arithmetic Instructions */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 0e7bf5d27f..9a39a0e2d2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -543,6 +543,71 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) +/* + *** load and store whole register instructions + */ +static void +vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra, + MMUAccessType access_type) +{ + uint32_t i, k; + uint32_t nf = vext_nf(desc); + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + uint32_t max_elems = vlenb >> esz; + + /* probe every access */ + probe_pages(env, base, vlenb * nf, ra, access_type); + + /* load bytes from guest memory */ + for (k = 0; k < nf; k++) { + for (i = 0; i < max_elems; i++) { + target_ulong addr = base + ((i + k * max_elems) << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); + } + } +} + +#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, LOAD_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), \ + MMU_DATA_LOAD); \ +} + +GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d) + +#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, STORE_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), \ + MMU_DATA_STORE); \ +} + +GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b) +GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b) +GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b) +GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) + /* *** Vector Integer Arithmetic Instructions */ From 5a9f8e15522819c3315544de5b13ca3a058a3132 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:11 +0800 Subject: [PATCH 359/421] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-26-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 ++++++-- target/riscv/vector_helper.c | 99 ++++++++++++++----------- 2 files changed, 80 insertions(+), 51 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5e8e49d43f..e12db9aae8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -540,6 +540,12 @@ static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \ return false; \ } +static uint8_t vext_get_emul(DisasContext *s, uint8_t eew) +{ + int8_t emul = eew - s->sew + s->lmul; + return emul < 0 ? 0 : emul; +} + /* *** unit stride load and store */ @@ -604,8 +610,14 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) return false; } + /* + * Vector load/store instructions have the EEW encoded + * directly in the instructions. The maximum vector size is + * calculated with EMUL rather than LMUL. + */ + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } @@ -640,8 +652,9 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) return false; } + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } @@ -711,8 +724,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) return false; } + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } @@ -739,8 +753,9 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) gen_helper_vsse32_v, gen_helper_vsse64_v }; + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); fn = fns[eew]; if (fn == NULL) { @@ -836,8 +851,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) fn = fns[eew][s->sew]; + uint8_t emul = vext_get_emul(s, s->sew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } @@ -887,8 +903,9 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) fn = fns[eew][s->sew]; + uint8_t emul = vext_get_emul(s, s->sew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } @@ -949,8 +966,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) return false; } + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldff_trans(a->rd, a->rs1, data, fn, s); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9a39a0e2d2..f9919273dc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -17,6 +17,7 @@ */ #include "qemu/osdep.h" +#include "qemu/host-utils.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -116,14 +117,21 @@ static inline int32_t vext_lmul(uint32_t desc) } /* - * Get vector group length in bytes. Its range is [64, 2048]. + * Get the maximum number of elements can be operated. * - * As simd_desc support at most 256, the max vlen is 512 bits. - * So vlen in bytes is encoded as maxsz. + * esz: log2 of element size in bytes. */ -static inline uint32_t vext_maxsz(uint32_t desc) +static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz) { - return simd_maxsz(desc) << vext_lmul(desc); + /* + * As simd_desc support at most 256 bytes, the max vlen is 256 bits. + * so vlen in bytes (vlenb) is encoded as maxsz. + */ + uint32_t vlenb = simd_maxsz(desc); + + /* Return VLMAX */ + int scale = vext_lmul(desc) - esz; + return scale < 0 ? vlenb >> -scale : vlenb << scale; } /* @@ -216,14 +224,14 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); /* probe every access*/ for (i = 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, base + stride * i, nf * esz, ra, access_type); + probe_pages(env, base + stride * i, nf << esz, ra, access_type); } /* do real access */ for (i = 0; i < env->vl; i++) { @@ -232,8 +240,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - target_ulong addr = base + stride * i + k * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + target_ulong addr = base + stride * i + (k << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -246,7 +254,7 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ - sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b) @@ -261,7 +269,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ - sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ } GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) @@ -281,16 +289,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); /* probe every access */ - probe_pages(env, base, env->vl * nf * esz, ra, access_type); + probe_pages(env, base, env->vl * (nf << esz), ra, access_type); /* load bytes from guest memory */ for (i = 0; i < env->vl; i++) { k = 0; while (k < nf) { - target_ulong addr = base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + target_ulong addr = base + ((i * nf + k) << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -305,16 +313,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \ + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, LOAD_FN, \ - sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) @@ -326,16 +334,16 @@ GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \ + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, STORE_FN, \ - sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ } GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) @@ -371,14 +379,14 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); /* probe every access*/ for (i = 0; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra, + probe_pages(env, get_index_addr(base, i, vs2), nf << esz, ra, access_type); } /* load bytes from guest memory */ @@ -388,8 +396,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, continue; } while (k < nf) { - abi_ptr addr = get_index_addr(base, i, vs2) + k * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -400,7 +408,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ + LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b) @@ -425,7 +433,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - STORE_FN, sizeof(ETYPE), \ + STORE_FN, ctzl(sizeof(ETYPE)), \ GETPC(), MMU_DATA_STORE); \ } @@ -459,7 +467,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t i, k, vl = 0; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); target_ulong addr, offset, remain; /* probe every access*/ @@ -467,24 +475,24 @@ vext_ldff(void *vd, void *v0, target_ulong base, if (!vm && !vext_elem_mask(v0, i)) { continue; } - addr = base + nf * i * esz; + addr = base + i * (nf << esz); if (i == 0) { - probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD); } else { /* if it triggers an exception, no need to check watchpoint */ - remain = nf * esz; + remain = nf << esz; while (remain > 0) { offset = -(addr | TARGET_PAGE_MASK); host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * esz, PAGE_READ) < 0) { + if (page_check_range(addr, nf << esz, PAGE_READ) < 0) { vl = i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD); #endif } else { vl = i; @@ -509,8 +517,8 @@ ProbeSuccess: continue; } while (k < nf) { - target_ulong addr = base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + target_ulong addr = base + ((i * nf + k) << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -521,7 +529,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ - sizeof(ETYPE), GETPC()); \ + ctzl(sizeof(ETYPE)), GETPC()); \ } GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b) @@ -986,7 +994,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, \ + ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1016,7 +1025,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1190,7 +1199,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, \ + ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1242,7 +1252,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -3644,7 +3654,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, \ + ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -3671,7 +3682,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -4457,7 +4468,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index; \ @@ -4486,7 +4497,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index = s1; \ From a689a82b7fe65d1e09d27f7af1aead8a3ef471ce Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:12 +0800 Subject: [PATCH 360/421] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-27-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 27 ++++++++++++++++--------- target/riscv/cpu_helper.c | 16 ++++++++++++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++- 3 files changed, 42 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 709b7c3abb..11a0f41b27 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -430,18 +430,27 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif /* - * A simplification for VLMAX - * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * = (VLEN << LMUL) / (8 << SEW) - * = (VLEN << LMUL) >> (SEW + 3) - * = VLEN >> (SEW + 3 - LMUL) + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + * + * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) + * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 + * => VLMAX = vlen >> (1 + 3 - (-3)) + * = 256 >> 7 + * = 2 */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { - uint8_t sew, lmul; - - sew = FIELD_EX64(vtype, VTYPE, VSEW); - lmul = FIELD_EX64(vtype, VTYPE, VLMUL); + uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); + int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); return cpu->cfg.vlen >> (sew + 3 - lmul); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1b31d0ad47..10f3baba53 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,12 +75,22 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *cs_base = 0; if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to true + * only when maxsz >= 8 bytes. + */ uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz = vlmax << sew; + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && + (maxsz >= 8); flags = FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags = FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index e12db9aae8..5c04ac90da 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1049,7 +1049,17 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale = s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} static bool opivv_check(DisasContext *s, arg_rmrr *a) { From 20f2079acfcab639d602c6a865bea43a3458b6e9 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:13 +0800 Subject: [PATCH 361/421] target/riscv: rvv-1.0: floating-point square-root instruction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-28-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7d8441d1f2..92a0e6fe51 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -563,7 +563,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm -vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm +vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm From 0676d8e3dcd5c569a473bd90eb328b376b720ee0 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:14 +0800 Subject: [PATCH 362/421] target/riscv: rvv-1.0: floating-point classify instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-29-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 92a0e6fe51..f61eaf7c6b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -586,7 +586,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm -vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm +vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm From 0014aa741dedb1810d19a747c581d265b2b43298 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:15 +0800 Subject: [PATCH 363/421] target/riscv: rvv-1.0: count population in mask instruction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-30-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 7 ++++--- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b8894d6151..3f30882aec 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1020,7 +1020,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vcpop_m, tl, ptr, ptr, env, i32) DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f61eaf7c6b..e748f7ca71 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -627,7 +627,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm +vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5c04ac90da..b53cd2e6f3 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2664,8 +2664,8 @@ GEN_MM_TRANS(vmnor_mm) GEN_MM_TRANS(vmornot_mm) GEN_MM_TRANS(vmxnor_mm) -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +/* Vector count population in mask vcpop */ +static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2684,11 +2684,12 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + return true; } return false; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f9919273dc..9451112b3d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4214,9 +4214,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) -/* Vector mask population count vmpopc */ -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* Vector count population in mask vcpop */ +target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { target_ulong cnt = 0; uint32_t vm = vext_vm(desc); From d71a24fc82c50f6fe0d86feece01a4ef43b1af82 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:16 +0800 Subject: [PATCH 364/421] target/riscv: rvv-1.0: find-first-set mask bit instruction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-31-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3f30882aec..7646567eb2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1022,7 +1022,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_4(vcpop_m, tl, ptr, ptr, env, i32) -DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32) DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e748f7ca71..4df2aa9cdd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -628,7 +628,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm -vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm +vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index b53cd2e6f3..3645bb9635 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2696,7 +2696,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) } /* vmfirst find-first-set mask bit */ -static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) +static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2715,7 +2715,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); + gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9451112b3d..f97783acf0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4233,9 +4233,9 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env, return cnt; } -/* vmfirst find-first-set mask bit*/ -target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* vfirst find-first-set mask bit*/ +target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; From 40c1495d69b17d34f073a5b92970b1b82e6ad7ef Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:17 +0800 Subject: [PATCH 365/421] target/riscv: rvv-1.0: set-X-first mask bit instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-32-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++- target/riscv/vector_helper.c | 4 ---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4df2aa9cdd..d139c0aade 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -629,9 +629,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 3645bb9635..9206e6f06c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2731,7 +2731,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s) && \ + require_vm(a->vm, a->rd) && \ + (a->rd != a->rs2)) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f97783acf0..b0dc971a86 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4260,7 +4260,6 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t vlmax = env_archcpu(env)->cfg.vlen; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; @@ -4290,9 +4289,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, } } } - for (; i < vlmax; i++) { - vext_set_elem_mask(vd, i, 0); - } } void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, From ee17eaa120fc58a7737880b6a88114bee09dc616 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:18 +0800 Subject: [PATCH 366/421] target/riscv: rvv-1.0: iota instruction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-33-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d139c0aade..3ac5162aeb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -632,7 +632,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9206e6f06c..80cbf0cadb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2757,12 +2757,18 @@ GEN_M_TRANS(vmsbf_m) GEN_M_TRANS(vmsif_m) GEN_M_TRANS(vmsof_m) -/* Vector Iota Instruction */ +/* + * Vector Iota Instruction + * + * 1. The destination register cannot overlap the source register. + * 2. If masked, cannot overlap the mask register ('v0'). + * 3. An illegal instruction exception is raised if vstart is non-zero. + */ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) { if (require_rvv(s) && vext_check_isa_ill(s) && - require_noover(a->rd, s->lmul, a->rs2, 0) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && require_vm(a->vm, a->rd) && require_align(a->rd, s->lmul)) { uint32_t data = 0; From f4f47e04de6185ddaf36e9b6ec34aa6e28923a07 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:19 +0800 Subject: [PATCH 367/421] target/riscv: rvv-1.0: element index instruction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-34-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3ac5162aeb..ab274dcde1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -633,7 +633,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm -vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm +vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd From 308ee805786a18f236daead36b11f53cd5017899 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:20 +0800 Subject: [PATCH 368/421] target/riscv: rvv-1.0: allow load element with sign-extended For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-35-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++-------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 80cbf0cadb..4207cc4e6b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2825,17 +2825,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) /* Integer Extract Instruction */ static void load_element(TCGv_i64 dest, TCGv_ptr base, - int ofs, int sew) + int ofs, int sew, bool sign) { switch (sew) { case MO_8: - tcg_gen_ld8u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld8u_i64(dest, base, ofs); + } else { + tcg_gen_ld8s_i64(dest, base, ofs); + } break; case MO_16: - tcg_gen_ld16u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld16u_i64(dest, base, ofs); + } else { + tcg_gen_ld16s_i64(dest, base, ofs); + } break; case MO_32: - tcg_gen_ld32u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld32u_i64(dest, base, ofs); + } else { + tcg_gen_ld32s_i64(dest, base, ofs); + } break; case MO_64: tcg_gen_ld_i64(dest, base, ofs); @@ -2890,7 +2902,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, /* Perform the load. */ load_element(dest, base, - vreg_ofs(s, vreg), s->sew); + vreg_ofs(s, vreg), s->sew, false); tcg_temp_free_ptr(base); tcg_temp_free_i32(ofs); @@ -2906,9 +2918,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, } static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, - int vreg, int idx) + int vreg, int idx, bool sign) { - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew); + load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); } static bool trans_vext_x_v(DisasContext *s, arg_r *a) @@ -2918,7 +2930,7 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a) if (a->rs1 == 0) { /* Special case vmv.x.s rd, vs2. */ - vec_element_loadi(s, tmp, a->rs2, 0); + vec_element_loadi(s, tmp, a->rs2, 0, false); } else { /* This instruction ignores LMUL and vector register groups */ int vlmax = s->vlen >> (3 + s->sew); @@ -3000,7 +3012,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) (s->mstatus_fs != 0) && (s->sew != 0)) { unsigned int len = 8 << s->sew; - vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); if (len < 64) { tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], MAKE_64BIT_MASK(len, 64 - len)); @@ -3102,7 +3114,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) TCGv_i64 dest = tcg_temp_new_i64(); if (a->rs1 == 0) { - vec_element_loadi(s, dest, a->rs2, 0); + vec_element_loadi(s, dest, a->rs2, 0, false); } else { vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); } From 50bfb45b2c5bbbac8ffb7f051eb8c88128cae88d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:21 +0800 Subject: [PATCH 369/421] target/riscv: rvv-1.0: register gather instructions * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-36-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 ++++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 27 ++++++++++++++++++++++--- target/riscv/vector_helper.c | 23 ++++++++++++--------- 4 files changed, 43 insertions(+), 12 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 7646567eb2..bd0768d048 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1059,6 +1059,10 @@ DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ab274dcde1..4653a9679e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -645,6 +645,7 @@ vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm +vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 4207cc4e6b..322fc5c4aa 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3090,7 +3090,25 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) require_vm(a->vm, a->rd); } +static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a) +{ + int8_t emul = MO_16 - s->sew + s->lmul; + return require_rvv(s) && + vext_check_isa_ill(s) && + (emul >= -3 && emul <= 3) && + require_align(a->rd, s->lmul) && + require_align(a->rs1, emul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2 && a->rd != a->rs1) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), + a->rs1, 1 << MAX(emul, 0)) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), + a->rs2, 1 << MAX(s->lmul, 0)) && + require_vm(a->vm, a->rd); +} + GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check) +GEN_OPIVV_TRANS(vrgatherei16_vv, vrgatherei16_vv_check) static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) { @@ -3110,7 +3128,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) } if (a->vm && s->vl_eq_vlmax) { - int vlmax = s->vlen; + int scale = s->lmul - (s->sew + 3); + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale; TCGv_i64 dest = tcg_temp_new_i64(); if (a->rs1 == 0) { @@ -3141,8 +3160,10 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) } if (a->vm && s->vl_eq_vlmax) { - if (a->rs1 >= s->vlen) { - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), + int scale = s->lmul - (s->sew + 3); + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale; + if (a->rs1 >= vlmax) { + tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); } else { tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd), diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b0dc971a86..86d03d8e39 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4460,11 +4460,11 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) /* Vector Register Gather Instruction */ -#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \ +#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS1))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index; \ @@ -4474,20 +4474,25 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - index = *((ETYPE *)vs1 + H(i)); \ + index = *((TS1 *)vs1 + HS1(i)); \ if (index >= vlmax) { \ - *((ETYPE *)vd + H(i)) = 0; \ + *((TS2 *)vd + HS2(i)) = 0; \ } else { \ - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ + *((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \ } \ } \ } /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */ -GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1) -GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2) -GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4) -GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8) +GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, uint8_t, H1, H1) +GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, uint16_t, H2, H2) +GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, uint32_t, H4, H4) +GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, uint64_t, H8, H8) + +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_b, uint16_t, uint8_t, H2, H1) +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_h, uint16_t, uint16_t, H2, H2) +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_w, uint16_t, uint32_t, H2, H4) +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_d, uint16_t, uint64_t, H2, H8) #define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ From dedc53cbc9f267e2ad037218ab07f9b4097efa65 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:22 +0800 Subject: [PATCH 370/421] target/riscv: rvv-1.0: integer scalar move instructions * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20211210075704.23951-37-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 43 ++++++++++++++++++++----- 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4653a9679e..e33ec82fdf 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -634,8 +634,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm +vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd +vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 322fc5c4aa..c250943dde 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2978,27 +2978,54 @@ static void vec_element_storei(DisasContext *s, int vreg, store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); } +/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */ +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) +{ + if (require_rvv(s) && + vext_check_isa_ill(s)) { + TCGv_i64 t1; + TCGv dest; + + t1 = tcg_temp_new_i64(); + dest = tcg_temp_new(); + /* + * load vreg and sign-extend to 64 bits, + * then truncate to XLEN bits before storing to gpr. + */ + vec_element_loadi(s, t1, a->rs2, 0, true); + tcg_gen_trunc_i64_tl(dest, t1); + gen_set_gpr(s, a->rd, dest); + tcg_temp_free_i64(t1); + tcg_temp_free(dest); + + return true; + } + return false; +} + /* vmv.s.x vd, rs1 # vd[0] = rs1 */ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { /* This instruction ignores LMUL and vector register groups */ - int maxsz = s->vlen >> 3; TCGv_i64 t1; + TCGv s1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0); - if (a->rs1 == 0) { - goto done; - } t1 = tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + + /* + * load gpr and sign-extend to 64 bits, + * then truncate to SEW bits when storing to vreg. + */ + s1 = get_gpr(s, a->rs1, EXT_NONE); + tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); mark_vs_dirty(s); - done: gen_set_label(over); return true; } From c4b3e46f0092ee9303787ae12ea9869eebcdc1ac Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:23 +0800 Subject: [PATCH 371/421] target/riscv: rvv-1.0: floating-point move instruction NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-38-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index c250943dde..2c8002af54 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2461,9 +2461,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) require_rvf(s) && vext_check_isa_ill(s) && require_align(a->rd, s->lmul)) { + TCGv_i64 t1; + if (s->vl_eq_vlmax) { + t1 = tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); + MAXSZ(s), MAXSZ(s), t1); mark_vs_dirty(s); } else { TCGv_ptr dest; @@ -2477,15 +2483,21 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + t1 = tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + dest = tcg_temp_new_ptr(); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); + + fns[s->sew - 1](dest, t1, cpu_env, desc); tcg_temp_free_ptr(dest); mark_vs_dirty(s); gen_set_label(over); } + tcg_temp_free_i64(t1); return true; } return false; From 5c4eb8fb5649f1fd137fb4d85a019332908fe066 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:24 +0800 Subject: [PATCH 372/421] target/riscv: rvv-1.0: floating-point scalar move instructions NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-39-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 38 ++++++++++++------------- target/riscv/internals.h | 5 ---- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e33ec82fdf..ab5fdbf9be 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -637,8 +637,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 2c8002af54..89f88a0ea7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3047,14 +3047,19 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) /* Floating-Point Scalar Move Instructions */ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) { - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs != 0) && (s->sew != 0)) { - unsigned int len = 8 << s->sew; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { + unsigned int ofs = (8 << s->sew); + unsigned int len = 64 - ofs; + TCGv_i64 t_nan; vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); + /* NaN-box f[rd] as necessary for SEW */ + if (len) { + t_nan = tcg_constant_i64(UINT64_MAX); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + t_nan, ofs, len); } mark_fs_dirty(s); @@ -3066,25 +3071,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) { - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { - TCGv_i64 t1; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax = s->vlen >> 3; + TCGv_i64 t1; + TCGLabel *over = gen_new_label(); /* if vl == 0, skip vector register write back */ - TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ + /* NaN-box f[rs1] */ t1 = tcg_temp_new_i64(); - if (s->sew == MO_64 && !has_ext(s, RVD)) { - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); - } else { - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); - } + do_nanbox(s, t1, cpu_fpr[a->rs1]); + vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); mark_vs_dirty(s); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 81f5dfa477..ac062dc0b4 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); -#define SEW8 0 -#define SEW16 1 -#define SEW32 2 -#define SEW64 3 - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; #endif From 6b85975e11952447c3a301f33d2736c7890003dd Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:25 +0800 Subject: [PATCH 373/421] target/riscv: rvv-1.0: whole register move instructions Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-40-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4 ++++ target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ab5fdbf9be..06a8076311 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -650,6 +650,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 89f88a0ea7..91e7c14ec4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3259,3 +3259,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) } return false; } + +/* + * Whole Vector Register Move Instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 16.6) + */ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + QEMU_IS_ALIGNED(a->rd, LEN) && \ + QEMU_IS_ALIGNED(a->rs2, LEN)) { \ + /* EEW = 8 */ \ + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ + vreg_ofs(s, a->rs2), \ + s->vlen / 8 * LEN, s->vlen / 8 * LEN); \ + mark_vs_dirty(s); \ + return true; \ + } \ + return false; \ +} + +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) From cd01340e75a700591de5715aa9f0aa226e5a0d34 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:26 +0800 Subject: [PATCH 374/421] target/riscv: rvv-1.0: integer extension instructions Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-41-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 14 +++++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.c.inc | 80 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 31 ++++++++++ 4 files changed, 133 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index bd0768d048..878d82caf6 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1072,3 +1072,17 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 06a8076311..a6f9e5dcc6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -655,6 +655,14 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd +# Vector Integer Extension +vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm +vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm +vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm +vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm +vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm +vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm + vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 91e7c14ec4..5285e21cc0 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3284,3 +3284,83 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) + +static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div) +{ + uint8_t from = (s->sew + 3) - div; + bool ret = require_rvv(s) && + (from >= 3 && from <= 8) && + (a->rd != a->rs2) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul - div) && + require_vm(a->vm, a->rd) && + require_noover(a->rd, s->lmul, a->rs2, s->lmul - div); + return ret; +} + +static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_gvec_3_ptr *fn; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + static gen_helper_gvec_3_ptr * const fns[6][4] = { + { + NULL, gen_helper_vzext_vf2_h, + gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d + }, + { + NULL, NULL, + gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d, + }, + { + NULL, NULL, + NULL, gen_helper_vzext_vf8_d + }, + { + NULL, gen_helper_vsext_vf2_h, + gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d + }, + { + NULL, NULL, + gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d, + }, + { + NULL, NULL, + NULL, gen_helper_vsext_vf8_d + } + }; + + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, VM, a->vm); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), cpu_env, + s->vlen / 8, s->vlen / 8, data, fn); + + mark_vs_dirty(s); + gen_set_label(over); + return true; +} + +/* Vector Integer Extension */ +#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (int_ext_check(s, a, DIV)) { \ + return int_ext_op(s, a, SEQ); \ + } \ + return false; \ +} + +GEN_INT_EXT_TRANS(vzext_vf2, 1, 0) +GEN_INT_EXT_TRANS(vzext_vf4, 2, 1) +GEN_INT_EXT_TRANS(vzext_vf8, 3, 2) +GEN_INT_EXT_TRANS(vsext_vf2, 1, 3) +GEN_INT_EXT_TRANS(vsext_vf4, 2, 4) +GEN_INT_EXT_TRANS(vsext_vf8, 3, 5) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 86d03d8e39..58ba2a7d99 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4544,3 +4544,34 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) + +/* Vector Integer Extension */ +#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vl = env->vl; \ + uint32_t vm = vext_vm(desc); \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \ + } \ +} + +GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1) +GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2) +GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4) +GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1) +GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2) +GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1) + +GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1) +GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2) +GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4) +GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1) +GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2) +GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1) From 8b99a110f7ff2c7e1d1294998226b84176384ef3 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:27 +0800 Subject: [PATCH 375/421] target/riscv: rvv-1.0: single-width averaging add and subtract instructions Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-42-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 16 ++++++ target/riscv/insn32.decode | 13 +++-- target/riscv/insn_trans/trans_rvv.c.inc | 5 +- target/riscv/vector_helper.c | 74 +++++++++++++++++++++++++ 4 files changed, 102 insertions(+), 6 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 878d82caf6..f2e8d107d2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -648,18 +648,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a6f9e5dcc6..f83c8daf24 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -493,11 +493,14 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm -vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm -vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm -vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm -vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm -vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm +vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm +vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm +vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm +vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm +vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm +vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm +vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm +vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5285e21cc0..0076ce5a0a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2004,10 +2004,13 @@ GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check) /* Vector Single-Width Averaging Add and Subtract */ GEN_OPIVV_TRANS(vaadd_vv, opivv_check) +GEN_OPIVV_TRANS(vaaddu_vv, opivv_check) GEN_OPIVV_TRANS(vasub_vv, opivv_check) +GEN_OPIVV_TRANS(vasubu_vv, opivv_check) GEN_OPIVX_TRANS(vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vaaddu_vx, opivx_check) GEN_OPIVX_TRANS(vasub_vx, opivx_check) -GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vasubu_vx, opivx_check) /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ GEN_OPIVV_TRANS(vsmul_vv, opivv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 58ba2a7d99..6891f28116 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2295,6 +2295,43 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2) GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4) GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8) +static inline uint32_t aaddu32(CPURISCVState *env, int vxrm, + uint32_t a, uint32_t b) +{ + uint64_t res = (uint64_t)a + b; + uint8_t round = get_round(vxrm, res, 1); + + return (res >> 1) + round; +} + +static inline uint64_t aaddu64(CPURISCVState *env, int vxrm, + uint64_t a, uint64_t b) +{ + uint64_t res = a + b; + uint8_t round = get_round(vxrm, res, 1); + uint64_t over = (uint64_t)(res < a) << 63; + + return ((res >> 1) | over) + round; +} + +RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64) +GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8) + +RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64) +GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8) + static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) { int64_t res = (int64_t)a - b; @@ -2331,6 +2368,43 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2, 2) GEN_VEXT_VX_RM(vasub_vx_w, 4, 4) GEN_VEXT_VX_RM(vasub_vx_d, 8, 8) +static inline uint32_t asubu32(CPURISCVState *env, int vxrm, + uint32_t a, uint32_t b) +{ + int64_t res = (int64_t)a - b; + uint8_t round = get_round(vxrm, res, 1); + + return (res >> 1) + round; +} + +static inline uint64_t asubu64(CPURISCVState *env, int vxrm, + uint64_t a, uint64_t b) +{ + uint64_t res = (uint64_t)a - b; + uint8_t round = get_round(vxrm, res, 1); + uint64_t over = (uint64_t)(res > a) << 63; + + return ((res >> 1) | over) + round; +} + +RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64) +GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8) + +RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64) +GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8) + /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { From a75ae09f2a7ed09c017f22f04bf71bd7b453fef7 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:28 +0800 Subject: [PATCH 376/421] target/riscv: rvv-1.0: single-width bit shift instructions Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-43-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 0076ce5a0a..4894212913 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1685,9 +1685,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) -GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) From bb45485ad1721cbbe2b35f4daad83f847bed3d36 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:29 +0800 Subject: [PATCH 377/421] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow * Only do carry-in or borrow-in if is masked (vm=0). * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-44-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 20 ++++++++++---------- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- target/riscv/vector_helper.c | 21 ++++++--------------- 3 files changed, 17 insertions(+), 26 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f83c8daf24..9c4089d7a7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -378,16 +378,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm -vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1 -vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1 -vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 +vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 +vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 +vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 +vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm +vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm +vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm +vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 +vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 +vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm +vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 4894212913..357615a11c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1547,7 +1547,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.3) + * destination vector register is v0 and LMUL > 1. (Section 12.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6891f28116..54405d898b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -944,7 +944,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, i); \ + ETYPE carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ } \ @@ -969,7 +969,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, i); \ + ETYPE carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ } \ @@ -994,20 +994,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_max_elems(desc, \ - ctzl(sizeof(ETYPE))); \ + uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, i); \ - \ + ETYPE carry = !vm && vext_elem_mask(v0, i); \ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC) @@ -1025,19 +1020,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ + uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, i); \ - \ + ETYPE carry = !vm && vext_elem_mask(v0, i); \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC) From 7daa5852bc25a843118a8bc46d8622d97bf5dab0 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:30 +0800 Subject: [PATCH 378/421] target/riscv: rvv-1.0: narrowing integer right shift instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-45-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 24 +++++++------- target/riscv/insn32.decode | 12 +++---- target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++------------- target/riscv/vector_helper.c | 24 +++++++------- 4 files changed, 51 insertions(+), 51 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index f2e8d107d2..304c12494d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -351,18 +351,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 9c4089d7a7..a3f1101cd6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -406,12 +406,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm -vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm -vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm -vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm -vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm -vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm -vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm +vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm +vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm +vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm +vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm +vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm +vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 357615a11c..f6202835ff 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1690,7 +1690,7 @@ GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ -static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && @@ -1698,10 +1698,10 @@ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) } /* OPIVV with NARROW */ -#define GEN_OPIVV_NARROW_TRANS(NAME) \ +#define GEN_OPIWV_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivv_narrow_check(s, a)) { \ + if (opiwv_narrow_check(s, a)) { \ uint32_t data = 0; \ static gen_helper_gvec_4_ptr * const fns[3] = { \ gen_helper_##NAME##_b, \ @@ -1724,10 +1724,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ } \ return false; \ } -GEN_OPIVV_NARROW_TRANS(vnsra_vv) -GEN_OPIVV_NARROW_TRANS(vnsrl_vv) +GEN_OPIWV_NARROW_TRANS(vnsra_wv) +GEN_OPIWV_NARROW_TRANS(vnsrl_wv) -static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && @@ -1735,10 +1735,10 @@ static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) } /* OPIVX with NARROW */ -#define GEN_OPIVX_NARROW_TRANS(NAME) \ +#define GEN_OPIWX_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] = { \ gen_helper_##NAME##_b, \ gen_helper_##NAME##_h, \ @@ -1749,14 +1749,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ return false; \ } -GEN_OPIVX_NARROW_TRANS(vnsra_vx) -GEN_OPIVX_NARROW_TRANS(vnsrl_vx) +GEN_OPIWX_NARROW_TRANS(vnsra_wx) +GEN_OPIWX_NARROW_TRANS(vnsrl_wx) -/* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ +/* OPIWI with NARROW */ +#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] = { \ gen_helper_##OPIVX##_b, \ gen_helper_##OPIVX##_h, \ @@ -1768,8 +1768,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ return false; \ } -GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx) +GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx) +GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx) /* Vector Integer Comparison Instructions */ /* @@ -2034,12 +2034,12 @@ GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check) GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) /* Vector Narrowing Fixed-Point Clip Instructions */ -GEN_OPIVV_NARROW_TRANS(vnclipu_vv) -GEN_OPIVV_NARROW_TRANS(vnclip_vv) -GEN_OPIVX_NARROW_TRANS(vnclipu_vx) -GEN_OPIVX_NARROW_TRANS(vnclip_vx) -GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx) -GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) +GEN_OPIWV_NARROW_TRANS(vnclipu_vv) +GEN_OPIWV_NARROW_TRANS(vnclip_vv) +GEN_OPIWX_NARROW_TRANS(vnclipu_vx) +GEN_OPIWX_NARROW_TRANS(vnclip_vx) +GEN_OPIWI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx) +GEN_OPIWI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) /* *** Vector Float Point Arithmetic Instructions diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 54405d898b..e885d4d353 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1164,18 +1164,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f) GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f) /* Vector Narrowing Integer Right Shift Instructions */ -GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) /* Vector Integer Comparison Instructions */ #define DO_MSEQ(N, M) (N == M) From f51c3cf1fa8681c45e3fb805a8136b58d093e988 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:31 +0800 Subject: [PATCH 379/421] target/riscv: rvv-1.0: widening integer multiply-add instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-46-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a3f1101cd6..7548b71efd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -474,9 +474,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm -vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm -vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm -vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm +vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 From d6be7a35041b010f3bb01197bd7ff06258f70a7f Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:32 +0800 Subject: [PATCH 380/421] target/riscv: rvv-1.0: single-width saturating add and subtract instructions Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-47-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f6202835ff..ed4554b6a1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1999,7 +1999,7 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) GEN_OPIVX_TRANS(vsadd_vx, opivx_check) GEN_OPIVX_TRANS(vssubu_vx, opivx_check) GEN_OPIVX_TRANS(vssub_vx, opivx_check) -GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check) GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check) /* Vector Single-Width Averaging Add and Subtract */ From 063f8bbca05d859461809c68319517fe711e7bd8 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:33 +0800 Subject: [PATCH 381/421] target/riscv: rvv-1.0: integer comparison instructions * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-48-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 9 --------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ed4554b6a1..804f423d5b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1809,9 +1809,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsleu_vi, IMM_SX, vmsleu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgtu_vi, IMM_SX, vmsgtu_vx, opivx_cmp_check) GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check) /* Vector Integer Min/Max Instructions */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e885d4d353..277a5e4120 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1190,8 +1190,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_max_elems(desc, \ - ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1202,9 +1200,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ } \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ) @@ -1243,7 +1238,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1254,9 +1248,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ) From e70aa16e5e506475459cd524449e39484b4a984f Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:34 +0800 Subject: [PATCH 382/421] target/riscv: rvv-1.0: floating-point compare instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-49-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 277a5e4120..71d7b1e879 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3710,8 +3710,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_max_elems(desc, \ - ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -3723,9 +3721,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, s1, &env->fp_status)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) @@ -3738,7 +3733,6 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -3749,9 +3743,6 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet) From 50f6696c0f87372348b0760f858187cda3e7eb7f Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:35 +0800 Subject: [PATCH 383/421] target/riscv: rvv-1.0: mask-register logical instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-50-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 804f423d5b..5c0c3d2547 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2652,7 +2652,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) #define GEN_MM_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_r *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s)) { \ uint32_t data = 0; \ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 71d7b1e879..f883fdf474 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4231,7 +4231,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ uint32_t vl = env->vl; \ uint32_t i; \ int a, b; \ @@ -4241,9 +4240,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ b = vext_elem_mask(vs2, i); \ vext_set_elem_mask(vd, i, OP(b, a)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ } #define DO_NAND(N, M) (!(N & M)) From 6438ed61de22d9fb945452b5fe5b0ea594aa8ccc Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:36 +0800 Subject: [PATCH 384/421] target/riscv: rvv-1.0: slide instructions * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-51-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index f883fdf474..d79f59e443 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4430,17 +4430,22 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - target_ulong offset = s1, i; \ + target_ulong i_max, i; \ \ - for (i = 0; i < vl; ++i) { \ - target_ulong j = i + offset; \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ + i_max = MIN(s1 < vlmax ? vlmax - s1 : 0, vl); \ + for (i = 0; i < i_max; ++i) { \ + if (vm || vext_elem_mask(v0, i)) { \ + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \ + } \ + } \ + \ + for (i = i_max; i < vl; ++i) { \ + if (vm || vext_elem_mask(v0, i)) { \ + *((ETYPE *)vd + H(i)) = 0; \ } \ - *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \ } \ } From 8500d4ab2e9b50cb8a23b751e991e5ece6b0d0cc Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:37 +0800 Subject: [PATCH 385/421] target/riscv: rvv-1.0: floating-point slide instructions Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-52-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 16 +++ target/riscv/vector_helper.c | 139 ++++++++++++++++-------- 4 files changed, 120 insertions(+), 44 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 304c12494d..012d034377 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1071,6 +1071,13 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32) + DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7548b71efd..c5cc14c45c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -577,6 +577,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5c0c3d2547..597a367444 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3121,6 +3121,22 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) +/* Vector Floating-Point Slide Instructions */ +static bool fslideup_check(DisasContext *s, arg_rmrr *a) +{ + return slideup_check(s, a) && + require_rvf(s); +} + +static bool fslidedown_check(DisasContext *s, arg_rmrr *a) +{ + return slidedown_check(s, a) && + require_rvf(s); +} + +GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check) +GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check) + /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index d79f59e443..7fa5189af4 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4455,57 +4455,108 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2) GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) -#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - if (i == 0) { \ - *((ETYPE *)vd + H(i)) = s1; \ - } else { \ - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ - } \ - } \ +#define GEN_VEXT_VSLIE1UP(ESZ, H) \ +static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + typedef uint##ESZ##_t ETYPE; \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + if (i == 0) { \ + *((ETYPE *)vd + H(i)) = s1; \ + } else { \ + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ + } \ + } \ +} + +GEN_VEXT_VSLIE1UP(8, H1) +GEN_VEXT_VSLIE1UP(16, H2) +GEN_VEXT_VSLIE1UP(32, H4) +GEN_VEXT_VSLIE1UP(64, H8) + +#define GEN_VEXT_VSLIDE1UP_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \ } /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */ -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, 8) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, 16) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64) -#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - if (i == vl - 1) { \ - *((ETYPE *)vd + H(i)) = s1; \ - } else { \ - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ - } \ - } \ +#define GEN_VEXT_VSLIDE1DOWN(ESZ, H) \ +static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + typedef uint##ESZ##_t ETYPE; \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + if (i == vl - 1) { \ + *((ETYPE *)vd + H(i)) = s1; \ + } else { \ + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ + } \ + } \ +} + +GEN_VEXT_VSLIDE1DOWN(8, H1) +GEN_VEXT_VSLIDE1DOWN(16, H2) +GEN_VEXT_VSLIDE1DOWN(32, H4) +GEN_VEXT_VSLIDE1DOWN(64, H8) + +#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \ } /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */ -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, 8) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, 16) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, 32) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, 64) + +/* Vector Floating-Point Slide Instructions */ +#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \ +} + +/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */ +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, 16) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, 32) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, 64) + +#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \ +} + +/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */ +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, 16) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, 32) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64) /* Vector Register Gather Instruction */ #define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \ From a70b3a73e75c6147ef4e08546038315d38c207a3 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:38 +0800 Subject: [PATCH 386/421] target/riscv: rvv-1.0: narrowing fixed-point clip instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-53-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 24 ++++++------ target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++--- target/riscv/vector_helper.c | 50 ++++++++++++------------- 4 files changed, 49 insertions(+), 49 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 012d034377..3ea21b4a57 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -725,18 +725,18 @@ DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c5cc14c45c..eeab6b00a1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -516,12 +516,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm -vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm -vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm -vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm -vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm -vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm -vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm +vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm +vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm +vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm +vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm +vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm +vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 597a367444..f5588d9832 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2034,12 +2034,12 @@ GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check) GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) /* Vector Narrowing Fixed-Point Clip Instructions */ -GEN_OPIWV_NARROW_TRANS(vnclipu_vv) -GEN_OPIWV_NARROW_TRANS(vnclip_vv) -GEN_OPIWX_NARROW_TRANS(vnclipu_vx) -GEN_OPIWX_NARROW_TRANS(vnclip_vx) -GEN_OPIWI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx) -GEN_OPIWI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx) +GEN_OPIWV_NARROW_TRANS(vnclipu_wv) +GEN_OPIWV_NARROW_TRANS(vnclip_wv) +GEN_OPIWX_NARROW_TRANS(vnclipu_wx) +GEN_OPIWX_NARROW_TRANS(vnclip_wx) +GEN_OPIWI_NARROW_TRANS(vnclipu_wi, IMM_ZX, vnclipu_wx) +GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx) /* *** Vector Float Point Arithmetic Instructions diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7fa5189af4..c95c8bd9db 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2875,19 +2875,19 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b) } } -RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8) -RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16) -RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32) -GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1) -GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2) -GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4) +RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8) +RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16) +RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32) +GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1) +GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2) +GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4) -RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8) -RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16) -RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32) -GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1) -GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2) -GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4) +RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8) +RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16) +RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32) +GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1) +GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2) +GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4) static inline uint8_t vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b) @@ -2925,7 +2925,7 @@ static inline uint32_t vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) { uint8_t round, shift = b & 0x3f; - int64_t res; + uint64_t res; round = get_round(vxrm, a, shift); res = (a >> shift) + round; @@ -2937,19 +2937,19 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) } } -RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) -RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) -RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) -GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1) -GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2) -GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4) +RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) +RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) +RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) +GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1) +GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2) +GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4) -RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8) -RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16) -RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32) -GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1) -GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2) -GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4) +RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8) +RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16) +RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32) +GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1) +GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2) +GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4) /* *** Vector Float Point Arithmetic Instructions From 08b60eebc4ac101eef94639553766c3c1969c4d3 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:39 +0800 Subject: [PATCH 387/421] target/riscv: rvv-1.0: single-width floating-point reduction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-54-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++--- target/riscv/vector_helper.c | 12 ++++++------ 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f5588d9832..998247d71d 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2637,9 +2637,15 @@ GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check) /* Vector Single-Width Floating-Point Reduction Instructions */ -GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) -GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) -GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) +static bool freduction_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_check(s, a) && + require_rvf(s); +} + +GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) +GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) +GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) /* Vector Widening Floating-Point Reduction Instructions */ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c95c8bd9db..79a2c3ff3a 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4173,14 +4173,14 @@ GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) /* Maximum value */ -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum) -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum) -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum) +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_number) /* Minimum value */ -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum) -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum) -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum) +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number) /* Vector Widening Floating-Point Reduction Instructions */ /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ From b8dd99f2d10311e0f4527507f56a1721e9c19505 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:40 +0800 Subject: [PATCH 388/421] target/riscv: rvv-1.0: widening floating-point reduction instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-55-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 998247d71d..b43234ed3f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2648,7 +2648,14 @@ GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) /* Vector Widening Floating-Point Reduction Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) +static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_widen_check(s, a) && + require_scale_rvf(s) && + (s->sew != MO_8); +} + +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) /* *** Vector Mask Operations From 74eb7834bc7b2033d8caa308320afacbaff0525f Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:41 +0800 Subject: [PATCH 389/421] target/riscv: rvv-1.0: single-width scaling shift instructions log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-56-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index b43234ed3f..03716ad706 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2030,8 +2030,8 @@ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) GEN_OPIVV_TRANS(vssra_vv, opivv_check) GEN_OPIVX_TRANS(vssrl_vx, opivx_check) GEN_OPIVX_TRANS(vssra_vx, opivx_check) -GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check) -GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check) +GEN_OPIVI_TRANS(vssrl_vi, IMM_TRUNC_SEW, vssrl_vx, opivx_check) +GEN_OPIVI_TRANS(vssra_vi, IMM_TRUNC_SEW, vssra_vx, opivx_check) /* Vector Narrowing Fixed-Point Clip Instructions */ GEN_OPIWV_NARROW_TRANS(vnclipu_wv) From a12c812d19008e964e35df3ece84503c8d3221c0 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:42 +0800 Subject: [PATCH 390/421] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-57-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.c.inc | 9 -- target/riscv/vector_helper.c | 205 ------------------------ 4 files changed, 243 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3ea21b4a57..af79570da8 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -686,28 +686,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) - DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index eeab6b00a1..aee3a6cd01 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -503,13 +503,6 @@ vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm -vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm -vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm -vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm -vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 03716ad706..119c82ca47 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2016,15 +2016,6 @@ GEN_OPIVX_TRANS(vasubu_vx, opivx_check) GEN_OPIVV_TRANS(vsmul_vv, opivv_check) GEN_OPIVX_TRANS(vsmul_vx, opivx_check) -/* Vector Widening Saturating Scaled Multiply-Add */ -GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx) - /* Vector Single-Width Scaling Shift Instructions */ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) GEN_OPIVV_TRANS(vssra_vv, opivv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 79a2c3ff3a..128406aa78 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2494,211 +2494,6 @@ GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2) GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4) GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8) -/* Vector Widening Saturating Scaled Multiply-Add */ -static inline uint16_t -vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b, - uint16_t c) -{ - uint8_t round; - uint16_t res = (uint16_t)a * b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return saddu16(env, vxrm, c, res); -} - -static inline uint32_t -vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b, - uint32_t c) -{ - uint8_t round; - uint32_t res = (uint32_t)a * b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return saddu32(env, vxrm, c, res); -} - -static inline uint64_t -vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b, - uint64_t c) -{ - uint8_t round; - uint64_t res = (uint64_t)a * b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return saddu64(env, vxrm, c, res); -} - -#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static inline void \ -do_##NAME(void *vd, void *vs1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ -{ \ - TX1 s1 = *((T1 *)vs1 + HS1(i)); \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - TD d = *((TD *)vd + HD(i)); \ - *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \ -} - -RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8) -RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16) -RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32) -GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2) -GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4) -GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8) - -#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static inline void \ -do_##NAME(void *vd, target_long s1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ -{ \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - TD d = *((TD *)vd + HD(i)); \ - *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \ -} - -RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8) -RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16) -RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32) -GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2) -GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4) -GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8) - -static inline int16_t -vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c) -{ - uint8_t round; - int16_t res = (int16_t)a * b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return sadd16(env, vxrm, c, res); -} - -static inline int32_t -vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c) -{ - uint8_t round; - int32_t res = (int32_t)a * b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return sadd32(env, vxrm, c, res); - -} - -static inline int64_t -vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c) -{ - uint8_t round; - int64_t res = (int64_t)a * b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return sadd64(env, vxrm, c, res); -} - -RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8) -RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16) -RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32) -GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2) -GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4) -GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8) -RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8) -RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16) -RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32) -GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2) -GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4) -GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8) - -static inline int16_t -vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c) -{ - uint8_t round; - int16_t res = a * (int16_t)b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return ssub16(env, vxrm, c, res); -} - -static inline int32_t -vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c) -{ - uint8_t round; - int32_t res = a * (int32_t)b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return ssub32(env, vxrm, c, res); -} - -static inline int64_t -vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c) -{ - uint8_t round; - int64_t res = a * (int64_t)b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return ssub64(env, vxrm, c, res); -} - -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8) -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16) -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32) -GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2) -GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4) -GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32) -GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2) -GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4) -GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8) - -static inline int16_t -vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c) -{ - uint8_t round; - int16_t res = (int16_t)a * b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return ssub16(env, vxrm, c, res); -} - -static inline int32_t -vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c) -{ - uint8_t round; - int32_t res = (int32_t)a * b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return ssub32(env, vxrm, c, res); -} - -static inline int64_t -vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c) -{ - uint8_t round; - int64_t res = (int64_t)a * b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return ssub64(env, vxrm, c, res); -} - -RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8) -RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16) -RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32) -GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2) -GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4) -GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8) - /* Vector Single-Width Scaling Shift Instructions */ static inline uint8_t vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) From e29c5cefd81caae221ab1eb9cef18923cf0f01ba Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:43 +0800 Subject: [PATCH 391/421] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-58-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 6 ------ target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.c.inc | 2 -- target/riscv/vector_helper.c | 7 ------- 4 files changed, 17 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index af79570da8..1727075dce 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -902,12 +902,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index aee3a6cd01..82484fda75 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -582,8 +582,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm -vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm -vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 119c82ca47..4c5f813ccf 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2425,7 +2425,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) { @@ -2441,7 +2440,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) /* Vector Floating-Point Classify Instruction */ GEN_OPFV_TRANS(vfclass_v, opfv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 128406aa78..aed230e1ad 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3630,13 +3630,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) -GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) -GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) -GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) - /* Vector Floating-Point Classify Instruction */ #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i) \ From c3536f2f5569da0072b9b42add093852f1469c37 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:44 +0800 Subject: [PATCH 392/421] target/riscv: rvv-1.0: remove integer extract instruction Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-59-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.c.inc | 23 ----------------------- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 82484fda75..20b3095f56 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -632,7 +632,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 -vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 4c5f813ccf..1ce5a10b6a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2840,8 +2840,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) *** Vector Permutation Instructions */ -/* Integer Extract Instruction */ - static void load_element(TCGv_i64 dest, TCGv_ptr base, int ofs, int sew, bool sign) { @@ -2941,27 +2939,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); } -static bool trans_vext_x_v(DisasContext *s, arg_r *a) -{ - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv dest = dest_gpr(s, a->rd); - - if (a->rs1 == 0) { - /* Special case vmv.x.s rd, vs2. */ - vec_element_loadi(s, tmp, a->rs2, 0, false); - } else { - /* This instruction ignores LMUL and vector register groups */ - int vlmax = s->vlen >> (3 + s->sew); - vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); - } - - tcg_gen_trunc_i64_tl(dest, tmp); - gen_set_gpr(s, a->rd, dest); - - tcg_temp_free_i64(tmp); - return true; -} - /* Integer Scalar Move Instruction */ static void store_element(TCGv_i64 val, TCGv_ptr base, From 49c5611a9716963759d36b80b278d68e4335f9d7 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:45 +0800 Subject: [PATCH 393/421] target/riscv: rvv-1.0: floating-point min/max instructions Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-60-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index aed230e1ad..cc95b69255 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3387,28 +3387,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) /* Vector Floating-Point MIN/MAX Instructions */ -RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) -RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) -RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number) GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2) GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4) GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8) -RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) -RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) -RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number) +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number) +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number) GEN_VEXT_VF(vfmin_vf_h, 2, 2) GEN_VEXT_VF(vfmin_vf_w, 4, 4) GEN_VEXT_VF(vfmin_vf_d, 8, 8) -RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) -RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) -RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number) +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number) +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number) GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2) GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4) GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8) -RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) -RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) -RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number) +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number) +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number) GEN_VEXT_VF(vfmax_vf_h, 2, 2) GEN_VEXT_VF(vfmax_vf_w, 4, 4) GEN_VEXT_VF(vfmax_vf_d, 8, 8) From 986c895de17c332c8cb241333dd478cb2ce8b8cc Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:46 +0800 Subject: [PATCH 394/421] target/riscv: introduce floating-point rounding mode enum Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Message-Id: <20211210075704.23951-61-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 12 ++++++------ target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- target/riscv/internals.h | 9 +++++++++ 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 388e23ca67..dec39d4a9e 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) { int softrm; - if (rm == 7) { + if (rm == RISCV_FRM_DYN) { rm = env->frm; } switch (rm) { - case 0: + case RISCV_FRM_RNE: softrm = float_round_nearest_even; break; - case 1: + case RISCV_FRM_RTZ: softrm = float_round_to_zero; break; - case 2: + case RISCV_FRM_RDN: softrm = float_round_down; break; - case 3: + case RISCV_FRM_RUP: softrm = float_round_up; break; - case 4: + case RISCV_FRM_RMM: softrm = float_round_ties_away; break; default: diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 1ce5a10b6a..047be5d5c4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2088,7 +2088,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2167,7 +2167,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_w, \ gen_helper_##NAME##_d, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2199,7 +2199,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2236,7 +2236,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2266,7 +2266,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2303,7 +2303,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2380,7 +2380,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2526,7 +2526,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2574,7 +2574,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ diff --git a/target/riscv/internals.h b/target/riscv/internals.h index ac062dc0b4..db105d4d64 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1); extern const VMStateDescription vmstate_riscv_cpu; #endif +enum { + RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ + RISCV_FRM_RTZ = 1, /* Round towards Zero */ + RISCV_FRM_RDN = 2, /* Round Down */ + RISCV_FRM_RUP = 3, /* Round Up */ + RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ + RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ +}; + static inline uint64_t nanbox_s(float32 f) { return f | MAKE_64BIT_MASK(32, 32); From 900da87ab966654be76cc9c2fb860329cb423bd4 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:47 +0800 Subject: [PATCH 395/421] target/riscv: rvv-1.0: floating-point/integer type-convert instructions Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-62-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 11 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 84 +++++++++++++++---------- 2 files changed, 59 insertions(+), 36 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 20b3095f56..02064f8ec9 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -585,10 +585,13 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 -vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm -vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm -vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm -vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm + +vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm +vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm +vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm +vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm +vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm +vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 047be5d5c4..4bc4dfa69f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1,5 +1,4 @@ /* - * RISC-V translation routines for the RVV Standard Extension. * * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. * @@ -2369,34 +2368,41 @@ static bool opfv_check(DisasContext *s, arg_rmr *a) vext_check_ss(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_3_ptr * const fns[3] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ - fns[s->sew - 1]); \ - mark_vs_dirty(s); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ +static bool do_opfv(DisasContext *s, arg_rmr *a, + gen_helper_gvec_3_ptr *fn, + bool (*checkfn)(DisasContext *, arg_rmr *), + int rm) +{ + if (checkfn(s, a)) { + uint32_t data = 0; + TCGLabel *over = gen_new_label(); + gen_set_rm(s, rm); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), cpu_env, + s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); + gen_set_label(over); + return true; + } + return false; } -GEN_OPFV_TRANS(vfsqrt_v, opfv_check) +#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d \ + }; \ + return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \ +} + +GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) @@ -2442,7 +2448,7 @@ GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) /* Vector Floating-Point Classify Instruction */ -GEN_OPFV_TRANS(vfclass_v, opfv_check) +GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point Merge Instruction */ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) @@ -2496,10 +2502,24 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) } /* Single-Width Floating-Point/Integer Type-Convert Instructions */ -GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) +#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + gen_helper_##HELPER##_d \ + }; \ + return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \ +} + +GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN) +GEN_OPFV_CVT_TRANS(vfcvt_x_f_v, vfcvt_x_f_v, RISCV_FRM_DYN) +GEN_OPFV_CVT_TRANS(vfcvt_f_xu_v, vfcvt_f_xu_v, RISCV_FRM_DYN) +GEN_OPFV_CVT_TRANS(vfcvt_f_x_v, vfcvt_f_x_v, RISCV_FRM_DYN) +/* Reuse the helper functions from vfcvt.xu.f.v and vfcvt.x.f.v */ +GEN_OPFV_CVT_TRANS(vfcvt_rtz_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_RTZ) +GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v, RISCV_FRM_RTZ) /* Widening Floating-Point/Integer Type-Convert Instructions */ From 3ce4c09df75529da0a5798279a01e24c02df15da Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:48 +0800 Subject: [PATCH 396/421] target/riscv: rvv-1.0: widening floating-point/integer type-convert Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-63-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 13 +++--- target/riscv/insn_trans/trans_rvv.c.inc | 57 +++++++++++++++++++++---- target/riscv/vector_helper.c | 7 ++- 4 files changed, 64 insertions(+), 15 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1727075dce..53cf88cd40 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -928,8 +928,10 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 02064f8ec9..664d0fb371 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -592,11 +592,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm -vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm -vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm -vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm -vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm -vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm + +vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm +vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm +vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm +vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm +vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm +vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm +vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 4bc4dfa69f..b4cf044450 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2536,17 +2536,17 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a) vext_check_ds(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_WIDEN_TRANS(NAME) \ +#define GEN_OPFV_WIDEN_TRANS(NAME, HELPER, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_widen_check(s, a)) { \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, RISCV_FRM_DYN); \ + gen_set_rm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2562,11 +2562,50 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ return false; \ } -GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, vfwcvt_x_f_v, RISCV_FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, vfwcvt_f_f_v, RISCV_FRM_DYN) +/* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */ +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_RTZ) +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, vfwcvt_x_f_v, RISCV_FRM_RTZ) + +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + require_scale_rvf(s) && + vext_check_isa_ill(s) && + /* OPFV widening instructions ignore vs1 check */ + vext_check_ds(s, a->rd, a->rs2, a->vm); +} + +#define GEN_OPFXV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfxv_widen_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, RISCV_FRM_DYN); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->vlen / 8, s->vlen / 8, data, \ + fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v) +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) /* Narrowing Floating-Point/Integer Type-Convert Instructions */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cc95b69255..c3b7719291 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3773,6 +3773,7 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8) /* Widening Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define WOP_UU_B uint16_t, uint8_t, uint8_t #define WOP_UU_H uint32_t, uint16_t, uint16_t #define WOP_UU_W uint64_t, uint32_t, uint32_t /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/ @@ -3788,19 +3789,23 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4) GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8) /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */ +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8) /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ +RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2) GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4) GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8) /* - * vfwcvt.f.f.v vd, vs2, vm # + * vfwcvt.f.f.v vd, vs2, vm * Convert single-width float to double-width float. */ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) From 75804f71319706308dd48441b408abc09481c5ae Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:49 +0800 Subject: [PATCH 397/421] target/riscv: add "set round to odd" rounding mode helper function helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-64-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/fpu_helper.c | 5 +++++ target/riscv/helper.h | 1 + target/riscv/internals.h | 1 + target/riscv/translate.c | 7 +++++++ 4 files changed, 14 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index dec39d4a9e..4a5982d594 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +void helper_set_rod_rounding_mode(CPURISCVState *env) +{ + set_float_rounding_mode(float_round_to_odd, &env->fp_status); +} + static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 53cf88cd40..606bf72d5c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index db105d4d64..065e8162a2 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -43,6 +43,7 @@ enum { RISCV_FRM_RUP = 3, /* Round Up */ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ + RISCV_FRM_ROD = 8, /* Round to Odd */ }; static inline uint64_t nanbox_s(float32 f) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3688e80d03..b4df21bda3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,6 +30,7 @@ #include "exec/log.h" #include "instmap.h" +#include "internals.h" /* global register indices */ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; @@ -403,6 +404,12 @@ static void gen_set_rm(DisasContext *ctx, int rm) return; } ctx->frm = rm; + + if (rm == RISCV_FRM_ROD) { + gen_helper_set_rod_rounding_mode(cpu_env); + return; + } + gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } From ff679b58e3efed7b03dcd08ea7f9018978a084e5 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:50 +0800 Subject: [PATCH 398/421] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-65-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 22 ++++----- target/riscv/insn32.decode | 15 ++++--- target/riscv/insn_trans/trans_rvv.c.inc | 59 +++++++++++++++++++++---- target/riscv/vector_helper.c | 45 ++++++++++--------- 4 files changed, 97 insertions(+), 44 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 606bf72d5c..1a0d817f0f 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -938,16 +938,18 @@ DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 664d0fb371..c4fdc76a26 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -600,11 +600,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm -vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm -vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm -vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm -vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm -vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm + +vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm +vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm +vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm +vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm +vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm +vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm +vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm +vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm + vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index b4cf044450..42e9449118 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2623,17 +2623,17 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) vext_check_sd(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_NARROW_TRANS(NAME) \ +#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_narrow_check(s, a)) { \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, RISCV_FRM_DYN); \ + gen_set_rm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2649,11 +2649,52 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ return false; \ } -GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN) +/* Reuse the helper function from vfncvt.f.f.w */ +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD) + +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + require_scale_rvf(s) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sd(s, a->rd, a->rs2, a->vm); +} + +#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opxfv_narrow_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##HELPER##_b, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, FRM); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->vlen / 8, s->vlen / 8, data, \ + fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN) +GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN) +/* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */ +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ) +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ) /* *** Vector Reduction Operations diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index c3b7719291..a78f36b4b3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3820,31 +3820,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8) /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define NOP_UU_B uint8_t, uint16_t, uint32_t #define NOP_UU_H uint16_t, uint32_t, uint32_t #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ -RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) -RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8) +RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16) +RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4) /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */ -RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) -RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) -GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8) +RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16) +RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32) +GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4) /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */ -RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4) /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ -RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4) /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */ static uint16_t vfncvtffv16(uint32_t a, float_status *s) @@ -3852,10 +3857,10 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s) return float32_to_float16(a, true, s); } -RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) -RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16) +RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4) /* *** Vector Reduction Operations From 8a4b52575ab1793f5cc86ddd0b5e986799dfc615 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:51 +0800 Subject: [PATCH 399/421] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-66-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11a0f41b27..5d93ccdfa7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -100,7 +100,7 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" #endif -#define RV_VLEN_MAX 256 +#define RV_VLEN_MAX 1024 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 42e9449118..be3f9f1327 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, base = get_gpr(s, rs1, EXT_NONE); /* - * As simd_desc supports at most 256 bytes, and in this implementation, - * the max vector group length is 2048 bytes. So split it into two parts. + * As simd_desc supports at most 2048 bytes, and in this implementation, + * the max vector group length is 4096 bytes. So split it into two parts. * * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a78f36b4b3..e61c873142 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc) static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz) { /* - * As simd_desc support at most 256 bytes, the max vlen is 256 bits. + * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits. * so vlen in bytes (vlenb) is encoded as maxsz. */ uint32_t vlenb = simd_maxsz(desc); From f714361ed79180a9780334cfe1b89b69f6c9bfe9 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:52 +0800 Subject: [PATCH 400/421] target/riscv: rvv-1.0: implement vstart CSR * Update and check vstart value for vector instructions. * Add whole register move instruction helper functions as we have to call helper function for case where vstart is not zero. * Remove probe_pages() calls in vector load/store instructions (except fault-only-first loads) to raise the memory access exception at the exact processed vector element. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 6 +- target/riscv/helper.h | 5 + target/riscv/insn_trans/trans_rvv.c.inc | 71 +++++--- target/riscv/translate.c | 6 +- target/riscv/vector_helper.c | 210 +++++++++++++++--------- 5 files changed, 197 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3dfbc17738..146447eac5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -343,7 +343,11 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno, #if !defined(CONFIG_USER_ONLY) env->mstatus |= MSTATUS_VS; #endif - env->vstart = val; + /* + * The vstart CSR is defined to have only enough writable bits + * to hold the largest element index, i.e. lg2(VLEN) bits. + */ + env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); return RISCV_EXCP_NONE; } diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1a0d817f0f..a717a87a0e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1073,6 +1073,11 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32) + DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index be3f9f1327..7589c8ce32 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -490,7 +490,7 @@ static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm) */ static bool vext_check_reduction(DisasContext *s, int vs2) { - return require_align(vs2, s->lmul); + return require_align(vs2, s->lmul) && (s->vstart == 0); } /* @@ -2786,7 +2786,8 @@ GEN_MM_TRANS(vmxnor_mm) static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && - vext_check_isa_ill(s)) { + vext_check_isa_ill(s) && + s->vstart == 0) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -2817,7 +2818,8 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && - vext_check_isa_ill(s)) { + vext_check_isa_ill(s) && + s->vstart == 0) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -2852,7 +2854,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ if (require_rvv(s) && \ vext_check_isa_ill(s) && \ require_vm(a->vm, a->rd) && \ - (a->rd != a->rs2)) { \ + (a->rd != a->rs2) && \ + (s->vstart == 0)) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ @@ -2888,7 +2891,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) vext_check_isa_ill(s) && !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && require_vm(a->vm, a->rd) && - require_align(a->rd, s->lmul)) { + require_align(a->rd, s->lmul) && + (s->vstart == 0)) { uint32_t data = 0; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -3109,6 +3113,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); t1 = tcg_temp_new_i64(); @@ -3161,8 +3166,9 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) TCGv_i64 t1; TCGLabel *over = gen_new_label(); - /* if vl == 0, skip vector register write back */ + /* if vl == 0 or vstart >= vl, skip vector register write back */ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); /* NaN-box f[rs1] */ t1 = tcg_temp_new_i64(); @@ -3333,7 +3339,8 @@ static bool vcompress_vm_check(DisasContext *s, arg_r *a) require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && (a->rd != a->rs2) && - !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1); + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) && + (s->vstart == 0); } static bool trans_vcompress_vm(DisasContext *s, arg_r *a) @@ -3363,26 +3370,40 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) * Whole Vector Register Move Instructions ignore vtype and vl setting. * Thus, we don't need to check vill bit. (Section 16.6) */ -#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ -static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ -{ \ - if (require_rvv(s) && \ - QEMU_IS_ALIGNED(a->rd, LEN) && \ - QEMU_IS_ALIGNED(a->rs2, LEN)) { \ - /* EEW = 8 */ \ - tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ - vreg_ofs(s, a->rs2), \ - s->vlen / 8 * LEN, s->vlen / 8 * LEN); \ - mark_vs_dirty(s); \ - return true; \ - } \ - return false; \ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + QEMU_IS_ALIGNED(a->rd, LEN) && \ + QEMU_IS_ALIGNED(a->rs2, LEN)) { \ + uint32_t maxsz = (s->vlen >> 3) * LEN; \ + if (s->vstart == 0) { \ + /* EEW = 8 */ \ + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ + vreg_ofs(s, a->rs2), maxsz, maxsz); \ + mark_vs_dirty(s); \ + } else { \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ + \ + static gen_helper_gvec_2_ptr * const fns[4] = { \ + gen_helper_vmv1r_v, gen_helper_vmv2r_v, \ + gen_helper_vmv4r_v, gen_helper_vmv8r_v, \ + }; \ + tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ + cpu_env, maxsz, maxsz, 0, fns[SEQ]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + } \ + return true; \ + } \ + return false; \ } -GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) -GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) -GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) -GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3) static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b4df21bda3..68edaaf6ac 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -33,7 +33,7 @@ #include "internals.h" /* global register indices */ -static TCGv cpu_gpr[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -96,6 +96,7 @@ typedef struct DisasContext { int8_t lmul; uint8_t sew; uint16_t vlen; + target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; CPUState *cs; @@ -710,6 +711,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); + ctx->vstart = env->vstart; ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; @@ -828,6 +830,8 @@ void riscv_translate_init(void) cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); + cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), + "vstart"); load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), "load_res"); load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index e61c873142..22848d6b68 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -226,25 +226,19 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, uint32_t nf = vext_nf(desc); uint32_t max_elems = vext_max_elems(desc, esz); - /* probe every access*/ - for (i = 0; i < env->vl; i++) { + for (i = env->vstart; i < env->vl; i++, env->vstart++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, base + stride * i, nf << esz, ra, access_type); - } - /* do real access */ - for (i = 0; i < env->vl; i++) { + k = 0; - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } while (k < nf) { target_ulong addr = base + stride * i + (k << esz); ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } + env->vstart = 0; } #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ @@ -291,10 +285,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, uint32_t nf = vext_nf(desc); uint32_t max_elems = vext_max_elems(desc, esz); - /* probe every access */ - probe_pages(env, base, env->vl * (nf << esz), ra, access_type); /* load bytes from guest memory */ - for (i = 0; i < env->vl; i++) { + for (i = env->vstart; i < env->vl; i++, env->vstart++) { k = 0; while (k < nf) { target_ulong addr = base + ((i * nf + k) << esz); @@ -302,6 +294,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, k++; } } + env->vstart = 0; } /* @@ -381,26 +374,20 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t vm = vext_vm(desc); uint32_t max_elems = vext_max_elems(desc, esz); - /* probe every access*/ - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - continue; - } - probe_pages(env, get_index_addr(base, i, vs2), nf << esz, ra, - access_type); - } /* load bytes from guest memory */ - for (i = 0; i < env->vl; i++) { - k = 0; + for (i = env->vstart; i < env->vl; i++, env->vstart++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } + + k = 0; while (k < nf) { abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz); ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } + env->vstart = 0; } #define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \ @@ -471,7 +458,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, target_ulong addr, offset, remain; /* probe every access*/ - for (i = 0; i < env->vl; i++) { + for (i = env->vstart; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } @@ -511,7 +498,7 @@ ProbeSuccess: if (vl != 0) { env->vl = vl; } - for (i = 0; i < env->vl; i++) { + for (i = env->vstart; i < env->vl; i++) { k = 0; if (!vm && !vext_elem_mask(v0, i)) { continue; @@ -522,6 +509,7 @@ ProbeSuccess: k++; } } + env->vstart = 0; } #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \ @@ -559,21 +547,32 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra, MMUAccessType access_type) { - uint32_t i, k; + uint32_t i, k, off, pos; uint32_t nf = vext_nf(desc); uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3; uint32_t max_elems = vlenb >> esz; - /* probe every access */ - probe_pages(env, base, vlenb * nf, ra, access_type); + k = env->vstart / max_elems; + off = env->vstart % max_elems; - /* load bytes from guest memory */ - for (k = 0; k < nf; k++) { - for (i = 0; i < max_elems; i++) { + if (off) { + /* load/store rest of elements of current segment pointed by vstart */ + for (pos = off; pos < max_elems; pos++, env->vstart++) { + target_ulong addr = base + ((pos + k * max_elems) << esz); + ldst_elem(env, addr, pos + k * max_elems, vd, ra); + } + k++; + } + + /* load/store elements for rest of segments */ + for (; k < nf; k++) { + for (i = 0; i < max_elems; i++, env->vstart++) { target_ulong addr = base + ((i + k * max_elems) << esz); ldst_elem(env, addr, i + k * max_elems, vd, ra); } } + + env->vstart = 0; } #define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \ @@ -686,12 +685,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, uint32_t vl = env->vl; uint32_t i; - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i); } + env->vstart = 0; } /* generate the helpers for OPIVV */ @@ -748,12 +748,13 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, uint32_t vl = env->vl; uint32_t i; - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i); } + env->vstart = 0; } /* generate the helpers for OPIVX */ @@ -941,13 +942,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ ETYPE carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ } \ + env->vstart = 0; \ } GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC) @@ -967,12 +969,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ ETYPE carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ } \ + env->vstart = 0; \ } GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC) @@ -997,12 +1000,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ ETYPE carry = !vm && vext_elem_mask(v0, i); \ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ + env->vstart = 0; \ } GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC) @@ -1023,12 +1027,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ ETYPE carry = !vm && vext_elem_mask(v0, i); \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ + env->vstart = 0; \ } GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC) @@ -1105,7 +1110,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -1113,6 +1118,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \ } \ + env->vstart = 0; \ } GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7) @@ -1139,13 +1145,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ } \ + env->vstart = 0; \ } GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7) @@ -1192,7 +1199,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -1200,6 +1207,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ } \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ) @@ -1240,7 +1248,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ @@ -1248,6 +1256,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ) @@ -1770,10 +1779,11 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ *((ETYPE *)vd + H(i)) = s1; \ } \ + env->vstart = 0; \ } GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1) @@ -1788,9 +1798,10 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ *((ETYPE *)vd + H(i)) = (ETYPE)s1; \ } \ + env->vstart = 0; \ } GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1) @@ -1805,10 +1816,11 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) = *(vt + H(i)); \ } \ + env->vstart = 0; \ } GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1) @@ -1823,12 +1835,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \ (ETYPE)(target_long)s1); \ *((ETYPE *)vd + H(i)) = d; \ } \ + env->vstart = 0; \ } GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) @@ -1865,12 +1878,13 @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn) { - for (uint32_t i = 0; i < vl; i++) { + for (uint32_t i = env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i, env, vxrm); } + env->vstart = 0; } static inline void @@ -1981,12 +1995,13 @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn) { - for (uint32_t i = 0; i < vl; i++) { + for (uint32_t i = env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i, env, vxrm); } + env->vstart = 0; } static inline void @@ -2768,12 +2783,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ } \ + env->vstart = 0; \ } RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) @@ -2800,12 +2816,13 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ } \ + env->vstart = 0; \ } RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) @@ -3371,12 +3388,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ if (vl == 0) { \ return; \ } \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ } \ + env->vstart = 0; \ } RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) @@ -3507,7 +3525,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ @@ -3516,6 +3534,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, s1, &env->fp_status)); \ } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) @@ -3530,7 +3549,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ @@ -3538,6 +3557,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet) @@ -3646,12 +3666,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i); \ } \ + env->vstart = 0; \ } target_ulong fclass_h(uint64_t frs1) @@ -3727,11 +3748,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ *((ETYPE *)vd + H(i)) \ = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ + env->vstart = 0; \ } GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2) @@ -3875,7 +3897,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t i; \ TD s1 = *((TD *)vs1 + HD(0)); \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ @@ -3883,6 +3905,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ s1 = OP(s1, (TD)s2); \ } \ *((TD *)vd + HD(0)) = s1; \ + env->vstart = 0; \ } /* vd[0] = sum(vs1[0], vs2[*]) */ @@ -3955,7 +3978,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t i; \ TD s1 = *((TD *)vs1 + HD(0)); \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ @@ -3963,6 +3986,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ s1 = OP(s1, (TD)s2, &env->fp_status); \ } \ *((TD *)vd + HD(0)) = s1; \ + env->vstart = 0; \ } /* Unordered sum */ @@ -3990,7 +4014,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, uint32_t i; uint32_t s1 = *((uint32_t *)vs1 + H4(0)); - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { uint16_t s2 = *((uint16_t *)vs2 + H2(i)); if (!vm && !vext_elem_mask(v0, i)) { continue; @@ -3999,6 +4023,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, &env->fp_status); } *((uint32_t *)vd + H4(0)) = s1; + env->vstart = 0; } void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, @@ -4009,7 +4034,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, uint32_t i; uint64_t s1 = *((uint64_t *)vs1); - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { uint32_t s2 = *((uint32_t *)vs2 + H4(i)); if (!vm && !vext_elem_mask(v0, i)) { continue; @@ -4018,6 +4043,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, &env->fp_status); } *((uint64_t *)vd) = s1; + env->vstart = 0; } /* @@ -4033,11 +4059,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t i; \ int a, b; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ a = vext_elem_mask(vs1, i); \ b = vext_elem_mask(vs2, i); \ vext_set_elem_mask(vd, i, OP(b, a)); \ } \ + env->vstart = 0; \ } #define DO_NAND(N, M) (!(N & M)) @@ -4064,13 +4091,14 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t vl = env->vl; int i; - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { if (vm || vext_elem_mask(v0, i)) { if (vext_elem_mask(vs2, i)) { cnt++; } } } + env->vstart = 0; return cnt; } @@ -4082,13 +4110,14 @@ target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t vl = env->vl; int i; - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { if (vm || vext_elem_mask(v0, i)) { if (vext_elem_mask(vs2, i)) { return i; } } } + env->vstart = 0; return -1LL; } @@ -4106,7 +4135,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, int i; bool first_mask_bit = false; - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; } @@ -4130,6 +4159,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, } } } + env->vstart = 0; } void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, @@ -4160,7 +4190,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ uint32_t sum = 0; \ int i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -4169,6 +4199,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ sum++; \ } \ } \ + env->vstart = 0; \ } GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1) @@ -4184,12 +4215,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ uint32_t vl = env->vl; \ int i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = i; \ } \ + env->vstart = 0; \ } GEN_VEXT_VID_V(vid_v_b, uint8_t, H1) @@ -4208,9 +4240,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - target_ulong offset = s1, i; \ + target_ulong offset = s1, i_min, i; \ \ - for (i = offset; i < vl; i++) { \ + i_min = MAX(env->vstart, offset); \ + for (i = i_min; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -4233,8 +4266,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vl = env->vl; \ target_ulong i_max, i; \ \ - i_max = MIN(s1 < vlmax ? vlmax - s1 : 0, vl); \ - for (i = 0; i < i_max; ++i) { \ + i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \ + for (i = env->vstart; i < i_max; ++i) { \ if (vm || vext_elem_mask(v0, i)) { \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \ } \ @@ -4245,6 +4278,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = 0; \ } \ } \ + \ + env->vstart = 0; \ } /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */ @@ -4262,7 +4297,7 @@ static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -4272,6 +4307,7 @@ static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ } \ } \ + env->vstart = 0; \ } GEN_VEXT_VSLIE1UP(8, H1) @@ -4301,7 +4337,7 @@ static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -4311,6 +4347,7 @@ static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ } \ } \ + env->vstart = 0; \ } GEN_VEXT_VSLIDE1DOWN(8, H1) @@ -4361,13 +4398,13 @@ GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS1))); \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -4378,6 +4415,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ *((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \ } \ } \ + env->vstart = 0; \ } /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */ @@ -4401,7 +4439,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ uint64_t index = s1; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ @@ -4411,6 +4449,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ } \ } \ + env->vstart = 0; \ } /* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ @@ -4427,13 +4466,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ uint32_t vl = env->vl; \ uint32_t num = 0, i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vext_elem_mask(vs1, i)) { \ continue; \ } \ *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ num++; \ } \ + env->vstart = 0; \ } /* Compress into vd elements of vs2 where vs1 is enabled */ @@ -4442,6 +4482,27 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) +/* Vector Whole Register Move */ +#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \ +void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + /* EEW = 8 */ \ + uint32_t maxsz = simd_maxsz(desc); \ + uint32_t i = env->vstart; \ + \ + memcpy((uint8_t *)vd + H1(i), \ + (uint8_t *)vs2 + H1(i), \ + maxsz - env->vstart); \ + \ + env->vstart = 0; \ +} + +GEN_VEXT_VMV_WHOLE(vmv1r_v, 1) +GEN_VEXT_VMV_WHOLE(vmv2r_v, 2) +GEN_VEXT_VMV_WHOLE(vmv4r_v, 4) +GEN_VEXT_VMV_WHOLE(vmv8r_v, 8) + /* Vector Integer Extension */ #define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ @@ -4451,12 +4512,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \ } \ + env->vstart = 0; \ } GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1) From d6c4d3f2a693f4520ec72b0bd25be6ec03fee13a Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:53 +0800 Subject: [PATCH 401/421] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trigger illegal instruction exception if frm field contains invalid value at run-time for vector floating-point instructions. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-68-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7589c8ce32..53c8573f11 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2374,6 +2374,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, int rm) { if (checkfn(s, a)) { + if (rm != RISCV_FRM_DYN) { + gen_set_rm(s, RISCV_FRM_DYN); + } + uint32_t data = 0; TCGLabel *over = gen_new_label(); gen_set_rm(s, rm); @@ -2459,6 +2463,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) require_rvf(s) && vext_check_isa_ill(s) && require_align(a->rd, s->lmul)) { + gen_set_rm(s, RISCV_FRM_DYN); + TCGv_i64 t1; if (s->vl_eq_vlmax) { @@ -2540,6 +2546,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_widen_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ gen_helper_##HELPER##_h, \ @@ -2627,6 +2637,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_narrow_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ gen_helper_##HELPER##_h, \ @@ -2668,6 +2682,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opxfv_narrow_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[3] = { \ gen_helper_##HELPER##_b, \ @@ -3138,6 +3156,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) if (require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s)) { + gen_set_rm(s, RISCV_FRM_DYN); + unsigned int ofs = (8 << s->sew); unsigned int len = 64 - ofs; TCGv_i64 t_nan; @@ -3162,6 +3182,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) if (require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s)) { + gen_set_rm(s, RISCV_FRM_DYN); + /* The instructions ignore LMUL and vector register group. */ TCGv_i64 t1; TCGLabel *over = gen_new_label(); From 719d3561b269d880b2d31e64ed7632407952bad0 Mon Sep 17 00:00:00 2001 From: Hsiangkai Wang Date: Fri, 10 Dec 2021 15:56:54 +0800 Subject: [PATCH 402/421] target/riscv: gdb: support vector registers for rv64 & rv32 Signed-off-by: Hsiangkai Wang Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-69-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/gdbstub.c | 184 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 187 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 728092f78c..9776297c79 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -675,6 +675,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) if (strcmp(xmlname, "riscv-csr.xml") == 0) { return cpu->dyn_csr_xml; + } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { + return cpu->dyn_vreg_xml; } return NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5d93ccdfa7..dc10f27093 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ struct RISCVCPU { CPURISCVState env; char *dyn_csr_xml; + char *dyn_vreg_xml; /* Configuration Settings */ struct { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..881ab33392 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -20,6 +20,32 @@ #include "exec/gdbstub.h" #include "cpu.h" +struct TypeSize { + const char *gdb_type; + const char *id; + int size; + const char suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", "quads", 128, 'q' }, + /* 64 bit */ + { "uint64", "longs", 64, 'l' }, + /* 32 bit */ + { "uint32", "words", 32, 'w' }, + /* 16 bit */ + { "uint16", "shorts", 16, 's' }, + /* + * TODO: currently there is no reliable way of telling + * if the remote gdb actually understands ieee_half so + * we don't expose it in the target description for now. + * { "ieee_half", 16, 'h', 'f' }, + */ + /* bytes */ + { "uint8", "bytes", 8, 'b' }, +}; + int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +/* + * Convert register index number passed by GDB to the correspond + * vector CSR number. Vector CSRs are defined after vector registers + * in dynamic generated riscv-vector.xml, thus the starting register index + * of vector CSRs is 32. + * Return 0 if register index number is out of range. + */ +static int riscv_gdb_vector_csrno(int num_regs) +{ + /* + * The order of vector CSRs in the switch case + * should match with the order defined in csr_ops[]. + */ + switch (num_regs) { + case 32: + return CSR_VSTART; + case 33: + return CSR_VXSAT; + case 34: + return CSR_VXRM; + case 35: + return CSR_VCSR; + case 36: + return CSR_VL; + case 37: + return CSR_VTYPE; + case 38: + return CSR_VLENB; + default: + /* Unknown register. */ + return 0; + } +} + +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt = 0; + for (i = 0; i < vlenb; i += 8) { + cnt += gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = 0; + int result = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + if (result == 0) { + return gdb_get_regl(buf, val); + } + + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i = 0; i < vlenb; i += 8) { + env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); + } + return vlenb; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = ldtul_p(mem_buf); + int result = riscv_csrrw_debug(env, csrno, NULL, val, -1); + + if (result == 0) { + return sizeof(target_ulong); + } + + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < CSR_TABLE_SIZE) { @@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) return CSR_TABLE_SIZE; } +static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + GString *s = g_string_new(NULL); + g_autoptr(GString) ts = g_string_new(""); + int reg_width = cpu->cfg.vlen; + int num_regs = 0; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "%s", vec_lanes[i].id); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + + /* Define unions */ + g_string_append_printf(s, ""); + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + g_string_append_printf(s, "", + vec_lanes[i].suffix, + vec_lanes[i].id); + } + g_string_append(s, ""); + + /* Define vector registers */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + num_regs++; + } + + /* Define vector CSRs */ + const char *vector_csrs[7] = { + "vstart", "vxsat", "vxrm", "vcsr", + "vl", "vtype", "vlenb" + }; + + for (i = 0; i < 7; i++) { + g_string_append_printf(s, + "", + vector_csrs[i], TARGET_LONG_BITS, base_reg++); + num_regs++; + } + + g_string_append_printf(s, ""); + + cpu->dyn_vreg_xml = g_string_free(s, false); + return num_regs; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa_ext & RVV) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, + ricsv_gen_dynamic_vector_xml(cs, + cs->gdb_num_regs), + "riscv-vector.xml", 0); + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); From e848a1e5632518647ac146d75b2fe006050ffb82 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:55 +0800 Subject: [PATCH 403/421] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction Implement the floating-point reciprocal square-root estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-70-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 183 ++++++++++++++++++++++++ 4 files changed, 189 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a717a87a0e..bdf06dfb24 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -841,6 +841,10 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32) + DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c4fdc76a26..6e5f288943 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -560,6 +560,7 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm +vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 53c8573f11..8fe718610a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2407,6 +2407,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ } GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 22848d6b68..d5f3229bcb 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" +#include "qemu/bitops.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -3404,6 +3405,188 @@ GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2) GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) +/* + * Vector Floating-Point Reciprocal Square-Root Estimate Instruction + * + * Adapted from riscv-v-spec recip.c: + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c + */ +static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size) +{ + uint64_t sign = extract64(f, frac_size + exp_size, 1); + uint64_t exp = extract64(f, frac_size, exp_size); + uint64_t frac = extract64(f, 0, frac_size); + + const uint8_t lookup_table[] = { + 52, 51, 50, 48, 47, 46, 44, 43, + 42, 41, 40, 39, 38, 36, 35, 34, + 33, 32, 31, 30, 30, 29, 28, 27, + 26, 25, 24, 23, 23, 22, 21, 20, + 19, 19, 18, 17, 16, 16, 15, 14, + 14, 13, 12, 12, 11, 10, 10, 9, + 9, 8, 7, 7, 6, 6, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0, + 127, 125, 123, 121, 119, 118, 116, 114, + 113, 111, 109, 108, 106, 105, 103, 102, + 100, 99, 97, 96, 95, 93, 92, 91, + 90, 88, 87, 86, 85, 84, 83, 82, + 80, 79, 78, 77, 76, 75, 74, 73, + 72, 71, 70, 70, 69, 68, 67, 66, + 65, 64, 63, 63, 62, 61, 60, 59, + 59, 58, 57, 56, 56, 55, 54, 53 + }; + const int precision = 7; + + if (exp == 0 && frac != 0) { /* subnormal */ + /* Normalize the subnormal. */ + while (extract64(frac, frac_size - 1, 1) == 0) { + exp--; + frac <<= 1; + } + + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size); + } + + int idx = ((exp & 1) << (precision - 1)) | + (frac >> (frac_size - precision + 1)); + uint64_t out_frac = (uint64_t)(lookup_table[idx]) << + (frac_size - precision); + uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2; + + uint64_t val = 0; + val = deposit64(val, 0, frac_size, out_frac); + val = deposit64(val, frac_size, exp_size, out_exp); + val = deposit64(val, frac_size + exp_size, 1, sign); + return val; +} + +static float16 frsqrt7_h(float16 f, float_status *s) +{ + int exp_size = 5, frac_size = 10; + bool sign = float16_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float16_is_signaling_nan(f, s) || + (float16_is_infinity(f) && sign) || + (float16_is_normal(f) && sign) || + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float16_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float16_is_quiet_nan(f, s)) { + return float16_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float16_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float16_set_sign(float16_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float16_is_infinity(f) && !sign) { + return float16_set_sign(float16_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float16(val); +} + +static float32 frsqrt7_s(float32 f, float_status *s) +{ + int exp_size = 8, frac_size = 23; + bool sign = float32_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float32_is_signaling_nan(f, s) || + (float32_is_infinity(f) && sign) || + (float32_is_normal(f) && sign) || + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float32_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float32_is_quiet_nan(f, s)) { + return float32_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float32_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float32_set_sign(float32_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float32_is_infinity(f) && !sign) { + return float32_set_sign(float32_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float32(val); +} + +static float64 frsqrt7_d(float64 f, float_status *s) +{ + int exp_size = 11, frac_size = 52; + bool sign = float64_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float64_is_signaling_nan(f, s) || + (float64_is_infinity(f) && sign) || + (float64_is_normal(f) && sign) || + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float64_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float64_is_quiet_nan(f, s)) { + return float64_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float64_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float64_set_sign(float64_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float64_is_infinity(f) && !sign) { + return float64_set_sign(float64_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float64(val); +} + +RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h) +RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s) +RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d) +GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2) +GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4) +GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8) + /* Vector Floating-Point MIN/MAX Instructions */ RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) From 55c35407c3706148761373aaa1d3350b57e86e8d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:56 +0800 Subject: [PATCH 404/421] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction Implement the floating-point reciprocal estimate to 7 bits instruction. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-71-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 191 ++++++++++++++++++++++++ 4 files changed, 197 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index bdf06dfb24..ab283d12b7 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -845,6 +845,10 @@ DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32) + DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6e5f288943..952768f8de 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -561,6 +561,7 @@ vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm +vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 8fe718610a..ff8f6df8f7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2408,6 +2408,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index d5f3229bcb..946dca53ff 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3587,6 +3587,197 @@ GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2) GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4) GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8) +/* + * Vector Floating-Point Reciprocal Estimate Instruction + * + * Adapted from riscv-v-spec recip.c: + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c + */ +static uint64_t frec7(uint64_t f, int exp_size, int frac_size, + float_status *s) +{ + uint64_t sign = extract64(f, frac_size + exp_size, 1); + uint64_t exp = extract64(f, frac_size, exp_size); + uint64_t frac = extract64(f, 0, frac_size); + + const uint8_t lookup_table[] = { + 127, 125, 123, 121, 119, 117, 116, 114, + 112, 110, 109, 107, 105, 104, 102, 100, + 99, 97, 96, 94, 93, 91, 90, 88, + 87, 85, 84, 83, 81, 80, 79, 77, + 76, 75, 74, 72, 71, 70, 69, 68, + 66, 65, 64, 63, 62, 61, 60, 59, + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 40, 40, 39, 38, 37, 36, + 35, 35, 34, 33, 32, 31, 31, 30, + 29, 28, 28, 27, 26, 25, 25, 24, + 23, 23, 22, 21, 21, 20, 19, 19, + 18, 17, 17, 16, 15, 15, 14, 14, + 13, 12, 12, 11, 11, 10, 9, 9, + 8, 8, 7, 7, 6, 5, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0 + }; + const int precision = 7; + + if (exp == 0 && frac != 0) { /* subnormal */ + /* Normalize the subnormal. */ + while (extract64(frac, frac_size - 1, 1) == 0) { + exp--; + frac <<= 1; + } + + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size); + + if (exp != 0 && exp != UINT64_MAX) { + /* + * Overflow to inf or max value of same sign, + * depending on sign and rounding mode. + */ + s->float_exception_flags |= (float_flag_inexact | + float_flag_overflow); + + if ((s->float_rounding_mode == float_round_to_zero) || + ((s->float_rounding_mode == float_round_down) && !sign) || + ((s->float_rounding_mode == float_round_up) && sign)) { + /* Return greatest/negative finite value. */ + return (sign << (exp_size + frac_size)) | + (MAKE_64BIT_MASK(frac_size, exp_size) - 1); + } else { + /* Return +-inf. */ + return (sign << (exp_size + frac_size)) | + MAKE_64BIT_MASK(frac_size, exp_size); + } + } + } + + int idx = frac >> (frac_size - precision); + uint64_t out_frac = (uint64_t)(lookup_table[idx]) << + (frac_size - precision); + uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp; + + if (out_exp == 0 || out_exp == UINT64_MAX) { + /* + * The result is subnormal, but don't raise the underflow exception, + * because there's no additional loss of precision. + */ + out_frac = (out_frac >> 1) | MAKE_64BIT_MASK(frac_size - 1, 1); + if (out_exp == UINT64_MAX) { + out_frac >>= 1; + out_exp = 0; + } + } + + uint64_t val = 0; + val = deposit64(val, 0, frac_size, out_frac); + val = deposit64(val, frac_size, exp_size, out_exp); + val = deposit64(val, frac_size + exp_size, 1, sign); + return val; +} + +static float16 frec7_h(float16 f, float_status *s) +{ + int exp_size = 5, frac_size = 10; + bool sign = float16_is_neg(f); + + /* frec7(+-inf) = +-0 */ + if (float16_is_infinity(f)) { + return float16_set_sign(float16_zero, sign); + } + + /* frec7(+-0) = +-inf */ + if (float16_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float16_set_sign(float16_infinity, sign); + } + + /* frec7(sNaN) = canonical NaN */ + if (float16_is_signaling_nan(f, s)) { + s->float_exception_flags |= float_flag_invalid; + return float16_default_nan(s); + } + + /* frec7(qNaN) = canonical NaN */ + if (float16_is_quiet_nan(f, s)) { + return float16_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val = frec7(f, exp_size, frac_size, s); + return make_float16(val); +} + +static float32 frec7_s(float32 f, float_status *s) +{ + int exp_size = 8, frac_size = 23; + bool sign = float32_is_neg(f); + + /* frec7(+-inf) = +-0 */ + if (float32_is_infinity(f)) { + return float32_set_sign(float32_zero, sign); + } + + /* frec7(+-0) = +-inf */ + if (float32_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float32_set_sign(float32_infinity, sign); + } + + /* frec7(sNaN) = canonical NaN */ + if (float32_is_signaling_nan(f, s)) { + s->float_exception_flags |= float_flag_invalid; + return float32_default_nan(s); + } + + /* frec7(qNaN) = canonical NaN */ + if (float32_is_quiet_nan(f, s)) { + return float32_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val = frec7(f, exp_size, frac_size, s); + return make_float32(val); +} + +static float64 frec7_d(float64 f, float_status *s) +{ + int exp_size = 11, frac_size = 52; + bool sign = float64_is_neg(f); + + /* frec7(+-inf) = +-0 */ + if (float64_is_infinity(f)) { + return float64_set_sign(float64_zero, sign); + } + + /* frec7(+-0) = +-inf */ + if (float64_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float64_set_sign(float64_infinity, sign); + } + + /* frec7(sNaN) = canonical NaN */ + if (float64_is_signaling_nan(f, s)) { + s->float_exception_flags |= float_flag_invalid; + return float64_default_nan(s); + } + + /* frec7(qNaN) = canonical NaN */ + if (float64_is_quiet_nan(f, s)) { + return float64_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val = frec7(f, exp_size, frac_size, s); + return make_float64(val); +} + +RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h) +RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s) +RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d) +GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2) +GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4) +GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8) + /* Vector Floating-Point MIN/MAX Instructions */ RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) From 6b5c8eb3e7de3c1b9dc2845b6b001ddd7d2eb359 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:57 +0800 Subject: [PATCH 405/421] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction. vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 952768f8de..d7c6bc9af2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -78,7 +78,7 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd -@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -671,7 +671,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm -vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r # *** RV32 Zba Standard Extension *** From 34a2c2d81ad94ff910051b8b93b4aaff895cec88 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:58 +0800 Subject: [PATCH 406/421] target/riscv: rvv-1.0: add vsetivli instruction Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.c.inc | 27 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d7c6bc9af2..3b6524bad9 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -79,6 +79,7 @@ @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -672,6 +673,7 @@ vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 +vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r # *** RV32 Zba Standard Extension *** diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ff8f6df8f7..e540b5d33c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -160,6 +160,26 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) return true; } +static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) +{ + TCGv dst; + + if (!require_rvv(s) || !has_ext(s, RVV)) { + return false; + } + + dst = dest_gpr(s, rd); + + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(s, rd, dst); + mark_vs_dirty(s); + tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); + tcg_gen_lookup_and_goto_ptr(); + s->base.is_jmp = DISAS_NORETURN; + + return true; +} + static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) { TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO); @@ -172,6 +192,13 @@ static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a) return do_vsetvl(s, a->rd, a->rs1, s2); } +static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a) +{ + TCGv s1 = tcg_const_tl(a->rs1); + TCGv s2 = tcg_const_tl(a->zimm); + return do_vsetivli(s, a->rd, s1, s2); +} + /* vector register offset from env */ static uint32_t vreg_ofs(DisasContext *s, int reg) { From 5c89e9c0966dd423207bc477fcda9eb454d4308f Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:59 +0800 Subject: [PATCH 407/421] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 946dca53ff..83373ca6fc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -279,15 +279,15 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) /* unmasked unit-stride load and store operation*/ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn *ldst_elem, - uint32_t esz, uintptr_t ra, MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl, + uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t max_elems = vext_max_elems(desc, esz); /* load bytes from guest memory */ - for (i = env->vstart; i < env->vl; i++, env->vstart++) { + for (i = env->vstart; i < evl; i++, env->vstart++) { k = 0; while (k < nf) { target_ulong addr = base + ((i * nf + k) << esz); @@ -316,7 +316,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \ } GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) @@ -324,20 +324,20 @@ GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) -#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ -void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ -} \ - \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldst_us(vd, base, env, desc, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ + vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ +} \ + \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_us(vd, base, env, desc, STORE_FN, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \ } GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) From 26086aea0d4f5575c0b66acd05ccb41349f8a32d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:57:00 +0800 Subject: [PATCH 408/421] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.c.inc | 40 +++++++++++++++++++++++++ target/riscv/vector_helper.c | 21 +++++++++++++ 4 files changed, 67 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index ab283d12b7..6e58343af3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -129,6 +129,8 @@ DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32) DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlm_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsm_v, void, ptr, ptr, tl, env, i32) DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32) DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3b6524bad9..1a4a287146 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -305,6 +305,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm +# Vector unit-stride mask load/store insns. +vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 +vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 + # Vector strided insns. vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index e540b5d33c..97b1dc1026 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -697,6 +697,46 @@ GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check) GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check) GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check) +/* + *** unit stride mask load and store + */ +static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn = gen_helper_vlm_v; + + /* EMUL = 1, NFIELDS = 1 */ + data = FIELD_DP32(data, VDATA, LMUL, 0); + data = FIELD_DP32(data, VDATA, NF, 1); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); +} + +static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew) +{ + /* EMUL = 1, NFIELDS = 1 */ + return require_rvv(s) && vext_check_isa_ill(s); +} + +static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn = gen_helper_vsm_v; + + /* EMUL = 1, NFIELDS = 1 */ + data = FIELD_DP32(data, VDATA, LMUL, 0); + data = FIELD_DP32(data, VDATA, NF, 1); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); +} + +static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew) +{ + /* EMUL = 1, NFIELDS = 1 */ + return require_rvv(s) && vext_check_isa_ill(s); +} + +GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check) +GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check) + /* *** stride load and store */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 83373ca6fc..4c1a1310e6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -345,6 +345,27 @@ GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) +/* + *** unit stride mask load and store, EEW = 1 + */ +void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl = ceil(vl/8) */ + uint8_t evl = (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, lde_b, + 0, evl, GETPC(), MMU_DATA_LOAD); +} + +void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl = ceil(vl/8) */ + uint8_t evl = (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, ste_b, + 0, evl, GETPC(), MMU_DATA_STORE); +} + /* *** index: access vector element from indexed memory */ From 9c0d2559deb11ee3d62153b5911e891d1b3679c1 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:57:01 +0800 Subject: [PATCH 409/421] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 4 ++-- target/riscv/insn32.decode | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6e58343af3..c15497e4a1 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1016,11 +1016,11 @@ DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmandn_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmorn_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_4(vcpop_m, tl, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1a4a287146..8617307b29 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -635,11 +635,11 @@ vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r -vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r +vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r -vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r +vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 97b1dc1026..33ef7926e6 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2862,11 +2862,11 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ GEN_MM_TRANS(vmand_mm) GEN_MM_TRANS(vmnand_mm) -GEN_MM_TRANS(vmandnot_mm) +GEN_MM_TRANS(vmandn_mm) GEN_MM_TRANS(vmxor_mm) GEN_MM_TRANS(vmor_mm) GEN_MM_TRANS(vmnor_mm) -GEN_MM_TRANS(vmornot_mm) +GEN_MM_TRANS(vmorn_mm) GEN_MM_TRANS(vmxnor_mm) /* Vector count population in mask vcpop */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4c1a1310e6..ad505ec9b2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4470,11 +4470,11 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ GEN_VEXT_MASK_VV(vmand_mm, DO_AND) GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND) -GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT) +GEN_VEXT_MASK_VV(vmandn_mm, DO_ANDNOT) GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR) GEN_VEXT_MASK_VV(vmor_mm, DO_OR) GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) -GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) +GEN_VEXT_MASK_VV(vmorn_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) /* Vector count population in mask vcpop */ From 45ca2ca6bdfbfc802fde87721ff3d164ea970d3d Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:57:02 +0800 Subject: [PATCH 410/421] target/riscv: rvv-1.0: update opivv_vadc_check() comment Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is moved to Section 11.4 in RVV v1.0 spec. Update the comment, no functional changes. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20211210075704.23951-77-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 33ef7926e6..47eb3119cb 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.4) + * destination vector register is v0 and LMUL > 1. (Section 11.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { From cc13aa3614519159e21f5bc1710c13fc79323853 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:57:03 +0800 Subject: [PATCH 411/421] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions SEW has the limitation which cannot exceed ELEN. Widening instructions have a destination group with EEW = 2*SEW and narrowing instructions have a source operand with EEW = 2*SEW. Both of the instructions have the limitation of: 2*SEW <= ELEN. Signed-off-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20211210075704.23951-78-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++++++++------ target/riscv/translate.c | 2 ++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 47eb3119cb..5e3f7fdb77 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -386,9 +386,10 @@ static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) * can not be greater than 8 vector registers (Section 5.2): * => LMUL < 8. * => SEW < 64. - * 2. Destination vector register number is multiples of 2 * LMUL. + * 2. Double-width SEW cannot greater than ELEN. + * 3. Destination vector register number is multiples of 2 * LMUL. * (Section 3.4.2) - * 3. Destination vector register group for a masked vector + * 4. Destination vector register group for a masked vector * instruction cannot overlap the source mask register (v0). * (Section 5.3) */ @@ -396,6 +397,7 @@ static bool vext_wide_check_common(DisasContext *s, int vd, int vm) { return (s->lmul <= 2) && (s->sew < MO_64) && + ((s->sew + 1) <= (s->elen >> 4)) && require_align(vd, s->lmul + 1) && require_vm(vm, vd); } @@ -409,11 +411,12 @@ static bool vext_wide_check_common(DisasContext *s, int vd, int vm) * can not be greater than 8 vector registers (Section 5.2): * => LMUL < 8. * => SEW < 64. - * 2. Source vector register number is multiples of 2 * LMUL. + * 2. Double-width SEW cannot greater than ELEN. + * 3. Source vector register number is multiples of 2 * LMUL. * (Section 3.4.2) - * 3. Destination vector register number is multiples of LMUL. + * 4. Destination vector register number is multiples of LMUL. * (Section 3.4.2) - * 4. Destination vector register group for a masked vector + * 5. Destination vector register group for a masked vector * instruction cannot overlap the source mask register (v0). * (Section 5.3) */ @@ -422,6 +425,7 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, { return (s->lmul <= 2) && (s->sew < MO_64) && + ((s->sew + 1) <= (s->elen >> 4)) && require_align(vs2, s->lmul + 1) && require_align(vd, s->lmul) && require_vm(vm, vd); @@ -2806,7 +2810,8 @@ GEN_OPIVV_TRANS(vredxor_vs, reduction_check) /* Vector Widening Integer Reduction Instructions */ static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) { - return reduction_check(s, a) && (s->sew < MO_64); + return reduction_check(s, a) && (s->sew < MO_64) && + ((s->sew + 1) <= (s->elen >> 4)); } GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 68edaaf6ac..5df6c0d800 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -96,6 +96,7 @@ typedef struct DisasContext { int8_t lmul; uint8_t sew; uint16_t vlen; + uint16_t elen; target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; @@ -705,6 +706,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->ext_zfh = cpu->cfg.ext_zfh; ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; ctx->vlen = cpu->cfg.vlen; + ctx->elen = cpu->cfg.elen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); From a7cad953fa2d5d4dd063a817c0d506eeb39310f5 Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Wed, 15 Dec 2021 23:31:11 -0800 Subject: [PATCH 412/421] riscv: Set 5.4 as minimum kernel version for riscv32 5.4 is first stable API as far as rv32 is concerned see [1] [1] https://sourceware.org/git/?p=glibc.git;a=commit;h=7a55dd3fb6d2c307a002a16776be84310b9c8989 Signed-off-by: Khem Raj Reviewed-by: Alistair Francis Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Message-Id: <20211216073111.2890607-1-raj.khem@gmail.com> Signed-off-by: Alistair Francis --- linux-user/riscv/target_syscall.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/riscv/target_syscall.h b/linux-user/riscv/target_syscall.h index dc597c8972..9b13161324 100644 --- a/linux-user/riscv/target_syscall.h +++ b/linux-user/riscv/target_syscall.h @@ -45,10 +45,11 @@ struct target_pt_regs { #ifdef TARGET_RISCV32 #define UNAME_MACHINE "riscv32" +#define UNAME_MINIMUM_RELEASE "5.4.0" #else #define UNAME_MACHINE "riscv64" -#endif #define UNAME_MINIMUM_RELEASE "4.15.0" +#endif #define TARGET_MINSIGSTKSZ 2048 #define TARGET_MCL_CURRENT 1 From 0643c12e4bc021ce5cb06aa1bfa02d25d8386b61 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Wed, 15 Dec 2021 21:18:44 -0800 Subject: [PATCH 413/421] target/riscv: Enable bitmanip Zb[abcs] instructions The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta Reviewed-by: Alistair Francis Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9776297c79..6ef3314bce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -641,10 +641,10 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), - DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), - DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), - DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ From 7e322a7f23a60b0e181b55ef722fdf390ec4e463 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Tue, 14 Dec 2021 03:24:56 +0000 Subject: [PATCH 414/421] hw/riscv: Use load address rather than entry point for fw_dynamic next_addr The original BBL boot method had the kernel embedded as an opaque blob that was blindly jumped to, which OpenSBI implemented as fw_payload. OpenSBI then implemented fw_jump, which allows the payload to be loaded elsewhere, but still blindly jumps to a fixed address at which the kernel is to be loaded. Finally, OpenSBI introduced fw_dynamic, which allows the previous stage to inform it where to jump to, rather than having to blindly guess like fw_jump, or embed the payload as part of the build like fw_payload. When used with an opaque binary (i.e. the output of objcopy -O binary), it matches the behaviour of the previous methods. However, when used with an ELF, QEMU currently passes on the ELF's entry point address, which causes a discrepancy compared with all the other boot methods if that entry point is not the first instruction in the binary. This difference specific to fw_dynamic with an ELF is not apparent when booting Linux, since its entry point is the first instruction in the binary. However, FreeBSD has a separate ELF entry point, following the calling convention used by its bootloader, that differs from the first instruction in the binary, used for the legacy SBI entry point, and so the specific combination of QEMU's default fw_dynamic firmware with booting FreeBSD as an ELF rather than a raw binary does not work. Thus, align the behaviour when loading an ELF with the behaviour when loading a raw binary; namely, use the base address of the loaded kernel in place of the entry point. The uImage code is left as-is in using the U-Boot header's entry point, since the calling convention for that entry point is the same as the SBI one and it mirrors what U-Boot will do. Signed-off-by: Jessica Clarke Reviewed-by: Alistair Francis Message-Id: <20211214032456.70203-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 519fa455a1..f67264374e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -151,12 +151,19 @@ target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { - uint64_t kernel_entry; + uint64_t kernel_load_base, kernel_entry; + /* + * NB: Use low address not ELF entry point to ensure that the fw_dynamic + * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL + * behaviour, as well as fw_dynamic with a raw binary, all of which jump to + * the (expected) load address load address. This allows kernels to have + * separate SBI and ELF entry points (used by FreeBSD, for example). + */ if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, NULL, NULL, 0, + NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_entry; + return kernel_load_base; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, From bbf15aaf7c7506c88062288b3ae122b882f65e69 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 16:14:00 +0100 Subject: [PATCH 415/421] common-user: Move safe-syscall.* from linux-user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move linux-user safe-syscall.S and safe-syscall-error.c to common-user so that bsd-user can also use it. Also move safe-syscall.h to include/user/. Since there is nothing here that is related to the guest, as opposed to the host, build it once. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- MAINTAINERS | 2 ++ bsd-user/meson.build | 2 ++ .../host/aarch64/safe-syscall.inc.S | 2 +- .../host/arm/safe-syscall.inc.S | 2 +- .../host/i386/safe-syscall.inc.S | 2 +- .../host/mips/safe-syscall.inc.S | 2 +- .../host/ppc64/safe-syscall.inc.S | 2 +- .../host/riscv/safe-syscall.inc.S | 2 +- .../host/s390x/safe-syscall.inc.S | 2 +- .../host/sparc64/safe-syscall.inc.S | 2 +- .../host/x86_64/safe-syscall.inc.S | 2 +- common-user/meson.build | 6 ++++++ .../safe-syscall-error.c | 2 +- {linux-user => common-user}/safe-syscall.S | 0 {linux-user => include/user}/safe-syscall.h | 0 linux-user/meson.build | 5 +++-- linux-user/signal.c | 2 +- linux-user/syscall.c | 2 +- meson.build | 18 +++++++++++++++++- 19 files changed, 42 insertions(+), 15 deletions(-) rename {linux-user => common-user}/host/aarch64/safe-syscall.inc.S (97%) rename {linux-user => common-user}/host/arm/safe-syscall.inc.S (98%) rename {linux-user => common-user}/host/i386/safe-syscall.inc.S (98%) rename {linux-user => common-user}/host/mips/safe-syscall.inc.S (98%) rename {linux-user => common-user}/host/ppc64/safe-syscall.inc.S (98%) rename {linux-user => common-user}/host/riscv/safe-syscall.inc.S (97%) rename {linux-user => common-user}/host/s390x/safe-syscall.inc.S (98%) rename {linux-user => common-user}/host/sparc64/safe-syscall.inc.S (97%) rename {linux-user => common-user}/host/x86_64/safe-syscall.inc.S (98%) create mode 100644 common-user/meson.build rename {linux-user => common-user}/safe-syscall-error.c (95%) rename {linux-user => common-user}/safe-syscall.S (100%) rename {linux-user => include/user}/safe-syscall.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 9a8d1bdf72..be8fc57538 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3079,6 +3079,8 @@ M: Riku Voipio S: Maintained F: thunk.c F: accel/tcg/user-exec*.c +F: include/user/ +F: common-user/ BSD user M: Warner Losh diff --git a/bsd-user/meson.build b/bsd-user/meson.build index 87885d91ed..25c3976ead 100644 --- a/bsd-user/meson.build +++ b/bsd-user/meson.build @@ -2,6 +2,8 @@ if not have_bsd_user subdir_done() endif +common_user_inc += include_directories('.') + bsd_user_ss.add(files( 'bsdload.c', 'elfload.c', diff --git a/linux-user/host/aarch64/safe-syscall.inc.S b/common-user/host/aarch64/safe-syscall.inc.S similarity index 97% rename from linux-user/host/aarch64/safe-syscall.inc.S rename to common-user/host/aarch64/safe-syscall.inc.S index 87c9580faa..73a04b73b3 100644 --- a/linux-user/host/aarch64/safe-syscall.inc.S +++ b/common-user/host/aarch64/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2016 Red Hat, Inc. diff --git a/linux-user/host/arm/safe-syscall.inc.S b/common-user/host/arm/safe-syscall.inc.S similarity index 98% rename from linux-user/host/arm/safe-syscall.inc.S rename to common-user/host/arm/safe-syscall.inc.S index f1a6aabfd3..66176a902c 100644 --- a/linux-user/host/arm/safe-syscall.inc.S +++ b/common-user/host/arm/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2016 Red Hat, Inc. diff --git a/linux-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S similarity index 98% rename from linux-user/host/i386/safe-syscall.inc.S rename to common-user/host/i386/safe-syscall.inc.S index 1fb031d228..aced8c5141 100644 --- a/linux-user/host/i386/safe-syscall.inc.S +++ b/common-user/host/i386/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2016 Red Hat, Inc. diff --git a/linux-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S similarity index 98% rename from linux-user/host/mips/safe-syscall.inc.S rename to common-user/host/mips/safe-syscall.inc.S index e9362e774d..fc75a337d1 100644 --- a/linux-user/host/mips/safe-syscall.inc.S +++ b/common-user/host/mips/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2021 Linaro, Inc. diff --git a/linux-user/host/ppc64/safe-syscall.inc.S b/common-user/host/ppc64/safe-syscall.inc.S similarity index 98% rename from linux-user/host/ppc64/safe-syscall.inc.S rename to common-user/host/ppc64/safe-syscall.inc.S index 69d3c70094..947a850dfd 100644 --- a/linux-user/host/ppc64/safe-syscall.inc.S +++ b/common-user/host/ppc64/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2016 Red Hat, Inc. diff --git a/linux-user/host/riscv/safe-syscall.inc.S b/common-user/host/riscv/safe-syscall.inc.S similarity index 97% rename from linux-user/host/riscv/safe-syscall.inc.S rename to common-user/host/riscv/safe-syscall.inc.S index ca456d8a46..dfe83c300e 100644 --- a/linux-user/host/riscv/safe-syscall.inc.S +++ b/common-user/host/riscv/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2018 Linaro, Inc. diff --git a/linux-user/host/s390x/safe-syscall.inc.S b/common-user/host/s390x/safe-syscall.inc.S similarity index 98% rename from linux-user/host/s390x/safe-syscall.inc.S rename to common-user/host/s390x/safe-syscall.inc.S index 66f84385a2..2ccbaa2402 100644 --- a/linux-user/host/s390x/safe-syscall.inc.S +++ b/common-user/host/s390x/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2016 Red Hat, Inc. diff --git a/linux-user/host/sparc64/safe-syscall.inc.S b/common-user/host/sparc64/safe-syscall.inc.S similarity index 97% rename from linux-user/host/sparc64/safe-syscall.inc.S rename to common-user/host/sparc64/safe-syscall.inc.S index f4b3c0f9ae..a2f2b9c967 100644 --- a/linux-user/host/sparc64/safe-syscall.inc.S +++ b/common-user/host/sparc64/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Written by Richard Henderson * Copyright (C) 2021 Linaro, Inc. diff --git a/linux-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S similarity index 98% rename from linux-user/host/x86_64/safe-syscall.inc.S rename to common-user/host/x86_64/safe-syscall.inc.S index f88cbe1347..84fed206f9 100644 --- a/linux-user/host/x86_64/safe-syscall.inc.S +++ b/common-user/host/x86_64/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Copyright (C) 2015 Timothy Edward Baldwin * diff --git a/common-user/meson.build b/common-user/meson.build new file mode 100644 index 0000000000..5cb42bc664 --- /dev/null +++ b/common-user/meson.build @@ -0,0 +1,6 @@ +common_user_inc += include_directories('host/' / host_arch) + +common_user_ss.add(files( + 'safe-syscall.S', + 'safe-syscall-error.c', +)) diff --git a/linux-user/safe-syscall-error.c b/common-user/safe-syscall-error.c similarity index 95% rename from linux-user/safe-syscall-error.c rename to common-user/safe-syscall-error.c index 55d95ac39a..cf74b504f8 100644 --- a/linux-user/safe-syscall-error.c +++ b/common-user/safe-syscall-error.c @@ -10,7 +10,7 @@ */ #include "qemu/osdep.h" -#include "safe-syscall.h" +#include "user/safe-syscall.h" /* * This is intended to be invoked via tail-call on the error path diff --git a/linux-user/safe-syscall.S b/common-user/safe-syscall.S similarity index 100% rename from linux-user/safe-syscall.S rename to common-user/safe-syscall.S diff --git a/linux-user/safe-syscall.h b/include/user/safe-syscall.h similarity index 100% rename from linux-user/safe-syscall.h rename to include/user/safe-syscall.h diff --git a/linux-user/meson.build b/linux-user/meson.build index 94ac3c58ce..eef1dd68bd 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -2,6 +2,9 @@ if not have_linux_user subdir_done() endif +common_user_inc += include_directories('host/' / host_arch) +common_user_inc += include_directories('.') + linux_user_ss.add(files( 'elfload.c', 'exit.c', @@ -9,8 +12,6 @@ linux_user_ss.add(files( 'linuxload.c', 'main.c', 'mmap.c', - 'safe-syscall.S', - 'safe-syscall-error.c', 'signal.c', 'strace.c', 'syscall.c', diff --git a/linux-user/signal.c b/linux-user/signal.c index 12b1705287..510db73c34 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -31,7 +31,7 @@ #include "trace.h" #include "signal-common.h" #include "host-signal.h" -#include "safe-syscall.h" +#include "user/safe-syscall.h" static struct target_sigaction sigact_table[TARGET_NSIG]; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index f5bf6d155c..56a3e17183 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -132,7 +132,7 @@ #include "signal-common.h" #include "loader.h" #include "user-mmap.h" -#include "safe-syscall.h" +#include "user/safe-syscall.h" #include "qemu/guest-random.h" #include "qemu/selfmap.h" #include "user/syscall-trace.h" diff --git a/meson.build b/meson.build index 2495360fd0..4e0a8033f7 100644 --- a/meson.build +++ b/meson.build @@ -2378,6 +2378,7 @@ block_ss = ss.source_set() bsd_user_ss = ss.source_set() chardev_ss = ss.source_set() common_ss = ss.source_set() +common_user_ss = ss.source_set() crypto_ss = ss.source_set() hwcore_ss = ss.source_set() io_ss = ss.source_set() @@ -2622,15 +2623,30 @@ subdir('tcg') subdir('fpu') subdir('accel') subdir('plugins') +subdir('ebpf') + +common_user_inc = [] + +subdir('common-user') subdir('bsd-user') subdir('linux-user') -subdir('ebpf') specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) linux_user_ss.add(files('thunk.c')) specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) +common_user_ss = common_user_ss.apply(config_all, strict: false) +common_user = static_library('common-user', + sources: common_user_ss.sources(), + dependencies: common_user_ss.dependencies(), + include_directories: common_user_inc, + name_suffix: 'fa', + build_by_default: false) +common_user = declare_dependency(link_with: common_user) + +user_ss.add(common_user) + # needed for fuzzing binaries subdir('tests/qtest/libqos') subdir('tests/qtest/fuzz') From 5bfd125ec8ba8aab04f3a636dcea39f6c4075ced Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 23 Nov 2021 15:18:49 +0100 Subject: [PATCH 416/421] common-user: Adjust system call return on FreeBSD FreeBSD system calls return positive errno. On the 4 hosts for which we have support, error is indicated by the C bit set or clear. Reviewed-by: Warner Losh Signed-off-by: Richard Henderson --- common-user/host/aarch64/safe-syscall.inc.S | 14 +++++++++++++- common-user/host/arm/safe-syscall.inc.S | 9 +++++++++ common-user/host/i386/safe-syscall.inc.S | 11 +++++++++++ common-user/host/x86_64/safe-syscall.inc.S | 11 +++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/common-user/host/aarch64/safe-syscall.inc.S b/common-user/host/aarch64/safe-syscall.inc.S index 73a04b73b3..b8fd5b553e 100644 --- a/common-user/host/aarch64/safe-syscall.inc.S +++ b/common-user/host/aarch64/safe-syscall.inc.S @@ -60,17 +60,29 @@ safe_syscall_start: cbnz w10, 2f svc 0x0 safe_syscall_end: + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ cmp x0, #-4096 b.hi 0f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + b.cs 1f +#else +#error "unsupported os" +#endif ret +#if defined(__linux__) /* code path setting errno */ 0: neg w0, w0 b safe_syscall_set_errno_tail +#endif /* code path when we didn't execute the syscall */ 2: mov w0, #QEMU_ERESTARTSYS - b safe_syscall_set_errno_tail +1: b safe_syscall_set_errno_tail + .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/host/arm/safe-syscall.inc.S b/common-user/host/arm/safe-syscall.inc.S index 66176a902c..bbfb89634e 100644 --- a/common-user/host/arm/safe-syscall.inc.S +++ b/common-user/host/arm/safe-syscall.inc.S @@ -74,10 +74,19 @@ safe_syscall_start: bne 2f swi 0 safe_syscall_end: + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ cmp r0, #-4096 neghi r0, r0 bhi 1f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + bcs 1f +#else +#error "unsupported os" +#endif pop { r4, r5, r6, r7, r8, pc } /* code path when we didn't execute the syscall */ diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S index aced8c5141..baf5400a29 100644 --- a/common-user/host/i386/safe-syscall.inc.S +++ b/common-user/host/i386/safe-syscall.inc.S @@ -71,9 +71,18 @@ safe_syscall_start: mov 8+16(%esp), %eax /* syscall number */ int $0x80 safe_syscall_end: + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ cmp $-4095, %eax jae 0f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + jc 1f +#else +#error "unsupported os" +#endif pop %ebx .cfi_remember_state .cfi_adjust_cfa_offset -4 @@ -90,8 +99,10 @@ safe_syscall_end: ret .cfi_restore_state +#if defined(__linux__) 0: neg %eax jmp 1f +#endif /* code path when we didn't execute the syscall */ 2: mov $QEMU_ERESTARTSYS, %eax diff --git a/common-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S index 84fed206f9..a20927a783 100644 --- a/common-user/host/x86_64/safe-syscall.inc.S +++ b/common-user/host/x86_64/safe-syscall.inc.S @@ -68,9 +68,18 @@ safe_syscall_start: jnz 2f syscall safe_syscall_end: + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ cmp $-4095, %rax jae 0f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + jc 1f +#else +#error "unsupported os" +#endif pop %rbp .cfi_remember_state .cfi_def_cfa_offset 8 @@ -78,8 +87,10 @@ safe_syscall_end: ret .cfi_restore_state +#if defined(__linux__) 0: neg %eax jmp 1f +#endif /* code path when we didn't execute the syscall */ 2: mov $QEMU_ERESTARTSYS, %eax From ff9c1e5500141df7be15446ccfbdc66752812a9a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 16:26:14 +0100 Subject: [PATCH 417/421] linux-user: Move thunk.c from top-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit So far, linux-user is the only user of these functions. Clean up the build machinery by restricting it to linux-user. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- MAINTAINERS | 1 - linux-user/meson.build | 1 + thunk.c => linux-user/thunk.c | 0 meson.build | 1 - 4 files changed, 1 insertion(+), 2 deletions(-) rename thunk.c => linux-user/thunk.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index be8fc57538..1de6ce6e44 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3077,7 +3077,6 @@ Usermode Emulation Overall usermode emulation M: Riku Voipio S: Maintained -F: thunk.c F: accel/tcg/user-exec*.c F: include/user/ F: common-user/ diff --git a/linux-user/meson.build b/linux-user/meson.build index eef1dd68bd..ca8b86f209 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -15,6 +15,7 @@ linux_user_ss.add(files( 'signal.c', 'strace.c', 'syscall.c', + 'thunk.c', 'uaccess.c', 'uname.c', )) diff --git a/thunk.c b/linux-user/thunk.c similarity index 100% rename from thunk.c rename to linux-user/thunk.c diff --git a/meson.build b/meson.build index 4e0a8033f7..eebeaab9ce 100644 --- a/meson.build +++ b/meson.build @@ -2633,7 +2633,6 @@ subdir('linux-user') specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) -linux_user_ss.add(files('thunk.c')) specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) common_user_ss = common_user_ss.apply(config_all, strict: false) From 4d06bb4e030fcb99c161d070f22e4ca79aced0a9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 16:32:06 +0100 Subject: [PATCH 418/421] meson: Move linux_user_ss to linux-user/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have no need to reference linux_user_ss outside of linux-user. Go ahead and merge it directly into specific_ss. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/meson.build | 4 ++++ meson.build | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/linux-user/meson.build b/linux-user/meson.build index ca8b86f209..b2f4afd5e7 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -2,6 +2,8 @@ if not have_linux_user subdir_done() endif +linux_user_ss = ss.source_set() + common_user_inc += include_directories('host/' / host_arch) common_user_inc += include_directories('.') @@ -42,3 +44,5 @@ subdir('sh4') subdir('sparc') subdir('x86_64') subdir('xtensa') + +specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) diff --git a/meson.build b/meson.build index eebeaab9ce..cc4df68b20 100644 --- a/meson.build +++ b/meson.build @@ -2382,7 +2382,6 @@ common_user_ss = ss.source_set() crypto_ss = ss.source_set() hwcore_ss = ss.source_set() io_ss = ss.source_set() -linux_user_ss = ss.source_set() qmp_ss = ss.source_set() qom_ss = ss.source_set() softmmu_ss = ss.source_set() @@ -2633,8 +2632,6 @@ subdir('linux-user') specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) -specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) - common_user_ss = common_user_ss.apply(config_all, strict: false) common_user = static_library('common-user', sources: common_user_ss.sources(), From 3363615a65af8a09d8adbd19ed3ae6b52f26ca7a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 17 Nov 2021 16:35:01 +0100 Subject: [PATCH 419/421] meson: Move bsd_user_ss to bsd-user/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have no need to reference bsd_user_ss outside of bsd-user. Go ahead and merge it directly into specific_ss. Reviewed-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- bsd-user/meson.build | 4 ++++ meson.build | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/bsd-user/meson.build b/bsd-user/meson.build index 25c3976ead..9fcb80c3fa 100644 --- a/bsd-user/meson.build +++ b/bsd-user/meson.build @@ -2,6 +2,8 @@ if not have_bsd_user subdir_done() endif +bsd_user_ss = ss.source_set() + common_user_inc += include_directories('.') bsd_user_ss.add(files( @@ -17,3 +19,5 @@ bsd_user_ss.add(files( # Pull in the OS-specific build glue, if any subdir(targetos) + +specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) diff --git a/meson.build b/meson.build index cc4df68b20..f45ecf31bd 100644 --- a/meson.build +++ b/meson.build @@ -2375,7 +2375,6 @@ genh += hxdep authz_ss = ss.source_set() blockdev_ss = ss.source_set() block_ss = ss.source_set() -bsd_user_ss = ss.source_set() chardev_ss = ss.source_set() common_ss = ss.source_set() common_user_ss = ss.source_set() @@ -2630,8 +2629,6 @@ subdir('common-user') subdir('bsd-user') subdir('linux-user') -specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) - common_user_ss = common_user_ss.apply(config_all, strict: false) common_user = static_library('common-user', sources: common_user_ss.sources(), From 6baba3a7bb90c38b94196ce934284e2cca2288b2 Mon Sep 17 00:00:00 2001 From: Andrea Fioraldi Date: Tue, 21 Dec 2021 12:27:45 +0100 Subject: [PATCH 420/421] Fix pic in declare_dependency in meson.build --- meson.build | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/meson.build b/meson.build index 4087a2cc91..250c596632 100644 --- a/meson.build +++ b/meson.build @@ -2797,8 +2797,7 @@ libmigration = static_library('migration', sources: migration_files + genh, build_by_default: false, pic: 'AS_SHARED_LIB' in config_host) migration = declare_dependency(link_with: libmigration, - dependencies: [zlib, qom, io], - pic: 'AS_SHARED_LIB' in config_host) + dependencies: [zlib, qom, io]) softmmu_ss.add(migration) block_ss = block_ss.apply(config_host, strict: false) From 652155bab71357380420f90a944e463ba4bcd372 Mon Sep 17 00:00:00 2001 From: Andrea Fioraldi Date: Tue, 21 Dec 2021 12:36:05 +0100 Subject: [PATCH 421/421] Fix pic in meson.build --- meson.build | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/meson.build b/meson.build index 250c596632..01a4eac83c 100644 --- a/meson.build +++ b/meson.build @@ -2208,7 +2208,8 @@ if have_system build_by_default: false, sources: slirp_files, c_args: slirp_cargs, - include_directories: slirp_inc) + include_directories: slirp_inc, + pic: 'AS_SHARED_LIB' in config_host) slirp = declare_dependency(link_with: libslirp, dependencies: slirp_deps, include_directories: slirp_inc) @@ -2268,7 +2269,8 @@ if have_system libfdt = static_library('fdt', build_by_default: false, sources: fdt_files, - include_directories: fdt_inc) + include_directories: fdt_inc, + pic: 'AS_SHARED_LIB' in config_host) fdt = declare_dependency(link_with: libfdt, include_directories: fdt_inc) endif @@ -2605,7 +2607,8 @@ if get_option('b_lto') pagevary_flags += '-fno-sanitize=cfi-icall' endif pagevary = static_library('page-vary-common', sources: pagevary, - c_args: pagevary_flags) + c_args: pagevary_flags, + pic: 'AS_SHARED_LIB' in config_host) pagevary = declare_dependency(link_with: pagevary) endif common_ss.add(pagevary) @@ -2637,7 +2640,8 @@ common_user = static_library('common-user', dependencies: common_user_ss.dependencies(), include_directories: common_user_inc, name_suffix: 'fa', - build_by_default: false) + build_by_default: false, + pic: 'AS_SHARED_LIB' in config_host) common_user = declare_dependency(link_with: common_user) user_ss.add(common_user) @@ -2738,7 +2742,8 @@ if enable_modules input: modinfo_files, command: [modinfo_generate, '@INPUT@'], capture: true) - modinfo_lib = static_library('modinfo', modinfo_src) + modinfo_lib = static_library('modinfo', modinfo_src, + pic: 'AS_SHARED_LIB' in config_host) modinfo_dep = declare_dependency(link_whole: modinfo_lib) softmmu_ss.add(modinfo_dep) endif