diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 71d0f407ad..7e1cb0b3c2 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -100,6 +100,17 @@ avocado-system-debian: IMAGE: debian-amd64 MAKE_CHECK_ARGS: check-avocado +crash-test-debian: + extends: .native_test_job_template + needs: + - job: build-system-debian + artifacts: true + variables: + IMAGE: debian-amd64 + script: + - cd build + - scripts/device-crash-test -q ./qemu-system-i386 + build-system-fedora: extends: .native_build_job_template needs: @@ -134,6 +145,18 @@ avocado-system-fedora: IMAGE: fedora MAKE_CHECK_ARGS: check-avocado +crash-test-fedora: + extends: .native_test_job_template + needs: + - job: build-system-fedora + artifacts: true + variables: + IMAGE: fedora + script: + - cd build + - scripts/device-crash-test -q ./qemu-system-ppc + - scripts/device-crash-test -q ./qemu-system-riscv32 + build-system-centos: extends: .native_build_job_template needs: diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml index d273a9e713..19e6c21401 100644 --- a/.gitlab-ci.d/cirrus.yml +++ b/.gitlab-ci.d/cirrus.yml @@ -89,3 +89,38 @@ x64-macos-11-base-build: PATH_EXTRA: /usr/local/opt/ccache/libexec:/usr/local/opt/gettext/bin PKG_CONFIG_PATH: /usr/local/opt/curl/lib/pkgconfig:/usr/local/opt/ncurses/lib/pkgconfig:/usr/local/opt/readline/lib/pkgconfig TEST_TARGETS: check-unit check-block check-qapi-schema check-softfloat check-qtest-x86_64 + + +# The following jobs run VM-based tests via KVM on a Linux-based Cirrus-CI job +.cirrus_kvm_job: + stage: build + image: registry.gitlab.com/libvirt/libvirt-ci/cirrus-run:master + needs: [] + timeout: 80m + allow_failure: true + script: + - sed -e "s|[@]CI_REPOSITORY_URL@|$CI_REPOSITORY_URL|g" + -e "s|[@]CI_COMMIT_REF_NAME@|$CI_COMMIT_REF_NAME|g" + -e "s|[@]CI_COMMIT_SHA@|$CI_COMMIT_SHA|g" + -e "s|[@]NAME@|$NAME|g" + -e "s|[@]CONFIGURE_ARGS@|$CONFIGURE_ARGS|g" + -e "s|[@]TEST_TARGETS@|$TEST_TARGETS|g" + <.gitlab-ci.d/cirrus/kvm-build.yml >.gitlab-ci.d/cirrus/$NAME.yml + - cat .gitlab-ci.d/cirrus/$NAME.yml + - cirrus-run -v --show-build-log always .gitlab-ci.d/cirrus/$NAME.yml + rules: + - when: manual + +x86-netbsd: + extends: .cirrus_kvm_job + variables: + NAME: netbsd + CONFIGURE_ARGS: --target-list=x86_64-softmmu,ppc64-softmmu,aarch64-softmmu + TEST_TARGETS: check + +x86-openbsd: + extends: .cirrus_kvm_job + variables: + NAME: openbsd + CONFIGURE_ARGS: --target-list=i386-softmmu,riscv64-softmmu,mips64-softmmu + TEST_TARGETS: check diff --git a/.gitlab-ci.d/cirrus/kvm-build.yml b/.gitlab-ci.d/cirrus/kvm-build.yml new file mode 100644 index 0000000000..4334fabf39 --- /dev/null +++ b/.gitlab-ci.d/cirrus/kvm-build.yml @@ -0,0 +1,31 @@ +container: + image: fedora:35 + cpu: 4 + memory: 8Gb + kvm: true + +env: + CIRRUS_CLONE_DEPTH: 1 + CI_REPOSITORY_URL: "@CI_REPOSITORY_URL@" + CI_COMMIT_REF_NAME: "@CI_COMMIT_REF_NAME@" + CI_COMMIT_SHA: "@CI_COMMIT_SHA@" + +@NAME@_task: + @NAME@_vm_cache: + folder: $HOME/.cache/qemu-vm + install_script: + - dnf update -y + - dnf install -y git make openssh-clients qemu-img qemu-system-x86 wget + clone_script: + - git clone --depth 100 "$CI_REPOSITORY_URL" . + - git fetch origin "$CI_COMMIT_REF_NAME" + - git reset --hard "$CI_COMMIT_SHA" + build_script: + - if [ -f $HOME/.cache/qemu-vm/images/@NAME@.img ]; then + make vm-build-@NAME@ J=$(getconf _NPROCESSORS_ONLN) + EXTRA_CONFIGURE_OPTS="@CONFIGURE_ARGS@" + BUILD_TARGET="@TEST_TARGETS@" ; + else + make vm-build-@NAME@ J=$(getconf _NPROCESSORS_ONLN) BUILD_TARGET=help + EXTRA_CONFIGURE_OPTS="--disable-system --disable-user --disable-tools" ; + fi diff --git a/.gitlab-ci.d/qemu-project.yml b/.gitlab-ci.d/qemu-project.yml index b3d79bc429..871262fe0e 100644 --- a/.gitlab-ci.d/qemu-project.yml +++ b/.gitlab-ci.d/qemu-project.yml @@ -11,3 +11,4 @@ include: - local: '/.gitlab-ci.d/static_checks.yml' - local: '/.gitlab-ci.d/custom-runners.yml' - local: '/.gitlab-ci.d/cirrus.yml' + - local: '/.gitlab-ci.d/windows.yml' diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml new file mode 100644 index 0000000000..62dd9ed832 --- /dev/null +++ b/.gitlab-ci.d/windows.yml @@ -0,0 +1,98 @@ +.shared_msys2_builder: + tags: + - shared-windows + - windows + - windows-1809 + cache: + key: "${CI_JOB_NAME}-cache" + paths: + - ${CI_PROJECT_DIR}/msys64/var/cache + needs: [] + stage: build + timeout: 70m + before_script: + - If ( !(Test-Path -Path msys64\var\cache ) ) { + mkdir msys64\var\cache + } + - If ( !(Test-Path -Path msys64\var\cache\msys2.exe ) ) { + Invoke-WebRequest + "https://github.com/msys2/msys2-installer/releases/download/2021-07-25/msys2-base-x86_64-20210725.sfx.exe" + -outfile "msys64\var\cache\msys2.exe" + } + - msys64\var\cache\msys2.exe -y + - ((Get-Content -path .\msys64\etc\\post-install\\07-pacman-key.post -Raw) + -replace '--refresh-keys', '--version') | + Set-Content -Path ${CI_PROJECT_DIR}\msys64\etc\\post-install\\07-pacman-key.post + - .\msys64\usr\bin\bash -lc "sed -i 's/^CheckSpace/#CheckSpace/g' /etc/pacman.conf" + - .\msys64\usr\bin\bash -lc 'pacman --noconfirm -Syuu' # Core update + - .\msys64\usr\bin\bash -lc 'pacman --noconfirm -Syuu' # Normal update + - taskkill /F /FI "MODULES eq msys-2.0.dll" + +msys2-64bit: + extends: .shared_msys2_builder + script: + - .\msys64\usr\bin\bash -lc "pacman -Sy --noconfirm --needed + diffutils git grep make sed + mingw-w64-x86_64-capstone + mingw-w64-x86_64-curl + mingw-w64-x86_64-cyrus-sasl + mingw-w64-x86_64-gcc + mingw-w64-x86_64-glib2 + mingw-w64-x86_64-gnutls + mingw-w64-x86_64-libnfs + mingw-w64-x86_64-libpng + mingw-w64-x86_64-libssh + mingw-w64-x86_64-libtasn1 + mingw-w64-x86_64-libusb + mingw-w64-x86_64-libxml2 + mingw-w64-x86_64-nettle + mingw-w64-x86_64-ninja + mingw-w64-x86_64-pixman + mingw-w64-x86_64-pkgconf + mingw-w64-x86_64-python + mingw-w64-x86_64-SDL2 + mingw-w64-x86_64-SDL2_image + mingw-w64-x86_64-snappy + mingw-w64-x86_64-usbredir + mingw-w64-x86_64-zstd " + - $env:CHERE_INVOKING = 'yes' # Preserve the current working directory + - $env:MSYSTEM = 'MINGW64' # Start a 64 bit Mingw environment + - .\msys64\usr\bin\bash -lc './configure --target-list=x86_64-softmmu + --enable-capstone=system --without-default-devices' + - .\msys64\usr\bin\bash -lc "sed -i '/^ROMS=/d' build/config-host.mak" + - .\msys64\usr\bin\bash -lc 'make -j2' + - .\msys64\usr\bin\bash -lc 'make check' + +msys2-32bit: + extends: .shared_msys2_builder + script: + - .\msys64\usr\bin\bash -lc "pacman -Sy --noconfirm --needed + diffutils git grep make sed + mingw-w64-i686-capstone + mingw-w64-i686-curl + mingw-w64-i686-cyrus-sasl + mingw-w64-i686-gcc + mingw-w64-i686-glib2 + mingw-w64-i686-gnutls + mingw-w64-i686-gtk3 + mingw-w64-i686-libgcrypt + mingw-w64-i686-libjpeg-turbo + mingw-w64-i686-libssh + mingw-w64-i686-libtasn1 + mingw-w64-i686-libusb + mingw-w64-i686-libxml2 + mingw-w64-i686-lzo2 + mingw-w64-i686-ninja + mingw-w64-i686-pixman + mingw-w64-i686-pkgconf + mingw-w64-i686-python + mingw-w64-i686-snappy + mingw-w64-i686-usbredir " + - $env:CHERE_INVOKING = 'yes' # Preserve the current working directory + - $env:MSYSTEM = 'MINGW32' # Start a 32-bit MinG environment + - mkdir output + - cd output + - ..\msys64\usr\bin\bash -lc "../configure --target-list=ppc64-softmmu + --enable-capstone=system" + - ..\msys64\usr\bin\bash -lc 'make -j2' + - ..\msys64\usr\bin\bash -lc 'make check' diff --git a/.mailmap b/.mailmap index 8beb2f95ae..c45d1c5301 100644 --- a/.mailmap +++ b/.mailmap @@ -50,6 +50,7 @@ Aleksandar Rikalo Aleksandar Rikalo Alexander Graf Anthony Liguori Anthony Liguori +Christian Borntraeger Filip Bozuta Frederic Konrad Greg Kurz diff --git a/MAINTAINERS b/MAINTAINERS index 7543eb4d59..1de6ce6e44 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -393,7 +393,7 @@ F: target/ppc/kvm.c S390 KVM CPUs M: Halil Pasic -M: Christian Borntraeger +M: Christian Borntraeger S: Supported F: target/s390x/kvm/ F: target/s390x/ioinst.[ch] @@ -1527,7 +1527,7 @@ S390 Machines ------------- S390 Virtio-ccw M: Halil Pasic -M: Christian Borntraeger +M: Christian Borntraeger S: Supported F: hw/char/sclp*.[hc] F: hw/char/terminal3270.c @@ -1541,7 +1541,7 @@ T: git https://github.com/borntraeger/qemu.git s390-next L: qemu-s390x@nongnu.org S390-ccw boot -M: Christian Borntraeger +M: Christian Borntraeger M: Thomas Huth S: Supported F: hw/s390x/ipl.* @@ -1825,6 +1825,7 @@ F: hw/scsi/* F: tests/qtest/virtio-scsi-test.c F: tests/qtest/fuzz-virtio-scsi-test.c F: tests/qtest/am53c974-test.c +F: tests/qtest/fuzz-lsi53c895a-test.c T: git https://github.com/bonzini/qemu.git scsi-next SSI @@ -3076,8 +3077,9 @@ Usermode Emulation Overall usermode emulation M: Riku Voipio S: Maintained -F: thunk.c F: accel/tcg/user-exec*.c +F: include/user/ +F: common-user/ BSD user M: Warner Losh diff --git a/VERSION b/VERSION index cbd3fe98d1..8e8e37d75b 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -6.1.93 +6.2.50 diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index eecd8031cf..0e66ebb497 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -61,6 +61,10 @@ #endif #define PAGE_SIZE qemu_real_host_page_size +#ifndef KVM_GUESTDBG_BLOCKIRQ +#define KVM_GUESTDBG_BLOCKIRQ 0 +#endif + //#define DEBUG_KVM #ifdef DEBUG_KVM @@ -168,6 +172,8 @@ bool kvm_vm_attributes_allowed; bool kvm_direct_msi_allowed; bool kvm_ioeventfd_any_length_allowed; bool kvm_msi_use_devid; +bool kvm_has_guest_debug; +int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size = ~0; @@ -2564,6 +2570,25 @@ static int kvm_init(MachineState *ms) kvm_ioeventfd_any_length_allowed = (kvm_check_extension(s, KVM_CAP_IOEVENTFD_ANY_LENGTH) > 0); +#ifdef KVM_CAP_SET_GUEST_DEBUG + kvm_has_guest_debug = + (kvm_check_extension(s, KVM_CAP_SET_GUEST_DEBUG) > 0); +#endif + + kvm_sstep_flags = 0; + if (kvm_has_guest_debug) { + kvm_sstep_flags = SSTEP_ENABLE; + +#if defined KVM_CAP_SET_GUEST_DEBUG2 + int guest_debug_flags = + kvm_check_extension(s, KVM_CAP_SET_GUEST_DEBUG2); + + if (guest_debug_flags & KVM_GUESTDBG_BLOCKIRQ) { + kvm_sstep_flags |= SSTEP_NOIRQ; + } +#endif + } + kvm_state = s; ret = kvm_arch_init(ms, s); @@ -3193,6 +3218,10 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) if (cpu->singlestep_enabled) { data.dbg.control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP; + + if (cpu->singlestep_enabled & SSTEP_NOIRQ) { + data.dbg.control |= KVM_GUESTDBG_BLOCKIRQ; + } } kvm_arch_update_guest_debug(cpu, &data.dbg); diff --git a/block/nvme.c b/block/nvme.c index e4f336d79c..fa360b9b3c 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -206,8 +206,9 @@ static void nvme_free_req_queue_cb(void *opaque) NVMeQueuePair *q = opaque; qemu_mutex_lock(&q->lock); - while (qemu_co_enter_next(&q->free_req_queue, &q->lock)) { - /* Retry all pending requests */ + while (q->free_req_head != -1 && + qemu_co_enter_next(&q->free_req_queue, &q->lock)) { + /* Retry waiting requests */ } qemu_mutex_unlock(&q->lock); } diff --git a/blockdev.c b/blockdev.c index b35072644e..0eb2823b1b 100644 --- a/blockdev.c +++ b/blockdev.c @@ -303,16 +303,6 @@ int drive_get_max_bus(BlockInterfaceType type) return max_bus; } -/* Get a block device. This should only be used for single-drive devices - (e.g. SD/Floppy/MTD). Multi-disk devices (scsi/ide) should use the - appropriate bus. */ -DriveInfo *drive_get_next(BlockInterfaceType type) -{ - static int next_block_unit[IF_COUNT]; - - return drive_get(type, 0, next_block_unit[type]++); -} - static void bdrv_format_print(void *opaque, const char *name) { qemu_printf(" %s", name); diff --git a/bsd-user/errno_defs.h b/bsd-user/errno_defs.h index 832671354f..73cfa24b7f 100644 --- a/bsd-user/errno_defs.h +++ b/bsd-user/errno_defs.h @@ -151,6 +151,10 @@ /* Internal errors: */ #define TARGET_EJUSTRETURN 254 /* Just return without modifing regs */ #define TARGET_ERESTART 255 /* Restart syscall */ -#define TARGET_ERESTARTSYS TARGET_ERESTART /* Linux compat */ + +#include "special-errno.h" + +_Static_assert(TARGET_ERESTART == QEMU_ERESTARTSYS, + "TARGET_ERESTART and QEMU_ERESTARTSYS expected to match"); #endif /* ! _ERRNO_DEFS_H_ */ diff --git a/bsd-user/meson.build b/bsd-user/meson.build index 87885d91ed..9fcb80c3fa 100644 --- a/bsd-user/meson.build +++ b/bsd-user/meson.build @@ -2,6 +2,10 @@ if not have_bsd_user subdir_done() endif +bsd_user_ss = ss.source_set() + +common_user_inc += include_directories('.') + bsd_user_ss.add(files( 'bsdload.c', 'elfload.c', @@ -15,3 +19,5 @@ bsd_user_ss.add(files( # Pull in the OS-specific build glue, if any subdir(targetos) + +specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) diff --git a/bsd-user/special-errno.h b/bsd-user/special-errno.h new file mode 100644 index 0000000000..03599d9b5a --- /dev/null +++ b/bsd-user/special-errno.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * QEMU internal errno values for implementing user-only POSIX. + * + * Copyright (c) 2021 Linaro, Ltd. + */ + +#ifndef SPECIAL_ERRNO_H +#define SPECIAL_ERRNO_H + +/* + * All of these are QEMU internal, not visible to the guest. + * They should be chosen so as to not overlap with any host + * or guest errno. + */ + +/* + * This is returned when a system call should be restarted, to tell the + * main loop that it should wind the guest PC backwards so it will + * re-execute the syscall after handling any pending signals. + */ +#define QEMU_ERESTARTSYS 255 + +#endif /* SPECIAL_ERRNO_H */ diff --git a/common-user/host/aarch64/safe-syscall.inc.S b/common-user/host/aarch64/safe-syscall.inc.S new file mode 100644 index 0000000000..b8fd5b553e --- /dev/null +++ b/common-user/host/aarch64/safe-syscall.inc.S @@ -0,0 +1,88 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2016 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, #function + .type safe_syscall_start, #function + .type safe_syscall_end, #function + + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .cfi_startproc + /* The syscall calling convention isn't the same as the + * C one: + * we enter with x0 == &signal_pending + * x1 == syscall number + * x2 ... x7, (stack) == syscall arguments + * and return the result in x0 + * and the syscall instruction needs + * x8 == syscall number + * x0 ... x6 == syscall arguments + * and returns the result in x0 + * Shuffle everything around appropriately. + */ + mov x9, x0 /* signal_pending pointer */ + mov x8, x1 /* syscall number */ + mov x0, x2 /* syscall arguments */ + mov x1, x3 + mov x2, x4 + mov x3, x5 + mov x4, x6 + mov x5, x7 + ldr x6, [sp] + + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + ldr w10, [x9] + cbnz w10, 2f + svc 0x0 +safe_syscall_end: + + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ + cmp x0, #-4096 + b.hi 0f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + b.cs 1f +#else +#error "unsupported os" +#endif + ret + +#if defined(__linux__) + /* code path setting errno */ +0: neg w0, w0 + b safe_syscall_set_errno_tail +#endif + + /* code path when we didn't execute the syscall */ +2: mov w0, #QEMU_ERESTARTSYS +1: b safe_syscall_set_errno_tail + + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/host/arm/safe-syscall.inc.S b/common-user/host/arm/safe-syscall.inc.S new file mode 100644 index 0000000000..bbfb89634e --- /dev/null +++ b/common-user/host/arm/safe-syscall.inc.S @@ -0,0 +1,108 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2016 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, %function + + .cfi_sections .debug_frame + + .text + .syntax unified + .arm + .align 2 + + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .fnstart + .cfi_startproc + mov r12, sp /* save entry stack */ + push { r4, r5, r6, r7, r8, lr } + .save { r4, r5, r6, r7, r8, lr } + .cfi_adjust_cfa_offset 24 + .cfi_rel_offset r4, 0 + .cfi_rel_offset r5, 4 + .cfi_rel_offset r6, 8 + .cfi_rel_offset r7, 12 + .cfi_rel_offset r8, 16 + .cfi_rel_offset lr, 20 + + /* The syscall calling convention isn't the same as the C one: + * we enter with r0 == &signal_pending + * r1 == syscall number + * r2, r3, [sp+0] ... [sp+12] == syscall arguments + * and return the result in r0 + * and the syscall instruction needs + * r7 == syscall number + * r0 ... r6 == syscall arguments + * and returns the result in r0 + * Shuffle everything around appropriately. + * Note the 16 bytes that we pushed to save registers. + */ + mov r8, r0 /* copy signal_pending */ + mov r7, r1 /* syscall number */ + mov r0, r2 /* syscall args */ + mov r1, r3 + ldm r12, { r2, r3, r4, r5, r6 } + + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + ldr r12, [r8] /* signal_pending */ + tst r12, r12 + bne 2f + swi 0 +safe_syscall_end: + + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ + cmp r0, #-4096 + neghi r0, r0 + bhi 1f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + bcs 1f +#else +#error "unsupported os" +#endif + pop { r4, r5, r6, r7, r8, pc } + + /* code path when we didn't execute the syscall */ +2: mov r0, #QEMU_ERESTARTSYS + + /* code path setting errno */ +1: pop { r4, r5, r6, r7, r8, lr } + .cfi_adjust_cfa_offset -24 + .cfi_restore r4 + .cfi_restore r5 + .cfi_restore r6 + .cfi_restore r7 + .cfi_restore r8 + .cfi_restore lr + b safe_syscall_set_errno_tail + + .fnend + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/host/i386/safe-syscall.inc.S b/common-user/host/i386/safe-syscall.inc.S new file mode 100644 index 0000000000..baf5400a29 --- /dev/null +++ b/common-user/host/i386/safe-syscall.inc.S @@ -0,0 +1,126 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2016 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .cfi_startproc + push %ebp + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebp, 0 + push %esi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset esi, 0 + push %edi + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset edi, 0 + push %ebx + .cfi_adjust_cfa_offset 4 + .cfi_rel_offset ebx, 0 + + /* The syscall calling convention isn't the same as the C one: + * we enter with 0(%esp) == return address + * 4(%esp) == &signal_pending + * 8(%esp) == syscall number + * 12(%esp) ... 32(%esp) == syscall arguments + * and return the result in eax + * and the syscall instruction needs + * eax == syscall number + * ebx, ecx, edx, esi, edi, ebp == syscall arguments + * and returns the result in eax + * Shuffle everything around appropriately. + * Note the 16 bytes that we pushed to save registers. + */ + mov 12+16(%esp), %ebx /* the syscall arguments */ + mov 16+16(%esp), %ecx + mov 20+16(%esp), %edx + mov 24+16(%esp), %esi + mov 28+16(%esp), %edi + mov 32+16(%esp), %ebp + + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + mov 4+16(%esp), %eax /* signal_pending */ + cmpl $0, (%eax) + jnz 2f + mov 8+16(%esp), %eax /* syscall number */ + int $0x80 +safe_syscall_end: + + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ + cmp $-4095, %eax + jae 0f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + jc 1f +#else +#error "unsupported os" +#endif + pop %ebx + .cfi_remember_state + .cfi_adjust_cfa_offset -4 + .cfi_restore ebx + pop %edi + .cfi_adjust_cfa_offset -4 + .cfi_restore edi + pop %esi + .cfi_adjust_cfa_offset -4 + .cfi_restore esi + pop %ebp + .cfi_adjust_cfa_offset -4 + .cfi_restore ebp + ret + .cfi_restore_state + +#if defined(__linux__) +0: neg %eax + jmp 1f +#endif + + /* code path when we didn't execute the syscall */ +2: mov $QEMU_ERESTARTSYS, %eax + + /* code path setting errno */ +1: pop %ebx + .cfi_adjust_cfa_offset -4 + .cfi_restore ebx + pop %edi + .cfi_adjust_cfa_offset -4 + .cfi_restore edi + pop %esi + .cfi_adjust_cfa_offset -4 + .cfi_restore esi + pop %ebp + .cfi_adjust_cfa_offset -4 + .cfi_restore ebp + jmp safe_syscall_set_errno_tail + + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S new file mode 100644 index 0000000000..fc75a337d1 --- /dev/null +++ b/common-user/host/mips/safe-syscall.inc.S @@ -0,0 +1,148 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2021 Linaro, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "sys/regdef.h" +#include "sys/asm.h" + + .text + .set nomips16 + .set reorder + + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_start, @function + .type safe_syscall_end, @function + + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ + +#if _MIPS_SIM == _ABIO32 +/* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */ +#define FRAME 40 +#define OFS_S0 32 +#else +/* 1 * 8 for s0 save; 1 * 8 for align. */ +#define FRAME 16 +#define OFS_S0 0 +#endif + + +NESTED(safe_syscall_base, FRAME, ra) + .cfi_startproc + PTR_ADDIU sp, sp, -FRAME + .cfi_adjust_cfa_offset FRAME + REG_S s0, OFS_S0(sp) + .cfi_rel_offset s0, OFS_S0 +#if _MIPS_SIM == _ABIO32 + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == &signal_pending + * a1 == syscall number + * a2, a3, stack == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * v0 == syscall number + * a0 ... a3, stack == syscall arguments + * and returns the result in v0 + * Shuffle everything around appropriately. + */ + move s0, a0 /* signal_pending pointer */ + move v0, a1 /* syscall number */ + move a0, a2 /* syscall arguments */ + move a1, a3 + lw a2, FRAME+16(sp) + lw a3, FRAME+20(sp) + lw t4, FRAME+24(sp) + lw t5, FRAME+28(sp) + lw t6, FRAME+32(sp) + lw t7, FRAME+40(sp) + sw t4, 16(sp) + sw t5, 20(sp) + sw t6, 24(sp) + sw t7, 28(sp) +#else + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == &signal_pending + * a1 == syscall number + * a2 ... a7 == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * v0 == syscall number + * a0 ... a5 == syscall arguments + * and returns the result in v0 + * Shuffle everything around appropriately. + */ + move s0, a0 /* signal_pending pointer */ + move v0, a1 /* syscall number */ + move a0, a2 /* syscall arguments */ + move a1, a3 + move a2, a4 + move a3, a5 + move a4, a6 + move a5, a7 +#endif + + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* If signal_pending is non-zero, don't do the call */ + lw t1, 0(s0) + bnez t1, 2f + syscall +safe_syscall_end: + + /* code path for having successfully executed the syscall */ + REG_L s0, OFS_S0(sp) + PTR_ADDIU sp, sp, FRAME + .cfi_remember_state + .cfi_adjust_cfa_offset -FRAME + .cfi_restore s0 + bnez a3, 1f + jr ra + .cfi_restore_state + + /* code path when we didn't execute the syscall */ +2: REG_L s0, OFS_S0(sp) + PTR_ADDIU sp, sp, FRAME + .cfi_adjust_cfa_offset -FRAME + .cfi_restore s0 + li v0, QEMU_ERESTARTSYS + + /* code path setting errno */ + /* + * We didn't setup GP on entry, optimistic of the syscall success. + * We must do so now to load the address of the helper, as required + * by the ABI, into t9. + * + * Note that SETUP_GPX and SETUP_GPX64 are themselves conditional, + * so we can simply let the one that's not empty succeed. + */ +1: USE_ALT_CP(t0) + SETUP_GPX(t1) + SETUP_GPX64(t0, t1) + PTR_LA t9, safe_syscall_set_errno_tail + jr t9 + + .cfi_endproc +END(safe_syscall_base) diff --git a/common-user/host/ppc64/safe-syscall.inc.S b/common-user/host/ppc64/safe-syscall.inc.S new file mode 100644 index 0000000000..947a850dfd --- /dev/null +++ b/common-user/host/ppc64/safe-syscall.inc.S @@ -0,0 +1,94 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2016 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + + .text + + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +#if _CALL_ELF == 2 +safe_syscall_base: + .cfi_startproc + .localentry safe_syscall_base,0 +#else + .section ".opd","aw" + .align 3 +safe_syscall_base: + .quad .L.safe_syscall_base,.TOC.@tocbase,0 + .previous +.L.safe_syscall_base: + .cfi_startproc +#endif + /* We enter with r3 == &signal_pending + * r4 == syscall number + * r5 ... r10 == syscall arguments + * and return the result in r3 + * and the syscall instruction needs + * r0 == syscall number + * r3 ... r8 == syscall arguments + * and returns the result in r3 + * Shuffle everything around appropriately. + */ + std 14, 16(1) /* Preserve r14 in SP+16 */ + .cfi_offset 14, 16 + mr 14, 3 /* signal_pending */ + mr 0, 4 /* syscall number */ + mr 3, 5 /* syscall arguments */ + mr 4, 6 + mr 5, 7 + mr 6, 8 + mr 7, 9 + mr 8, 10 + + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + lwz 12, 0(14) + cmpwi 0, 12, 0 + bne- 2f + sc +safe_syscall_end: + /* code path when we did execute the syscall */ + ld 14, 16(1) /* restore r14 */ + bso- 1f + blr + + /* code path when we didn't execute the syscall */ +2: ld 14, 16(1) /* restore r14 */ + addi 3, 0, QEMU_ERESTARTSYS + + /* code path setting errno */ +1: b safe_syscall_set_errno_tail + nop /* per abi, for the linker to modify */ + + .cfi_endproc + +#if _CALL_ELF == 2 + .size safe_syscall_base, .-safe_syscall_base +#else + .size safe_syscall_base, .-.L.safe_syscall_base + .size .L.safe_syscall_base, .-.L.safe_syscall_base +#endif diff --git a/common-user/host/riscv/safe-syscall.inc.S b/common-user/host/riscv/safe-syscall.inc.S new file mode 100644 index 0000000000..dfe83c300e --- /dev/null +++ b/common-user/host/riscv/safe-syscall.inc.S @@ -0,0 +1,79 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2018 Linaro, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + .type safe_syscall_start, @function + .type safe_syscall_end, @function + + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .cfi_startproc + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == &signal_pending + * a1 == syscall number + * a2 ... a7 == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * a7 == syscall number + * a0 ... a5 == syscall arguments + * and returns the result in a0 + * Shuffle everything around appropriately. + */ + mv t0, a0 /* signal_pending pointer */ + mv t1, a1 /* syscall number */ + mv a0, a2 /* syscall arguments */ + mv a1, a3 + mv a2, a4 + mv a3, a5 + mv a4, a6 + mv a5, a7 + mv a7, t1 + + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* If signal_pending is non-zero, don't do the call */ + lw t1, 0(t0) + bnez t1, 2f + scall +safe_syscall_end: + /* code path for having successfully executed the syscall */ + li t2, -4096 + bgtu a0, t2, 0f + ret + + /* code path setting errno */ +0: neg a0, a0 + j safe_syscall_set_errno_tail + + /* code path when we didn't execute the syscall */ +2: li a0, QEMU_ERESTARTSYS + j safe_syscall_set_errno_tail + + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/host/s390x/safe-syscall.inc.S b/common-user/host/s390x/safe-syscall.inc.S new file mode 100644 index 0000000000..2ccbaa2402 --- /dev/null +++ b/common-user/host/s390x/safe-syscall.inc.S @@ -0,0 +1,98 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2016 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + + /* This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .cfi_startproc + stmg %r6,%r15,48(%r15) /* save all call-saved registers */ + .cfi_offset %r15,-40 + .cfi_offset %r14,-48 + .cfi_offset %r13,-56 + .cfi_offset %r12,-64 + .cfi_offset %r11,-72 + .cfi_offset %r10,-80 + .cfi_offset %r9,-88 + .cfi_offset %r8,-96 + .cfi_offset %r7,-104 + .cfi_offset %r6,-112 + lgr %r1,%r15 + lg %r0,8(%r15) /* load eos */ + aghi %r15,-160 + .cfi_adjust_cfa_offset 160 + stg %r1,0(%r15) /* store back chain */ + stg %r0,8(%r15) /* store eos */ + + /* + * The syscall calling convention isn't the same as the C one: + * we enter with r2 == &signal_pending + * r3 == syscall number + * r4, r5, r6, (stack) == syscall arguments + * and return the result in r2 + * and the syscall instruction needs + * r1 == syscall number + * r2 ... r7 == syscall arguments + * and returns the result in r2 + * Shuffle everything around appropriately. + */ + lgr %r8,%r2 /* signal_pending pointer */ + lgr %r1,%r3 /* syscall number */ + lgr %r2,%r4 /* syscall args */ + lgr %r3,%r5 + lgr %r4,%r6 + lmg %r5,%r7,320(%r15) + + /* This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + icm %r0,15,0(%r8) + jne 2f + svc 0 +safe_syscall_end: + + /* code path for having successfully executed the syscall */ + lg %r15,0(%r15) /* load back chain */ + .cfi_remember_state + .cfi_adjust_cfa_offset -160 + lmg %r6,%r15,48(%r15) /* load saved registers */ + + lghi %r0, -4095 /* check for syscall error */ + clgr %r2, %r0 + blr %r14 /* return on success */ + lcr %r2, %r2 /* create positive errno */ + jg safe_syscall_set_errno_tail + .cfi_restore_state + + /* code path when we didn't execute the syscall */ +2: lg %r15,0(%r15) /* load back chain */ + .cfi_adjust_cfa_offset -160 + lmg %r6,%r15,48(%r15) /* load saved registers */ + lghi %r2, QEMU_ERESTARTSYS + jg safe_syscall_set_errno_tail + + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/host/sparc64/safe-syscall.inc.S b/common-user/host/sparc64/safe-syscall.inc.S new file mode 100644 index 0000000000..a2f2b9c967 --- /dev/null +++ b/common-user/host/sparc64/safe-syscall.inc.S @@ -0,0 +1,89 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by common-user/safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2021 Linaro, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .text + .balign 4 + + .register %g2, #scratch + .register %g3, #scratch + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + .type safe_syscall_start, @function + .type safe_syscall_end, @function + +#define STACK_BIAS 2047 +#define PARAM(N) STACK_BIAS + N*8 + + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + */ +safe_syscall_base: + .cfi_startproc + /* + * The syscall calling convention isn't the same as the C one: + * we enter with o0 == &signal_pending + * o1 == syscall number + * o2 ... o5, (stack) == syscall arguments + * and return the result in x0 + * and the syscall instruction needs + * g1 == syscall number + * o0 ... o5 == syscall arguments + * and returns the result in o0 + * Shuffle everything around appropriately. + */ + mov %o0, %g2 /* signal_pending pointer */ + mov %o1, %g1 /* syscall number */ + mov %o2, %o0 /* syscall arguments */ + mov %o3, %o1 + mov %o4, %o2 + mov %o5, %o3 + ldx [%sp + PARAM(6)], %o4 + ldx [%sp + PARAM(7)], %o5 + + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* if signal_pending is non-zero, don't do the call */ + lduw [%g2], %g3 + brnz,pn %g3, 2f + nop + ta 0x6d +safe_syscall_end: + /* code path for having successfully executed the syscall */ + bcs,pn %xcc, 1f + nop + ret + nop + + /* code path when we didn't execute the syscall */ +2: set QEMU_ERESTARTSYS, %o0 + + /* code path setting errno */ +1: mov %o7, %g1 + call safe_syscall_set_errno_tail + mov %g1, %o7 + + .cfi_endproc + .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/x86_64/safe-syscall.inc.S b/common-user/host/x86_64/safe-syscall.inc.S similarity index 81% rename from linux-user/host/x86_64/safe-syscall.inc.S rename to common-user/host/x86_64/safe-syscall.inc.S index f36992daa3..a20927a783 100644 --- a/linux-user/host/x86_64/safe-syscall.inc.S +++ b/common-user/host/x86_64/safe-syscall.inc.S @@ -1,7 +1,7 @@ /* * safe-syscall.inc.S : host-specific assembly fragment * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S + * This is intended to be included by common-user/safe-syscall.S * * Copyright (C) 2015 Timothy Edward Baldwin * @@ -19,9 +19,6 @@ * first argument an 'int *' to the signal_pending flag, the * second one the system call number (as a 'long'), and all further * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. */ safe_syscall_base: .cfi_startproc @@ -35,9 +32,9 @@ safe_syscall_base: .cfi_adjust_cfa_offset 8 .cfi_rel_offset rbp, 0 - /* The syscall calling convention isn't the same as the - * C one: - * we enter with rdi == *signal_pending + /* + * The syscall calling convention isn't the same as the C one: + * we enter with rdi == &signal_pending * rsi == syscall number * rdx, rcx, r8, r9, (stack), (stack) == syscall arguments * and return the result in rax @@ -67,25 +64,42 @@ safe_syscall_base: */ safe_syscall_start: /* if signal_pending is non-zero, don't do the call */ - cmpl $0, (%rbp) - jnz 1f + cmpl $0, (%rbp) + jnz 2f syscall safe_syscall_end: + /* code path for having successfully executed the syscall */ +#if defined(__linux__) + /* Linux kernel returns (small) negative errno. */ + cmp $-4095, %rax + jae 0f +#elif defined(__FreeBSD__) + /* FreeBSD kernel returns positive errno and C bit set. */ + jc 1f +#else +#error "unsupported os" +#endif pop %rbp .cfi_remember_state .cfi_def_cfa_offset 8 .cfi_restore rbp ret - -1: - /* code path when we didn't execute the syscall */ .cfi_restore_state - mov $-TARGET_ERESTARTSYS, %rax - pop %rbp + +#if defined(__linux__) +0: neg %eax + jmp 1f +#endif + + /* code path when we didn't execute the syscall */ +2: mov $QEMU_ERESTARTSYS, %eax + + /* code path setting errno */ +1: pop %rbp .cfi_def_cfa_offset 8 .cfi_restore rbp - ret + jmp safe_syscall_set_errno_tail .cfi_endproc .size safe_syscall_base, .-safe_syscall_base diff --git a/common-user/meson.build b/common-user/meson.build new file mode 100644 index 0000000000..5cb42bc664 --- /dev/null +++ b/common-user/meson.build @@ -0,0 +1,6 @@ +common_user_inc += include_directories('host/' / host_arch) + +common_user_ss.add(files( + 'safe-syscall.S', + 'safe-syscall-error.c', +)) diff --git a/common-user/safe-syscall-error.c b/common-user/safe-syscall-error.c new file mode 100644 index 0000000000..cf74b504f8 --- /dev/null +++ b/common-user/safe-syscall-error.c @@ -0,0 +1,25 @@ +/* + * safe-syscall-error.c: errno setting fragment + * This is intended to be invoked by safe-syscall.S + * + * Written by Richard Henderson + * Copyright (C) 2021 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "user/safe-syscall.h" + +/* + * This is intended to be invoked via tail-call on the error path + * from the assembly in host/arch/safe-syscall.inc.S. This takes + * care of the host specific addressing of errno. + * Return -1 to finalize the return value for safe_syscall_base. + */ +long safe_syscall_set_errno_tail(int value) +{ + errno = value; + return -1; +} diff --git a/linux-user/safe-syscall.S b/common-user/safe-syscall.S similarity index 91% rename from linux-user/safe-syscall.S rename to common-user/safe-syscall.S index 42ea7c40ba..74f7e35694 100644 --- a/linux-user/safe-syscall.S +++ b/common-user/safe-syscall.S @@ -10,15 +10,12 @@ * See the COPYING file in the top-level directory. */ -#include "hostdep.h" -#include "target_errno_defs.h" +#include "special-errno.h" /* We have the correct host directory on our include path * so that this will pull in the right fragment for the architecture. */ -#ifdef HAVE_SAFE_SYSCALL #include "safe-syscall.inc.S" -#endif /* We must specifically say that we're happy for the stack to not be * executable, otherwise the toolchain will default to assuming our diff --git a/configure b/configure index 7f5a34b350..43b903b35c 100755 --- a/configure +++ b/configure @@ -344,7 +344,6 @@ debug_stack_usage="no" crypto_afalg="no" tls_priority="NORMAL" tpm="$default_feature" -libssh="$default_feature" live_block_migration=${default_feature:-yes} numa="$default_feature" replication=${default_feature:-yes} @@ -502,42 +501,93 @@ EOF } if check_define __linux__ ; then - targetos="Linux" + targetos=linux elif check_define _WIN32 ; then - targetos='MINGW32' + targetos=windows elif check_define __OpenBSD__ ; then - targetos='OpenBSD' + targetos=openbsd elif check_define __sun__ ; then - targetos='SunOS' + targetos=sunos elif check_define __HAIKU__ ; then - targetos='Haiku' + targetos=haiku elif check_define __FreeBSD__ ; then - targetos='FreeBSD' + targetos=freebsd elif check_define __FreeBSD_kernel__ && check_define __GLIBC__; then - targetos='GNU/kFreeBSD' + targetos=gnu/kfreebsd elif check_define __DragonFly__ ; then - targetos='DragonFly' + targetos=dragonfly elif check_define __NetBSD__; then - targetos='NetBSD' + targetos=netbsd elif check_define __APPLE__; then - targetos='Darwin' + targetos=darwin else # This is a fatal error, but don't report it yet, because we # might be going to just print the --help text, or it might # be the result of a missing compiler. - targetos='bogus' + targetos=bogus fi -# Some host OSes need non-standard checks for which CPU to use. -# Note that these checks are broken for cross-compilation: if you're -# cross-compiling to one of these OSes then you'll need to specify -# the correct CPU with the --cpu option. +# OS specific + case $targetos in -SunOS) +windows) + mingw32="yes" + plugins="no" + pie="no" +;; +gnu/kfreebsd) + bsd="yes" +;; +freebsd) + bsd="yes" + bsd_user="yes" + make="${MAKE-gmake}" + # needed for kinfo_getvmmap(3) in libutil.h +;; +dragonfly) + bsd="yes" + make="${MAKE-gmake}" +;; +netbsd) + bsd="yes" + make="${MAKE-gmake}" +;; +openbsd) + bsd="yes" + make="${MAKE-gmake}" +;; +darwin) + bsd="yes" + darwin="yes" + # Disable attempts to use ObjectiveC features in os/object.h since they + # won't work when we're compiling with gcc as a C compiler. + QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" +;; +sunos) + solaris="yes" + make="${MAKE-gmake}" + smbd="${SMBD-/usr/sfw/sbin/smbd}" +# needed for CMSG_ macros in sys/socket.h + QEMU_CFLAGS="-D_XOPEN_SOURCE=600 $QEMU_CFLAGS" +# needed for TIOCWIN* defines in termios.h + QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" # $(uname -m) returns i86pc even on an x86_64 box, so default based on isainfo + # Note that this check is broken for cross-compilation: if you're + # cross-compiling to one of these OSes then you'll need to specify + # the correct CPU with the --cpu option. if test -z "$cpu" && test "$(isainfo -k)" = "amd64"; then cpu="x86_64" fi +;; +haiku) + pie="no" + QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -D_BSD_SOURCE -fPIC $QEMU_CFLAGS" +;; +linux) + linux="yes" + linux_user="yes" + vhost_user=${default_feature:-yes} +;; esac if test ! -z "$cpu" ; then @@ -585,98 +635,46 @@ else cpu=$(uname -m) fi -ARCH= -# Normalise host CPU name and set ARCH. +# Normalise host CPU name, set multilib cflags # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390x|sparc64|x32|riscv) - ;; - ppc64le) - ARCH="ppc64" - ;; + armv*b|armv*l|arm) + cpu="arm" ;; + i386|i486|i586|i686|i86pc|BePC) cpu="i386" - ;; + CPU_CFLAGS="-m32" ;; + x32) + cpu="x86_64" + CPU_CFLAGS="-mx32" ;; x86_64|amd64) cpu="x86_64" - ;; - armv*b|armv*l|arm) - cpu="arm" - ;; - aarch64) - cpu="aarch64" - ;; + # ??? Only extremely old AMD cpus do not have cmpxchg16b. + # If we truly care, we should simply detect this case at + # runtime and generate the fallback to serial emulation. + CPU_CFLAGS="-m64 -mcx16" ;; + mips*) - cpu="mips" - ;; + cpu="mips" ;; + + ppc) + CPU_CFLAGS="-m32" ;; + ppc64) + CPU_CFLAGS="-m64 -mbig" ;; + ppc64le) + cpu="ppc64" + CPU_CFLAGS="-m64 -mlittle" ;; + + s390) + CPU_CFLAGS="-m31" ;; + s390x) + CPU_CFLAGS="-m64" ;; + sparc|sun4[cdmuv]) cpu="sparc" - ;; - *) - # This will result in either an error or falling back to TCI later - ARCH=unknown - ;; -esac -if test -z "$ARCH"; then - ARCH="$cpu" -fi - -# OS specific - -case $targetos in -MINGW32*) - mingw32="yes" - supported_os="yes" - plugins="no" - pie="no" -;; -GNU/kFreeBSD) - bsd="yes" -;; -FreeBSD) - bsd="yes" - bsd_user="yes" - make="${MAKE-gmake}" - # needed for kinfo_getvmmap(3) in libutil.h -;; -DragonFly) - bsd="yes" - make="${MAKE-gmake}" -;; -NetBSD) - bsd="yes" - make="${MAKE-gmake}" -;; -OpenBSD) - bsd="yes" - make="${MAKE-gmake}" -;; -Darwin) - bsd="yes" - darwin="yes" - # Disable attempts to use ObjectiveC features in os/object.h since they - # won't work when we're compiling with gcc as a C compiler. - QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS" -;; -SunOS) - solaris="yes" - make="${MAKE-gmake}" - smbd="${SMBD-/usr/sfw/sbin/smbd}" -# needed for CMSG_ macros in sys/socket.h - QEMU_CFLAGS="-D_XOPEN_SOURCE=600 $QEMU_CFLAGS" -# needed for TIOCWIN* defines in termios.h - QEMU_CFLAGS="-D__EXTENSIONS__ $QEMU_CFLAGS" -;; -Haiku) - haiku="yes" - pie="no" - QEMU_CFLAGS="-DB_USE_POSITIVE_POSIX_ERRORS -D_BSD_SOURCE -fPIC $QEMU_CFLAGS" -;; -Linux) - linux="yes" - linux_user="yes" - vhost_user=${default_feature:-yes} -;; + CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" ;; + sparc64) + CPU_CFLAGS="-m64 -mcpu=ultrasparc" ;; esac : ${make=${MAKE-make}} @@ -1080,10 +1078,6 @@ for opt do ;; --enable-tpm) tpm="yes" ;; - --disable-libssh) libssh="no" - ;; - --enable-libssh) libssh="yes" - ;; --disable-live-block-migration) live_block_migration="no" ;; --enable-live-block-migration) live_block_migration="yes" @@ -1276,24 +1270,6 @@ local_statedir="${local_statedir:-$prefix/var}" firmwarepath="${firmwarepath:-$datadir/qemu-firmware}" localedir="${localedir:-$datadir/locale}" -case "$cpu" in - ppc) CPU_CFLAGS="-m32" ;; - ppc64) CPU_CFLAGS="-m64" ;; - sparc) CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" ;; - sparc64) CPU_CFLAGS="-m64 -mcpu=ultrasparc" ;; - s390) CPU_CFLAGS="-m31" ;; - s390x) CPU_CFLAGS="-m64" ;; - i386) CPU_CFLAGS="-m32" ;; - x32) CPU_CFLAGS="-mx32" ;; - - # ??? Only extremely old AMD cpus do not have cmpxchg16b. - # If we truly care, we should simply detect this case at - # runtime and generate the fallback to serial emulation. - x86_64) CPU_CFLAGS="-m64 -mcx16" ;; - - # No special flags required for other host CPUs -esac - if eval test -z "\${cross_cc_$cpu}"; then eval "cross_cc_${cpu}=\$cc" cross_cc_vars="$cross_cc_vars cross_cc_${cpu}" @@ -1460,7 +1436,6 @@ cat << EOF live-block-migration Block migration in the main migration stream coroutine-pool coroutine freelist (better performance) tpm TPM support - libssh ssh block device support numa libnuma support avx2 AVX2 optimization support avx512f AVX512F optimization support @@ -2573,21 +2548,6 @@ if test "$modules" = yes; then fi fi -########################################## -# libssh probe -if test "$libssh" != "no" ; then - if $pkg_config --exists "libssh >= 0.8.7"; then - libssh_cflags=$($pkg_config libssh --cflags) - libssh_libs=$($pkg_config libssh --libs) - libssh=yes - else - if test "$libssh" = "yes" ; then - error_exit "libssh required for --enable-libssh" - fi - libssh=no - fi -fi - ########################################## # TPM emulation is only on POSIX @@ -3369,8 +3329,8 @@ QEMU_GA_MSI_MINGW_DLL_PATH="$($pkg_config --variable=prefix glib-2.0)/bin" # Mac OS X ships with a broken assembler roms= if { test "$cpu" = "i386" || test "$cpu" = "x86_64"; } && \ - test "$targetos" != "Darwin" && test "$targetos" != "SunOS" && \ - test "$targetos" != "Haiku" && test "$softmmu" = yes ; then + test "$targetos" != "darwin" && test "$targetos" != "sunos" && \ + test "$targetos" != "haiku" && test "$softmmu" = yes ; then # Different host OS linkers have different ideas about the name of the ELF # emulation. Linux and OpenBSD/amd64 use 'elf_i386'; FreeBSD uses the _fbsd # variant; OpenBSD/i386 uses the _obsd variant; and Windows uses i386pe. @@ -3447,8 +3407,6 @@ echo "GIT=$git" >> $config_host_mak echo "GIT_SUBMODULES=$git_submodules" >> $config_host_mak echo "GIT_SUBMODULES_ACTION=$git_submodules_action" >> $config_host_mak -echo "ARCH=$ARCH" >> $config_host_mak - if test "$debug_tcg" = "yes" ; then echo "CONFIG_DEBUG_TCG=y" >> $config_host_mak fi @@ -3484,9 +3442,6 @@ fi if test "$solaris" = "yes" ; then echo "CONFIG_SOLARIS=y" >> $config_host_mak fi -if test "$haiku" = "yes" ; then - echo "CONFIG_HAIKU=y" >> $config_host_mak -fi if test "$static" = "yes" ; then echo "CONFIG_STATIC=y" >> $config_host_mak fi @@ -3648,12 +3603,6 @@ if test "$cmpxchg128" = "yes" ; then echo "CONFIG_CMPXCHG128=y" >> $config_host_mak fi -if test "$libssh" = "yes" ; then - echo "CONFIG_LIBSSH=y" >> $config_host_mak - echo "LIBSSH_CFLAGS=$libssh_cflags" >> $config_host_mak - echo "LIBSSH_LIBS=$libssh_libs" >> $config_host_mak -fi - if test "$live_block_migration" = "yes" ; then echo "CONFIG_LIVE_BLOCK_MIGRATION=y" >> $config_host_mak fi @@ -3777,10 +3726,10 @@ fi if test "$linux" = "yes" ; then mkdir -p linux-headers case "$cpu" in - i386|x86_64|x32) + i386|x86_64) linux_arch=x86 ;; - ppc|ppc64|ppc64le) + ppc|ppc64) linux_arch=powerpc ;; s390x) @@ -3805,7 +3754,7 @@ fi for target in $target_list; do target_dir="$target" - target_name=$(echo $target | cut -d '-' -f 1) + target_name=$(echo $target | cut -d '-' -f 1)$EXESUF mkdir -p $target_dir case $target in *-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" ;; @@ -3832,7 +3781,6 @@ if test "$safe_stack" = "yes"; then fi # If we're using a separate build tree, set it up now. -# DIRS are directories which we simply mkdir in the build tree; # LINKS are things to symlink back into the source tree # (these can be both files and directories). # Caution: do not add files or directories here using wildcards. This @@ -3844,12 +3792,6 @@ fi # UNLINK is used to remove symlinks from older development versions # that might get into the way when doing "git update" without doing # a "make distclean" in between. -DIRS="tests tests/tcg tests/qapi-schema tests/qtest/libqos" -DIRS="$DIRS tests/qtest tests/qemu-iotests tests/vm tests/fp tests/qgraph" -DIRS="$DIRS docs docs/interop fsdev scsi" -DIRS="$DIRS pc-bios/optionrom pc-bios/s390-ccw" -DIRS="$DIRS roms/seabios" -DIRS="$DIRS contrib/plugins/" LINKS="Makefile" LINKS="$LINKS tests/tcg/Makefile.target" LINKS="$LINKS pc-bios/optionrom/Makefile" @@ -3871,16 +3813,15 @@ for bios_file in \ $source_path/pc-bios/*.img \ $source_path/pc-bios/openbios-* \ $source_path/pc-bios/u-boot.* \ - $source_path/pc-bios/edk2-*.fd.bz2 \ $source_path/pc-bios/palcode-* \ $source_path/pc-bios/qemu_vga.ndrv do LINKS="$LINKS pc-bios/$(basename $bios_file)" done -mkdir -p $DIRS for f in $LINKS ; do if [ -e "$source_path/$f" ]; then + mkdir -p `dirname ./$f` symlink "$source_path/$f" "$f" fi done @@ -3954,27 +3895,13 @@ if test "$skip_meson" = no; then if test "$cross_compile" = "yes"; then cross_arg="--cross-file config-meson.cross" echo "[host_machine]" >> $cross - if test "$mingw32" = "yes" ; then - echo "system = 'windows'" >> $cross - fi - if test "$linux" = "yes" ; then - echo "system = 'linux'" >> $cross - fi - if test "$darwin" = "yes" ; then - echo "system = 'darwin'" >> $cross - fi - case "$ARCH" in + echo "system = '$targetos'" >> $cross + case "$cpu" in i386) echo "cpu_family = 'x86'" >> $cross ;; - x86_64|x32) - echo "cpu_family = 'x86_64'" >> $cross - ;; - ppc64le) - echo "cpu_family = 'ppc64'" >> $cross - ;; *) - echo "cpu_family = '$ARCH'" >> $cross + echo "cpu_family = '$cpu'" >> $cross ;; esac echo "cpu = '$cpu'" >> $cross diff --git a/cpu.c b/cpu.c index 79ff2dd946..80ccadecd6 100644 --- a/cpu.c +++ b/cpu.c @@ -318,12 +318,10 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) if (!accel_cpu_realizefn(cpu, errp)) { return; } -#ifdef CONFIG_TCG /* NB: errp parameter is unused currently */ if (tcg_enabled()) { tcg_exec_realizefn(cpu, errp); } -#endif /* CONFIG_TCG */ #ifdef CONFIG_USER_ONLY assert(qdev_get_vmsd(DEVICE(cpu)) == NULL || @@ -350,12 +348,9 @@ void cpu_exec_unrealizefn(CPUState *cpu) vmstate_unregister(NULL, &vmstate_cpu_common, cpu); } #endif -#ifdef CONFIG_TCG - /* NB: errp parameter is unused currently */ if (tcg_enabled()) { tcg_exec_unrealizefn(cpu); } -#endif /* CONFIG_TCG */ cpu_list_remove(cpu); } diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index ff7488cb63..5693abb663 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -315,6 +315,15 @@ This machine is deprecated because we have enough AST2500 based OpenPOWER machines. It can be easily replaced by the ``witherspoon-bmc`` or the ``romulus-bmc`` machines. +PPC 405 ``taihu`` machine (since 7.0) +''''''''''''''''''''''''''''''''''''' + +The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar, +except for some external periphery. However, the periphery of the ``taihu`` +machine is hardly emulated at all (e.g. neither the LCD nor the USB part had +been implemented), so there is not much value added by this board. Use the +``ref405ep`` machine instead. + Backend options --------------- diff --git a/docs/block-replication.txt b/docs/block-replication.txt index b0f23761c6..e1b28a6cc1 100644 --- a/docs/block-replication.txt +++ b/docs/block-replication.txt @@ -179,7 +179,7 @@ Primary: Secondary: -drive if=none,driver=raw,file.filename=1.raw,id=colo1 \ - -drive if=none,id=childs1,driver=replication,mode=secondary,top-id=childs1 + -drive if=none,id=childs1,driver=replication,mode=secondary,top-id=top-disk1 file.file.filename=active_disk.qcow2,\ file.driver=qcow2,\ file.backing.file.filename=hidden_disk.qcow2,\ diff --git a/docs/meson.build b/docs/meson.build index 27c6e156ff..57b28a3146 100644 --- a/docs/meson.build +++ b/docs/meson.build @@ -18,12 +18,12 @@ if sphinx_build.found() # This is a bit awkward but works: create a trivial document and # try to run it with our configuration file (which enforces a # version requirement). This will fail if sphinx-build is too old. - run_command('mkdir', ['-p', tmpdir / 'sphinx']) - run_command('touch', [tmpdir / 'sphinx/index.rst']) + run_command('mkdir', ['-p', tmpdir / 'sphinx'], check: true) + run_command('touch', [tmpdir / 'sphinx/index.rst'], check: true) sphinx_build_test_out = run_command(SPHINX_ARGS + [ '-c', meson.current_source_dir(), '-b', 'html', tmpdir / 'sphinx', - tmpdir / 'sphinx/out']) + tmpdir / 'sphinx/out'], check: false) build_docs = (sphinx_build_test_out.returncode() == 0) if not build_docs diff --git a/docs/specs/ppc-spapr-hcalls.rst b/docs/specs/ppc-spapr-hcalls.rst new file mode 100644 index 0000000000..28daf9734a --- /dev/null +++ b/docs/specs/ppc-spapr-hcalls.rst @@ -0,0 +1,100 @@ +sPAPR hypervisor calls +---------------------- + +When used with the ``pseries`` machine type, ``qemu-system-ppc64`` implements +a set of hypervisor calls (a.k.a. hcalls) defined in the `Linux on Power +Architecture Reference document (LoPAR) +`_. +This document is a subset of the Power Architecture Platform Reference (PAPR+) +specification (IBM internal only), which is what PowerVM, the IBM proprietary +hypervisor, adheres to. + +The subset in LoPAR is selected based on the requirements of Linux as a guest. + +In addition to those calls, we have added our own private hypervisor +calls which are mostly used as a private interface between the firmware +running in the guest and QEMU. + +All those hypercalls start at hcall number 0xf000 which correspond +to an implementation specific range in PAPR. + +H_RTAS (0xf000) +^^^^^^^^^^^^^^^ + +RTAS stands for Run-Time Abstraction Sercies and is a set of runtime services +generally provided by the firmware inside the guest to the operating system. It +predates the existence of hypervisors (it was originally an extension to Open +Firmware) and is still used by PAPR and LoPAR to provide various services that +are not performance sensitive. + +We currently implement the RTAS services in QEMU itself. The actual RTAS +"firmware" blob in the guest is a small stub of a few instructions which +calls our private H_RTAS hypervisor call to pass the RTAS calls to QEMU. + +Arguments: + + ``r3``: ``H_RTAS (0xf000)`` + + ``r4``: Guest physical address of RTAS parameter block. + +Returns: + + ``H_SUCCESS``: Successfully called the RTAS function (RTAS result will have + been stored in the parameter block). + + ``H_PARAMETER``: Unknown token. + +H_LOGICAL_MEMOP (0xf001) +^^^^^^^^^^^^^^^^^^^^^^^^ + +When the guest runs in "real mode" (in powerpc terminology this means with MMU +disabled, i.e. guest effective address equals to guest physical address), it +only has access to a subset of memory and no I/Os. + +PAPR and LoPAR provides a set of hypervisor calls to perform cacheable or +non-cacheable accesses to any guest physical addresses that the +guest can use in order to access IO devices while in real mode. + +This is typically used by the firmware running in the guest. + +However, doing a hypercall for each access is extremely inefficient +(even more so when running KVM) when accessing the frame buffer. In +that case, things like scrolling become unusably slow. + +This hypercall allows the guest to request a "memory op" to be applied +to memory. The supported memory ops at this point are to copy a range +of memory (supports overlap of source and destination) and XOR which +is used by our SLOF firmware to invert the screen. + +Arguments: + + ``r3 ``: ``H_LOGICAL_MEMOP (0xf001)`` + + ``r4``: Guest physical address of destination. + + ``r5``: Guest physical address of source. + + ``r6``: Individual element size, defined by the binary logarithm of the + desired size. Supported values are: + + ``0`` = 1 byte + + ``1`` = 2 bytes + + ``2`` = 4 bytes + + ``3`` = 8 bytes + + ``r7``: Number of elements. + + ``r8``: Operation. Supported values are: + + ``0``: copy + + ``1``: xor + +Returns: + + ``H_SUCCESS``: Success. + + ``H_PARAMETER``: Invalid argument. diff --git a/docs/specs/ppc-spapr-hcalls.txt b/docs/specs/ppc-spapr-hcalls.txt deleted file mode 100644 index 93fe3da91b..0000000000 --- a/docs/specs/ppc-spapr-hcalls.txt +++ /dev/null @@ -1,78 +0,0 @@ -When used with the "pseries" machine type, QEMU-system-ppc64 implements -a set of hypervisor calls using a subset of the server "PAPR" specification -(IBM internal at this point), which is also what IBM's proprietary hypervisor -adheres too. - -The subset is selected based on the requirements of Linux as a guest. - -In addition to those calls, we have added our own private hypervisor -calls which are mostly used as a private interface between the firmware -running in the guest and QEMU. - -All those hypercalls start at hcall number 0xf000 which correspond -to an implementation specific range in PAPR. - -- H_RTAS (0xf000) - -RTAS is a set of runtime services generally provided by the firmware -inside the guest to the operating system. It predates the existence -of hypervisors (it was originally an extension to Open Firmware) and -is still used by PAPR to provide various services that aren't performance -sensitive. - -We currently implement the RTAS services in QEMU itself. The actual RTAS -"firmware" blob in the guest is a small stub of a few instructions which -calls our private H_RTAS hypervisor call to pass the RTAS calls to QEMU. - -Arguments: - - r3 : H_RTAS (0xf000) - r4 : Guest physical address of RTAS parameter block - -Returns: - - H_SUCCESS : Successfully called the RTAS function (RTAS result - will have been stored in the parameter block) - H_PARAMETER : Unknown token - -- H_LOGICAL_MEMOP (0xf001) - -When the guest runs in "real mode" (in powerpc lingua this means -with MMU disabled, ie guest effective == guest physical), it only -has access to a subset of memory and no IOs. - -PAPR provides a set of hypervisor calls to perform cacheable or -non-cacheable accesses to any guest physical addresses that the -guest can use in order to access IO devices while in real mode. - -This is typically used by the firmware running in the guest. - -However, doing a hypercall for each access is extremely inefficient -(even more so when running KVM) when accessing the frame buffer. In -that case, things like scrolling become unusably slow. - -This hypercall allows the guest to request a "memory op" to be applied -to memory. The supported memory ops at this point are to copy a range -of memory (supports overlap of source and destination) and XOR which -is used by our SLOF firmware to invert the screen. - -Arguments: - - r3: H_LOGICAL_MEMOP (0xf001) - r4: Guest physical address of destination - r5: Guest physical address of source - r6: Individual element size - 0 = 1 byte - 1 = 2 bytes - 2 = 4 bytes - 3 = 8 bytes - r7: Number of elements - r8: Operation - 0 = copy - 1 = xor - -Returns: - - H_SUCCESS : Success - H_PARAMETER : Invalid argument - diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index cec87e3743..d8b102fa0a 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -14,6 +14,7 @@ AST2400 SoC based machines : - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC - ``quanta-q71l-bmc`` OpenBMC Quanta BMC +- ``supermicrox11-bmc`` Supermicro X11 BMC AST2500 SoC based machines : @@ -21,12 +22,16 @@ AST2500 SoC based machines : - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC - ``sonorapass-bmc`` OCP SonoraPass BMC -- ``swift-bmc`` OpenPOWER Swift BMC POWER9 +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0) +- ``fp5280g2-bmc`` Inspur FP5280G2 BMC +- ``g220a-bmc`` Bytedance G220A BMC AST2600 SoC based machines : - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC +- ``rainier-bmc`` IBM Rainier POWER10 BMC +- ``fuji-bmc`` Facebook Fuji BMC Supported devices ----------------- @@ -51,13 +56,13 @@ Supported devices * Front LEDs (PCA9552 on I2C bus) * LPC Peripheral Controller (a subset of subdevices are supported) * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA + * ADC Missing devices --------------- * Coprocessor support - * ADC (out of tree implementation) * PWM and Fan Controller * Slave GPIO Controller * Super I/O Controller @@ -73,16 +78,25 @@ Missing devices Boot options ------------ -The Aspeed machines can be started using the ``-kernel`` option to -load a Linux kernel or from a firmware. Images can be downloaded from -the OpenBMC jenkins : +The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options +to load a Linux kernel or from a firmware. Images can be downloaded from the +OpenBMC jenkins : - https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ or directly from the OpenBMC GitHub release repository : https://github.com/openbmc/openbmc/releases +To boot a kernel directly from a Linux build tree: + +.. code-block:: bash + + $ qemu-system-arm -M ast2600-evb -nographic \ + -kernel arch/arm/boot/zImage \ + -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ + -initrd rootfs.cpio + The image should be attached as an MTD drive. Run : .. code-block:: bash diff --git a/docs/system/i386/sgx.rst b/docs/system/i386/sgx.rst index f8fade5ac2..0f0a73f758 100644 --- a/docs/system/i386/sgx.rst +++ b/docs/system/i386/sgx.rst @@ -141,8 +141,7 @@ To launch a SGX guest: |qemu_system_x86| \\ -cpu host,+sgx-provisionkey \\ -object memory-backend-epc,id=mem1,size=64M,prealloc=on \\ - -object memory-backend-epc,id=mem2,size=28M \\ - -M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2 + -M sgx-epc.0.memdev=mem1,sgx-epc.0.node=0 Utilizing SGX in the guest requires a kernel/OS with SGX support. The support can be determined in guest by:: @@ -152,8 +151,32 @@ The support can be determined in guest by:: and SGX epc info by:: $ dmesg | grep sgx - [ 1.242142] sgx: EPC section 0x180000000-0x181bfffff - [ 1.242319] sgx: EPC section 0x181c00000-0x1837fffff + [ 0.182807] sgx: EPC section 0x140000000-0x143ffffff + [ 0.183695] sgx: [Firmware Bug]: Unable to map EPC section to online node. Fallback to the NUMA node 0. + +To launch a SGX numa guest: + +.. parsed-literal:: + + |qemu_system_x86| \\ + -cpu host,+sgx-provisionkey \\ + -object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \\ + -object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \\ + -numa node,nodeid=0,cpus=0-1,memdev=node0 \\ + -object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \\ + -object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \\ + -numa node,nodeid=1,cpus=2-3,memdev=node1 \\ + -M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 + +and SGX epc numa info by:: + + $ dmesg | grep sgx + [ 0.369937] sgx: EPC section 0x180000000-0x183ffffff + [ 0.370259] sgx: EPC section 0x184000000-0x185bfffff + + $ dmesg | grep SRAT + [ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff] + [ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff] References ---------- diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst index 86186b7d2c..c8f9762342 100644 --- a/docs/system/ppc/powernv.rst +++ b/docs/system/ppc/powernv.rst @@ -1,7 +1,7 @@ -PowerNV family boards (``powernv8``, ``powernv9``) +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``) ================================================================== -PowerNV (as Non-Virtualized) is the "baremetal" platform using the +PowerNV (as Non-Virtualized) is the "bare metal" platform using the OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can be used as an hypervisor OS, running KVM guests, or simply as a host OS. @@ -16,16 +16,14 @@ Supported devices ----------------- * Multi processor support for POWER8, POWER8NVL and POWER9. - * XSCOM, serial communication sideband bus to configure chiplets - * Simple LPC Controller - * Processor Service Interface (PSI) Controller - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) - * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge - * Simple OCC is an on-chip microcontroller used for power management - tasks - * iBT device to handle BMC communication, with the internal BMC - simulator provided by QEMU or an external BMC such as an Aspeed - QEMU machine. + * XSCOM, serial communication sideband bus to configure chiplets. + * Simple LPC Controller. + * Processor Service Interface (PSI) Controller. + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10). + * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge. + * Simple OCC is an on-chip micro-controller used for power management tasks. + * iBT device to handle BMC communication, with the internal BMC simulator + provided by QEMU or an external BMC such as an Aspeed QEMU machine. * PNOR containing the different firmware partitions. Missing devices @@ -33,31 +31,42 @@ Missing devices A lot is missing, among which : - * POWER10 processor - * XIVE2 (POWER10) interrupt controller - * I2C controllers (yet to be merged) - * NPU/NPU2/NPU3 controllers - * EEH support for PCIe Host bridge controllers - * NX controller - * VAS controller - * chipTOD (Time Of Day) + * I2C controllers (yet to be merged). + * NPU/NPU2/NPU3 controllers. + * EEH support for PCIe Host bridge controllers. + * NX controller. + * VAS controller. + * chipTOD (Time Of Day). * Self Boot Engine (SBE). - * FSI bus + * FSI bus. Firmware -------- The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems includes the runtime services ``skiboot`` and the bootloader kernel and -initramfs ``skiroot``. Source code can be found on GitHub: +initramfs ``skiroot``. Source code can be found on the `OpenPOWER account at +GitHub `_. - https://github.com/open-power. - -Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the `OpenPOWER `__ site. +Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the +`OpenPOWER `__ site. QEMU includes a prebuilt image of ``skiboot`` which is updated when a more recent version is required by the models. +Current acceleration status +--------------------------- + +KVM acceleration in Linux Power hosts is provided by the kvm-hv and +kvm-pr modules. kvm-hv is adherent to PAPR and it's not compliant with +powernv. kvm-pr in theory could be used as a valid accel option but +this isn't supported by kvm-pr at this moment. + +To spare users from dealing with not so informative errors when attempting +to use accel=kvm, the powernv machine will throw an error informing that +KVM is not supported. This can be revisited in the future if kvm-pr (or +any other KVM alternative) is usable as KVM accel for this machine. + Boot options ------------ @@ -83,6 +92,7 @@ and a SATA disk : Complex PCIe configuration ~~~~~~~~~~~~~~~~~~~~~~~~~~ + Six PHBs are defined per chip (POWER9) but no default PCI layout is provided (to be compatible with libvirt). One PCI device can be added on any of the available PCIe slots using command line options such as: @@ -157,7 +167,7 @@ one on the command line : The files `palmetto-SDR.bin `__ and `palmetto-FRU.bin `__ define a Sensor Data Record repository and a Field Replaceable Unit -inventory for a palmetto BMC. They can be used to extend the QEMU BMC +inventory for a Palmetto BMC. They can be used to extend the QEMU BMC simulator. .. code-block:: bash @@ -189,4 +199,8 @@ CAVEATS ------- * No support for multiple HW threads (SMT=1). Same as pseries. - * CPU can hang when doing intensive I/Os. Use ``-append powersave=off`` in that case. + +Maintainer contact information +------------------------------ + +Cédric Le Goater diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst index 932d4dd17d..72e315eff6 100644 --- a/docs/system/ppc/pseries.rst +++ b/docs/system/ppc/pseries.rst @@ -1,12 +1,238 @@ pSeries family boards (``pseries``) =================================== +The Power machine para-virtualized environment described by the `Linux on Power +Architecture Reference document (LoPAR) +`_ +is called pSeries. This environment is also known as sPAPR, System p guests, or +simply Power Linux guests (although it is capable of running other operating +systems, such as AIX). + +Even though pSeries is designed to behave as a guest environment, it is also +capable of acting as a hypervisor OS, providing, on that role, nested +virtualization capabilities. + Supported devices ----------------- + * Multi processor support for many Power processors generations: POWER7, + POWER7+, POWER8, POWER8NVL, POWER9, and Power10. Support for POWER5+ exists, + but its state is unknown. + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9 and Power10) + * vPHB PCIe Host bridge. + * vscsi and vnet devices, compatible with the same devices available on a + PowerVM hypervisor with VIOS managing LPARs. + * Virtio based devices. + * PCIe device pass through. + Missing devices --------------- + * SPICE support. Firmware -------- + +`SLOF `_ (Slimline Open Firmware) is an +implementation of the `IEEE 1275-1994, Standard for Boot (Initialization +Configuration) Firmware: Core Requirements and Practices +`_. + +QEMU includes a prebuilt image of SLOF which is updated when a more recent +version is required. + +Build directions +---------------- + +.. code-block:: bash + + ./configure --target-list=ppc64-softmmu && make + +Running instructions +-------------------- + +Someone can select the pSeries machine type by running QEMU with the following +options: + +.. code-block:: bash + + qemu-system-ppc64 -M pseries + +sPAPR devices +------------- + +The sPAPR specification defines a set of para-virtualized devices, which are +also supported by the pSeries machine in QEMU and can be instantiated with the +``-device`` option: + +* ``spapr-vlan`` : a virtual network interface. +* ``spapr-vscsi`` : a virtual SCSI disk interface. +* ``spapr-rng`` : a pseudo-device for passing random number generator data to the + guest (see the `H_RANDOM hypercall feature + `_ for details). +* ``spapr-vty``: a virtual teletype. +* ``spapr-pci-host-bridge``: a PCI host bridge. +* ``tpm-spapr``: a Trusted Platform Module (TPM). +* ``spapr-tpm-proxy``: a TPM proxy. + +These are compatible with the devices historically available for use when +running the IBM PowerVM hypervisor with LPARs. + +However, since these devices have originally been specified with another +hypervisor and non-Linux guests in mind, you should use the virtio counterparts +(virtio-net, virtio-blk/scsi and virtio-rng for instance) if possible instead, +since they will most probably give you better performance with Linux guests in a +QEMU environment. + +The pSeries machine in QEMU is always instantiated with the following devices: + +* A NVRAM device (``spapr-nvram``). +* A virtual teletype (``spapr-vty``). +* A PCI host bridge (``spapr-pci-host-bridge``). + +Hence, it is not needed to add them manually, unless you use the ``-nodefaults`` +command line option in QEMU. + +In the case of the default ``spapr-nvram`` device, if someone wants to make the +contents of the NVRAM device persistent, they will need to specify a PFLASH +device when starting QEMU, i.e. either use +``-drive if=pflash,file=,format=raw`` to set the default PFLASH +device, or specify one with an ID +(``-drive if=none,file=,format=raw,id=pfid``) and pass that ID to the +NVRAM device with ``-global spapr-nvram.drive=pfid``. + +sPAPR specification +^^^^^^^^^^^^^^^^^^^ + +The main source of documentation on the sPAPR standard is the `Linux on Power +Architecture Reference document (LoPAR) +`_. +However, documentation specific to QEMU's implementation of the specification +can also be found in QEMU documentation: + +.. toctree:: + :maxdepth: 1 + + ../../specs/ppc-spapr-hcalls.rst + ../../specs/ppc-spapr-numa.rst + ../../specs/ppc-spapr-xive.rst + +Other documentation available in QEMU docs directory: + +* Hot plug (``/docs/specs/ppc-spapr-hotplug.txt``). +* Hypervisor calls needed by the Ultravisor + (``/docs/specs/ppc-spapr-uv-hcalls.txt``). + +Switching between the KVM-PR and KVM-HV kernel module +----------------------------------------------------- + +Currently, there are two implementations of KVM on Power, ``kvm_hv.ko`` and +``kvm_pr.ko``. + + +If a host supports both KVM modes, and both KVM kernel modules are loaded, it is +possible to switch between the two modes with the ``kvm-type`` parameter: + +* Use ``qemu-system-ppc64 -M pseries,accel=kvm,kvm-type=PR`` to use the + ``kvm_pr.ko`` kernel module. +* Use ``qemu-system-ppc64 -M pseries,accel=kvm,kvm-type=HV`` to use ``kvm_hv.ko`` + instead. + +KVM-PR +^^^^^^ + +KVM-PR uses the so-called **PR**\ oblem state of the PPC CPUs to run the guests, +i.e. the virtual machine is run in user mode and all privileged instructions +trap and have to be emulated by the host. That means you can run KVM-PR inside +a pSeries guest (or a PowerVM LPAR for that matter), and that is where it has +originated, as historically (prior to POWER7) it was not possible to run Linux +on hypervisor mode on a Power processor (this function was restricted to +PowerVM, the IBM proprietary hypervisor). + +Because all privileged instructions are trapped, guests that use a lot of +privileged instructions run quite slow with KVM-PR. On the other hand, because +of that, this kernel module can run on pretty much every PPC hardware, and is +able to emulate a lot of guests CPUs. This module can even be used to run other +PowerPC guests like an emulated PowerMac. + +As KVM-PR can be run inside a pSeries guest, it can also provide nested +virtualization capabilities (i.e. running a guest from within a guest). + +It is important to notice that, as KVM-HV provides a much better execution +performance, maintenance work has been much more focused on it in the past +years. Maintenance for KVM-PR has been minimal. + +In order to run KVM-PR guests with POWER9 processors, someone will need to start +QEMU with ``kernel_irqchip=off`` command line option. + +KVM-HV +^^^^^^ + +KVM-HV uses the hypervisor mode of more recent Power processors, that allow +access to the bare metal hardware directly. Although POWER7 had this capability, +it was only starting with POWER8 that this was officially supported by IBM. + +Originally, KVM-HV was only available when running on a PowerNV platform (a.k.a. +Power bare metal). Although it runs on a PowerNV platform, it can only be used +to start pSeries guests. As the pSeries guest doesn't have access to the +hypervisor mode of the Power CPU, it wasn't possible to run KVM-HV on a guest. +This limitation has been lifted, and now it is possible to run KVM-HV inside +pSeries guests as well, making nested virtualization possible with KVM-HV. + +As KVM-HV has access to privileged instructions, guests that use a lot of these +can run much faster than with KVM-PR. On the other hand, the guest CPU has to be +of the same type as the host CPU this way, e.g. it is not possible to specify an +embedded PPC CPU for the guest with KVM-HV. However, there is at least the +possibility to run the guest in a backward-compatibility mode of the previous +CPUs generations, e.g. you can run a POWER7 guest on a POWER8 host by using +``-cpu POWER8,compat=power7`` as parameter to QEMU. + +Modules support +--------------- + +As noticed in the sections above, each module can run in a different +environment. The following table shows with which environment each module can +run. As long as you are in a supported environment, you can run KVM-PR or KVM-HV +nested. Combinations not shown in the table are not available. + ++--------------+------------+------+-------------------+----------+--------+ +| Platform | Host type | Bits | Page table format | KVM-HV | KVM-PR | ++==============+============+======+===================+==========+========+ +| PowerNV | bare metal | 32 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | N/A | N/A | +| | +------+-------------------+----------+--------+ +| | | 64 | hash | yes | yes | +| | | +-------------------+----------+--------+ +| | | | radix | yes | no | ++--------------+------------+------+-------------------+----------+--------+ +| pSeries [1]_ | PowerNV | 32 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | N/A | N/A | +| | +------+-------------------+----------+--------+ +| | | 64 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | yes [2]_ | no | +| +------------+------+-------------------+----------+--------+ +| | PowerVM | 32 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix | N/A | N/A | +| | +------+-------------------+----------+--------+ +| | | 64 | hash | no | yes | +| | | +-------------------+----------+--------+ +| | | | radix [3]_ | no | yes | ++--------------+------------+------+-------------------+----------+--------+ + +.. [1] On POWER9 DD2.1 processors, the page table format on the host and guest + must be the same. + +.. [2] KVM-HV cannot run nested on POWER8 machines. + +.. [3] Introduced on Power10 machines. + +Maintainer contact information +------------------------------ + +Cédric Le Goater + +Daniel Henrique Barboza diff --git a/dump/dump.c b/dump/dump.c index 662d0a62cd..a84d8b1598 100644 --- a/dump/dump.c +++ b/dump/dump.c @@ -1293,14 +1293,6 @@ static size_t get_len_buf_out(size_t page_size, uint32_t flag_compress) return 0; } -/* - * check if the page is all 0 - */ -static inline bool is_zero_page(const uint8_t *buf, size_t page_size) -{ - return buffer_is_zero(buf, page_size); -} - static void write_dump_pages(DumpState *s, Error **errp) { int ret = 0; @@ -1357,7 +1349,7 @@ static void write_dump_pages(DumpState *s, Error **errp) */ while (get_next_page(&block_iter, &pfn_iter, &buf, s)) { /* check zero page */ - if (is_zero_page(buf, s->dump_info.page_size)) { + if (buffer_is_zero(buf, s->dump_info.page_size)) { ret = write_cache(&page_desc, &pd_zero, sizeof(PageDescriptor), false); if (ret < 0) { diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 41d4b17e41..db3e1f393d 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -19,7 +19,7 @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s) { switch (a->cls) { case float_class_snan: - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_snan, s); if (s->default_nan_mode) { parts_default_nan(a, s); } else { @@ -40,7 +40,7 @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b, float_status *s) { if (is_snan(a->cls) || is_snan(b->cls)) { - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_snan, s); } if (s->default_nan_mode) { @@ -68,7 +68,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int which; if (unlikely(abc_mask & float_cmask_snan)) { - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_snan, s); } which = pickNaNMulAdd(a->cls, b->cls, c->cls, @@ -354,7 +354,7 @@ static FloatPartsN *partsN(addsub)(FloatPartsN *a, FloatPartsN *b, return a; } /* Inf - Inf */ - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_isi, s); parts_default_nan(a, s); return a; } @@ -423,7 +423,7 @@ static FloatPartsN *partsN(mul)(FloatPartsN *a, FloatPartsN *b, /* Inf * Zero == NaN */ if (unlikely(ab_mask == float_cmask_infzero)) { - float_raise(float_flag_invalid, s); + float_raise(float_flag_invalid | float_flag_invalid_imz, s); parts_default_nan(a, s); return a; } @@ -489,11 +489,13 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, if (unlikely(ab_mask != float_cmask_normal)) { if (unlikely(ab_mask == float_cmask_infzero)) { + float_raise(float_flag_invalid | float_flag_invalid_imz, s); goto d_nan; } if (ab_mask & float_cmask_inf) { if (c->cls == float_class_inf && a->sign != c->sign) { + float_raise(float_flag_invalid | float_flag_invalid_isi, s); goto d_nan; } goto return_inf; @@ -566,7 +568,6 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b, goto finish_sign; d_nan: - float_raise(float_flag_invalid, s); parts_default_nan(a, s); return a; } @@ -589,11 +590,13 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, } /* 0/0 or Inf/Inf => NaN */ - if (unlikely(ab_mask == float_cmask_zero) || - unlikely(ab_mask == float_cmask_inf)) { - float_raise(float_flag_invalid, s); - parts_default_nan(a, s); - return a; + if (unlikely(ab_mask == float_cmask_zero)) { + float_raise(float_flag_invalid | float_flag_invalid_zdz, s); + goto d_nan; + } + if (unlikely(ab_mask == float_cmask_inf)) { + float_raise(float_flag_invalid | float_flag_invalid_idi, s); + goto d_nan; } /* All the NaN cases */ @@ -624,6 +627,10 @@ static FloatPartsN *partsN(div)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_divbyzero, s); a->cls = float_class_inf; return a; + + d_nan: + parts_default_nan(a, s); + return a; } /* @@ -862,7 +869,7 @@ static void partsN(sqrt)(FloatPartsN *a, float_status *status, return; d_nan: - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_sqrt, status); parts_default_nan(a, status); } @@ -1042,13 +1049,15 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, switch (p->cls) { case float_class_snan: + flags |= float_flag_invalid_snan; + /* fall through */ case float_class_qnan: - flags = float_flag_invalid; + flags |= float_flag_invalid; r = max; break; case float_class_inf: - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = p->sign ? min : max; break; @@ -1070,11 +1079,11 @@ static int64_t partsN(float_to_sint)(FloatPartsN *p, FloatRoundMode rmode, if (r <= -(uint64_t)min) { r = -r; } else { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = min; } } else if (r > max) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = max; } break; @@ -1107,13 +1116,15 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, switch (p->cls) { case float_class_snan: + flags |= float_flag_invalid_snan; + /* fall through */ case float_class_qnan: - flags = float_flag_invalid; + flags |= float_flag_invalid; r = max; break; case float_class_inf: - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = p->sign ? 0 : max; break; @@ -1131,15 +1142,15 @@ static uint64_t partsN(float_to_uint)(FloatPartsN *p, FloatRoundMode rmode, } if (p->sign) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = 0; } else if (p->exp > DECOMPOSED_BINARY_POINT) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = max; } else { r = p->frac_hi >> (DECOMPOSED_BINARY_POINT - p->exp); if (r > max) { - flags = float_flag_invalid; + flags = float_flag_invalid | float_flag_invalid_cvti; r = max; } } @@ -1334,7 +1345,9 @@ static FloatRelation partsN(compare)(FloatPartsN *a, FloatPartsN *b, } if (unlikely(ab_mask & float_cmask_anynan)) { - if (!is_quiet || (ab_mask & float_cmask_snan)) { + if (ab_mask & float_cmask_snan) { + float_raise(float_flag_invalid | float_flag_invalid_snan, s); + } else if (!is_quiet) { float_raise(float_flag_invalid, s); } return float_relation_unordered; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f2ad0f335e..943e3301d2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -506,7 +506,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -533,7 +533,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -556,7 +556,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the input value 'c' */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 2; } /* Prefer sNaN over qNaN, in the c, a, b order. */ @@ -580,7 +580,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 2; } @@ -597,7 +597,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, #elif defined(TARGET_RISCV) /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); } return 3; /* default NaN */ #elif defined(TARGET_XTENSA) @@ -606,7 +606,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * an input NaN if we have one (ie c). */ if (infzero) { - float_raise(float_flag_invalid, status); + float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 2; } if (status->use_first_nan) { diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 9a28720d82..7f524d4377 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1693,6 +1693,50 @@ static float64 float64_round_pack_canonical(FloatParts64 *p, return float64_pack_raw(p); } +static float64 float64r32_round_pack_canonical(FloatParts64 *p, + float_status *s) +{ + parts_uncanon(p, s, &float32_params); + + /* + * In parts_uncanon, we placed the fraction for float32 at the lsb. + * We need to adjust the fraction higher so that the least N bits are + * zero, and the fraction is adjacent to the float64 implicit bit. + */ + switch (p->cls) { + case float_class_normal: + if (unlikely(p->exp == 0)) { + /* + * The result is denormal for float32, but can be represented + * in normalized form for float64. Adjust, per canonicalize. + */ + int shift = frac_normalize(p); + p->exp = (float32_params.frac_shift - + float32_params.exp_bias - shift + 1 + + float64_params.exp_bias); + frac_shr(p, float64_params.frac_shift); + } else { + frac_shl(p, float32_params.frac_shift - float64_params.frac_shift); + p->exp += float64_params.exp_bias - float32_params.exp_bias; + } + break; + case float_class_snan: + case float_class_qnan: + frac_shl(p, float32_params.frac_shift - float64_params.frac_shift); + p->exp = float64_params.exp_max; + break; + case float_class_inf: + p->exp = float64_params.exp_max; + break; + case float_class_zero: + break; + default: + g_assert_not_reached(); + } + + return float64_pack_raw(p); +} + static void float128_unpack_canonical(FloatParts128 *p, float128 f, float_status *s) { @@ -1938,6 +1982,28 @@ float64_sub(float64 a, float64 b, float_status *s) return float64_addsub(a, b, s, hard_f64_sub, soft_f64_sub); } +static float64 float64r32_addsub(float64 a, float64 b, float_status *status, + bool subtract) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_addsub(&pa, &pb, status, subtract); + + return float64r32_round_pack_canonical(pr, status); +} + +float64 float64r32_add(float64 a, float64 b, float_status *status) +{ + return float64r32_addsub(a, b, status, false); +} + +float64 float64r32_sub(float64 a, float64 b, float_status *status) +{ + return float64r32_addsub(a, b, status, true); +} + static bfloat16 QEMU_FLATTEN bfloat16_addsub(bfloat16 a, bfloat16 b, float_status *status, bool subtract) { @@ -2069,6 +2135,17 @@ float64_mul(float64 a, float64 b, float_status *s) f64_is_zon2, f64_addsubmul_post); } +float64 float64r32_mul(float64 a, float64 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_mul(&pa, &pb, status); + + return float64r32_round_pack_canonical(pr, status); +} + bfloat16 QEMU_FLATTEN bfloat16_mul(bfloat16 a, bfloat16 b, float_status *status) { @@ -2296,6 +2373,19 @@ float64_muladd(float64 xa, float64 xb, float64 xc, int flags, float_status *s) return soft_f64_muladd(ua.s, ub.s, uc.s, flags, s); } +float64 float64r32_muladd(float64 a, float64 b, float64 c, + int flags, float_status *status) +{ + FloatParts64 pa, pb, pc, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + float64_unpack_canonical(&pc, c, status); + pr = parts_muladd(&pa, &pb, &pc, flags, status); + + return float64r32_round_pack_canonical(pr, status); +} + bfloat16 QEMU_FLATTEN bfloat16_muladd(bfloat16 a, bfloat16 b, bfloat16 c, int flags, float_status *status) { @@ -2419,6 +2509,17 @@ float64_div(float64 a, float64 b, float_status *s) f64_div_pre, f64_div_post); } +float64 float64r32_div(float64 a, float64 b, float_status *status) +{ + FloatParts64 pa, pb, *pr; + + float64_unpack_canonical(&pa, a, status); + float64_unpack_canonical(&pb, b, status); + pr = parts_div(&pa, &pb, status); + + return float64r32_round_pack_canonical(pr, status); +} + bfloat16 QEMU_FLATTEN bfloat16_div(bfloat16 a, bfloat16 b, float_status *status) { @@ -2543,8 +2644,10 @@ floatx80 floatx80_mod(floatx80 a, floatx80 b, float_status *status) static void parts_float_to_ahp(FloatParts64 *a, float_status *s) { switch (a->cls) { - case float_class_qnan: case float_class_snan: + float_raise(float_flag_invalid_snan, s); + /* fall through */ + case float_class_qnan: /* * There is no NaN in the destination format. Raise Invalid * and return a zero with the sign of the input NaN. @@ -4283,6 +4386,15 @@ float64 QEMU_FLATTEN float64_sqrt(float64 xa, float_status *s) return soft_f64_sqrt(ua.s, s); } +float64 float64r32_sqrt(float64 a, float_status *status) +{ + FloatParts64 p; + + float64_unpack_canonical(&p, a, status); + parts_sqrt(&p, status, &float64_params); + return float64r32_round_pack_canonical(&p, status); +} + bfloat16 QEMU_FLATTEN bfloat16_sqrt(bfloat16 a, float_status *status) { FloatParts64 p; diff --git a/gdbstub.c b/gdbstub.c index 141d7bc4ec..3c14c6a038 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -368,27 +368,10 @@ typedef struct GDBState { gdb_syscall_complete_cb current_syscall_cb; GString *str_buf; GByteArray *mem_buf; + int sstep_flags; + int supported_sstep_flags; } GDBState; -/* By default use no IRQs and no timers while single stepping so as to - * make single stepping like an ICE HW step. - */ -static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; - -/* Retrieves flags for single step mode. */ -static int get_sstep_flags(void) -{ - /* - * In replay mode all events written into the log should be replayed. - * That is why NOIRQ flag is removed in this mode. - */ - if (replay_mode != REPLAY_MODE_NONE) { - return SSTEP_ENABLE; - } else { - return sstep_flags; - } -} - static GDBState gdbserver_state; static void init_gdbserver_state(void) @@ -399,6 +382,29 @@ static void init_gdbserver_state(void) gdbserver_state.str_buf = g_string_new(NULL); gdbserver_state.mem_buf = g_byte_array_sized_new(MAX_PACKET_LENGTH); gdbserver_state.last_packet = g_byte_array_sized_new(MAX_PACKET_LENGTH + 4); + + /* + * In replay mode all events will come from the log and can't be + * suppressed otherwise we would break determinism. However as those + * events are tied to the number of executed instructions we won't see + * them occurring every time we single step. + */ + if (replay_mode != REPLAY_MODE_NONE) { + gdbserver_state.supported_sstep_flags = SSTEP_ENABLE; + } else if (kvm_enabled()) { + gdbserver_state.supported_sstep_flags = kvm_get_supported_sstep_flags(); + } else { + gdbserver_state.supported_sstep_flags = + SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + } + + /* + * By default use no IRQs and no timers while single stepping so as to + * make single stepping like an ICE HW step. + */ + gdbserver_state.sstep_flags = SSTEP_ENABLE | SSTEP_NOIRQ | SSTEP_NOTIMER; + gdbserver_state.sstep_flags &= gdbserver_state.supported_sstep_flags; + } #ifndef CONFIG_USER_ONLY @@ -505,7 +511,7 @@ static int gdb_continue_partial(char *newstates) CPU_FOREACH(cpu) { if (newstates[cpu->cpu_index] == 's') { trace_gdbstub_op_stepping(cpu->cpu_index); - cpu_single_step(cpu, sstep_flags); + cpu_single_step(cpu, gdbserver_state.sstep_flags); } } gdbserver_state.running_state = 1; @@ -524,7 +530,7 @@ static int gdb_continue_partial(char *newstates) break; /* nothing to do here */ case 's': trace_gdbstub_op_stepping(cpu->cpu_index); - cpu_single_step(cpu, get_sstep_flags()); + cpu_single_step(cpu, gdbserver_state.sstep_flags); cpu_resume(cpu); flag = 1; break; @@ -1883,7 +1889,7 @@ static void handle_step(GArray *params, void *user_ctx) gdb_set_cpu_pc((target_ulong)get_param(params, 0)->val_ull); } - cpu_single_step(gdbserver_state.c_cpu, get_sstep_flags()); + cpu_single_step(gdbserver_state.c_cpu, gdbserver_state.sstep_flags); gdb_continue(); } @@ -2017,24 +2023,44 @@ static void handle_v_commands(GArray *params, void *user_ctx) static void handle_query_qemu_sstepbits(GArray *params, void *user_ctx) { - g_string_printf(gdbserver_state.str_buf, "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", - SSTEP_ENABLE, SSTEP_NOIRQ, SSTEP_NOTIMER); + g_string_printf(gdbserver_state.str_buf, "ENABLE=%x", SSTEP_ENABLE); + + if (gdbserver_state.supported_sstep_flags & SSTEP_NOIRQ) { + g_string_append_printf(gdbserver_state.str_buf, ",NOIRQ=%x", + SSTEP_NOIRQ); + } + + if (gdbserver_state.supported_sstep_flags & SSTEP_NOTIMER) { + g_string_append_printf(gdbserver_state.str_buf, ",NOTIMER=%x", + SSTEP_NOTIMER); + } + put_strbuf(); } static void handle_set_qemu_sstep(GArray *params, void *user_ctx) { + int new_sstep_flags; + if (!params->len) { return; } - sstep_flags = get_param(params, 0)->val_ul; + new_sstep_flags = get_param(params, 0)->val_ul; + + if (new_sstep_flags & ~gdbserver_state.supported_sstep_flags) { + put_packet("E22"); + return; + } + + gdbserver_state.sstep_flags = new_sstep_flags; put_packet("OK"); } static void handle_query_qemu_sstep(GArray *params, void *user_ctx) { - g_string_printf(gdbserver_state.str_buf, "0x%x", sstep_flags); + g_string_printf(gdbserver_state.str_buf, "0x%x", + gdbserver_state.sstep_flags); put_strbuf(); } @@ -3497,6 +3523,11 @@ int gdbserver_start(const char *device) return -1; } + if (kvm_enabled() && !kvm_supports_guest_debug()) { + error_report("gdbstub: KVM doesn't support guest debugging"); + return -1; + } + if (!device) return -1; if (strcmp(device, "none") != 0) { diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2d37d29f02..e652590943 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -27,6 +27,7 @@ config ARM_VIRT select DIMM select ACPI_HW_REDUCED select ACPI_APEI + select ACPI_VIOT config CHEETAH bool diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a77f46b3ad..cf20ae0db5 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -284,12 +284,13 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, } static void aspeed_board_init_flashes(AspeedSMCState *s, - const char *flashtype) + const char *flashtype, + int unit0) { int i ; for (i = 0; i < s->num_cs; ++i) { - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); qemu_irq cs_line; DeviceState *dev; @@ -382,10 +383,12 @@ static void aspeed_machine_init(MachineState *machine) "max_ram", max_ram_size - machine->ram_size); memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram); - aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? - bmc->fmc_model : amc->fmc_model); - aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? - bmc->spi_model : amc->spi_model); + aspeed_board_init_flashes(&bmc->soc.fmc, + bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, + 0); + aspeed_board_init_flashes(&bmc->soc.spi[0], + bmc->spi_model ? bmc->spi_model : amc->spi_model, + bmc->soc.fmc.num_cs); /* Install first FMC flash content as a boot rom. */ if (drive0) { @@ -435,11 +438,13 @@ static void aspeed_machine_init(MachineState *machine) } for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { - sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); + sdhci_attach_drive(&bmc->soc.sdhci.slots[i], + drive_get(IF_SD, 0, i)); } if (bmc->soc.emmc.num_slots) { - sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); + sdhci_attach_drive(&bmc->soc.emmc.slots[0], + drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots)); } arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 74ad397b1f..399f8e837c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/error-report.h" #include "qapi/error.h" diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 294ba5de6e..5e3372a3c7 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -81,7 +81,7 @@ static void cubieboard_init(MachineState *machine) } /* Retrieve SD bus */ - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, 0); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(a10), "sd-bus"); diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index b771a3d8b7..4093af09cb 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c3cb315dbc..4210894d81 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "hw/sysbus.h" diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index bd16acd4d9..6dff000163 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -123,7 +123,7 @@ static void imx25_pdk_init(MachineState *machine) DriveInfo *di; BlockBackend *blk; - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, i); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus"); carddev = qdev_new(TYPE_SD_CARD); diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 16e8985953..b109ece3ae 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -649,7 +649,7 @@ static void integratorcp_init(MachineState *machine) qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); qdev_connect_gpio_out_named(dev, "card-inserted", 0, qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index 77fae874b1..28b4886f48 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -52,7 +52,7 @@ static void mcimx6ul_evk_init(MachineState *machine) DriveInfo *di; BlockBackend *blk; - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, i); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); carddev = qdev_new(TYPE_SD_CARD); diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 935d4b0f1c..50a5ecde31 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -52,7 +52,7 @@ static void mcimx7d_sabre_init(MachineState *machine) DriveInfo *di; BlockBackend *blk; - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, i); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); carddev = qdev_new(TYPE_SD_CARD); diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index 396e8b9913..d9f881690e 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -45,7 +45,7 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) DeviceState *spi_flash; MSF2State *soc; MachineClass *mc = MACHINE_GET_CLASS(machine); - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); qemu_irq cs_line; BusState *spi_bus; MemoryRegion *sysmem = get_system_memory(); diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index dec7d16ae5..0866d2f4f0 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -24,7 +24,6 @@ #include "hw/qdev-core.h" #include "hw/qdev-properties.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "sysemu/blockdev.h" @@ -84,9 +83,9 @@ static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram) &error_abort); } -static void sdhci_attach_drive(SDHCIState *sdhci) +static void sdhci_attach_drive(SDHCIState *sdhci, int unit) { - DriveInfo *di = drive_get_next(IF_SD); + DriveInfo *di = drive_get(IF_SD, 0, unit); BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; BusState *bus = qdev_get_child_bus(DEVICE(sdhci), "sd-bus"); @@ -374,7 +373,7 @@ static void quanta_gbs_init(MachineState *machine) drive_get(IF_MTD, 0, 0)); quanta_gbs_i2c_init(soc); - sdhci_attach_drive(&soc->mmc.sdhci); + sdhci_attach_drive(&soc->mmc.sdhci, 0); npcm7xx_load_kernel(machine, soc); } diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 0cf9895ce7..e796382236 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -85,7 +85,7 @@ static void orangepi_init(MachineState *machine) qdev_realize(DEVICE(h3), NULL, &error_abort); /* Retrieve SD bus */ - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, 0); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(h3), "sd-bus"); diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 146d35382b..b4dd6c1e99 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -284,7 +284,7 @@ static void raspi_machine_init(MachineState *machine) qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); /* Create and plug in the SD cards */ - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, 0); blk = di ? blk_by_legacy_dinfo(di) : NULL; bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus"); if (bus == NULL) { diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 1c54316ba3..ddc70b54a5 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -237,7 +237,7 @@ static void realview_init(MachineState *machine, qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 553608e583..cce49aa25c 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -76,7 +76,7 @@ static void sabrelite_init(MachineState *machine) if (spi_bus) { DeviceState *flash_dev; qemu_irq cs_line; - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); flash_dev = qdev_new("sst25vf016b"); if (dinfo) { diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 358714bd3e..dd944553f7 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 78827ace6b..b6c8a5d609 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/sysbus.h" +#include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "hw/arm/boot.h" #include "qemu/timer.h" @@ -1157,6 +1158,9 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) void *bus; DeviceState *sddev; DeviceState *ssddev; + DriveInfo *dinfo; + DeviceState *carddev; + BlockBackend *blk; /* * Some boards have both an OLED controller and SD card connected to @@ -1221,8 +1225,17 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) * - Make the ssd0323 OLED controller chipselect active-low */ bus = qdev_get_child_bus(dev, "ssi"); - sddev = ssi_create_peripheral(bus, "ssi-sd"); + + dinfo = drive_get(IF_SD, 0, 0); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + carddev = qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_prop_set_bit(carddev, "spi", true); + qdev_realize_and_unref(carddev, + qdev_get_child_bus(sddev, "sd-bus"), + &error_fatal); + ssddev = ssi_create_peripheral(bus, "ssd0323"); gpio_out[GPIO_D][0] = qemu_irq_split( qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index 0019b7f478..c07947d9f8 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/arm/stm32f405_soc.h" diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 575399c4fc..ecc1f6cf74 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -310,7 +310,7 @@ static void versatile_init(MachineState *machine, int board_id) qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); dev = sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; @@ -322,7 +322,7 @@ static void versatile_init(MachineState *machine, int board_id) } dev = sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 1); if (dinfo) { DeviceState *card; diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 58481c0762..3e99b7918a 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "cpu.h" #include "hw/sysbus.h" @@ -625,7 +624,7 @@ static void vexpress_common_init(MachineState *machine) qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); qdev_connect_gpio_out_named(dev, "card-inserted", 0, qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); - dinfo = drive_get_next(IF_SD); + dinfo = drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; @@ -657,7 +656,7 @@ static void vexpress_common_init(MachineState *machine) sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); - dinfo = drive_get_next(IF_PFLASH); + dinfo = drive_get(IF_PFLASH, 0, 0); pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", dinfo); if (!pflash0) { @@ -673,7 +672,7 @@ static void vexpress_common_init(MachineState *machine) memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); } - dinfo = drive_get_next(IF_PFLASH); + dinfo = drive_get(IF_PFLASH, 0, 1); if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo)) { error_report("vexpress: error registering flash 1"); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 674f902652..d0f4867fdf 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -55,6 +55,7 @@ #include "kvm_arm.h" #include "migration/vmstate.h" #include "hw/acpi/ghes.h" +#include "hw/acpi/viot.h" #define ARM_SPI_BASE 32 @@ -1011,6 +1012,12 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) } #endif + if (vms->iommu == VIRT_IOMMU_VIRTIO) { + acpi_add_table(table_offsets, tables_blob); + build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, + vms->oem_id, vms->oem_table_id); + } + /* XSDT is pointed to by RSDP */ xsdt = tables_blob->len; build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 30da05dfe0..6bce595aba 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -29,7 +29,6 @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" #include "qemu/option.h" @@ -2494,6 +2493,11 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, hwaddr db_start = 0, db_end = 0; char *resv_prop_str; + if (vms->iommu != VIRT_IOMMU_NONE) { + error_setg(errp, "virt machine does not support multiple IOMMUs"); + return; + } + switch (vms->msi_controller) { case VIRT_MSI_CTRL_NONE: return; @@ -2513,8 +2517,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, db_start, db_end, VIRTIO_IOMMU_RESV_MEM_T_MSI); - qdev_prop_set_uint32(dev, "len-reserved-regions", 1); - qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); + object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); + object_property_set_str(OBJECT(dev), "reserved-regions[0]", + resv_prop_str, errp); g_free(resv_prop_str); } } @@ -2614,16 +2619,10 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, MachineClass *mc = MACHINE_GET_CLASS(machine); if (device_is_dynamic_sysbus(mc, dev) || - (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { + object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { return HOTPLUG_HANDLER(machine); } - if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { - VirtMachineState *vms = VIRT_MACHINE(machine); - - if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { - return HOTPLUG_HANDLER(machine); - } - } return NULL; } diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 69c333e91b..50e7268396 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -125,9 +125,10 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } -static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi) +static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, + bool is_qspi, int unit0) { + int unit = unit0; DeviceState *dev; SysBusDevice *busdev; SSIBus *spi; @@ -156,7 +157,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); for (j = 0; j < num_ss; ++j) { - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); flash_dev = qdev_new("n25q128"); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", @@ -170,6 +171,7 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, } } + return unit; } static void zynq_init(MachineState *machine) @@ -247,9 +249,9 @@ static void zynq_init(MachineState *machine) pic[n] = qdev_get_gpio_in(dev, n); } - zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); - zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); - zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); + n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0); + n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n); + n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); @@ -298,7 +300,7 @@ static void zynq_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); - di = drive_get_next(IF_SD); + di = drive_get(IF_SD, 0, n); blk = di ? blk_by_legacy_dinfo(di) : NULL; carddev = qdev_new(TYPE_SD_CARD); qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index d2f55e29b6..0c5edc898e 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -669,7 +669,8 @@ static void versal_virt_init(MachineState *machine) /* Plugin SD cards. */ for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { - sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); + sd_plugin_card(&s->soc.pmc.iou.sd[i], + drive_get(IF_SD, 0, i)); } s->binfo.ram_size = machine->ram_size; diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 3dc2b5e8ca..45eb19ab3b 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -169,7 +169,7 @@ static void xlnx_zcu102_init(MachineState *machine) /* Create and plug in the SD cards */ for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { BusState *bus; - DriveInfo *di = drive_get_next(IF_SD); + DriveInfo *di = drive_get(IF_SD, 0, i); BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; DeviceState *carddev; char *bus_name; @@ -190,7 +190,7 @@ static void xlnx_zcu102_init(MachineState *machine) BusState *spi_bus; DeviceState *flash_dev; qemu_irq cs_line; - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, i); gchar *bus_name = g_strdup_printf("spi%d", i); spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name); @@ -212,7 +212,7 @@ static void xlnx_zcu102_init(MachineState *machine) BusState *spi_bus; DeviceState *flash_dev; qemu_irq cs_line; - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, XLNX_ZYNQMP_NUM_SPIS + i); int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; gchar *bus_name = g_strdup_printf("qspi%d", bus); diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 0608e2d475..a34803e642 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -233,7 +233,7 @@ static void atmega_realize(DeviceState *dev, Error **errp) /* CPU */ object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type); - object_property_set_bool(OBJECT(&s->cpu), "realized", true, &error_abort); + qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev = DEVICE(&s->cpu); /* SRAM */ diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index 252c3a7a23..ee5a5352dc 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -222,7 +222,7 @@ int virtio_blk_data_plane_start(VirtIODevice *vdev) memory_region_transaction_commit(); while (j--) { - virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), i); + virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), j); } goto fail_host_notifiers; } diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 8df0832424..fde67f4f03 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -103,10 +103,11 @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, return retvalue; case USART_DR: DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); + retvalue = s->usart_dr & 0x3FF; s->usart_sr &= ~USART_SR_RXNE; qemu_chr_fe_accept_input(&s->chr); qemu_set_irq(s->irq, 0); - return s->usart_dr & 0x3FF; + return retvalue; case USART_BRR: return s->usart_brr; case USART_CR1: diff --git a/hw/core/numa.c b/hw/core/numa.c index e6050b2273..1aa05dcf42 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -784,9 +784,8 @@ static void numa_stat_memory_devices(NumaNodeMem node_mem[]) break; case MEMORY_DEVICE_INFO_KIND_SGX_EPC: se = value->u.sgx_epc.data; - /* TODO: once we support numa, assign to right node */ - node_mem[0].node_mem += se->size; - node_mem[0].node_plugged_mem += se->size; + node_mem[se->node].node_mem += se->size; + node_mem[se->node].node_plugged_mem = 0; break; default: g_assert_not_reached(); diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index 8cea84f2be..90851e730b 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -33,7 +33,6 @@ #include "hw/loader.h" #include "hw/qdev-properties.h" #include "qom/object.h" -#include "qapi/error.h" #define TYPE_ISA_VGA "isa-vga" OBJECT_DECLARE_SIMPLE_TYPE(ISAVGAState, ISA_VGA) @@ -62,15 +61,6 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp) MemoryRegion *vga_io_memory; const MemoryRegionPortio *vga_ports, *vbe_ports; - /* - * make sure this device is not being added twice, if so - * exit without crashing qemu - */ - if (object_resolve_path_type("", TYPE_ISA_VGA, NULL)) { - error_setg(errp, "at most one %s device is permitted", TYPE_ISA_VGA); - return; - } - s->global_vmstate = true; vga_common_init(s, OBJECT(dev)); s->legacy_address_space = isa_address_space(isadev); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a99c6e4fe3..8383b83ee3 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2068,6 +2068,8 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) nvdimm_build_srat(table_data); } + sgx_epc_build_srat(table_data); + /* * TODO: this part is not in ACPI spec and current linux kernel boots fine * without these entries. But I recall there were issues the last time I diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c index e508827e78..96b2940d75 100644 --- a/hw/i386/sgx-epc.c +++ b/hw/i386/sgx-epc.c @@ -21,6 +21,7 @@ static Property sgx_epc_properties[] = { DEFINE_PROP_UINT64(SGX_EPC_ADDR_PROP, SGXEPCDevice, addr, 0), + DEFINE_PROP_UINT32(SGX_EPC_NUMA_NODE_PROP, SGXEPCDevice, node, 0), DEFINE_PROP_LINK(SGX_EPC_MEMDEV_PROP, SGXEPCDevice, hostmem, TYPE_MEMORY_BACKEND_EPC, HostMemoryBackendEpc *), DEFINE_PROP_END_OF_LIST(), @@ -139,6 +140,8 @@ static void sgx_epc_md_fill_device_info(const MemoryDeviceState *md, se->memaddr = epc->addr; se->size = object_property_get_uint(OBJECT(epc), SGX_EPC_SIZE_PROP, NULL); + se->node = object_property_get_uint(OBJECT(epc), SGX_EPC_NUMA_NODE_PROP, + NULL); se->memdev = object_get_canonical_path(OBJECT(epc->hostmem)); info->u.sgx_epc.data = se; diff --git a/hw/i386/sgx-stub.c b/hw/i386/sgx-stub.c index c9b379e665..26833eb233 100644 --- a/hw/i386/sgx-stub.c +++ b/hw/i386/sgx-stub.c @@ -6,6 +6,10 @@ #include "qapi/error.h" #include "qapi/qapi-commands-misc-target.h" +void sgx_epc_build_srat(GArray *table_data) +{ +} + SGXInfo *qmp_query_sgx(Error **errp) { error_setg(errp, "SGX support is not compiled in"); diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c index 8fef3dd8fa..5de5dd0893 100644 --- a/hw/i386/sgx.c +++ b/hw/i386/sgx.c @@ -23,6 +23,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/reset.h" #include +#include "hw/acpi/aml-build.h" #define SGX_MAX_EPC_SECTIONS 8 #define SGX_CPUID_EPC_INVALID 0x0 @@ -36,17 +37,59 @@ #define RETRY_NUM 2 +static int sgx_epc_device_list(Object *obj, void *opaque) +{ + GSList **list = opaque; + + if (object_dynamic_cast(obj, TYPE_SGX_EPC)) { + *list = g_slist_append(*list, DEVICE(obj)); + } + + object_child_foreach(obj, sgx_epc_device_list, opaque); + return 0; +} + +static GSList *sgx_epc_get_device_list(void) +{ + GSList *list = NULL; + + object_child_foreach(qdev_get_machine(), sgx_epc_device_list, &list); + return list; +} + +void sgx_epc_build_srat(GArray *table_data) +{ + GSList *device_list = sgx_epc_get_device_list(); + + for (; device_list; device_list = device_list->next) { + DeviceState *dev = device_list->data; + Object *obj = OBJECT(dev); + uint64_t addr, size; + int node; + + node = object_property_get_uint(obj, SGX_EPC_NUMA_NODE_PROP, + &error_abort); + addr = object_property_get_uint(obj, SGX_EPC_ADDR_PROP, &error_abort); + size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP, &error_abort); + + build_srat_memory(table_data, addr, size, node, MEM_AFFINITY_ENABLED); + } + g_slist_free(device_list); +} + static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high) { return (low & MAKE_64BIT_MASK(12, 20)) + ((high & MAKE_64BIT_MASK(0, 20)) << 32); } -static uint64_t sgx_calc_host_epc_section_size(void) +static SGXEPCSectionList *sgx_calc_host_epc_sections(void) { + SGXEPCSectionList *head = NULL, **tail = &head; + SGXEPCSection *section; uint32_t i, type; uint32_t eax, ebx, ecx, edx; - uint64_t size = 0; + uint32_t j = 0; for (i = 0; i < SGX_MAX_EPC_SECTIONS; i++) { host_cpuid(0x12, i + 2, &eax, &ebx, &ecx, &edx); @@ -60,10 +103,13 @@ static uint64_t sgx_calc_host_epc_section_size(void) break; } - size += sgx_calc_section_metric(ecx, edx); + section = g_new0(SGXEPCSection, 1); + section->node = j++; + section->size = sgx_calc_section_metric(ecx, edx); + QAPI_LIST_APPEND(tail, section); } - return size; + return head; } static void sgx_epc_reset(void *opaque) @@ -127,13 +173,35 @@ SGXInfo *qmp_query_sgx_capabilities(Error **errp) info->sgx1 = eax & (1U << 0) ? true : false; info->sgx2 = eax & (1U << 1) ? true : false; - info->section_size = sgx_calc_host_epc_section_size(); + info->sections = sgx_calc_host_epc_sections(); close(fd); return info; } +static SGXEPCSectionList *sgx_get_epc_sections_list(void) +{ + GSList *device_list = sgx_epc_get_device_list(); + SGXEPCSectionList *head = NULL, **tail = &head; + SGXEPCSection *section; + + for (; device_list; device_list = device_list->next) { + DeviceState *dev = device_list->data; + Object *obj = OBJECT(dev); + + section = g_new0(SGXEPCSection, 1); + section->node = object_property_get_uint(obj, SGX_EPC_NUMA_NODE_PROP, + &error_abort); + section->size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP, + &error_abort); + QAPI_LIST_APPEND(tail, section); + } + g_slist_free(device_list); + + return head; +} + SGXInfo *qmp_query_sgx(Error **errp) { SGXInfo *info = NULL; @@ -152,14 +220,13 @@ SGXInfo *qmp_query_sgx(Error **errp) return NULL; } - SGXEPCState *sgx_epc = &pcms->sgx_epc; info = g_new0(SGXInfo, 1); info->sgx = true; info->sgx1 = true; info->sgx2 = true; info->flc = true; - info->section_size = sgx_epc->size; + info->sections = sgx_get_epc_sections_list(); return info; } @@ -167,6 +234,7 @@ SGXInfo *qmp_query_sgx(Error **errp) void hmp_info_sgx(Monitor *mon, const QDict *qdict) { Error *err = NULL; + SGXEPCSectionList *section_list, *section; g_autoptr(SGXInfo) info = qmp_query_sgx(&err); if (err) { @@ -181,8 +249,14 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict) info->sgx2 ? "enabled" : "disabled"); monitor_printf(mon, "FLC support: %s\n", info->flc ? "enabled" : "disabled"); - monitor_printf(mon, "size: %" PRIu64 "\n", - info->section_size); + + section_list = info->sections; + for (section = section_list; section; section = section->next) { + monitor_printf(mon, "NUMA node #%" PRId64 ": ", + section->value->node); + monitor_printf(mon, "size=%" PRIu64 "\n", + section->value->size); + } } bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size) @@ -226,6 +300,9 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms) /* set the memdev link with memory backend */ object_property_parse(obj, SGX_EPC_MEMDEV_PROP, list->value->memdev, &error_fatal); + /* set the numa node property for sgx epc object */ + object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, list->value->node, + &error_fatal); object_property_set_bool(obj, "realized", true, &error_fatal); object_unref(obj); } diff --git a/hw/i386/vmmouse.c b/hw/i386/vmmouse.c index 3d66368286..a56c185f15 100644 --- a/hw/i386/vmmouse.c +++ b/hw/i386/vmmouse.c @@ -286,6 +286,10 @@ static void vmmouse_realizefn(DeviceState *dev, Error **errp) DPRINTF("vmmouse_init\n"); + if (!s->i8042) { + error_setg(errp, "'i8042' link is not set"); + return; + } if (!object_resolve_path_type("", TYPE_VMPORT, NULL)) { error_setg(errp, "vmmouse needs a machine with vmport"); return; diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 78aed93c45..010ded7eae 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -25,6 +25,11 @@ config APIC select MSI_NONBROKEN select I8259 +config ARM_GIC_TCG + bool + default y + depends on ARM_GIC && TCG + config ARM_GIC_KVM bool default y diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 9f5f815db9..715df5421d 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -1,5 +1,5 @@ /* - * ARM Generic Interrupt Controller v3 + * ARM Generic Interrupt Controller v3 (emulation) * * Copyright (c) 2015 Huawei. * Copyright (c) 2016 Linaro Limited diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 7fba931450..d7e03d0cab 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1,5 +1,5 @@ /* - * ARM Generic Interrupt Controller v3 + * ARM Generic Interrupt Controller v3 (emulation) * * Copyright (c) 2016 Linaro Limited * Written by Peter Maydell @@ -21,14 +21,6 @@ #include "hw/irq.h" #include "cpu.h" -void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) -{ - ARMCPU *arm_cpu = ARM_CPU(cpu); - CPUARMState *env = &arm_cpu->env; - - env->gicv3state = (void *)s; -}; - static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { return env->gicv3state; @@ -351,7 +343,8 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) /* Scan list registers and fill in the U, NP and EOI bits */ eoi_maintenance_interrupt_state(cs, &value); - if (cs->ich_hcr_el2 & (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) { + if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && + (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { value |= ICH_MISR_EL2_LRENP; } diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c new file mode 100644 index 0000000000..ff1239f65d --- /dev/null +++ b/hw/intc/arm_gicv3_cpuif_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller v3 + * + * Copyright (c) 2016 Linaro Limited + * Written by Peter Maydell + * + * This code is licensed under the GPL, version 2 or (at your option) + * any later version. + */ + +#include "qemu/osdep.h" +#include "gicv3_internal.h" +#include "cpu.h" + +void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + + env->gicv3state = (void *)s; +}; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index c929a9cb5c..b99e63d58f 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -274,21 +274,36 @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, if (res != MEMTX_OK) { return result; } + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n", + __func__, dte, devid, res); + return result; } - if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || - !cte_valid || (eventid > max_eventid)) { + + /* + * In this implementation, in case of guest errors we ignore the + * command and move onto the next command in the queue. + */ + if (devid > s->dt.maxids.max_devids) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid command attributes " - "devid %d or eventid %d or invalid dte %d or" - "invalid cte %d or invalid ite %d\n", - __func__, devid, eventid, dte_valid, cte_valid, - ite_valid); - /* - * in this implementation, in case of error - * we ignore this command and move onto the next - * command in the queue - */ + "%s: invalid command attributes: devid %d>%d", + __func__, devid, s->dt.maxids.max_devids); + + } else if (!dte_valid || !ite_valid || !cte_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "dte: %s, ite: %s, cte: %s\n", + __func__, + dte_valid ? "valid" : "invalid", + ite_valid ? "valid" : "invalid", + cte_valid ? "valid" : "invalid"); + } else if (eventid > max_eventid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: eventid %d > %d\n", + __func__, eventid, max_eventid); } else { /* * Current implementation only supports rdbase == procnum diff --git a/hw/intc/meson.build b/hw/intc/meson.build index c89d2ca180..70080bc161 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -3,12 +3,14 @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( 'arm_gic.c', 'arm_gic_common.c', 'arm_gicv2m.c', - 'arm_gicv3.c', 'arm_gicv3_common.c', - 'arm_gicv3_dist.c', 'arm_gicv3_its_common.c', - 'arm_gicv3_redist.c', +)) +softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( + 'arm_gicv3.c', + 'arm_gicv3_dist.c', 'arm_gicv3_its.c', + 'arm_gicv3_redist.c', )) softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) @@ -25,7 +27,8 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) +specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index 159db6cbe2..a24fadddca 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -183,7 +183,7 @@ petalogix_ml605_init(MachineState *machine) spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); for (i = 0; i < NUM_SPI_FLASHES; i++) { - DriveInfo *dinfo = drive_get_next(IF_MTD); + DriveInfo *dinfo = drive_get(IF_MTD, 0, i); qemu_irq cs_line; dev = qdev_new("n25q128"); diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c index 6ec8314490..99991f8b2b 100644 --- a/hw/mips/bootloader.c +++ b/hw/mips/bootloader.c @@ -182,7 +182,11 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val) { bl_gen_load_ulong(p, BL_REG_K0, val); bl_gen_load_ulong(p, BL_REG_K1, addr); - bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + if (bootcpu_supports_isa(ISA_MIPS3)) { + bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); + } else { + bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); + } } void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 0e3cca5511..59ca08b93a 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -777,14 +777,15 @@ static void boston_mach_init(MachineState *machine) exit(1); } } else if (machine->kernel_filename) { - uint64_t kernel_entry, kernel_high, kernel_size; + uint64_t kernel_entry, kernel_high; + ssize_t kernel_size; kernel_size = load_elf(machine->kernel_filename, NULL, cpu_mips_kseg0_to_phys, NULL, &kernel_entry, NULL, &kernel_high, NULL, 0, EM_MIPS, 1, 0); - if (kernel_size) { + if (kernel_size > 0) { int dt_size; g_autofree const void *dtb_file_data, *dtb_load_data; hwaddr dtb_paddr = QEMU_ALIGN_UP(kernel_high, 64 * KiB); diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 1ba4a98377..299837e5c1 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -243,7 +243,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, static const MemoryRegionOps ivshmem_mmio_ops = { .read = ivshmem_io_read, .write = ivshmem_io_write, - .endianness = DEVICE_NATIVE_ENDIAN, + .endianness = DEVICE_LITTLE_ENDIAN, .impl = { .min_access_size = 4, .max_access_size = 4, diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 52fdb750c0..6d5f84e6c2 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -209,9 +209,9 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); - dinfo = drive_get_next(IF_PFLASH); + dinfo = drive_get(IF_PFLASH, 0, 0); if (!dinfo) { - dinfo = drive_get_next(IF_NONE); + dinfo = drive_get(IF_NONE, 0, 0); if (dinfo) { warn_report("using \"-drive if=none\" for the OTP is deprecated, " "use \"-drive if=pflash\" instead."); diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c index 7c892f820f..545b2b7410 100644 --- a/hw/net/npcm7xx_emc.c +++ b/hw/net/npcm7xx_emc.c @@ -284,6 +284,12 @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) emc_set_mista(emc, mista_flag); } +static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) +{ + emc->rx_active = true; + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); +} + static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, const NPCM7xxEMCTxDesc *tx_desc, uint32_t desc_addr) @@ -581,13 +587,6 @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) return len; } -static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) -{ - if (emc_can_receive(qemu_get_queue(emc->nic))) { - qemu_flush_queued_packets(qemu_get_queue(emc->nic)); - } -} - static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) { NPCM7xxEMCState *emc = opaque; @@ -703,7 +702,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; } if (value & REG_MCMDR_RXON) { - emc->rx_active = true; + emc_enable_rx_and_flush(emc); } else { emc_halt_rx(emc, 0); } @@ -739,8 +738,7 @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, break; case REG_RSDR: if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { - emc->rx_active = true; - emc_try_receive_next_packet(emc); + emc_enable_rx_and_flush(emc); } break; case REG_MIIDA: diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a7f9685005..9c4451ca0d 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -993,7 +993,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp) PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); int i; - if (phb->phb_id >= PNV8_CHIP_PHB3_MAX) { + if (phb->phb_id >= PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; } @@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, static Property pnv_phb3_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c index a0526aa1ec..c7426cd27a 100644 --- a/hw/pci-host/pnv_phb3_pbcq.c +++ b/hw/pci-host/pnv_phb3_pbcq.c @@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev), &pnv_pbcq_spci_xscom_ops, pbcq, name, PNV_XSCOM_PBCQ_SPCI_SIZE); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_nest_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_pci_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, + &pbcq->xscom_spci_regs); } static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 5c375a9f28..40b793201a 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1205,6 +1205,7 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) &phb->pci_mmio, &phb->pci_io, 0, 4, TYPE_PNV_PHB4_ROOT_BUS); pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); + pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; /* Add a single Root port */ qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id); diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 741ddc90ed..24a3adcae3 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -124,7 +124,7 @@ static uint64_t pnv_pec_stk_nest_xscom_read(void *opaque, hwaddr addr, static void pnv_pec_stk_update_map(PnvPhb4PecStack *stack) { PnvPhb4PecState *pec = stack->pec; - MemoryRegion *sysmem = pec->system_memory; + MemoryRegion *sysmem = get_system_memory(); uint64_t bar_en = stack->nest_regs[PEC_NEST_STK_BAR_EN]; uint64_t bar, mask, size; char name[64]; @@ -374,20 +374,41 @@ static void pnv_pec_instance_init(Object *obj) } } +static int pnv_pec_phb_offset(PnvPhb4PecState *pec) +{ + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + int index = pec->index; + int offset = 0; + + while (index--) { + offset += pecc->num_stacks[index]; + } + + return offset; +} + static void pnv_pec_realize(DeviceState *dev, Error **errp) { PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); char name[64]; int i; - assert(pec->system_memory); + if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { + error_setg(errp, "invalid PEC index: %d", pec->index); + return; + } + + pec->num_stacks = pecc->num_stacks[pec->index]; /* Create stacks */ for (i = 0; i < pec->num_stacks; i++) { PnvPhb4PecStack *stack = &pec->stacks[i]; Object *stk_obj = OBJECT(stack); + int phb_id = pnv_pec_phb_offset(pec) + i; object_property_set_int(stk_obj, "stack-no", i, &error_abort); + object_property_set_int(stk_obj, "phb-id", phb_id, &error_abort); object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort); if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { return; @@ -460,10 +481,9 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, static Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), - DEFINE_PROP_UINT32("num-stacks", PnvPhb4PecState, num_stacks, 0), DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), - DEFINE_PROP_LINK("system-memory", PnvPhb4PecState, system_memory, - TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, + PnvChip *), DEFINE_PROP_END_OF_LIST(), }; @@ -477,6 +497,13 @@ static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; } +/* + * PEC0 -> 1 stack + * PEC1 -> 2 stacks + * PEC2 -> 3 stacks + */ +static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 }; + static void pnv_pec_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -499,6 +526,9 @@ static void pnv_pec_class_init(ObjectClass *klass, void *data) pecc->compat_size = sizeof(compat); pecc->stk_compat = stk_compat; pecc->stk_compat_size = sizeof(stk_compat); + pecc->version = PNV_PHB4_VERSION; + pecc->device_id = PNV_PHB4_DEVICE_ID; + pecc->num_stacks = pnv_pec_num_stacks; } static const TypeInfo pnv_pec_type_info = { @@ -519,12 +549,17 @@ static void pnv_pec_stk_instance_init(Object *obj) PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj); object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); + object_property_add_alias(obj, "phb-id", OBJECT(&stack->phb), "index"); } static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) { PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); PnvPhb4PecState *pec = stack->pec; + PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); + PnvChip *chip = pec->chip; + uint32_t pec_nest_base; + uint32_t pec_pci_base; char name[64]; assert(pec); @@ -548,10 +583,32 @@ static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&stack->phb_regs_mr, OBJECT(&stack->phb), &pnv_phb4_xscom_ops, &stack->phb, name, 0x40); - /* - * Let the machine/chip realize the PHB object to customize more - * easily some fields - */ + object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, + &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, + &error_fatal); + object_property_set_int(OBJECT(&stack->phb), "device-id", pecc->device_id, + &error_fatal); + object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { + return; + } + + pec_nest_base = pecc->xscom_nest_base(pec); + pec_pci_base = pecc->xscom_pci_base(pec); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(chip, + pec_nest_base + 0x40 * (stack->stack_no + 1), + &stack->nest_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + 0x40 * (stack->stack_no + 1), + &stack->pci_regs_mr); + pnv_xscom_add_subregion(chip, + pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + + 0x40 * stack->stack_no, + &stack->phb_regs_mr); } static Property pnv_pec_stk_properties[] = { diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 22c8408078..a1fa8f8e41 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -36,9 +36,6 @@ #include "hw/pci-host/uninorth.h" #include "qom/object.h" -/* SMP is not enabled, for now */ -#define MAX_CPUS 1 - #define NVRAM_SIZE 0x2000 #define PROM_FILENAME "openbios-ppc" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 7bb7ac3997..4bddb529c2 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -581,7 +581,8 @@ static void core99_machine_class_init(ObjectClass *oc, void *data) mc->desc = "Mac99 based PowerMAC"; mc->init = ppc_core99_init; mc->block_default_type = IF_IDE; - mc->max_cpus = MAX_CPUS; + /* SMP is not supported currently */ + mc->max_cpus = 1; mc->default_boot_order = "cd"; mc->default_display = "std"; mc->kvm_type = core99_kvm_type; diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index de2be960e6..7016979a7c 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -423,7 +423,8 @@ static void heathrow_class_init(ObjectClass *oc, void *data) mc->desc = "Heathrow based PowerMAC"; mc->init = ppc_heathrow_init; mc->block_default_type = IF_IDE; - mc->max_cpus = MAX_CPUS; + /* SMP is not supported currently */ + mc->max_cpus = 1; #ifndef TARGET_PPC64 mc->is_default = true; #endif diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 71e45515f1..29ee0d0f08 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -522,7 +522,7 @@ static void *pnv_dt_create(MachineState *machine) buf = qemu_uuid_unparse_strdup(&qemu_uuid); _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); if (qemu_uuid_set) { - _FDT((fdt_property_string(fdt, "system-id", buf))); + _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); } g_free(buf); @@ -638,32 +638,47 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); } +static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) +{ + Monitor *mon = opaque; + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + pnv_phb3_msi_pic_print_info(&phb3->msis, mon); + ics_pic_print_info(&phb3->lsis, mon); + } + return 0; +} + static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv8Chip *chip8 = PNV8_CHIP(chip); - int i; ics_pic_print_info(&chip8->psi.ics, mon); - for (i = 0; i < chip->num_phbs; i++) { - pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); - ics_pic_print_info(&chip8->phbs[i].lsis, mon); + object_child_foreach(OBJECT(chip), + pnv_chip_power8_pic_print_info_child, mon); +} + +static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) +{ + Monitor *mon = opaque; + PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); + + if (phb4) { + pnv_phb4_pic_print_info(phb4, mon); } + return 0; } static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) { Pnv9Chip *chip9 = PNV9_CHIP(chip); - int i, j; pnv_xive_pic_print_info(&chip9->xive, mon); pnv_psi_pic_print_info(&chip9->psi, mon); - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { - PnvPhb4PecState *pec = &chip9->pecs[i]; - for (j = 0; j < pec->num_stacks; j++) { - pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); - } - } + object_child_foreach_recursive(OBJECT(chip), + pnv_chip_power9_pic_print_info_child, mon); } static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, @@ -742,6 +757,11 @@ static void pnv_init(MachineState *machine) DriveInfo *pnor = drive_get(IF_MTD, 0, 0); DeviceState *dev; + if (kvm_enabled()) { + error_report("The powernv machine does not work with KVM acceleration"); + exit(EXIT_FAILURE); + } + /* allocate RAM */ if (machine->ram_size < mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -1221,25 +1241,15 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* PHB3 controllers */ for (i = 0; i < chip->num_phbs; i++) { PnvPHB3 *phb = &chip8->phbs[i]; - PnvPBCQState *pbcq = &phb->pbcq; object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, &error_fatal); + object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), + &error_fatal); if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_nest_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_pci_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, - &pbcq->xscom_spci_regs); } } @@ -1340,15 +1350,13 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + /* Number of PECs is the chip default */ + chip->num_pecs = pcc->num_pecs; + + for (i = 0; i < chip->num_pecs; i++) { object_initialize_child(obj, "pec[*]", &chip9->pecs[i], TYPE_PNV_PHB4_PEC); } - - /* - * Number of PHBs is the chip default - */ - chip->num_phbs = pcc->num_phbs; } static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) @@ -1378,30 +1386,22 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) } } -static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) +static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) { Pnv9Chip *chip9 = PNV9_CHIP(chip); - int i, j; - int phb_id = 0; + int i; - for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { + for (i = 0; i < chip->num_pecs; i++) { PnvPhb4PecState *pec = &chip9->pecs[i]; PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); uint32_t pec_nest_base; uint32_t pec_pci_base; object_property_set_int(OBJECT(pec), "index", i, &error_fatal); - /* - * PEC0 -> 1 stack - * PEC1 -> 2 stacks - * PEC2 -> 3 stacks - */ - object_property_set_int(OBJECT(pec), "num-stacks", i + 1, - &error_fatal); object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, &error_fatal); - object_property_set_link(OBJECT(pec), "system-memory", - OBJECT(get_system_memory()), &error_abort); + object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), + &error_fatal); if (!qdev_realize(DEVICE(pec), NULL, errp)) { return; } @@ -1411,37 +1411,6 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); - - for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; - j++, phb_id++) { - PnvPhb4PecStack *stack = &pec->stacks[j]; - Object *obj = OBJECT(&stack->phb); - - object_property_set_int(obj, "index", phb_id, &error_fatal); - object_property_set_int(obj, "chip-id", chip->chip_id, - &error_fatal); - object_property_set_int(obj, "version", PNV_PHB4_VERSION, - &error_fatal); - object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, - &error_fatal); - object_property_set_link(obj, "stack", OBJECT(stack), - &error_abort); - if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { - return; - } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - pec_nest_base + 0x40 * (stack->stack_no + 1), - &stack->nest_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + 0x40 * (stack->stack_no + 1), - &stack->pci_regs_mr); - pnv_xscom_add_subregion(chip, - pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + - 0x40 * stack->stack_no, - &stack->phb_regs_mr); - } } } @@ -1537,8 +1506,8 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), &chip9->homer.regs); - /* PHBs */ - pnv_chip_power9_phb_realize(chip, &local_err); + /* PEC PHBs */ + pnv_chip_power9_pec_realize(chip, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -1569,7 +1538,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->xscom_core_base = pnv_chip_power9_xscom_core_base; k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; - k->num_phbs = 6; + k->num_pecs = PNV9_CHIP_MAX_PEC; device_class_set_parent_realize(dc, pnv_chip_power9_realize, &k->parent_realize); @@ -1764,7 +1733,6 @@ static Property pnv_chip_properties[] = { DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), - DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -1795,10 +1763,32 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) return NULL; } +typedef struct ForeachPhb3Args { + int irq; + ICSState *ics; +} ForeachPhb3Args; + +static int pnv_ics_get_child(Object *child, void *opaque) +{ + ForeachPhb3Args *args = opaque; + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + if (ics_valid_irq(&phb3->lsis, args->irq)) { + args->ics = &phb3->lsis; + } + if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { + args->ics = ICS(&phb3->msis); + } + } + return args->ics ? 1 : 0; +} + static ICSState *pnv_ics_get(XICSFabric *xi, int irq) { PnvMachineState *pnv = PNV_MACHINE(xi); - int i, j; + ForeachPhb3Args args = { irq, NULL }; + int i; for (i = 0; i < pnv->num_chips; i++) { PnvChip *chip = pnv->chips[i]; @@ -1807,32 +1797,37 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) if (ics_valid_irq(&chip8->psi.ics, irq)) { return &chip8->psi.ics; } - for (j = 0; j < chip->num_phbs; j++) { - if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { - return &chip8->phbs[j].lsis; - } - if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { - return ICS(&chip8->phbs[j].msis); - } + + object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); + if (args.ics) { + return args.ics; } } return NULL; } +static int pnv_ics_resend_child(Object *child, void *opaque) +{ + PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); + + if (phb3) { + ics_resend(&phb3->lsis); + ics_resend(ICS(&phb3->msis)); + } + return 0; +} + static void pnv_ics_resend(XICSFabric *xi) { PnvMachineState *pnv = PNV_MACHINE(xi); - int i, j; + int i; for (i = 0; i < pnv->num_chips; i++) { PnvChip *chip = pnv->chips[i]; Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); ics_resend(&chip8->psi.ics); - for (j = 0; j < chip->num_phbs; j++) { - ics_resend(&chip8->phbs[j].lsis); - ics_resend(ICS(&chip8->phbs[j].msis)); - } + object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); } } diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index e8127599c9..818d757985 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1367,6 +1367,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) if (dcr->dcr_read == NULL) goto error; *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); + trace_ppc_dcr_read(dcrn, *valp); return 0; @@ -1386,6 +1387,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) dcr = &dcr_env->dcrn[dcrn]; if (dcr->dcr_write == NULL) goto error; + trace_ppc_dcr_write(dcrn, val); (*dcr->dcr_write)(dcr->opaque, dcrn, val); return 0; diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index c58f739886..83f156f585 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -27,6 +27,13 @@ #include "hw/ppc/ppc4xx.h" +#define PPC405EP_SDRAM_BASE 0x00000000 +#define PPC405EP_NVRAM_BASE 0xF0000000 +#define PPC405EP_FPGA_BASE 0xF0300000 +#define PPC405EP_SRAM_BASE 0xFFF00000 +#define PPC405EP_SRAM_SIZE (512 * KiB) +#define PPC405EP_FLASH_BASE 0xFFF80000 + /* Bootinfo as set-up by u-boot */ typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t; struct ppc4xx_bd_info_t { @@ -50,19 +57,18 @@ struct ppc4xx_bd_info_t { uint32_t bi_plb_busfreq; uint32_t bi_pci_busfreq; uint8_t bi_pci_enetaddr[6]; - uint32_t bi_pci_enetaddr2[6]; + uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */ uint32_t bi_opbfreq; uint32_t bi_iic_fast[2]; }; /* PowerPC 405 core */ -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags); +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); -CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, +PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 972a7a4a3e..3ae2b36373 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -41,11 +41,12 @@ #include "qemu/error-report.h" #include "hw/loader.h" #include "qemu/cutils.h" +#include "elf.h" #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2 * MiB) -#define KERNEL_LOAD_ADDR 0x00000000 +#define KERNEL_LOAD_ADDR 0x01000000 #define INITRD_LOAD_ADDR 0x01800000 #define USE_FLASH_BIOS @@ -136,32 +137,101 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) qemu_register_reset(&ref405ep_fpga_reset, fpga); } +/* + * CPU reset handler when booting directly from a loaded kernel + */ +static struct boot_info { + uint32_t entry; + uint32_t bdloc; + uint32_t initrd_base; + uint32_t initrd_size; + uint32_t cmdline_base; + uint32_t cmdline_size; +} boot_info; + +static void main_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + struct boot_info *bi = env->load_info; + + cpu_reset(CPU(cpu)); + + /* stack: top of sram */ + env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8; + + /* Tune our boot state */ + env->gpr[3] = bi->bdloc; + env->gpr[4] = bi->initrd_base; + env->gpr[5] = bi->initrd_base + bi->initrd_size; + env->gpr[6] = bi->cmdline_base; + env->gpr[7] = bi->cmdline_size; + + env->nip = bi->entry; +} + +static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + hwaddr boot_entry; + hwaddr kernel_base; + int kernel_size; + hwaddr initrd_base; + int initrd_size; + ram_addr_t bdloc; + int len; + + bdloc = ppc405_set_bootinfo(env, machine->ram_size); + boot_info.bdloc = bdloc; + + kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL, + &boot_entry, &kernel_base, NULL, NULL, + 1, PPC_ELF_MACHINE, 0, 0); + if (kernel_size < 0) { + error_report("Could not load kernel '%s' : %s", + machine->kernel_filename, load_elf_strerror(kernel_size)); + exit(1); + } + boot_info.entry = boot_entry; + + /* load initrd */ + if (machine->initrd_filename) { + initrd_base = INITRD_LOAD_ADDR; + initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, + machine->ram_size - initrd_base); + if (initrd_size < 0) { + error_report("could not load initial ram disk '%s'", + machine->initrd_filename); + exit(1); + } + + boot_info.initrd_base = initrd_base; + boot_info.initrd_size = initrd_size; + } + + if (machine->kernel_cmdline) { + len = strlen(machine->kernel_cmdline); + bdloc -= ((len + 255) & ~255); + cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1); + boot_info.cmdline_base = bdloc; + boot_info.cmdline_size = bdloc + len; + } + + /* Install our custom reset handler to start from Linux */ + qemu_register_reset(main_cpu_reset, cpu); + env->load_info = &boot_info; +} + static void ref405ep_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); - const char *bios_name = machine->firmware ?: BIOS_FILENAME; const char *kernel_filename = machine->kernel_filename; - const char *kernel_cmdline = machine->kernel_cmdline; - const char *initrd_filename = machine->initrd_filename; - char *filename; - ppc4xx_bd_info_t bd; - CPUPPCState *env; + PowerPCCPU *cpu; DeviceState *dev; SysBusDevice *s; - MemoryRegion *bios; MemoryRegion *sram = g_new(MemoryRegion, 1); - ram_addr_t bdloc; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); hwaddr ram_bases[2], ram_sizes[2]; - target_ulong sram_size; - long bios_size; - //int phy_addr = 0; - //static int phy_addr = 1; - target_ulong kernel_base, initrd_base; - long kernel_size, initrd_size; - int linux_boot; - int len; - DriveInfo *dinfo; MemoryRegion *sysmem = get_system_memory(); DeviceState *uicdev; @@ -180,132 +250,80 @@ static void ref405ep_init(MachineState *machine) memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; - env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, + + cpu = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &uicdev, kernel_filename == NULL ? 0 : 1); + /* allocate SRAM */ - sram_size = 512 * KiB; - memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, + memory_region_init_ram(sram, NULL, "ef405ep.sram", PPC405EP_SRAM_SIZE, &error_fatal); - memory_region_add_subregion(sysmem, 0xFFF00000, sram); + memory_region_add_subregion(sysmem, PPC405EP_SRAM_BASE, sram); + /* allocate and load BIOS */ -#ifdef USE_FLASH_BIOS - dinfo = drive_get(IF_PFLASH, 0, 0); - if (dinfo) { - bios_size = 8 * MiB; - pflash_cfi02_register((uint32_t)(-bios_size), - "ef405ep.bios", bios_size, - blk_by_legacy_dinfo(dinfo), - 64 * KiB, 1, - 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, - 1); - } else -#endif - { - bios = g_new(MemoryRegion, 1); + if (machine->firmware) { + MemoryRegion *bios = g_new(MemoryRegion, 1); + g_autofree char *filename; + long bios_size; + memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE, &error_fatal); - filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - if (filename) { - bios_size = load_image_size(filename, - memory_region_get_ram_ptr(bios), - BIOS_SIZE); - g_free(filename); - if (bios_size < 0) { - error_report("Could not load PowerPC BIOS '%s'", bios_name); - exit(1); - } - bios_size = (bios_size + 0xfff) & ~0xfff; - memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); - } else if (!qtest_enabled() || kernel_filename != NULL) { - error_report("Could not load PowerPC BIOS '%s'", bios_name); + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); + if (!filename) { + error_report("Could not find firmware '%s'", machine->firmware); exit(1); - } else { - /* Avoid an uninitialized variable warning */ - bios_size = -1; } + + bios_size = load_image_size(filename, + memory_region_get_ram_ptr(bios), + BIOS_SIZE); + if (bios_size < 0) { + error_report("Could not load PowerPC BIOS '%s'", machine->firmware); + exit(1); + } + + bios_size = (bios_size + 0xfff) & ~0xfff; + memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios); } + /* Register FPGA */ - ref405ep_fpga_init(sysmem, 0xF0300000); + ref405ep_fpga_init(sysmem, PPC405EP_FPGA_BASE); /* Register NVRAM */ dev = qdev_new("sysbus-m48t08"); qdev_prop_set_int32(dev, "base-year", 1968); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, 0xF0000000); - /* Load kernel */ - linux_boot = (kernel_filename != NULL); - if (linux_boot) { - memset(&bd, 0, sizeof(bd)); - bd.bi_memstart = 0x00000000; - bd.bi_memsize = machine->ram_size; - bd.bi_flashstart = -bios_size; - bd.bi_flashsize = -bios_size; - bd.bi_flashoffset = 0; - bd.bi_sramstart = 0xFFF00000; - bd.bi_sramsize = sram_size; - bd.bi_bootflags = 0; - bd.bi_intfreq = 133333333; - bd.bi_busfreq = 33333333; - bd.bi_baudrate = 115200; - bd.bi_s_version[0] = 'Q'; - bd.bi_s_version[1] = 'M'; - bd.bi_s_version[2] = 'U'; - bd.bi_s_version[3] = '\0'; - bd.bi_r_version[0] = 'Q'; - bd.bi_r_version[1] = 'E'; - bd.bi_r_version[2] = 'M'; - bd.bi_r_version[3] = 'U'; - bd.bi_r_version[4] = '\0'; - bd.bi_procfreq = 133333333; - bd.bi_plb_busfreq = 33333333; - bd.bi_pci_busfreq = 33333333; - bd.bi_opbfreq = 33333333; - bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001); - env->gpr[3] = bdloc; + sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE); + + /* Load kernel and initrd using U-Boot images */ + if (kernel_filename && machine->firmware) { + target_ulong kernel_base, initrd_base; + long kernel_size, initrd_size; + kernel_base = KERNEL_LOAD_ADDR; - /* now we can load the kernel */ kernel_size = load_image_targphys(kernel_filename, kernel_base, machine->ram_size - kernel_base); if (kernel_size < 0) { error_report("could not load kernel '%s'", kernel_filename); exit(1); } - printf("Load kernel size %ld at " TARGET_FMT_lx, - kernel_size, kernel_base); + /* load initrd */ - if (initrd_filename) { + if (machine->initrd_filename) { initrd_base = INITRD_LOAD_ADDR; - initrd_size = load_image_targphys(initrd_filename, initrd_base, + initrd_size = load_image_targphys(machine->initrd_filename, + initrd_base, machine->ram_size - initrd_base); if (initrd_size < 0) { error_report("could not load initial ram disk '%s'", - initrd_filename); + machine->initrd_filename); exit(1); } - } else { - initrd_base = 0; - initrd_size = 0; } - env->gpr[4] = initrd_base; - env->gpr[5] = initrd_size; - if (kernel_cmdline != NULL) { - len = strlen(kernel_cmdline); - bdloc -= ((len + 255) & ~255); - cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1); - env->gpr[6] = bdloc; - env->gpr[7] = bdloc + len; - } else { - env->gpr[6] = 0; - env->gpr[7] = 0; - } - env->nip = KERNEL_LOAD_ADDR; - } else { - kernel_base = 0; - kernel_size = 0; - initrd_base = 0; - initrd_size = 0; - bdloc = 0; + + /* Load ELF kernel and rootfs.cpio */ + } else if (kernel_filename && !machine->firmware) { + boot_from_kernel(machine, cpu); } } @@ -547,6 +565,7 @@ static void taihu_class_init(ObjectClass *oc, void *data) mc->init = taihu_405ep_init; mc->default_ram_size = 0x08000000; mc->default_ram_id = "taihu_405ep.ram"; + mc->deprecation_reason = "incomplete, use 'ref405ep' instead"; } static const TypeInfo taihu_type = { diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index e632c408bd..ec97b22bd0 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/ppc/ppc.h" #include "hw/i2c/ppc4xx_i2c.h" @@ -38,18 +39,37 @@ #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" #include "qapi/error.h" +#include "trace.h" -//#define DEBUG_OPBA -//#define DEBUG_SDRAM -//#define DEBUG_GPIO -//#define DEBUG_SERIAL -//#define DEBUG_OCM -//#define DEBUG_GPT -//#define DEBUG_CLOCKS -//#define DEBUG_CLOCKS_LL +static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, + ram_addr_t ram_size) +{ + memset(bd, 0, sizeof(*bd)); -ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, - uint32_t flags) + bd->bi_memstart = PPC405EP_SDRAM_BASE; + bd->bi_memsize = ram_size; + bd->bi_sramstart = PPC405EP_SRAM_BASE; + bd->bi_sramsize = PPC405EP_SRAM_SIZE; + bd->bi_bootflags = 0; + bd->bi_intfreq = 133333333; + bd->bi_busfreq = 33333333; + bd->bi_baudrate = 115200; + bd->bi_s_version[0] = 'Q'; + bd->bi_s_version[1] = 'M'; + bd->bi_s_version[2] = 'U'; + bd->bi_s_version[3] = '\0'; + bd->bi_r_version[0] = 'Q'; + bd->bi_r_version[1] = 'E'; + bd->bi_r_version[2] = 'M'; + bd->bi_r_version[3] = 'U'; + bd->bi_r_version[4] = '\0'; + bd->bi_procfreq = 133333333; + bd->bi_plb_busfreq = 33333333; + bd->bi_pci_busfreq = 33333333; + bd->bi_opbfreq = 33333333; +} + +static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) { CPUState *cs = env_cpu(env); ram_addr_t bdloc; @@ -82,15 +102,15 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, for (i = 0; i < 32; i++) { stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); } - stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); - stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); + stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq); + stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq); + stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq); for (i = 0; i < 6; i++) { - stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); + stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]); } - n = 0x6A; - if (flags & 0x00000001) { - for (i = 0; i < 6; i++) - stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); + n = 0x70; /* includes 2 bytes hole */ + for (i = 0; i < 6; i++) { + stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); } stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); n += 4; @@ -102,6 +122,17 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, return bdloc; } +ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) +{ + ppc4xx_bd_info_t bd; + + memset(&bd, 0, sizeof(bd)); + + ppc405_set_default_bootinfo(&bd, ram_size); + + return __ppc405_set_bootinfo(env, &bd); +} + /*****************************************************************************/ /* Shared peripherals */ @@ -287,13 +318,9 @@ struct ppc4xx_opba_t { static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_opba_t *opba; + ppc4xx_opba_t *opba = opaque; uint32_t ret; -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - opba = opaque; switch (addr) { case 0x00: ret = opba->cr; @@ -306,19 +333,17 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) break; } + trace_opba_readb(addr, ret); return ret; } static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_opba_t *opba; + ppc4xx_opba_t *opba = opaque; + + trace_opba_writeb(addr, value); -#ifdef DEBUG_OPBA - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - opba = opaque; switch (addr) { case 0x00: opba->cr = value & 0xF8; @@ -353,10 +378,9 @@ static void ppc4xx_opba_init(hwaddr base) { ppc4xx_opba_t *opba; + trace_opba_init(base); + opba = g_malloc0(sizeof(ppc4xx_opba_t)); -#ifdef DEBUG_OPBA - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); memory_region_add_subregion(get_system_memory(), base, &opba->io); qemu_register_reset(ppc4xx_opba_reset, opba); @@ -707,20 +731,14 @@ struct ppc405_gpio_t { static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) { -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); -#endif - + trace_ppc405_gpio_read(addr, size); return 0; } static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { -#ifdef DEBUG_GPIO - printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", - __func__, addr, size, value); -#endif + trace_ppc405_gpio_write(addr, size, value); } static const MemoryRegionOps ppc405_gpio_ops = { @@ -737,10 +755,9 @@ static void ppc405_gpio_init(hwaddr base) { ppc405_gpio_t *gpio; + trace_ppc405_gpio_init(base); + gpio = g_malloc0(sizeof(ppc405_gpio_t)); -#ifdef DEBUG_GPIO - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); memory_region_add_subregion(get_system_memory(), base, &gpio->io); qemu_register_reset(&ppc405_gpio_reset, gpio); @@ -770,25 +787,19 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl) { -#ifdef DEBUG_OCM - printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 - " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 - " (%08" PRIx32 " %08" PRIx32 ")\n", - isarc, isacntl, dsarc, dsacntl, - ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); -#endif + trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, + ocm->isacntl, ocm->dsarc, ocm->dsacntl); + if (ocm->isarc != isarc || (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { if (ocm->isacntl & 0x80000000) { /* Unmap previously assigned memory region */ - printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); + trace_ocm_unmap("ISA", ocm->isarc); memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); } if (isacntl & 0x80000000) { /* Map new instruction memory region */ -#ifdef DEBUG_OCM - printf("OCM map ISA %08" PRIx32 "\n", isarc); -#endif + trace_ocm_map("ISA", isarc); memory_region_add_subregion(get_system_memory(), isarc, &ocm->isarc_ram); } @@ -799,9 +810,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, /* Beware not to unmap the region we just mapped */ if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { /* Unmap previously assigned memory region */ -#ifdef DEBUG_OCM - printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); -#endif + trace_ocm_unmap("DSA", ocm->dsarc); memory_region_del_subregion(get_system_memory(), &ocm->dsarc_ram); } @@ -810,9 +819,7 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm, /* Beware not to remap the region we just mapped */ if (!(isacntl & 0x80000000) || dsarc != isarc) { /* Map new data memory region */ -#ifdef DEBUG_OCM - printf("OCM map DSA %08" PRIx32 "\n", dsarc); -#endif + trace_ocm_map("DSA", dsarc); memory_region_add_subregion(get_system_memory(), dsarc, &ocm->dsarc_ram); } @@ -988,14 +995,12 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_gpt_t *gpt; + ppc4xx_gpt_t *gpt = opaque; uint32_t ret; int idx; -#ifdef DEBUG_GPT - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif - gpt = opaque; + trace_ppc4xx_gpt_read(addr, size); + switch (addr) { case 0x00: /* Time base counter */ @@ -1044,14 +1049,11 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_gpt_t *gpt; + ppc4xx_gpt_t *gpt = opaque; int idx; -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, - value); -#endif - gpt = opaque; + trace_ppc4xx_gpt_write(addr, size, value); + switch (addr) { case 0x00: /* Time base counter */ @@ -1144,14 +1146,13 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) ppc4xx_gpt_t *gpt; int i; + trace_ppc4xx_gpt_init(base); + gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); for (i = 0; i < 5; i++) { gpt->irqs[i] = irqs[i]; } gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); -#ifdef DEBUG_GPT - printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); -#endif memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); qemu_register_reset(ppc4xx_gpt_reset, gpt); @@ -1215,17 +1216,14 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) VCO_out = 0; if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ -#ifdef DEBUG_CLOCKS_LL - printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); -#endif + trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ -#ifdef DEBUG_CLOCKS_LL - printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); -#endif + trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); VCO_out = (uint64_t)cpc->sysclk * M * D; if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { /* Error - unlock the PLL */ - printf("VCO out of range %" PRIu64 "\n", VCO_out); + qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", + VCO_out); #if 0 cpc->pllmr[1] &= ~0x80000000; goto pll_bypass; @@ -1246,54 +1244,43 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) } /* Now, compute all other clocks */ D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ -#ifdef DEBUG_CLOCKS_LL - printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); CPU_clk = PLL_out / D; D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ -#ifdef DEBUG_CLOCKS_LL - printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); PLB_clk = CPU_clk / D; D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); OPB_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); EBC_clk = PLB_clk / D; D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); MAL_clk = PLB_clk / D; D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ -#ifdef DEBUG_CLOCKS_LL - printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); -#endif + trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); PCI_clk = PLB_clk / D; D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ -#ifdef DEBUG_CLOCKS_LL - printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); -#endif + trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); UART0_clk = PLL_out / D; D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ -#ifdef DEBUG_CLOCKS_LL - printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); -#endif + trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); UART1_clk = PLL_out / D; -#ifdef DEBUG_CLOCKS - printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 - " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); - printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 - " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 - " UART1 %" PRIu32 "\n", - CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, - UART0_clk, UART1_clk); -#endif + + if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { + g_autofree char *trace = g_strdup_printf( + "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 + " PLL out %" PRIu64 " Hz\n" + "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 + " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 + " UART1 %" PRIu32 "\n", + cpc->sysclk, VCO_out, PLL_out, + CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, + UART0_clk, UART1_clk); + trace_ppc405ep_clocks_setup(trace); + } + /* Setup CPU clocks */ clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); /* Setup PLB clock */ @@ -1395,9 +1382,9 @@ static void ppc405ep_cpc_reset (void *opaque) cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ cpc->epctl = 0x00000000; - cpc->pllmr[0] = 0x00011010; - cpc->pllmr[1] = 0x40000000; - cpc->ucr = 0x00000000; + cpc->pllmr[0] = 0x00021002; + cpc->pllmr[1] = 0x80a552be; + cpc->ucr = 0x00004646; cpc->srr = 0x00040000; cpc->pci = 0x00000000; cpc->er = 0x00000000; @@ -1444,7 +1431,7 @@ static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], #endif } -CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, +PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, MemoryRegion ram_memories[2], hwaddr ram_bases[2], hwaddr ram_sizes[2], @@ -1543,5 +1530,5 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, /* CPU control */ ppc405ep_cpc_init(env, clk_setup, sysclk); - return env; + return cpu; } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 58e7341cb7..a57ba70a87 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -20,6 +20,7 @@ #include "target/ppc/kvm_ppc.h" #include "hw/ppc/ppc.h" #include "target/ppc/mmu-hash64.h" +#include "target/ppc/power8-pmu.h" #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/hw_accel.h" diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 3bf43fa340..ada644652d 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -119,6 +119,9 @@ ppc_irq_set_state(const char *name, uint32_t level) "\"%s\" level %d" ppc_irq_reset(const char *name) "%s" ppc_irq_cpu(const char *action) "%s" +ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" +ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" + # prep_systemio.c prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x" @@ -141,3 +144,23 @@ ppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of ppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 ppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 + +# ppc405_boards.c +opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 +opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64 +opba_init(uint64_t addr) "offet 0x%" PRIx64 + +ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" +ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64 +ppc405_gpio_init(uint64_t addr) "offet 0x%" PRIx64 + +ocm_update_mappings(uint32_t isarc, uint32_t isacntl, uint32_t dsarc, uint32_t dsacntl, uint32_t ocm_isarc, uint32_t ocm_isacntl, uint32_t ocm_dsarc, uint32_t ocm_dsacntl) "OCM update ISA 0x%08" PRIx32 " 0x%08" PRIx32 " (0x%08" PRIx32" 0x%08" PRIx32 ") DSA 0x%08" PRIx32 " 0x%08" PRIx32" (0x%08" PRIx32 " 0x%08" PRIx32 ")" +ocm_map(const char* prefix, uint32_t isarc) "OCM map %s 0x%08" PRIx32 +ocm_unmap(const char* prefix, uint32_t isarc) "OCM unmap %s 0x%08" PRIx32 + +ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" +ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64 +ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64 + +ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) "%s 0x%1" PRIx32 " %d" +ppc405ep_clocks_setup(const char *trace) "%s" diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 519fa455a1..f67264374e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -151,12 +151,19 @@ target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { - uint64_t kernel_entry; + uint64_t kernel_load_base, kernel_entry; + /* + * NB: Use low address not ELF entry point to ensure that the fw_dynamic + * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL + * behaviour, as well as fw_dynamic with a raw binary, all of which jump to + * the (expected) load address load address. This allows kernels to have + * separate SBI and ELF entry points (used by FreeBSD, for example). + */ if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, - &kernel_entry, NULL, NULL, NULL, 0, + NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_entry; + return kernel_load_base; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 57d779fb55..d1d065efbc 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -458,7 +458,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) target_ulong firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; uint32_t fdt_load_addr; - DriveInfo *dinfo = drive_get_next(IF_SD); + DriveInfo *dinfo = drive_get(IF_SD, 0, 0); /* Sanity check on RAM size */ if (machine->ram_size < mc->default_ram_size) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 589ae72a59..aa74e67889 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -46,6 +46,7 @@ #include "hw/char/serial.h" #include "hw/cpu/cluster.h" #include "hw/misc/unimp.h" +#include "hw/sd/sd.h" #include "hw/ssi/ssi.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" @@ -536,7 +537,8 @@ static void sifive_u_machine_init(MachineState *machine) uint32_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; - DeviceState *flash_dev, *sd_dev; + BlockBackend *blk; + DeviceState *flash_dev, *sd_dev, *card_dev; qemu_irq flash_cs, sd_cs; /* Initialize SoC */ @@ -670,7 +672,7 @@ static void sifive_u_machine_init(MachineState *machine) /* Connect an SPI flash to SPI0 */ flash_dev = qdev_new("is25wp256"); - dinfo = drive_get_next(IF_MTD); + dinfo = drive_get(IF_MTD, 0, 0); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -686,6 +688,15 @@ static void sifive_u_machine_init(MachineState *machine) sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); + + dinfo = drive_get(IF_SD, 0, 0); + blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; + card_dev = qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); + qdev_prop_set_bit(card_dev, "spi", true); + qdev_realize_and_unref(card_dev, + qdev_get_child_bus(sd_dev, "sd-bus"), + &error_fatal); } static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 1b51a72838..01b58ebc70 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -782,6 +782,7 @@ static void s390_pci_init_default_group(void) resgrp->i = 128; resgrp->maxstbl = 128; resgrp->version = 0; + resgrp->dtsm = ZPCI_DTSM; } static void set_pbdev_info(S390PCIBusDevice *pbdev) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 1c8ad91175..6d400d4147 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -329,6 +329,7 @@ int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) stw_p(&resgrp->i, group->zpci_group.i); stw_p(&resgrp->maxstbl, group->zpci_group.maxstbl); resgrp->version = group->zpci_group.version; + resgrp->dtsm = group->zpci_group.dtsm; stw_p(&resgrp->hdr.rsp, CLP_RC_OK); break; } @@ -916,9 +917,10 @@ int pci_dereg_irqs(S390PCIBusDevice *pbdev) return 0; } -static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, +static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib, uintptr_t ra) { + S390PCIIOMMU *iommu = pbdev->iommu; uint64_t pba = ldq_p(&fib.pba); uint64_t pal = ldq_p(&fib.pal); uint64_t g_iota = ldq_p(&fib.iota); @@ -927,7 +929,7 @@ static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, pba &= ~0xfff; pal |= 0xfff; - if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { + if (pba > pal || pba < pbdev->zpci_fn.sdma || pal > pbdev->zpci_fn.edma) { s390_program_interrupt(env, PGM_OPERAND, ra); return -EINVAL; } @@ -1045,7 +1047,7 @@ static void fmb_update(void *opaque) sizeof(pbdev->fmb.last_update))) { return; } - timer_mod(pbdev->fmb_timer, t + DEFAULT_MUI); + timer_mod(pbdev->fmb_timer, t + pbdev->pci_group->zpci_group.mui); } int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, @@ -1125,7 +1127,7 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, } else if (pbdev->iommu->enabled) { cc = ZPCI_PCI_LS_ERR; s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); - } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { + } else if (reg_ioat(env, pbdev, fib, ra)) { cc = ZPCI_PCI_LS_ERR; s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); } @@ -1150,7 +1152,7 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); } else { pci_dereg_ioat(pbdev->iommu); - if (reg_ioat(env, pbdev->iommu, fib, ra)) { + if (reg_ioat(env, pbdev, fib, ra)) { cc = ZPCI_PCI_LS_ERR; s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); } @@ -1203,7 +1205,8 @@ int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, } pbdev->fmb_addr = fmb_addr; timer_mod(pbdev->fmb_timer, - qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + DEFAULT_MUI); + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + + pbdev->pci_group->zpci_group.mui); break; } default: diff --git a/hw/s390x/s390-pci-vfio.c b/hw/s390x/s390-pci-vfio.c index 2a153fa8c9..6f80a47e29 100644 --- a/hw/s390x/s390-pci-vfio.c +++ b/hw/s390x/s390-pci-vfio.c @@ -160,6 +160,7 @@ static void s390_pci_read_group(S390PCIBusDevice *pbdev, resgrp->i = cap->noi; resgrp->maxstbl = cap->maxstbl; resgrp->version = cap->version; + resgrp->dtsm = ZPCI_DTSM; } } diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 85e907a785..4c431adb77 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -621,8 +621,7 @@ static void lsi_do_dma(LSIState *s, int out) dma_addr_t addr; SCSIDevice *dev; - assert(s->current); - if (!s->current->dma_len) { + if (!s->current || !s->current->dma_len) { /* Wait until data is available. */ trace_lsi_do_dma_unavailable(); return; diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 4ff51221d4..8f35784100 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -303,6 +303,7 @@ static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl) } if (cmd->iov_size > iov_size) { trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size); + goto unmap; } else if (cmd->iov_size < iov_size) { trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size); } diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index e60854eeef..167c03b780 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -368,36 +368,9 @@ static const VMStateDescription vmstate_ssi_sd = { static void ssi_sd_realize(SSIPeripheral *d, Error **errp) { - ERRP_GUARD(); ssi_sd_state *s = SSI_SD(d); - DeviceState *carddev; - DriveInfo *dinfo; qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(d), "sd-bus"); - - /* Create and plug in the sd card */ - /* FIXME use a qdev drive property instead of drive_get_next() */ - dinfo = drive_get_next(IF_SD); - carddev = qdev_new(TYPE_SD_CARD); - if (dinfo) { - if (!qdev_prop_set_drive_err(carddev, "drive", - blk_by_legacy_dinfo(dinfo), errp)) { - goto fail; - } - } - - if (!object_property_set_bool(OBJECT(carddev), "spi", true, errp)) { - goto fail; - } - - if (!qdev_realize_and_unref(carddev, BUS(&s->sdbus), errp)) { - goto fail; - } - - return; - -fail: - error_prepend(errp, "failed to init SD card: "); } static void ssi_sd_reset(DeviceState *dev) @@ -426,7 +399,7 @@ static void ssi_sd_class_init(ObjectClass *klass, void *data) k->cs_polarity = SSI_CS_LOW; dc->vmsd = &vmstate_ssi_sd; dc->reset = ssi_sd_reset; - /* Reason: init() method uses drive_get_next() */ + /* Reason: GPIO chip-select line should be wired up */ dc->user_creatable = false; } diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index f3e42d0326..ccad2c43a3 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -98,7 +98,7 @@ static void add_rom_or_fail(const char *file, const hwaddr addr) static void niagara_init(MachineState *machine) { NiagaraBoardState *s = g_new(NiagaraBoardState, 1); - DriveInfo *dinfo = drive_get_next(IF_PFLASH); + DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); MemoryRegion *sysmem = get_system_memory(); /* init CPUs */ diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 650e521e35..f7ad6be5fb 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -91,8 +91,7 @@ virtio_mmio_setting_irq(int level) "virtio_mmio setting IRQ %d" virtio_iommu_device_reset(void) "reset!" virtio_iommu_get_features(uint64_t features) "device supports features=0x%"PRIx64 virtio_iommu_device_status(uint8_t status) "driver status = %d" -virtio_iommu_get_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_range, uint32_t probe_size) "page_size_mask=0x%"PRIx64" start=0x%"PRIx64" end=0x%"PRIx64" domain_range=%d probe_size=0x%x" -virtio_iommu_set_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_range, uint32_t probe_size) "page_size_mask=0x%"PRIx64" start=0x%"PRIx64" end=0x%"PRIx64" domain_bits=%d probe_size=0x%x" +virtio_iommu_get_config(uint64_t page_size_mask, uint64_t start, uint64_t end, uint32_t domain_start, uint32_t domain_end, uint32_t probe_size) "page_size_mask=0x%"PRIx64" input range start=0x%"PRIx64" input range end=0x%"PRIx64" domain range start=%d domain range end=%d probe_size=0x%x" virtio_iommu_attach(uint32_t domain_id, uint32_t ep_id) "domain=%d endpoint=%d" virtio_iommu_detach(uint32_t domain_id, uint32_t ep_id) "domain=%d endpoint=%d" virtio_iommu_map(uint32_t domain_id, uint64_t virt_start, uint64_t virt_end, uint64_t phys_start, uint32_t flags) "domain=%d virt_start=0x%"PRIx64" virt_end=0x%"PRIx64 " phys_start=0x%"PRIx64" flags=%d" diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 437347ad01..20913cf8fb 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -313,7 +313,7 @@ static int vhost_dev_has_iommu(struct vhost_dev *dev) * For vhost, VIRTIO_F_IOMMU_PLATFORM means the backend support * incremental memory mapping API via IOTLB API. For platform that * does not have IOMMU, there's no need to enable this feature - * which may cause unnecessary IOTLB miss/update trnasactions. + * which may cause unnecessary IOTLB miss/update transactions. */ return virtio_bus_device_iommu_enabled(vdev) && virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM); diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index a160ae6b41..6a1df7fe50 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -48,16 +48,8 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); - - error_setg(errp, - "%s machine fails to create iommu-map device tree bindings", - mc->name); - error_append_hint(errp, - "Check your machine implements a hotplug handler " - "for the virtio-iommu-pci device\n"); - error_append_hint(errp, "Check the guest is booted without FW or with " - "-no-acpi\n"); + error_setg(errp, "Check your machine implements a hotplug handler " + "for the virtio-iommu-pci device"); return; } for (int i = 0; i < s->nb_reserved_regions; i++) { diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 1b23e8e18c..aa9c16a17b 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -822,27 +822,22 @@ unlock: static void virtio_iommu_get_config(VirtIODevice *vdev, uint8_t *config_data) { VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev); - struct virtio_iommu_config *config = &dev->config; + struct virtio_iommu_config *dev_config = &dev->config; + struct virtio_iommu_config *out_config = (void *)config_data; - trace_virtio_iommu_get_config(config->page_size_mask, - config->input_range.start, - config->input_range.end, - config->domain_range.end, - config->probe_size); - memcpy(config_data, &dev->config, sizeof(struct virtio_iommu_config)); -} + out_config->page_size_mask = cpu_to_le64(dev_config->page_size_mask); + out_config->input_range.start = cpu_to_le64(dev_config->input_range.start); + out_config->input_range.end = cpu_to_le64(dev_config->input_range.end); + out_config->domain_range.start = cpu_to_le32(dev_config->domain_range.start); + out_config->domain_range.end = cpu_to_le32(dev_config->domain_range.end); + out_config->probe_size = cpu_to_le32(dev_config->probe_size); -static void virtio_iommu_set_config(VirtIODevice *vdev, - const uint8_t *config_data) -{ - struct virtio_iommu_config config; - - memcpy(&config, config_data, sizeof(struct virtio_iommu_config)); - trace_virtio_iommu_set_config(config.page_size_mask, - config.input_range.start, - config.input_range.end, - config.domain_range.end, - config.probe_size); + trace_virtio_iommu_get_config(dev_config->page_size_mask, + dev_config->input_range.start, + dev_config->input_range.end, + dev_config->domain_range.start, + dev_config->domain_range.end, + dev_config->probe_size); } static uint64_t virtio_iommu_get_features(VirtIODevice *vdev, uint64_t f, @@ -983,8 +978,8 @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) s->event_vq = virtio_add_queue(vdev, VIOMMU_DEFAULT_QUEUE_SIZE, NULL); s->config.page_size_mask = TARGET_PAGE_MASK; - s->config.input_range.end = -1UL; - s->config.domain_range.end = 32; + s->config.input_range.end = UINT64_MAX; + s->config.domain_range.end = UINT32_MAX; s->config.probe_size = VIOMMU_PROBE_SIZE; virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX); @@ -1185,7 +1180,6 @@ static void virtio_iommu_class_init(ObjectClass *klass, void *data) vdc->unrealize = virtio_iommu_device_unrealize; vdc->reset = virtio_iommu_device_reset; vdc->get_config = virtio_iommu_get_config; - vdc->set_config = virtio_iommu_set_config; vdc->get_features = virtio_iommu_get_features; vdc->set_status = virtio_iommu_set_status; vdc->vmsd = &vmstate_virtio_iommu_device; diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 3c8e24292b..bb37239efa 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -437,12 +437,10 @@ void dump_opcount_info(GString *buf); #endif /* !CONFIG_USER_ONLY */ -#ifdef CONFIG_TCG /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); void tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); -#endif /* CONFIG_TCG */ /* Returns: 0 on success, -1 on error */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 5bcbd041f7..8abd9ab4ec 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -145,13 +145,20 @@ typedef enum __attribute__((__packed__)) { */ enum { - float_flag_invalid = 1, - float_flag_divbyzero = 4, - float_flag_overflow = 8, - float_flag_underflow = 16, - float_flag_inexact = 32, - float_flag_input_denormal = 64, - float_flag_output_denormal = 128 + float_flag_invalid = 0x0001, + float_flag_divbyzero = 0x0002, + float_flag_overflow = 0x0004, + float_flag_underflow = 0x0008, + float_flag_inexact = 0x0010, + float_flag_input_denormal = 0x0020, + float_flag_output_denormal = 0x0040, + float_flag_invalid_isi = 0x0080, /* inf - inf */ + float_flag_invalid_imz = 0x0100, /* inf * 0 */ + float_flag_invalid_idi = 0x0200, /* inf / inf */ + float_flag_invalid_zdz = 0x0400, /* 0 / 0 */ + float_flag_invalid_sqrt = 0x0800, /* sqrt(-x) */ + float_flag_invalid_cvti = 0x1000, /* non-nan to integer */ + float_flag_invalid_snan = 0x2000, /* any operand was snan */ }; /* @@ -171,8 +178,8 @@ typedef enum __attribute__((__packed__)) { */ typedef struct float_status { + uint16_t float_exception_flags; FloatRoundMode float_rounding_mode; - uint8_t float_exception_flags; FloatX80RoundPrec floatx80_rounding_precision; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a249991e61..d34b2c44d2 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -100,7 +100,7 @@ typedef enum { | Routine to raise any or all of the software IEC/IEEE floating-point | exception flags. *----------------------------------------------------------------------------*/ -static inline void float_raise(uint8_t flags, float_status *status) +static inline void float_raise(uint16_t flags, float_status *status) { status->float_exception_flags |= flags; } @@ -908,6 +908,18 @@ static inline bool float64_unordered_quiet(float64 a, float64 b, *----------------------------------------------------------------------------*/ float64 float64_default_nan(float_status *status); +/*---------------------------------------------------------------------------- +| Software IEC/IEEE double-precision operations, rounding to single precision, +| returning a result in double precision, with only one rounding step. +*----------------------------------------------------------------------------*/ + +float64 float64r32_add(float64, float64, float_status *status); +float64 float64r32_sub(float64, float64, float_status *status); +float64 float64r32_mul(float64, float64, float_status *status); +float64 float64r32_div(float64, float64, float_status *status); +float64 float64r32_muladd(float64, float64, float64, int, float_status *status); +float64 float64r32_sqrt(float64, float_status *status); + /*---------------------------------------------------------------------------- | Software IEC/IEEE extended double-precision conversion routines. *----------------------------------------------------------------------------*/ diff --git a/include/glib-compat.h b/include/glib-compat.h index 9e95c888f5..8d01a8c01f 100644 --- a/include/glib-compat.h +++ b/include/glib-compat.h @@ -68,6 +68,43 @@ * without generating warnings. */ +/* + * g_memdup2_qemu: + * @mem: (nullable): the memory to copy. + * @byte_size: the number of bytes to copy. + * + * Allocates @byte_size bytes of memory, and copies @byte_size bytes into it + * from @mem. If @mem is %NULL it returns %NULL. + * + * This replaces g_memdup(), which was prone to integer overflows when + * converting the argument from a #gsize to a #guint. + * + * This static inline version is a backport of the new public API from + * GLib 2.68, kept internal to GLib for backport to older stable releases. + * See https://gitlab.gnome.org/GNOME/glib/-/issues/2319. + * + * Returns: (nullable): a pointer to the newly-allocated copy of the memory, + * or %NULL if @mem is %NULL. + */ +static inline gpointer g_memdup2_qemu(gconstpointer mem, gsize byte_size) +{ +#if GLIB_CHECK_VERSION(2, 68, 0) + return g_memdup2(mem, byte_size); +#else + gpointer new_mem; + + if (mem && byte_size != 0) { + new_mem = g_malloc(byte_size); + memcpy(new_mem, mem, byte_size); + } else { + new_mem = NULL; + } + + return new_mem; +#endif +} +#define g_memdup2(m, s) g_memdup2_qemu(m, s) + #if defined(G_OS_UNIX) /* * Note: The fallback implementation is not MT-safe, and it returns a copy of diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 4d9c732d4b..efcbd926fd 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -18,7 +18,6 @@ #ifndef HW_I386_MICROVM_H #define HW_I386_MICROVM_H -#include "qemu-common.h" #include "exec/hwaddr.h" #include "qemu/notify.h" diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h index a6a65be854..581fac389a 100644 --- a/include/hw/i386/sgx-epc.h +++ b/include/hw/i386/sgx-epc.h @@ -25,6 +25,7 @@ #define SGX_EPC_ADDR_PROP "addr" #define SGX_EPC_SIZE_PROP "size" #define SGX_EPC_MEMDEV_PROP "memdev" +#define SGX_EPC_NUMA_NODE_PROP "node" /** * SGXEPCDevice: @@ -38,6 +39,7 @@ typedef struct SGXEPCDevice { /* public */ uint64_t addr; + uint32_t node; HostMemoryBackendEpc *hostmem; } SGXEPCDevice; @@ -56,6 +58,7 @@ typedef struct SGXEPCState { } SGXEPCState; bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size); +void sgx_epc_build_srat(GArray *table_data); static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc) { diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index bb1cfb8896..a145a30370 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -17,7 +17,6 @@ #ifndef HW_I386_X86_H #define HW_I386_X86_H -#include "qemu-common.h" #include "exec/hwaddr.h" #include "qemu/notify.h" diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index e2a2e36245..e9c13e6bd8 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -16,6 +16,7 @@ #include "qom/object.h" typedef struct PnvPHB3 PnvPHB3; +typedef struct PnvChip PnvChip; /* * PHB3 XICS Source for MSIs @@ -157,6 +158,8 @@ struct PnvPHB3 { PnvPHB3RootPort root; QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; + + PnvChip *chip; }; uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 27556ae534..60de3031a6 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -205,6 +205,8 @@ struct PnvPhb4PecState { #define PHB4_PEC_MAX_STACKS 3 uint32_t num_stacks; PnvPhb4PecStack stacks[PHB4_PEC_MAX_STACKS]; + + PnvChip *chip; }; @@ -219,6 +221,9 @@ struct PnvPhb4PecClass { int compat_size; const char *stk_compat; int stk_compat_size; + uint64_t version; + uint64_t device_id; + const uint32_t *num_stacks; }; #endif /* PCI_HOST_PNV_PHB4_H */ diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index a94d350034..30691a6e57 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -138,6 +138,7 @@ typedef struct PCIBridgeQemuCap { uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */ } PCIBridgeQemuCap; +#define REDHAT_PCI_CAP_TYPE_OFFSET 3 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 /* @@ -152,6 +153,13 @@ typedef struct PCIResReserve { uint64_t mem_pref_64; } PCIResReserve; +#define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES 4 +#define REDHAT_PCI_CAP_RES_RESERVE_IO 8 +#define REDHAT_PCI_CAP_RES_RESERVE_MEM 16 +#define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20 +#define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24 +#define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE 32 + int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, PCIResReserve res_reserve, Error **errp); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index aa08d79d24..c781525277 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -53,6 +53,7 @@ struct PnvChip { PnvCore **cores; uint32_t num_phbs; + uint32_t num_pecs; MemoryRegion xscom_mmio; MemoryRegion xscom; @@ -136,6 +137,7 @@ struct PnvChipClass { uint64_t chip_cfam_id; uint64_t cores_mask; uint32_t num_phbs; + uint32_t num_pecs; DeviceRealize parent_realize; diff --git a/include/hw/s390x/s390-pci-bus.h b/include/hw/s390x/s390-pci-bus.h index aa891c178d..da3cde2bb4 100644 --- a/include/hw/s390x/s390-pci-bus.h +++ b/include/hw/s390x/s390-pci-bus.h @@ -37,6 +37,7 @@ #define ZPCI_MAX_UID 0xffff #define UID_UNDEFINED 0 #define UID_CHECKING_ENABLED 0x01 +#define ZPCI_DTSM 0x40 OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE) OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS) @@ -313,7 +314,7 @@ typedef struct ZpciFmb { } ZpciFmb; QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb"); -#define ZPCI_DEFAULT_FN_GRP 0x20 +#define ZPCI_DEFAULT_FN_GRP 0xFF typedef struct S390PCIGroup { ClpRspQueryPciGrp zpci_group; int id; diff --git a/include/hw/s390x/s390-pci-clp.h b/include/hw/s390x/s390-pci-clp.h index 96b8e3f133..cc8c8662b8 100644 --- a/include/hw/s390x/s390-pci-clp.h +++ b/include/hw/s390x/s390-pci-clp.h @@ -163,7 +163,8 @@ typedef struct ClpRspQueryPciGrp { uint8_t fr; uint16_t maxstbl; uint16_t mui; - uint64_t reserved3; + uint8_t dtsm; + uint8_t reserved3[7]; uint64_t dasm; /* dma address space mask */ uint64_t msia; /* MSI address */ uint64_t reserved4; diff --git a/include/hw/scsi/scsi.h b/include/hw/scsi/scsi.h index a567a5ed86..2ef80af6dc 100644 --- a/include/hw/scsi/scsi.h +++ b/include/hw/scsi/scsi.h @@ -158,7 +158,7 @@ struct SCSIBus { * provided by the caller. It is the caller's responsibility to make * sure that name does not clash with the name of any other bus in the * system. Unless you need the new bus to have a specific name, you - * should use scsi_bus_new() instead. + * should use scsi_bus_init() instead. */ void scsi_bus_init_named(SCSIBus *bus, size_t bus_size, DeviceState *host, const SCSIBusInfo *info, const char *bus_name); diff --git a/include/hw/virtio/virtio-gpu-bswap.h b/include/hw/virtio/virtio-gpu-bswap.h index e2bee8f595..5faac0d8d5 100644 --- a/include/hw/virtio/virtio-gpu-bswap.h +++ b/include/hw/virtio/virtio-gpu-bswap.h @@ -24,7 +24,6 @@ virtio_gpu_ctrl_hdr_bswap(struct virtio_gpu_ctrl_hdr *hdr) le32_to_cpus(&hdr->flags); le64_to_cpus(&hdr->fence_id); le32_to_cpus(&hdr->ctx_id); - le32_to_cpus(&hdr->padding); } static inline void diff --git a/include/migration/colo.h b/include/migration/colo.h index 768e1f04c3..5fbe1a6d5d 100644 --- a/include/migration/colo.h +++ b/include/migration/colo.h @@ -37,4 +37,5 @@ COLOMode get_colo_mode(void); void colo_do_failover(void); void colo_checkpoint_notify(void *opaque); +void colo_shutdown(void); #endif diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h index 352b51fd0a..2c025cb4fe 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -103,6 +103,12 @@ extern "C" { /* 8 bpp Red */ #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */ +/* 10 bpp Red */ +#define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */ + +/* 12 bpp Red */ +#define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */ + /* 16 bpp Red */ #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */ @@ -372,6 +378,12 @@ extern "C" { #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#define fourcc_mod_get_vendor(modifier) \ + (((modifier) >> 56) & 0xff) + +#define fourcc_mod_is_vendor(modifier, vendor) \ + (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor) + #define fourcc_mod_code(vendor, val) \ ((((uint64_t)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL)) @@ -899,9 +911,9 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) /* * The top 4 bits (out of the 56 bits alloted for specifying vendor specific - * modifiers) denote the category for modifiers. Currently we have only two - * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen - * different categories. + * modifiers) denote the category for modifiers. Currently we have three + * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of + * sixteen different categories. */ #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) @@ -1016,6 +1028,109 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) */ #define AFBC_FORMAT_MOD_USM (1ULL << 12) +/* + * Arm Fixed-Rate Compression (AFRC) modifiers + * + * AFRC is a proprietary fixed rate image compression protocol and format, + * designed to provide guaranteed bandwidth and memory footprint + * reductions in graphics and media use-cases. + * + * AFRC buffers consist of one or more planes, with the same components + * and meaning as an uncompressed buffer using the same pixel format. + * + * Within each plane, the pixel/luma/chroma values are grouped into + * "coding unit" blocks which are individually compressed to a + * fixed size (in bytes). All coding units within a given plane of a buffer + * store the same number of values, and have the same compressed size. + * + * The coding unit size is configurable, allowing different rates of compression. + * + * The start of each AFRC buffer plane must be aligned to an alignment granule which + * depends on the coding unit size. + * + * Coding Unit Size Plane Alignment + * ---------------- --------------- + * 16 bytes 1024 bytes + * 24 bytes 512 bytes + * 32 bytes 2048 bytes + * + * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned + * to a multiple of the paging tile dimensions. + * The dimensions of each paging tile depend on whether the buffer is optimised for + * scanline (SCAN layout) or rotated (ROT layout) access. + * + * Layout Paging Tile Width Paging Tile Height + * ------ ----------------- ------------------ + * SCAN 16 coding units 4 coding units + * ROT 8 coding units 8 coding units + * + * The dimensions of each coding unit depend on the number of components + * in the compressed plane and whether the buffer is optimised for + * scanline (SCAN layout) or rotated (ROT layout) access. + * + * Number of Components in Plane Layout Coding Unit Width Coding Unit Height + * ----------------------------- --------- ----------------- ------------------ + * 1 SCAN 16 samples 4 samples + * Example: 16x4 luma samples in a 'Y' plane + * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 1 ROT 8 samples 8 samples + * Example: 8x8 luma samples in a 'Y' plane + * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 2 DONT CARE 8 samples 4 samples + * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer + * ----------------------------- --------- ----------------- ------------------ + * 3 DONT CARE 4 samples 4 samples + * Example: 4x4 pixels in an RGB buffer without alpha + * ----------------------------- --------- ----------------- ------------------ + * 4 DONT CARE 4 samples 4 samples + * Example: 4x4 pixels in an RGB buffer with alpha + */ + +#define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02 + +#define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode) + +/* + * AFRC coding unit size modifier. + * + * Indicates the number of bytes used to store each compressed coding unit for + * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance + * is the same for both Cb and Cr, which may be stored in separate planes. + * + * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store + * each compressed coding unit in the first plane of the buffer. For RGBA buffers + * this is the only plane, while for semi-planar and fully-planar YUV buffers, + * this corresponds to the luma plane. + * + * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store + * each compressed coding unit in the second and third planes in the buffer. + * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s). + * + * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified + * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero. + * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and + * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified. + */ +#define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf +#define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL) +#define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL) +#define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL) + +#define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size) +#define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4) + +/* + * AFRC scanline memory layout. + * + * Indicates if the buffer uses the scanline-optimised layout + * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout. + * The memory layout is the same for all planes. + */ +#define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8) + /* * Arm 16x16 Block U-Interleaved modifier * diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h index 053d3fafdf..688eb8dc39 100644 --- a/include/standard-headers/linux/ethtool.h +++ b/include/standard-headers/linux/ethtool.h @@ -603,6 +603,7 @@ enum ethtool_link_ext_state { ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, ETHTOOL_LINK_EXT_STATE_OVERHEAT, + ETHTOOL_LINK_EXT_STATE_MODULE, }; /* More information in addition to ETHTOOL_LINK_EXT_STATE_AUTONEG. */ @@ -639,6 +640,8 @@ enum ethtool_link_ext_substate_link_logical_mismatch { enum ethtool_link_ext_substate_bad_signal_integrity { ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1, ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE, + ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST, + ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS, }; /* More information in addition to ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE. */ @@ -647,6 +650,11 @@ enum ethtool_link_ext_substate_cable_issue { ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE, }; +/* More information in addition to ETHTOOL_LINK_EXT_STATE_MODULE. */ +enum ethtool_link_ext_substate_module { + ETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY = 1, +}; + #define ETH_GSTRING_LEN 32 /** @@ -704,6 +712,29 @@ enum ethtool_stringset { ETH_SS_COUNT }; +/** + * enum ethtool_module_power_mode_policy - plug-in module power mode policy + * @ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH: Module is always in high power mode. + * @ETHTOOL_MODULE_POWER_MODE_POLICY_AUTO: Module is transitioned by the host + * to high power mode when the first port using it is put administratively + * up and to low power mode when the last port using it is put + * administratively down. + */ +enum ethtool_module_power_mode_policy { + ETHTOOL_MODULE_POWER_MODE_POLICY_HIGH = 1, + ETHTOOL_MODULE_POWER_MODE_POLICY_AUTO, +}; + +/** + * enum ethtool_module_power_mode - plug-in module power mode + * @ETHTOOL_MODULE_POWER_MODE_LOW: Module is in low power mode. + * @ETHTOOL_MODULE_POWER_MODE_HIGH: Module is in high power mode. + */ +enum ethtool_module_power_mode { + ETHTOOL_MODULE_POWER_MODE_LOW = 1, + ETHTOOL_MODULE_POWER_MODE_HIGH, +}; + /** * struct ethtool_gstrings - string set for data tagging * @cmd: Command number = %ETHTOOL_GSTRINGS diff --git a/include/standard-headers/linux/fuse.h b/include/standard-headers/linux/fuse.h index cce105bfba..23ea31708b 100644 --- a/include/standard-headers/linux/fuse.h +++ b/include/standard-headers/linux/fuse.h @@ -181,6 +181,9 @@ * - add FUSE_OPEN_KILL_SUIDGID * - extend fuse_setxattr_in, add FUSE_SETXATTR_EXT * - add FUSE_SETXATTR_ACL_KILL_SGID + * + * 7.34 + * - add FUSE_SYNCFS */ #ifndef _LINUX_FUSE_H @@ -212,7 +215,7 @@ #define FUSE_KERNEL_VERSION 7 /** Minor version number of this interface */ -#define FUSE_KERNEL_MINOR_VERSION 33 +#define FUSE_KERNEL_MINOR_VERSION 34 /** The node ID of the root inode */ #define FUSE_ROOT_ID 1 @@ -505,6 +508,7 @@ enum fuse_opcode { FUSE_COPY_FILE_RANGE = 47, FUSE_SETUPMAPPING = 48, FUSE_REMOVEMAPPING = 49, + FUSE_SYNCFS = 50, /* CUSE specific operations */ CUSE_INIT = 4096, @@ -967,4 +971,8 @@ struct fuse_removemapping_one { #define FUSE_REMOVEMAPPING_MAX_ENTRY \ (PAGE_SIZE / sizeof(struct fuse_removemapping_one)) +struct fuse_syncfs_in { + uint64_t padding; +}; + #endif /* _LINUX_FUSE_H */ diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index e709ae8235..ff6ccbc6ef 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -504,6 +504,12 @@ #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */ +#define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */ #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ diff --git a/include/standard-headers/linux/virtio_gpu.h b/include/standard-headers/linux/virtio_gpu.h index 1357e4774e..2da48d3d4c 100644 --- a/include/standard-headers/linux/virtio_gpu.h +++ b/include/standard-headers/linux/virtio_gpu.h @@ -59,6 +59,11 @@ * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */ #define VIRTIO_GPU_F_RESOURCE_BLOB 3 +/* + * VIRTIO_GPU_CMD_CREATE_CONTEXT with + * context_init and multiple timelines + */ +#define VIRTIO_GPU_F_CONTEXT_INIT 4 enum virtio_gpu_ctrl_type { VIRTIO_GPU_UNDEFINED = 0, @@ -122,14 +127,20 @@ enum virtio_gpu_shm_id { VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 }; -#define VIRTIO_GPU_FLAG_FENCE (1 << 0) +#define VIRTIO_GPU_FLAG_FENCE (1 << 0) +/* + * If the following flag is set, then ring_idx contains the index + * of the command ring that needs to used when creating the fence + */ +#define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1) struct virtio_gpu_ctrl_hdr { uint32_t type; uint32_t flags; uint64_t fence_id; uint32_t ctx_id; - uint32_t padding; + uint8_t ring_idx; + uint8_t padding[3]; }; /* data passed in the cursor vq */ @@ -269,10 +280,11 @@ struct virtio_gpu_resource_create_3d { }; /* VIRTIO_GPU_CMD_CTX_CREATE */ +#define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff struct virtio_gpu_ctx_create { struct virtio_gpu_ctrl_hdr hdr; uint32_t nlen; - uint32_t padding; + uint32_t context_init; char debug_name[64]; }; diff --git a/include/standard-headers/linux/virtio_ids.h b/include/standard-headers/linux/virtio_ids.h index 4fe842c3a3..80d76b75bc 100644 --- a/include/standard-headers/linux/virtio_ids.h +++ b/include/standard-headers/linux/virtio_ids.h @@ -54,7 +54,31 @@ #define VIRTIO_ID_SOUND 25 /* virtio sound */ #define VIRTIO_ID_FS 26 /* virtio filesystem */ #define VIRTIO_ID_PMEM 27 /* virtio pmem */ +#define VIRTIO_ID_RPMB 28 /* virtio rpmb */ #define VIRTIO_ID_MAC80211_HWSIM 29 /* virtio mac80211-hwsim */ +#define VIRTIO_ID_VIDEO_ENCODER 30 /* virtio video encoder */ +#define VIRTIO_ID_VIDEO_DECODER 31 /* virtio video decoder */ +#define VIRTIO_ID_SCMI 32 /* virtio SCMI */ +#define VIRTIO_ID_NITRO_SEC_MOD 33 /* virtio nitro secure module*/ +#define VIRTIO_ID_I2C_ADAPTER 34 /* virtio i2c adapter */ +#define VIRTIO_ID_WATCHDOG 35 /* virtio watchdog */ +#define VIRTIO_ID_CAN 36 /* virtio can */ +#define VIRTIO_ID_DMABUF 37 /* virtio dmabuf */ +#define VIRTIO_ID_PARAM_SERV 38 /* virtio parameter server */ +#define VIRTIO_ID_AUDIO_POLICY 39 /* virtio audio policy */ #define VIRTIO_ID_BT 40 /* virtio bluetooth */ +#define VIRTIO_ID_GPIO 41 /* virtio gpio */ + +/* + * Virtio Transitional IDs + */ + +#define VIRTIO_TRANS_ID_NET 1000 /* transitional virtio net */ +#define VIRTIO_TRANS_ID_BLOCK 1001 /* transitional virtio block */ +#define VIRTIO_TRANS_ID_BALLOON 1002 /* transitional virtio balloon */ +#define VIRTIO_TRANS_ID_CONSOLE 1003 /* transitional virtio console */ +#define VIRTIO_TRANS_ID_SCSI 1004 /* transitional virtio SCSI */ +#define VIRTIO_TRANS_ID_RNG 1005 /* transitional virtio rng */ +#define VIRTIO_TRANS_ID_9P 1009 /* transitional virtio 9p console */ #endif /* _LINUX_VIRTIO_IDS_H */ diff --git a/include/standard-headers/linux/virtio_vsock.h b/include/standard-headers/linux/virtio_vsock.h index 3a23488e42..467e751b17 100644 --- a/include/standard-headers/linux/virtio_vsock.h +++ b/include/standard-headers/linux/virtio_vsock.h @@ -97,7 +97,8 @@ enum virtio_vsock_shutdown { /* VIRTIO_VSOCK_OP_RW flags values */ enum virtio_vsock_rw { - VIRTIO_VSOCK_SEQ_EOR = 1, + VIRTIO_VSOCK_SEQ_EOM = 1, + VIRTIO_VSOCK_SEQ_EOR = 2, }; #endif /* _LINUX_VIRTIO_VSOCK_H */ diff --git a/include/sysemu/blockdev.h b/include/sysemu/blockdev.h index 32c2d6023c..a750f99b79 100644 --- a/include/sysemu/blockdev.h +++ b/include/sysemu/blockdev.h @@ -50,7 +50,6 @@ void drive_check_orphaned(void); DriveInfo *drive_get_by_index(BlockInterfaceType type, int index); int drive_get_max_bus(BlockInterfaceType type); int drive_get_max_devs(BlockInterfaceType type); -DriveInfo *drive_get_next(BlockInterfaceType type); QemuOpts *drive_def(const char *optstr); QemuOpts *drive_add(BlockInterfaceType type, int index, const char *file, diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 7b22aeb6ae..6eb39a088b 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -46,6 +46,8 @@ extern bool kvm_readonly_mem_allowed; extern bool kvm_direct_msi_allowed; extern bool kvm_ioeventfd_any_length_allowed; extern bool kvm_msi_use_devid; +extern bool kvm_has_guest_debug; +extern int kvm_sstep_flags; #define kvm_enabled() (kvm_allowed) /** @@ -167,6 +169,17 @@ extern bool kvm_msi_use_devid; */ #define kvm_msi_devid_required() (kvm_msi_use_devid) +/* + * Does KVM support guest debugging + */ +#define kvm_supports_guest_debug() (kvm_has_guest_debug) + +/* + * kvm_supported_sstep_flags + * Returns: SSTEP_* flags that KVM supports for guest debug + */ +#define kvm_get_supported_sstep_flags() (kvm_sstep_flags) + #else #define kvm_enabled() (0) @@ -184,6 +197,8 @@ extern bool kvm_msi_use_devid; #define kvm_direct_msi_enabled() (false) #define kvm_ioeventfd_any_length_enabled() (false) #define kvm_msi_devid_required() (false) +#define kvm_supports_guest_debug() (false) +#define kvm_get_supported_sstep_flags() (0) #endif /* CONFIG_KVM_IS_POSSIBLE */ diff --git a/linux-user/safe-syscall.h b/include/user/safe-syscall.h similarity index 83% rename from linux-user/safe-syscall.h rename to include/user/safe-syscall.h index aaa9ffc0e2..61a04e2b5a 100644 --- a/linux-user/safe-syscall.h +++ b/include/user/safe-syscall.h @@ -25,10 +25,10 @@ * * Call a system call if guest signal not pending. * This has the same API as the libc syscall() function, except that it - * may return -1 with errno == TARGET_ERESTARTSYS if a signal was pending. + * may return -1 with errno == QEMU_ERESTARTSYS if a signal was pending. * * Returns: the system call result, or -1 with an error code in errno - * (Errnos are host errnos; we rely on TARGET_ERESTARTSYS not clashing + * (Errnos are host errnos; we rely on QEMU_ERESTARTSYS not clashing * with any of the host errno values.) */ @@ -81,7 +81,7 @@ * which are only technically blocking (ie which we know in practice won't * stay in the host kernel indefinitely) it's OK to use libc if necessary. * You must be able to cope with backing out correctly if some safe_syscall - * you make in the implementation returns either -TARGET_ERESTARTSYS or + * you make in the implementation returns either -QEMU_ERESTARTSYS or * EINTR though.) * * block_signals() cannot be used for interruptible syscalls. @@ -94,7 +94,7 @@ * handler checks the interrupted host PC against the addresse of that * known section. If the PC is before or at the address of the syscall * instruction then we change the PC to point at a "return - * -TARGET_ERESTARTSYS" code path instead, and then exit the signal handler + * -QEMU_ERESTARTSYS" code path instead, and then exit the signal handler * (causing the safe_syscall() call to immediately return that value). * Then in the main.c loop if we see this magic return value we adjust * the guest PC to wind it back to before the system call, and invoke @@ -124,34 +124,17 @@ * need to check SA_RESTART flags in QEMU or distinguish the various * kinds of restartability. */ -#ifdef HAVE_SAFE_SYSCALL + /* The core part of this function is implemented in assembly */ extern long safe_syscall_base(int *pending, long number, ...); +extern long safe_syscall_set_errno_tail(int value); + /* These are defined by the safe-syscall.inc.S file */ extern char safe_syscall_start[]; extern char safe_syscall_end[]; -#define safe_syscall(...) \ - ({ \ - long ret_; \ - int *psp_ = &((TaskState *)thread_cpu->opaque)->signal_pending; \ - ret_ = safe_syscall_base(psp_, __VA_ARGS__); \ - if (is_error(ret_)) { \ - errno = -ret_; \ - ret_ = -1; \ - } \ - ret_; \ - }) - -#else - -/* - * Fallback for architectures which don't yet provide a safe-syscall assembly - * fragment; note that this is racy! - * This should go away when all host architectures have been updated. - */ -#define safe_syscall syscall - -#endif +#define safe_syscall(...) \ + safe_syscall_base(&((TaskState *)thread_cpu->opaque)->signal_pending, \ + __VA_ARGS__) #endif diff --git a/linux-headers/asm-arm64/unistd.h b/linux-headers/asm-arm64/unistd.h index f83a70e07d..ce2ee8f1e3 100644 --- a/linux-headers/asm-arm64/unistd.h +++ b/linux-headers/asm-arm64/unistd.h @@ -20,5 +20,6 @@ #define __ARCH_WANT_SET_GET_RLIMIT #define __ARCH_WANT_TIME32_SYSCALLS #define __ARCH_WANT_SYS_CLONE3 +#define __ARCH_WANT_MEMFD_SECRET #include diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h index f211961ce1..4557a8b608 100644 --- a/linux-headers/asm-generic/unistd.h +++ b/linux-headers/asm-generic/unistd.h @@ -673,15 +673,15 @@ __SYSCALL(__NR_madvise, sys_madvise) #define __NR_remap_file_pages 234 __SYSCALL(__NR_remap_file_pages, sys_remap_file_pages) #define __NR_mbind 235 -__SC_COMP(__NR_mbind, sys_mbind, compat_sys_mbind) +__SYSCALL(__NR_mbind, sys_mbind) #define __NR_get_mempolicy 236 -__SC_COMP(__NR_get_mempolicy, sys_get_mempolicy, compat_sys_get_mempolicy) +__SYSCALL(__NR_get_mempolicy, sys_get_mempolicy) #define __NR_set_mempolicy 237 -__SC_COMP(__NR_set_mempolicy, sys_set_mempolicy, compat_sys_set_mempolicy) +__SYSCALL(__NR_set_mempolicy, sys_set_mempolicy) #define __NR_migrate_pages 238 -__SC_COMP(__NR_migrate_pages, sys_migrate_pages, compat_sys_migrate_pages) +__SYSCALL(__NR_migrate_pages, sys_migrate_pages) #define __NR_move_pages 239 -__SC_COMP(__NR_move_pages, sys_move_pages, compat_sys_move_pages) +__SYSCALL(__NR_move_pages, sys_move_pages) #endif #define __NR_rt_tgsigqueueinfo 240 @@ -873,8 +873,18 @@ __SYSCALL(__NR_landlock_add_rule, sys_landlock_add_rule) #define __NR_landlock_restrict_self 446 __SYSCALL(__NR_landlock_restrict_self, sys_landlock_restrict_self) +#ifdef __ARCH_WANT_MEMFD_SECRET +#define __NR_memfd_secret 447 +__SYSCALL(__NR_memfd_secret, sys_memfd_secret) +#endif +#define __NR_process_mrelease 448 +__SYSCALL(__NR_process_mrelease, sys_process_mrelease) + +#define __NR_futex_waitv 449 +__SYSCALL(__NR_futex_waitv, sys_futex_waitv) + #undef __NR_syscalls -#define __NR_syscalls 447 +#define __NR_syscalls 450 /* * 32 bit systems traditionally used different diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h index 09cd297698..4b3e7ad1ec 100644 --- a/linux-headers/asm-mips/unistd_n32.h +++ b/linux-headers/asm-mips/unistd_n32.h @@ -376,5 +376,6 @@ #define __NR_landlock_create_ruleset (__NR_Linux + 444) #define __NR_landlock_add_rule (__NR_Linux + 445) #define __NR_landlock_restrict_self (__NR_Linux + 446) +#define __NR_process_mrelease (__NR_Linux + 448) #endif /* _ASM_UNISTD_N32_H */ diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h index 780e0cead6..488d9298d9 100644 --- a/linux-headers/asm-mips/unistd_n64.h +++ b/linux-headers/asm-mips/unistd_n64.h @@ -352,5 +352,6 @@ #define __NR_landlock_create_ruleset (__NR_Linux + 444) #define __NR_landlock_add_rule (__NR_Linux + 445) #define __NR_landlock_restrict_self (__NR_Linux + 446) +#define __NR_process_mrelease (__NR_Linux + 448) #endif /* _ASM_UNISTD_N64_H */ diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h index 06a2b3b55e..f47399870a 100644 --- a/linux-headers/asm-mips/unistd_o32.h +++ b/linux-headers/asm-mips/unistd_o32.h @@ -422,5 +422,6 @@ #define __NR_landlock_create_ruleset (__NR_Linux + 444) #define __NR_landlock_add_rule (__NR_Linux + 445) #define __NR_landlock_restrict_self (__NR_Linux + 446) +#define __NR_process_mrelease (__NR_Linux + 448) #endif /* _ASM_UNISTD_O32_H */ diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h index cd5a8a41b2..11d54696dc 100644 --- a/linux-headers/asm-powerpc/unistd_32.h +++ b/linux-headers/asm-powerpc/unistd_32.h @@ -429,6 +429,7 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h index 8458effa8d..cf740bab13 100644 --- a/linux-headers/asm-powerpc/unistd_64.h +++ b/linux-headers/asm-powerpc/unistd_64.h @@ -401,6 +401,7 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h index 0c3cd299e4..8f97d98128 100644 --- a/linux-headers/asm-s390/unistd_32.h +++ b/linux-headers/asm-s390/unistd_32.h @@ -419,5 +419,6 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_S390_UNISTD_32_H */ diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h index 8dfc08b5e6..021ffc30e6 100644 --- a/linux-headers/asm-s390/unistd_64.h +++ b/linux-headers/asm-s390/unistd_64.h @@ -367,5 +367,6 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_process_mrelease 448 #endif /* _ASM_S390_UNISTD_64_H */ diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index a6c327f8ad..5a776a08f7 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -295,6 +295,7 @@ struct kvm_debug_exit_arch { #define KVM_GUESTDBG_USE_HW_BP 0x00020000 #define KVM_GUESTDBG_INJECT_DB 0x00040000 #define KVM_GUESTDBG_INJECT_BP 0x00080000 +#define KVM_GUESTDBG_BLOCKIRQ 0x00100000 /* for KVM_SET_GUEST_DEBUG */ struct kvm_guest_debug_arch { @@ -503,4 +504,8 @@ struct kvm_pmu_event_filter { #define KVM_PMU_EVENT_ALLOW 0 #define KVM_PMU_EVENT_DENY 1 +/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */ +#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */ +#define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */ + #endif /* _ASM_X86_KVM_H */ diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h index 66e96c0c68..9c9ffe312b 100644 --- a/linux-headers/asm-x86/unistd_32.h +++ b/linux-headers/asm-x86/unistd_32.h @@ -437,6 +437,9 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_memfd_secret 447 +#define __NR_process_mrelease 448 +#define __NR_futex_waitv 449 #endif /* _ASM_UNISTD_32_H */ diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h index b8ff6f14ee..084f1eef9c 100644 --- a/linux-headers/asm-x86/unistd_64.h +++ b/linux-headers/asm-x86/unistd_64.h @@ -359,6 +359,9 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_memfd_secret 447 +#define __NR_process_mrelease 448 +#define __NR_futex_waitv 449 #endif /* _ASM_UNISTD_64_H */ diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h index 06a1097c15..a2441affc2 100644 --- a/linux-headers/asm-x86/unistd_x32.h +++ b/linux-headers/asm-x86/unistd_x32.h @@ -312,6 +312,9 @@ #define __NR_landlock_create_ruleset (__X32_SYSCALL_BIT + 444) #define __NR_landlock_add_rule (__X32_SYSCALL_BIT + 445) #define __NR_landlock_restrict_self (__X32_SYSCALL_BIT + 446) +#define __NR_memfd_secret (__X32_SYSCALL_BIT + 447) +#define __NR_process_mrelease (__X32_SYSCALL_BIT + 448) +#define __NR_futex_waitv (__X32_SYSCALL_BIT + 449) #define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512) #define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513) #define __NR_ioctl (__X32_SYSCALL_BIT + 514) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index bcaf66cc4d..02c5e7b7bb 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -269,6 +269,7 @@ struct kvm_xen_exit { #define KVM_EXIT_AP_RESET_HOLD 32 #define KVM_EXIT_X86_BUS_LOCK 33 #define KVM_EXIT_XEN 34 +#define KVM_EXIT_RISCV_SBI 35 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -397,13 +398,23 @@ struct kvm_run { * "ndata" is correct, that new fields are enumerated in "flags", * and that each flag enumerates fields that are 64-bit aligned * and sized (so that ndata+internal.data[] is valid/accurate). + * + * Space beyond the defined fields may be used to store arbitrary + * debug information relating to the emulation failure. It is + * accounted for in "ndata" but the format is unspecified and is + * not represented in "flags". Any such information is *not* ABI! */ struct { __u32 suberror; __u32 ndata; __u64 flags; - __u8 insn_size; - __u8 insn_bytes[15]; + union { + struct { + __u8 insn_size; + __u8 insn_bytes[15]; + }; + }; + /* Arbitrary debug data may follow. */ } emulation_failure; /* KVM_EXIT_OSI */ struct { @@ -469,6 +480,13 @@ struct kvm_run { } msr; /* KVM_EXIT_XEN */ struct kvm_xen_exit xen; + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; /* Fix the size of the union. */ char padding[256]; }; @@ -1223,11 +1241,16 @@ struct kvm_irqfd { /* Do not use 1, KVM_CHECK_EXTENSION returned it before we had flags. */ #define KVM_CLOCK_TSC_STABLE 2 +#define KVM_CLOCK_REALTIME (1 << 2) +#define KVM_CLOCK_HOST_TSC (1 << 3) struct kvm_clock_data { __u64 clock; __u32 flags; - __u32 pad[9]; + __u32 pad0; + __u64 realtime; + __u64 host_tsc; + __u32 pad[4]; }; /* For KVM_CAP_SW_TLB */ @@ -1965,7 +1988,9 @@ struct kvm_stats_header { #define KVM_STATS_TYPE_CUMULATIVE (0x0 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_INSTANT (0x1 << KVM_STATS_TYPE_SHIFT) #define KVM_STATS_TYPE_PEAK (0x2 << KVM_STATS_TYPE_SHIFT) -#define KVM_STATS_TYPE_MAX KVM_STATS_TYPE_PEAK +#define KVM_STATS_TYPE_LINEAR_HIST (0x3 << KVM_STATS_TYPE_SHIFT) +#define KVM_STATS_TYPE_LOG_HIST (0x4 << KVM_STATS_TYPE_SHIFT) +#define KVM_STATS_TYPE_MAX KVM_STATS_TYPE_LOG_HIST #define KVM_STATS_UNIT_SHIFT 4 #define KVM_STATS_UNIT_MASK (0xF << KVM_STATS_UNIT_SHIFT) @@ -1988,8 +2013,9 @@ struct kvm_stats_header { * @size: The number of data items for this stats. * Every data item is of type __u64. * @offset: The offset of the stats to the start of stat structure in - * struture kvm or kvm_vcpu. - * @unused: Unused field for future usage. Always 0 for now. + * structure kvm or kvm_vcpu. + * @bucket_size: A parameter value used for histogram stats. It is only used + * for linear histogram stats, specifying the size of the bucket; * @name: The name string for the stats. Its size is indicated by the * &kvm_stats_header->name_size. */ @@ -1998,7 +2024,7 @@ struct kvm_stats_desc { __s16 exponent; __u16 size; __u32 offset; - __u32 unused; + __u32 bucket_size; char name[]; }; diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 04add21180..aa948420b6 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -109,9 +109,9 @@ void cpu_loop(CPUARMState *env) env->xregs[4], env->xregs[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->xregs[0] = ret; } break; @@ -123,27 +123,35 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ ec = syn_get_ec(env->exception.syndrome); - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); - - /* Both EC have the same format for FSC, or close enough. */ - fsc = extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MAPERR; + switch (ec) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + fsc = extract32(env->exception.syndrome, 0, 6); + switch (fsc) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo = TARGET_SIGSEGV; + si_code = TARGET_SEGV_MTESERR; + break; + case 0x21: /* Alignment fault */ + si_signo = TARGET_SIGBUS; + si_code = TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_signo = TARGET_SIGSEGV; - si_code = TARGET_SEGV_MTESERR; - break; - case 0x21: /* Alignment fault */ + case EC_PCALIGNMENT: si_signo = TARGET_SIGBUS; si_code = TARGET_BUS_ADRALN; break; diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 29c52db3f1..df9e39a4ba 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -556,12 +556,12 @@ long do_rt_sigreturn(CPUARMState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_sigreturn(CPUARMState *env) diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 4029849d5c..37c33f0ccd 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -98,11 +98,11 @@ void cpu_loop(CPUAlphaState *env) env->ir[IR_A2], env->ir[IR_A3], env->ir[IR_A4], env->ir[IR_A5], 0, 0); - if (sysret == -TARGET_ERESTARTSYS) { + if (sysret == -QEMU_ERESTARTSYS) { env->pc -= 4; break; } - if (sysret == -TARGET_QEMU_ESIGRETURN) { + if (sysret == -QEMU_ESIGRETURN) { break; } /* Syscall writes 0 to V0 to bypass error check, similar diff --git a/linux-user/alpha/signal.c b/linux-user/alpha/signal.c index bbe3dd175a..4ec42994d4 100644 --- a/linux-user/alpha/signal.c +++ b/linux-user/alpha/signal.c @@ -225,11 +225,11 @@ long do_sigreturn(CPUAlphaState *env) restore_sigcontext(env, sc); unlock_user_struct(sc, sc_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUAlphaState *env) @@ -249,13 +249,13 @@ long do_rt_sigreturn(CPUAlphaState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 963137e7d2..e087cb4032 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -417,9 +417,9 @@ void cpu_loop(CPUARMState *env) env->regs[4], env->regs[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->regs[15] -= env->thumb ? 2 : 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[0] = ret; } } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index df9f8e8eb2..cf99fd7b8a 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -511,12 +511,12 @@ long do_sigreturn(CPUARMState *env) } unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUARMState *env) @@ -546,12 +546,12 @@ long do_rt_sigreturn(CPUARMState *env) } unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } /* diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h index 8828af28a4..dc0042e4de 100644 --- a/linux-user/cpu_loop-common.h +++ b/linux-user/cpu_loop-common.h @@ -21,6 +21,7 @@ #define CPU_LOOP_COMMON_H #include "exec/log.h" +#include "special-errno.h" #define EXCP_DUMP(env, fmt, ...) \ do { \ diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index 0d5d268609..5213aebf55 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -50,9 +50,9 @@ void cpu_loop(CPUCRISState *env) env->pregs[7], env->pregs[11], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[10] = ret; } break; diff --git a/linux-user/cris/signal.c b/linux-user/cris/signal.c index 7f6aca934e..4f532b2903 100644 --- a/linux-user/cris/signal.c +++ b/linux-user/cris/signal.c @@ -177,10 +177,10 @@ long do_sigreturn(CPUCRISState *env) restore_sigcontext(&frame->sc, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUCRISState *env) diff --git a/linux-user/generic/target_errno_defs.h b/linux-user/generic/target_errno_defs.h index 17d85e0b61..c2f9d403e7 100644 --- a/linux-user/generic/target_errno_defs.h +++ b/linux-user/generic/target_errno_defs.h @@ -147,21 +147,4 @@ #define TARGET_ERFKILL 132 /* Operation not possible due to RF-kill */ #define TARGET_EHWPOISON 133 /* Memory page has hardware error */ -/* QEMU internal, not visible to the guest. This is returned when a - * system call should be restarted, to tell the main loop that it - * should wind the guest PC backwards so it will re-execute the syscall - * after handling any pending signals. They match with the ones the guest - * kernel uses for the same purpose. - */ -#define TARGET_ERESTARTSYS 512 /* Restart system call (if SA_RESTART) */ - -/* QEMU internal, not visible to the guest. This is returned by the - * do_sigreturn() code after a successful sigreturn syscall, to indicate - * that it has correctly set the guest registers and so the main loop - * should not touch them. We use the value the guest would use for - * ERESTART_NOINTR (which is kernel internal) to guarantee that we won't - * clash with a valid guest errno now or in the future. - */ -#define TARGET_QEMU_ESIGRETURN 513 /* Return from signal */ - #endif diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 6b24cbaba9..0d73934d31 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" +#include "qemu-common.h" #include "qemu.h" #include "user-internals.h" #include "cpu_loop-common.h" @@ -54,9 +55,9 @@ void cpu_loop(CPUHexagonState *env) env->gpr[4], env->gpr[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->gpr[HEX_REG_PC] -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->gpr[0] = ret; } break; diff --git a/linux-user/hexagon/signal.c b/linux-user/hexagon/signal.c index 74e61739a0..ad4e3822d5 100644 --- a/linux-user/hexagon/signal.c +++ b/linux-user/hexagon/signal.c @@ -268,7 +268,7 @@ long do_rt_sigreturn(CPUHexagonState *env) target_restore_altstack(&frame->uc.uc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); diff --git a/linux-user/host/aarch64/hostdep.h b/linux-user/host/aarch64/hostdep.h deleted file mode 100644 index 39299d798a..0000000000 --- a/linux-user/host/aarch64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef AARCH64_HOSTDEP_H -#define AARCH64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/aarch64/safe-syscall.inc.S b/linux-user/host/aarch64/safe-syscall.inc.S deleted file mode 100644 index bc1f5a9792..0000000000 --- a/linux-user/host/aarch64/safe-syscall.inc.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, #function - .type safe_syscall_start, #function - .type safe_syscall_end, #function - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ -safe_syscall_base: - .cfi_startproc - /* The syscall calling convention isn't the same as the - * C one: - * we enter with x0 == *signal_pending - * x1 == syscall number - * x2 ... x7, (stack) == syscall arguments - * and return the result in x0 - * and the syscall instruction needs - * x8 == syscall number - * x0 ... x6 == syscall arguments - * and returns the result in x0 - * Shuffle everything around appropriately. - */ - mov x9, x0 /* signal_pending pointer */ - mov x8, x1 /* syscall number */ - mov x0, x2 /* syscall arguments */ - mov x1, x3 - mov x2, x4 - mov x3, x5 - mov x4, x6 - mov x5, x7 - ldr x6, [sp] - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - ldr w10, [x9] - cbnz w10, 0f - svc 0x0 -safe_syscall_end: - /* code path for having successfully executed the syscall */ - ret - -0: - /* code path when we didn't execute the syscall */ - mov x0, #-TARGET_ERESTARTSYS - ret - .cfi_endproc - - .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/arm/hostdep.h b/linux-user/host/arm/hostdep.h deleted file mode 100644 index 86b137875a..0000000000 --- a/linux-user/host/arm/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef ARM_HOSTDEP_H -#define ARM_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/arm/safe-syscall.inc.S b/linux-user/host/arm/safe-syscall.inc.S deleted file mode 100644 index 88c4958504..0000000000 --- a/linux-user/host/arm/safe-syscall.inc.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, %function - - .cfi_sections .debug_frame - - .text - .syntax unified - .arm - .align 2 - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ -safe_syscall_base: - .fnstart - .cfi_startproc - mov r12, sp /* save entry stack */ - push { r4, r5, r6, r7, r8, lr } - .save { r4, r5, r6, r7, r8, lr } - .cfi_adjust_cfa_offset 24 - .cfi_rel_offset r4, 0 - .cfi_rel_offset r5, 4 - .cfi_rel_offset r6, 8 - .cfi_rel_offset r7, 12 - .cfi_rel_offset r8, 16 - .cfi_rel_offset lr, 20 - - /* The syscall calling convention isn't the same as the C one: - * we enter with r0 == *signal_pending - * r1 == syscall number - * r2, r3, [sp+0] ... [sp+12] == syscall arguments - * and return the result in r0 - * and the syscall instruction needs - * r7 == syscall number - * r0 ... r6 == syscall arguments - * and returns the result in r0 - * Shuffle everything around appropriately. - * Note the 16 bytes that we pushed to save registers. - */ - mov r8, r0 /* copy signal_pending */ - mov r7, r1 /* syscall number */ - mov r0, r2 /* syscall args */ - mov r1, r3 - ldm r12, { r2, r3, r4, r5, r6 } - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - ldr r12, [r8] /* signal_pending */ - tst r12, r12 - bne 1f - swi 0 -safe_syscall_end: - /* code path for having successfully executed the syscall */ - pop { r4, r5, r6, r7, r8, pc } - -1: - /* code path when we didn't execute the syscall */ - ldr r0, =-TARGET_ERESTARTSYS - pop { r4, r5, r6, r7, r8, pc } - .fnend - .cfi_endproc - - .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/i386/hostdep.h b/linux-user/host/i386/hostdep.h deleted file mode 100644 index ce7136501f..0000000000 --- a/linux-user/host/i386/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef I386_HOSTDEP_H -#define I386_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/i386/safe-syscall.inc.S b/linux-user/host/i386/safe-syscall.inc.S deleted file mode 100644 index 9e58fc6504..0000000000 --- a/linux-user/host/i386/safe-syscall.inc.S +++ /dev/null @@ -1,100 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ -safe_syscall_base: - .cfi_startproc - push %ebp - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset ebp, 0 - push %esi - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset esi, 0 - push %edi - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset edi, 0 - push %ebx - .cfi_adjust_cfa_offset 4 - .cfi_rel_offset ebx, 0 - - /* The syscall calling convention isn't the same as the C one: - * we enter with 0(%esp) == return address - * 4(%esp) == *signal_pending - * 8(%esp) == syscall number - * 12(%esp) ... 32(%esp) == syscall arguments - * and return the result in eax - * and the syscall instruction needs - * eax == syscall number - * ebx, ecx, edx, esi, edi, ebp == syscall arguments - * and returns the result in eax - * Shuffle everything around appropriately. - * Note the 16 bytes that we pushed to save registers. - */ - mov 12+16(%esp), %ebx /* the syscall arguments */ - mov 16+16(%esp), %ecx - mov 20+16(%esp), %edx - mov 24+16(%esp), %esi - mov 28+16(%esp), %edi - mov 32+16(%esp), %ebp - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - mov 4+16(%esp), %eax /* signal_pending */ - cmpl $0, (%eax) - jnz 1f - mov 8+16(%esp), %eax /* syscall number */ - int $0x80 -safe_syscall_end: - /* code path for having successfully executed the syscall */ - pop %ebx - .cfi_remember_state - .cfi_adjust_cfa_offset -4 - .cfi_restore ebx - pop %edi - .cfi_adjust_cfa_offset -4 - .cfi_restore edi - pop %esi - .cfi_adjust_cfa_offset -4 - .cfi_restore esi - pop %ebp - .cfi_adjust_cfa_offset -4 - .cfi_restore ebp - ret - -1: - /* code path when we didn't execute the syscall */ - .cfi_restore_state - mov $-TARGET_ERESTARTSYS, %eax - jmp safe_syscall_end - .cfi_endproc - - .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/ia64/hostdep.h b/linux-user/host/ia64/hostdep.h deleted file mode 100644 index 263bf7658e..0000000000 --- a/linux-user/host/ia64/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef IA64_HOSTDEP_H -#define IA64_HOSTDEP_H - -#endif diff --git a/linux-user/host/mips/hostdep.h b/linux-user/host/mips/hostdep.h deleted file mode 100644 index ba111d75c3..0000000000 --- a/linux-user/host/mips/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef MIPS_HOSTDEP_H -#define MIPS_HOSTDEP_H - -#endif diff --git a/linux-user/host/ppc/hostdep.h b/linux-user/host/ppc/hostdep.h deleted file mode 100644 index 23d8bd9d47..0000000000 --- a/linux-user/host/ppc/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef PPC_HOSTDEP_H -#define PPC_HOSTDEP_H - -#endif diff --git a/linux-user/host/ppc64/hostdep.h b/linux-user/host/ppc64/hostdep.h deleted file mode 100644 index 0c290dd904..0000000000 --- a/linux-user/host/ppc64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef PPC64_HOSTDEP_H -#define PPC64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/ppc64/safe-syscall.inc.S b/linux-user/host/ppc64/safe-syscall.inc.S deleted file mode 100644 index 875133173b..0000000000 --- a/linux-user/host/ppc64/safe-syscall.inc.S +++ /dev/null @@ -1,96 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - - .text - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ -#if _CALL_ELF == 2 -safe_syscall_base: - .cfi_startproc - .localentry safe_syscall_base,0 -#else - .section ".opd","aw" - .align 3 -safe_syscall_base: - .quad .L.safe_syscall_base,.TOC.@tocbase,0 - .previous -.L.safe_syscall_base: - .cfi_startproc -#endif - /* We enter with r3 == *signal_pending - * r4 == syscall number - * r5 ... r10 == syscall arguments - * and return the result in r3 - * and the syscall instruction needs - * r0 == syscall number - * r3 ... r8 == syscall arguments - * and returns the result in r3 - * Shuffle everything around appropriately. - */ - std 14, 16(1) /* Preserve r14 in SP+16 */ - .cfi_offset 14, 16 - mr 14, 3 /* signal_pending */ - mr 0, 4 /* syscall number */ - mr 3, 5 /* syscall arguments */ - mr 4, 6 - mr 5, 7 - mr 6, 8 - mr 7, 9 - mr 8, 10 - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - lwz 12, 0(14) - cmpwi 0, 12, 0 - bne- 0f - sc -safe_syscall_end: - /* code path when we did execute the syscall */ - ld 14, 16(1) /* restore r14 to its original value */ - bnslr+ - - /* syscall failed; return negative errno */ - neg 3, 3 - blr - - /* code path when we didn't execute the syscall */ -0: addi 3, 0, -TARGET_ERESTARTSYS - ld 14, 16(1) /* restore r14 to its original value */ - blr - .cfi_endproc - -#if _CALL_ELF == 2 - .size safe_syscall_base, .-safe_syscall_base -#else - .size safe_syscall_base, .-.L.safe_syscall_base - .size .L.safe_syscall_base, .-.L.safe_syscall_base -#endif diff --git a/linux-user/host/riscv/hostdep.h b/linux-user/host/riscv/hostdep.h deleted file mode 100644 index 7f67c22868..0000000000 --- a/linux-user/host/riscv/hostdep.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef RISCV_HOSTDEP_H -#define RISCV_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/riscv/safe-syscall.inc.S b/linux-user/host/riscv/safe-syscall.inc.S deleted file mode 100644 index 9ca3fbfd1e..0000000000 --- a/linux-user/host/riscv/safe-syscall.inc.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2018 Linaro, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - .type safe_syscall_start, @function - .type safe_syscall_end, @function - - /* - * This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ -safe_syscall_base: - .cfi_startproc - /* - * The syscall calling convention is nearly the same as C: - * we enter with a0 == *signal_pending - * a1 == syscall number - * a2 ... a7 == syscall arguments - * and return the result in a0 - * and the syscall instruction needs - * a7 == syscall number - * a0 ... a5 == syscall arguments - * and returns the result in a0 - * Shuffle everything around appropriately. - */ - mv t0, a0 /* signal_pending pointer */ - mv t1, a1 /* syscall number */ - mv a0, a2 /* syscall arguments */ - mv a1, a3 - mv a2, a4 - mv a3, a5 - mv a4, a6 - mv a5, a7 - mv a7, t1 - - /* - * This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* If signal_pending is non-zero, don't do the call */ - lw t1, 0(t0) - bnez t1, 0f - scall -safe_syscall_end: - /* code path for having successfully executed the syscall */ - ret - -0: - /* code path when we didn't execute the syscall */ - li a0, -TARGET_ERESTARTSYS - ret - .cfi_endproc - - .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/s390/hostdep.h b/linux-user/host/s390/hostdep.h deleted file mode 100644 index afcba5a16a..0000000000 --- a/linux-user/host/s390/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef S390_HOSTDEP_H -#define S390_HOSTDEP_H - -#endif diff --git a/linux-user/host/s390x/hostdep.h b/linux-user/host/s390x/hostdep.h deleted file mode 100644 index d801145854..0000000000 --- a/linux-user/host/s390x/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef S390X_HOSTDEP_H -#define S390X_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/host/s390x/safe-syscall.inc.S b/linux-user/host/s390x/safe-syscall.inc.S deleted file mode 100644 index 414b44ad38..0000000000 --- a/linux-user/host/s390x/safe-syscall.inc.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * safe-syscall.inc.S : host-specific assembly fragment - * to handle signals occurring at the same time as system calls. - * This is intended to be included by linux-user/safe-syscall.S - * - * Written by Richard Henderson - * Copyright (C) 2016 Red Hat, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - - .global safe_syscall_base - .global safe_syscall_start - .global safe_syscall_end - .type safe_syscall_base, @function - - /* This is the entry point for making a system call. The calling - * convention here is that of a C varargs function with the - * first argument an 'int *' to the signal_pending flag, the - * second one the system call number (as a 'long'), and all further - * arguments being syscall arguments (also 'long'). - * We return a long which is the syscall's return value, which - * may be negative-errno on failure. Conversion to the - * -1-and-errno-set convention is done by the calling wrapper. - */ -safe_syscall_base: - .cfi_startproc - stmg %r6,%r15,48(%r15) /* save all call-saved registers */ - .cfi_offset %r15,-40 - .cfi_offset %r14,-48 - .cfi_offset %r13,-56 - .cfi_offset %r12,-64 - .cfi_offset %r11,-72 - .cfi_offset %r10,-80 - .cfi_offset %r9,-88 - .cfi_offset %r8,-96 - .cfi_offset %r7,-104 - .cfi_offset %r6,-112 - lgr %r1,%r15 - lg %r0,8(%r15) /* load eos */ - aghi %r15,-160 - .cfi_adjust_cfa_offset 160 - stg %r1,0(%r15) /* store back chain */ - stg %r0,8(%r15) /* store eos */ - - /* The syscall calling convention isn't the same as the - * C one: - * we enter with r2 == *signal_pending - * r3 == syscall number - * r4, r5, r6, (stack) == syscall arguments - * and return the result in r2 - * and the syscall instruction needs - * r1 == syscall number - * r2 ... r7 == syscall arguments - * and returns the result in r2 - * Shuffle everything around appropriately. - */ - lgr %r8,%r2 /* signal_pending pointer */ - lgr %r1,%r3 /* syscall number */ - lgr %r2,%r4 /* syscall args */ - lgr %r3,%r5 - lgr %r4,%r6 - lmg %r5,%r7,320(%r15) - - /* This next sequence of code works in conjunction with the - * rewind_if_safe_syscall_function(). If a signal is taken - * and the interrupted PC is anywhere between 'safe_syscall_start' - * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. - * The code sequence must therefore be able to cope with this, and - * the syscall instruction must be the final one in the sequence. - */ -safe_syscall_start: - /* if signal_pending is non-zero, don't do the call */ - icm %r0,15,0(%r8) - jne 2f - svc 0 -safe_syscall_end: - -1: lg %r15,0(%r15) /* load back chain */ - .cfi_remember_state - .cfi_adjust_cfa_offset -160 - lmg %r6,%r15,48(%r15) /* load saved registers */ - br %r14 - .cfi_restore_state -2: lghi %r2, -TARGET_ERESTARTSYS - j 1b - .cfi_endproc - - .size safe_syscall_base, .-safe_syscall_base diff --git a/linux-user/host/sparc/hostdep.h b/linux-user/host/sparc/hostdep.h deleted file mode 100644 index 391ad923cf..0000000000 --- a/linux-user/host/sparc/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef SPARC_HOSTDEP_H -#define SPARC_HOSTDEP_H - -#endif diff --git a/linux-user/host/sparc64/hostdep.h b/linux-user/host/sparc64/hostdep.h deleted file mode 100644 index ce3968fca0..0000000000 --- a/linux-user/host/sparc64/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef SPARC64_HOSTDEP_H -#define SPARC64_HOSTDEP_H - -#endif diff --git a/linux-user/host/x32/hostdep.h b/linux-user/host/x32/hostdep.h deleted file mode 100644 index 2c2d6d37da..0000000000 --- a/linux-user/host/x32/hostdep.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef X32_HOSTDEP_H -#define X32_HOSTDEP_H - -#endif diff --git a/linux-user/host/x86_64/hostdep.h b/linux-user/host/x86_64/hostdep.h deleted file mode 100644 index 9c62bd26bd..0000000000 --- a/linux-user/host/x86_64/hostdep.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * hostdep.h : things which are dependent on the host architecture - * - * * Written by Peter Maydell - * - * Copyright (C) 2016 Linaro Limited - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef X86_64_HOSTDEP_H -#define X86_64_HOSTDEP_H - -/* We have a safe-syscall.inc.S */ -#define HAVE_SAFE_SYSCALL - -#endif diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 375576c8f0..a47a63176b 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -133,8 +133,8 @@ void cpu_loop(CPUHPPAState *env) env->iaoq_f = env->gr[31]; env->iaoq_b = env->gr[31] + 4; break; - case -TARGET_ERESTARTSYS: - case -TARGET_QEMU_ESIGRETURN: + case -QEMU_ERESTARTSYS: + case -QEMU_ESIGRETURN: break; } break; diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index c2fbc26ebb..962f551c04 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -191,9 +191,9 @@ long do_rt_sigreturn(CPUArchState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index b399e646e3..95fe7f6eb7 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -180,8 +180,8 @@ static void emulate_vsyscall(CPUX86State *env) ret = do_syscall(env, syscall, env->regs[R_EDI], env->regs[R_ESI], env->regs[R_EDX], env->regs[10], env->regs[8], env->regs[9], 0, 0); - g_assert(ret != -TARGET_ERESTARTSYS); - g_assert(ret != -TARGET_QEMU_ESIGRETURN); + g_assert(ret != -QEMU_ERESTARTSYS); + g_assert(ret != -QEMU_ESIGRETURN); if (ret == -TARGET_EFAULT) { goto sigsegv; } @@ -233,9 +233,9 @@ void cpu_loop(CPUX86State *env) env->regs[R_EDI], env->regs[R_EBP], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->eip -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[R_EAX] = ret; } break; @@ -251,9 +251,9 @@ void cpu_loop(CPUX86State *env) env->regs[8], env->regs[9], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->eip -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[R_EAX] = ret; } break; diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 433efa3d69..4372621a4d 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -559,12 +559,12 @@ long do_sigreturn(CPUX86State *env) if (restore_sigcontext(env, &frame->sc)) goto badframe; unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #endif @@ -588,12 +588,12 @@ long do_rt_sigreturn(CPUX86State *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #ifndef TARGET_X86_64 diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 790bd558c3..3181594414 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -80,9 +80,9 @@ void cpu_loop(CPUM68KState *env) env->dregs[5], env->aregs[0], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->dregs[0] = ret; } } diff --git a/linux-user/m68k/signal.c b/linux-user/m68k/signal.c index ec33482e14..5f35354487 100644 --- a/linux-user/m68k/signal.c +++ b/linux-user/m68k/signal.c @@ -353,11 +353,11 @@ long do_sigreturn(CPUM68KState *env) restore_sigcontext(env, &frame->sc); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUM68KState *env) @@ -381,12 +381,12 @@ long do_rt_sigreturn(CPUM68KState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/meson.build b/linux-user/meson.build index bf62c13e37..b2f4afd5e7 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -2,6 +2,11 @@ if not have_linux_user subdir_done() endif +linux_user_ss = ss.source_set() + +common_user_inc += include_directories('host/' / host_arch) +common_user_inc += include_directories('.') + linux_user_ss.add(files( 'elfload.c', 'exit.c', @@ -9,10 +14,10 @@ linux_user_ss.add(files( 'linuxload.c', 'main.c', 'mmap.c', - 'safe-syscall.S', 'signal.c', 'strace.c', 'syscall.c', + 'thunk.c', 'uaccess.c', 'uname.c', )) @@ -39,3 +44,5 @@ subdir('sh4') subdir('sparc') subdir('x86_64') subdir('xtensa') + +specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index a94467dd2d..ff1fb26c8b 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -53,10 +53,10 @@ void cpu_loop(CPUMBState *env) env->regs[9], env->regs[10], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { /* Wind back to before the syscall. */ env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[3] = ret; } /* All syscall exits result in guest r14 being equal to the diff --git a/linux-user/microblaze/signal.c b/linux-user/microblaze/signal.c index 8ebb6a1b7d..5188d74025 100644 --- a/linux-user/microblaze/signal.c +++ b/linux-user/microblaze/signal.c @@ -207,12 +207,12 @@ long do_rt_sigreturn(CPUMBState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index b735c99a24..32f9fc1c1c 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -141,11 +141,11 @@ done_syscall: env->active_tc.gpr[8], env->active_tc.gpr[9], env->active_tc.gpr[10], env->active_tc.gpr[11]); # endif /* O32 */ - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->active_tc.PC -= 4; break; } - if (ret == -TARGET_QEMU_ESIGRETURN) { + if (ret == -QEMU_ESIGRETURN) { /* Returning from a successful sigreturn syscall. Avoid clobbering register state. */ break; diff --git a/linux-user/mips/signal.c b/linux-user/mips/signal.c index 8f79e405ec..58a9d7a8a3 100644 --- a/linux-user/mips/signal.c +++ b/linux-user/mips/signal.c @@ -281,11 +281,11 @@ long do_sigreturn(CPUMIPSState *regs) /* I am not sure this is right, but it seems to work * maybe a problem with nested signals ? */ regs->CP0_EPC = 0; - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } # endif /* O32 */ @@ -371,11 +371,11 @@ long do_rt_sigreturn(CPUMIPSState *env) /* I am not sure this is right, but it seems to work * maybe a problem with nested signals ? */ env->CP0_EPC = 0; - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index 3cfdbbf037..592901a68b 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -48,9 +48,9 @@ void cpu_loop(CPUOpenRISCState *env) cpu_get_gpr(env, 6), cpu_get_gpr(env, 7), cpu_get_gpr(env, 8), 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { cpu_set_gpr(env, 11, ret); } break; diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 483e669300..30c82f2354 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -428,11 +428,11 @@ void cpu_loop(CPUPPCState *env) ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6], env->gpr[7], env->gpr[8], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->nip -= 4; break; } - if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) { + if (ret == (target_ulong)(-QEMU_ESIGRETURN)) { /* Returning from a successful sigreturn syscall. Avoid corrupting register state. */ break; diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index 90a0369632..176c9d8503 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -591,13 +591,13 @@ long do_sigreturn(CPUPPCState *env) unlock_user_struct(sr, sr_addr, 1); unlock_user_struct(sc, sc_addr, 1); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; sigsegv: unlock_user_struct(sr, sr_addr, 1); unlock_user_struct(sc, sc_addr, 1); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #endif /* !defined(TARGET_PPC64) */ @@ -646,12 +646,12 @@ long do_rt_sigreturn(CPUPPCState *env) target_restore_altstack(&rt_sf->uc.tuc_stack, env); unlock_user_struct(rt_sf, rt_sf_addr, 1); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; sigsegv: unlock_user_struct(rt_sf, rt_sf_addr, 1); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } /* This syscall implements {get,set,swap}context for userland. */ @@ -704,7 +704,7 @@ abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx, /* We cannot return to a partially updated context. */ force_sig(TARGET_SIGSEGV); } - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } return 0; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index b301dac802..0cd8985cb8 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -69,9 +69,9 @@ void cpu_loop(CPURISCVState *env) env->gpr[xA5], 0, 0); } - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 4; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->gpr[xA0] = ret; } if (cs->singlestep_enabled) { diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index a0f9542ce3..296e39fbf0 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -188,7 +188,7 @@ long do_rt_sigreturn(CPURISCVState *env) target_restore_altstack(&frame->uc.uc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); diff --git a/linux-user/riscv/target_syscall.h b/linux-user/riscv/target_syscall.h index dc597c8972..9b13161324 100644 --- a/linux-user/riscv/target_syscall.h +++ b/linux-user/riscv/target_syscall.h @@ -45,10 +45,11 @@ struct target_pt_regs { #ifdef TARGET_RISCV32 #define UNAME_MACHINE "riscv32" +#define UNAME_MINIMUM_RELEASE "5.4.0" #else #define UNAME_MACHINE "riscv64" -#endif #define UNAME_MINIMUM_RELEASE "4.15.0" +#endif #define TARGET_MINSIGSTKSZ 2048 #define TARGET_MCL_CURRENT 1 diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index d089c8417e..ad0c3cd263 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -83,9 +83,9 @@ void cpu_loop(CPUS390XState *env) ret = do_syscall(env, n, env->regs[2], env->regs[3], env->regs[4], env->regs[5], env->regs[6], env->regs[7], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->psw.addr -= env->int_svc_ilen; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->regs[2] = ret; } break; diff --git a/linux-user/s390x/signal.c b/linux-user/s390x/signal.c index 676b948147..f47713e04a 100644 --- a/linux-user/s390x/signal.c +++ b/linux-user/s390x/signal.c @@ -359,7 +359,7 @@ long do_sigreturn(CPUS390XState *env) trace_user_do_sigreturn(env, frame_addr); if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } /* Make sure that we're initializing all of target_set. */ @@ -373,7 +373,7 @@ long do_sigreturn(CPUS390XState *env) restore_sigregs_ext(env, &frame->sregs_ext); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUS390XState *env) @@ -385,7 +385,7 @@ long do_rt_sigreturn(CPUS390XState *env) trace_user_do_rt_sigreturn(env, frame_addr); if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) { force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } target_to_host_sigset(&set, &frame->uc.tuc_sigmask); @@ -397,7 +397,7 @@ long do_rt_sigreturn(CPUS390XState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index ac9b01840c..3290f6445c 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -50,9 +50,9 @@ void cpu_loop(CPUSH4State *env) env->gregs[0], env->gregs[1], 0, 0); - if (ret == -TARGET_ERESTARTSYS) { + if (ret == -QEMU_ERESTARTSYS) { env->pc -= 2; - } else if (ret != -TARGET_QEMU_ESIGRETURN) { + } else if (ret != -QEMU_ESIGRETURN) { env->gregs[0] = ret; } break; diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c index faa869fb19..f6a18bc6b5 100644 --- a/linux-user/sh4/signal.c +++ b/linux-user/sh4/signal.c @@ -286,12 +286,12 @@ long do_sigreturn(CPUSH4State *regs) restore_sigcontext(regs, &frame->sc); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } long do_rt_sigreturn(CPUSH4State *regs) @@ -313,12 +313,12 @@ long do_rt_sigreturn(CPUSH4State *regs) target_restore_altstack(&frame->uc.tuc_stack, regs); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/linux-user/signal-common.h b/linux-user/signal-common.h index 7457f8025c..42aa479080 100644 --- a/linux-user/signal-common.h +++ b/linux-user/signal-common.h @@ -20,6 +20,8 @@ #ifndef SIGNAL_COMMON_H #define SIGNAL_COMMON_H +#include "special-errno.h" + /* Fallback addresses into sigtramp page. */ extern abi_ulong default_sigreturn; extern abi_ulong default_rt_sigreturn; @@ -76,7 +78,7 @@ abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx, * Block all signals, and arrange that the signal mask is returned to * its correct value for the guest before we resume execution of guest code. * If this function returns non-zero, then the caller should immediately - * return -TARGET_ERESTARTSYS to the main loop, which will take the pending + * return -QEMU_ERESTARTSYS to the main loop, which will take the pending * signal and restart execution of the syscall. * If block_signals() returns zero, then the caller can continue with * emulation of the system call knowing that no signals can be taken diff --git a/linux-user/signal.c b/linux-user/signal.c index 6d5e5b698c..510db73c34 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -31,7 +31,7 @@ #include "trace.h" #include "signal-common.h" #include "host-signal.h" -#include "safe-syscall.h" +#include "user/safe-syscall.h" static struct target_sigaction sigact_table[TARGET_NSIG]; @@ -213,7 +213,7 @@ int block_signals(void) /* Wrapper for sigprocmask function * Emulates a sigprocmask in a safe way for the guest. Note that set and oldset - * are host signal set, not guest ones. Returns -TARGET_ERESTARTSYS if + * are host signal set, not guest ones. Returns -QEMU_ERESTARTSYS if * a signal was already pending and the syscall must be restarted, or * 0 on success. * If set is NULL, this is guaranteed not to fail. @@ -230,7 +230,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset) int i; if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } switch (how) { @@ -798,7 +798,6 @@ int queue_signal(CPUArchState *env, int sig, int si_type, /* Adjust the signal context to rewind out of safe-syscall if we're in it */ static inline void rewind_if_in_safe_syscall(void *puc) { -#ifdef HAVE_SAFE_SYSCALL ucontext_t *uc = (ucontext_t *)puc; uintptr_t pcreg = host_signal_pc(uc); @@ -806,7 +805,6 @@ static inline void rewind_if_in_safe_syscall(void *puc) && pcreg < (uintptr_t)safe_syscall_end) { host_signal_set_pc(uc, (uintptr_t)safe_syscall_start); } -#endif } static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) @@ -987,7 +985,7 @@ int do_sigaction(int sig, const struct target_sigaction *act, } if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } k = &sigact_table[sig - 1]; diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 0ba65e431c..8765ab6020 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -181,7 +181,7 @@ void cpu_loop (CPUSPARCState *env) env->regwptr[2], env->regwptr[3], env->regwptr[4], env->regwptr[5], 0, 0); - if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) { + if (ret == -QEMU_ERESTARTSYS || ret == -QEMU_ESIGRETURN) { break; } if ((abi_ulong)ret >= (abi_ulong)(-515)) { diff --git a/linux-user/sparc/signal.c b/linux-user/sparc/signal.c index 23e1e761de..b501750fe0 100644 --- a/linux-user/sparc/signal.c +++ b/linux-user/sparc/signal.c @@ -431,12 +431,12 @@ long do_sigreturn(CPUSPARCState *env) set_sigmask(&host_set); unlock_user_struct(sf, sf_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; segv_and_exit: unlock_user_struct(sf, sf_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; #else return -TARGET_ENOSYS; #endif @@ -495,12 +495,12 @@ long do_rt_sigreturn(CPUSPARCState *env) env->npc = tnpc; unlock_user_struct(sf, sf_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; segv_and_exit: unlock_user_struct(sf, sf_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32) diff --git a/linux-user/special-errno.h b/linux-user/special-errno.h new file mode 100644 index 0000000000..4120455baa --- /dev/null +++ b/linux-user/special-errno.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU internal errno values for implementing user-only POSIX. + * + * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2021 Linaro, Ltd. + */ + +#ifndef SPECIAL_ERRNO_H +#define SPECIAL_ERRNO_H + +/* + * All of these are QEMU internal, not visible to the guest. + * They should be chosen so as to not overlap with any host + * or guest errno. + */ + +/* + * This is returned when a system call should be restarted, to tell the + * main loop that it should wind the guest PC backwards so it will + * re-execute the syscall after handling any pending signals. + */ +#define QEMU_ERESTARTSYS 512 + +/* + * This is returned after a successful sigreturn syscall, to indicate + * that it has correctly set the guest registers and so the main loop + * should not touch them. + */ +#define QEMU_ESIGRETURN 513 + +#endif /* SPECIAL_ERRNO_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 185b133983..ffa33d2fbf 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -132,10 +132,11 @@ #include "signal-common.h" #include "loader.h" #include "user-mmap.h" -#include "safe-syscall.h" +#include "user/safe-syscall.h" #include "qemu/guest-random.h" #include "qemu/selfmap.h" #include "user/syscall-trace.h" +#include "special-errno.h" #include "qapi/error.h" #include "fd-trans.h" #include "tcg/tcg.h" @@ -547,10 +548,10 @@ static inline abi_long get_errno(abi_long ret) const char *target_strerror(int err) { - if (err == TARGET_ERESTARTSYS) { + if (err == QEMU_ERESTARTSYS) { return "To be restarted"; } - if (err == TARGET_QEMU_ESIGRETURN) { + if (err == QEMU_ESIGRETURN) { return "Successful exit from sigreturn"; } @@ -6475,7 +6476,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, } if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } fork_start(); @@ -8345,7 +8346,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, Do thread termination if we have more then one thread. */ if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } pthread_mutex_lock(&clone_lock); @@ -9334,7 +9335,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, #endif ret = get_errno(safe_rt_sigsuspend(&ts->sigsuspend_mask, SIGSET_T_SIZE)); - if (ret != -TARGET_ERESTARTSYS) { + if (ret != -QEMU_ERESTARTSYS) { ts->in_sigsuspend = 1; } } @@ -9353,7 +9354,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, unlock_user(p, arg1, 0); ret = get_errno(safe_rt_sigsuspend(&ts->sigsuspend_mask, SIGSET_T_SIZE)); - if (ret != -TARGET_ERESTARTSYS) { + if (ret != -QEMU_ERESTARTSYS) { ts->in_sigsuspend = 1; } } @@ -9469,13 +9470,13 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, #ifdef TARGET_NR_sigreturn case TARGET_NR_sigreturn: if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } return do_sigreturn(cpu_env); #endif case TARGET_NR_rt_sigreturn: if (block_signals()) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } return do_rt_sigreturn(cpu_env); case TARGET_NR_sethostname: @@ -13220,7 +13221,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, static bool flag; flag = !flag; if (flag) { - return -TARGET_ERESTARTSYS; + return -QEMU_ERESTARTSYS; } } #endif diff --git a/thunk.c b/linux-user/thunk.c similarity index 100% rename from thunk.c rename to linux-user/thunk.c diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index 661612a088..f71f372829 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -18,7 +18,6 @@ #ifndef LINUX_USER_USER_INTERNALS_H #define LINUX_USER_USER_INTERNALS_H -#include "hostdep.h" #include "exec/user/thunk.h" #include "exec/exec-all.h" #include "qemu/log.h" diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index a83490ab35..6bc6d6dee6 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -184,11 +184,11 @@ void cpu_loop(CPUXtensaState *env) env->regs[2] = ret; break; - case -TARGET_ERESTARTSYS: + case -QEMU_ERESTARTSYS: env->pc -= 3; break; - case -TARGET_QEMU_ESIGRETURN: + case -QEMU_ESIGRETURN: break; } break; diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c index 81572a5fc7..06d91a37ec 100644 --- a/linux-user/xtensa/signal.c +++ b/linux-user/xtensa/signal.c @@ -263,12 +263,12 @@ long do_rt_sigreturn(CPUXtensaState *env) target_restore_altstack(&frame->uc.tuc_stack, env); unlock_user_struct(frame, frame_addr, 0); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; badframe: unlock_user_struct(frame, frame_addr, 0); force_sig(TARGET_SIGSEGV); - return -TARGET_QEMU_ESIGRETURN; + return -QEMU_ESIGRETURN; } void setup_sigtramp(abi_ulong sigtramp_page) diff --git a/meson.build b/meson.build index 32799ce312..4087a2cc91 100644 --- a/meson.build +++ b/meson.build @@ -67,6 +67,14 @@ endif targetos = host_machine.system() +if cpu not in supported_cpus + host_arch = 'unknown' +elif cpu == 'x86' + host_arch = 'i386' +else + host_arch = cpu +endif + if cpu in ['x86', 'x86_64'] kvm_targets = ['i386-softmmu', 'x86_64-softmmu'] elif cpu == 'aarch64' @@ -335,9 +343,9 @@ if targetos == 'netbsd' endif endif -tcg_arch = config_host['ARCH'] +tcg_arch = host_arch if not get_option('tcg').disabled() - if cpu not in supported_cpus + if host_arch == 'unknown' if get_option('tcg_interpreter') warning('Unsupported CPU @0@, will use TCG with TCI (slow)'.format(cpu)) else @@ -353,11 +361,11 @@ if not get_option('tcg').disabled() endif if get_option('tcg_interpreter') tcg_arch = 'tci' - elif config_host['ARCH'] == 'sparc64' + elif host_arch == 'sparc64' tcg_arch = 'sparc' - elif config_host['ARCH'] in ['x86_64', 'x32'] + elif host_arch == 'x86_64' tcg_arch = 'i386' - elif config_host['ARCH'] == 'ppc64' + elif host_arch == 'ppc64' tcg_arch = 'ppc' endif add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch, @@ -874,11 +882,15 @@ if not get_option('glusterfs').auto() or have_block ''', dependencies: glusterfs) endif endif + libssh = not_found -if 'CONFIG_LIBSSH' in config_host - libssh = declare_dependency(compile_args: config_host['LIBSSH_CFLAGS'].split(), - link_args: config_host['LIBSSH_LIBS'].split()) +if not get_option('libssh').auto() or have_block + libssh = dependency('libssh', version: '>=0.8.7', + method: 'pkg-config', + required: get_option('libssh'), + kwargs: static_kwargs) endif + libbzip2 = not_found if not get_option('bzip2').auto() or have_block libbzip2 = cc.find_library('bz2', has_headers: ['bzlib.h'], @@ -1422,6 +1434,8 @@ config_host_data.set_quoted('CONFIG_QEMU_LOCALSTATEDIR', get_option('prefix') / config_host_data.set_quoted('CONFIG_QEMU_MODDIR', get_option('prefix') / qemu_moddir) config_host_data.set_quoted('CONFIG_SYSCONFDIR', get_option('prefix') / get_option('sysconfdir')) +config_host_data.set('HOST_' + host_arch.to_upper(), 1) + config_host_data.set('CONFIG_ATTR', libattr.found()) config_host_data.set('CONFIG_BRLAPI', brlapi.found()) config_host_data.set('CONFIG_COCOA', cocoa.found()) @@ -1451,6 +1465,7 @@ config_host_data.set('CONFIG_EBPF', libbpf.found()) config_host_data.set('CONFIG_LIBDAXCTL', libdaxctl.found()) config_host_data.set('CONFIG_LIBISCSI', libiscsi.found()) config_host_data.set('CONFIG_LIBNFS', libnfs.found()) +config_host_data.set('CONFIG_LIBSSH', libssh.found()) config_host_data.set('CONFIG_LINUX_AIO', libaio.found()) config_host_data.set('CONFIG_LINUX_IO_URING', linux_io_uring.found()) config_host_data.set('CONFIG_LIBPMEM', libpmem.found()) @@ -1770,8 +1785,6 @@ foreach k, v: config_host v = '"' + '", "'.join(v.split()) + '", ' endif config_host_data.set(k, v) - elif k == 'ARCH' - config_host_data.set('HOST_' + v.to_upper(), 1) elif strings.contains(k) config_host_data.set_quoted(k, v) elif k.startswith('CONFIG_') @@ -1801,7 +1814,6 @@ disassemblers = { 'hppa' : ['CONFIG_HPPA_DIS'], 'i386' : ['CONFIG_I386_DIS'], 'x86_64' : ['CONFIG_I386_DIS'], - 'x32' : ['CONFIG_I386_DIS'], 'm68k' : ['CONFIG_M68K_DIS'], 'microblaze' : ['CONFIG_MICROBLAZE_DIS'], 'mips' : ['CONFIG_MIPS_DIS'], @@ -1915,7 +1927,7 @@ foreach target : target_dirs endif foreach k, v: disassemblers - if config_host['ARCH'].startswith(k) or config_target['TARGET_BASE_ARCH'].startswith(k) + if host_arch.startswith(k) or config_target['TARGET_BASE_ARCH'].startswith(k) foreach sym: v config_target += { sym: 'y' } config_all_disas += { sym: 'y' } @@ -2364,13 +2376,12 @@ genh += hxdep authz_ss = ss.source_set() blockdev_ss = ss.source_set() block_ss = ss.source_set() -bsd_user_ss = ss.source_set() chardev_ss = ss.source_set() common_ss = ss.source_set() +common_user_ss = ss.source_set() crypto_ss = ss.source_set() hwcore_ss = ss.source_set() io_ss = ss.source_set() -linux_user_ss = ss.source_set() qmp_ss = ss.source_set() qom_ss = ss.source_set() softmmu_ss = ss.source_set() @@ -2612,14 +2623,24 @@ subdir('tcg') subdir('fpu') subdir('accel') subdir('plugins') -subdir('bsd-user') -subdir('linux-user') subdir('ebpf') -specific_ss.add_all(when: 'CONFIG_BSD_USER', if_true: bsd_user_ss) +common_user_inc = [] -linux_user_ss.add(files('thunk.c')) -specific_ss.add_all(when: 'CONFIG_LINUX_USER', if_true: linux_user_ss) +subdir('common-user') +subdir('bsd-user') +subdir('linux-user') + +common_user_ss = common_user_ss.apply(config_all, strict: false) +common_user = static_library('common-user', + sources: common_user_ss.sources(), + dependencies: common_user_ss.dependencies(), + include_directories: common_user_inc, + name_suffix: 'fa', + build_by_default: false) +common_user = declare_dependency(link_with: common_user) + +user_ss.add(common_user) # needed for fuzzing binaries subdir('tests/qtest/libqos') @@ -2860,7 +2881,7 @@ emulators = {} foreach target : target_dirs config_target = config_target_mak[target] target_name = config_target['TARGET_NAME'] - arch = config_target['TARGET_BASE_ARCH'] + target_base_arch = config_target['TARGET_BASE_ARCH'] arch_srcs = [config_target_h[target]] arch_deps = [] c_args = ['-DNEED_CPU_H', @@ -2876,11 +2897,11 @@ foreach target : target_dirs if target.endswith('-softmmu') qemu_target_name = 'qemu-system-' + target_name target_type='system' - t = target_softmmu_arch[arch].apply(config_target, strict: false) + t = target_softmmu_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() - hw_dir = target_name == 'sparc64' ? 'sparc64' : arch + hw_dir = target_name == 'sparc64' ? 'sparc64' : target_base_arch hw = hw_arch[hw_dir].apply(config_target, strict: false) arch_srcs += hw.sources() arch_deps += hw.dependencies() @@ -2891,14 +2912,14 @@ foreach target : target_dirs abi = config_target['TARGET_ABI_DIR'] target_type='user' qemu_target_name = 'qemu-' + target_name - if arch in target_user_arch - t = target_user_arch[arch].apply(config_target, strict: false) + if target_base_arch in target_user_arch + t = target_user_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() endif if 'CONFIG_LINUX_USER' in config_target base_dir = 'linux-user' - target_inc += include_directories('linux-user/host/' / config_host['ARCH']) + target_inc += include_directories('linux-user/host/' / host_arch) endif if 'CONFIG_BSD_USER' in config_target base_dir = 'bsd-user' @@ -2930,7 +2951,7 @@ foreach target : target_dirs arch_srcs += gdbstub_xml endif - t = target_arch[arch].apply(config_target, strict: false) + t = target_arch[target_base_arch].apply(config_target, strict: false) arch_srcs += t.sources() arch_deps += t.dependencies() @@ -3464,7 +3485,7 @@ endif summary_info += {'seccomp support': seccomp} summary_info += {'GlusterFS support': glusterfs} summary_info += {'TPM support': config_host.has_key('CONFIG_TPM')} -summary_info += {'libssh support': config_host.has_key('CONFIG_LIBSSH')} +summary_info += {'libssh support': libssh} summary_info += {'lzo support': lzo} summary_info += {'snappy support': snappy} summary_info += {'bzip2 support': libbzip2} diff --git a/meson_options.txt b/meson_options.txt index e392323732..4114bfcaa4 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -105,6 +105,8 @@ option('libdaxctl', type : 'feature', value : 'auto', description: 'libdaxctl support') option('libpmem', type : 'feature', value : 'auto', description: 'libpmem support') +option('libssh', type : 'feature', value : 'auto', + description: 'ssh block device support') option('libudev', type : 'feature', value : 'auto', description: 'Use libudev to enumerate host devices') option('libusb', type : 'feature', value : 'auto', diff --git a/migration/colo.c b/migration/colo.c index 2415325262..5f7071b3cd 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -530,7 +530,6 @@ static void colo_process_checkpoint(MigrationState *s) { QIOChannelBuffer *bioc; QEMUFile *fb = NULL; - int64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_HOST); Error *local_err = NULL; int ret; @@ -578,8 +577,8 @@ static void colo_process_checkpoint(MigrationState *s) qemu_mutex_unlock_iothread(); trace_colo_vm_state_change("stop", "run"); - timer_mod(s->colo_delay_timer, - current_time + s->parameters.x_checkpoint_delay); + timer_mod(s->colo_delay_timer, qemu_clock_get_ms(QEMU_CLOCK_HOST) + + s->parameters.x_checkpoint_delay); while (s->state == MIGRATION_STATUS_COLO) { if (failover_get_state() != FAILOVER_STATUS_NONE) { @@ -667,8 +666,6 @@ void migrate_start_colo_process(MigrationState *s) colo_checkpoint_notify, s); qemu_sem_init(&s->colo_exit_sem, 0); - migrate_set_state(&s->state, MIGRATION_STATUS_ACTIVE, - MIGRATION_STATUS_COLO); colo_process_checkpoint(s); qemu_mutex_lock_iothread(); } @@ -683,8 +680,8 @@ static void colo_incoming_process_checkpoint(MigrationIncomingState *mis, qemu_mutex_lock_iothread(); vm_stop_force_state(RUN_STATE_COLO); - trace_colo_vm_state_change("run", "stop"); qemu_mutex_unlock_iothread(); + trace_colo_vm_state_change("run", "stop"); /* FIXME: This is unnecessary for periodic checkpoint mode */ colo_send_message(mis->to_src_file, COLO_MESSAGE_CHECKPOINT_REPLY, @@ -786,8 +783,8 @@ static void colo_incoming_process_checkpoint(MigrationIncomingState *mis, vmstate_loading = false; vm_start(); - trace_colo_vm_state_change("stop", "run"); qemu_mutex_unlock_iothread(); + trace_colo_vm_state_change("stop", "run"); if (failover_get_state() == FAILOVER_STATUS_RELAUNCH) { return; @@ -820,6 +817,26 @@ static void colo_wait_handle_message(MigrationIncomingState *mis, } } +void colo_shutdown(void) +{ + MigrationIncomingState *mis = NULL; + MigrationState *s = NULL; + + switch (get_colo_mode()) { + case COLO_MODE_PRIMARY: + s = migrate_get_current(); + qemu_event_set(&s->colo_checkpoint_event); + qemu_sem_post(&s->colo_exit_sem); + break; + case COLO_MODE_SECONDARY: + mis = migration_incoming_get_current(); + qemu_sem_post(&mis->colo_incoming_sem); + break; + default: + break; + } +} + void *colo_process_incoming_thread(void *opaque) { MigrationIncomingState *mis = opaque; @@ -870,8 +887,8 @@ void *colo_process_incoming_thread(void *opaque) abort(); #endif vm_start(); - trace_colo_vm_state_change("stop", "run"); qemu_mutex_unlock_iothread(); + trace_colo_vm_state_change("stop", "run"); colo_send_message(mis->to_src_file, COLO_MESSAGE_CHECKPOINT_READY, &local_err); diff --git a/migration/migration.c b/migration/migration.c index abaf6f9e3d..3de11ae921 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -225,6 +225,12 @@ void migration_cancel(const Error *error) void migration_shutdown(void) { + /* + * When the QEMU main thread exit, the COLO thread + * may wait a semaphore. So, we should wakeup the + * COLO thread before migration shutdown. + */ + colo_shutdown(); /* * Cancel the current migration - that will (eventually) * stop the migration using this structure @@ -990,6 +996,8 @@ static void populate_time_info(MigrationInfo *info, MigrationState *s) static void populate_ram_info(MigrationInfo *info, MigrationState *s) { + size_t page_size = qemu_target_page_size(); + info->has_ram = true; info->ram = g_malloc0(sizeof(*info->ram)); info->ram->transferred = ram_counters.transferred; @@ -998,12 +1006,11 @@ static void populate_ram_info(MigrationInfo *info, MigrationState *s) /* legacy value. It is not used anymore */ info->ram->skipped = 0; info->ram->normal = ram_counters.normal; - info->ram->normal_bytes = ram_counters.normal * - qemu_target_page_size(); + info->ram->normal_bytes = ram_counters.normal * page_size; info->ram->mbps = s->mbps; info->ram->dirty_sync_count = ram_counters.dirty_sync_count; info->ram->postcopy_requests = ram_counters.postcopy_requests; - info->ram->page_size = qemu_target_page_size(); + info->ram->page_size = page_size; info->ram->multifd_bytes = ram_counters.multifd_bytes; info->ram->pages_per_second = s->pages_per_second; @@ -3607,12 +3614,7 @@ static void migration_iteration_finish(MigrationState *s) migration_calculate_complete(s); runstate_set(RUN_STATE_POSTMIGRATE); break; - - case MIGRATION_STATUS_ACTIVE: - /* - * We should really assert here, but since it's during - * migration, let's try to reduce the usage of assertions. - */ + case MIGRATION_STATUS_COLO: if (!migrate_colo_enabled()) { error_report("%s: critical error: calling COLO code without " "COLO enabled", __func__); @@ -3622,6 +3624,12 @@ static void migration_iteration_finish(MigrationState *s) * Fixme: we will run VM in COLO no matter its old running state. * After exited COLO, we will keep running. */ + /* Fallthrough */ + case MIGRATION_STATUS_ACTIVE: + /* + * We should really assert here, but since it's during + * migration, let's try to reduce the usage of assertions. + */ s->vm_was_running = true; /* Fallthrough */ case MIGRATION_STATUS_FAILED: diff --git a/migration/multifd-zlib.c b/migration/multifd-zlib.c index ab4ba75d75..da6201704c 100644 --- a/migration/multifd-zlib.c +++ b/migration/multifd-zlib.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include #include "qemu/rcu.h" +#include "exec/ramblock.h" #include "exec/target_page.h" #include "qapi/error.h" #include "migration.h" @@ -42,7 +43,6 @@ struct zlib_data { */ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zlib_data *z = g_malloc0(sizeof(struct zlib_data)); z_stream *zs = &z->zs; @@ -54,9 +54,8 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) error_setg(errp, "multifd %d: deflate init failed", p->id); return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { deflateEnd(&z->zs); @@ -74,6 +73,7 @@ static int zlib_send_setup(MultiFDSendParams *p, Error **errp) * Close the channel and return memory. * * @p: Params for the channel that we are using + * @errp: pointer to an error */ static void zlib_send_cleanup(MultiFDSendParams *p, Error **errp) { @@ -95,27 +95,27 @@ static void zlib_send_cleanup(MultiFDSendParams *p, Error **errp) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used + * @errp: pointer to an error */ -static int zlib_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) +static int zlib_send_prepare(MultiFDSendParams *p, Error **errp) { - struct iovec *iov = p->pages->iov; struct zlib_data *z = p->data; + size_t page_size = qemu_target_page_size(); z_stream *zs = &z->zs; uint32_t out_size = 0; int ret; uint32_t i; - for (i = 0; i < used; i++) { + for (i = 0; i < p->pages->num; i++) { uint32_t available = z->zbuff_len - out_size; int flush = Z_NO_FLUSH; - if (i == used - 1) { + if (i == p->pages->num - 1) { flush = Z_SYNC_FLUSH; } - zs->avail_in = iov[i].iov_len; - zs->next_in = iov[i].iov_base; + zs->avail_in = page_size; + zs->next_in = p->pages->block->host + p->pages->offset[i]; zs->avail_out = available; zs->next_out = z->zbuff + out_size; @@ -180,7 +180,6 @@ static int zlib_send_write(MultiFDSendParams *p, uint32_t used, Error **errp) */ static int zlib_recv_setup(MultiFDRecvParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zlib_data *z = g_malloc0(sizeof(struct zlib_data)); z_stream *zs = &z->zs; @@ -194,10 +193,8 @@ static int zlib_recv_setup(MultiFDRecvParams *p, Error **errp) error_setg(errp, "multifd %d: inflate init failed", p->id); return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - /* We know compression "could" use more space */ - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { inflateEnd(zs); @@ -234,17 +231,17 @@ static void zlib_recv_cleanup(MultiFDRecvParams *p) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int zlib_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) +static int zlib_recv_pages(MultiFDRecvParams *p, Error **errp) { struct zlib_data *z = p->data; + size_t page_size = qemu_target_page_size(); z_stream *zs = &z->zs; uint32_t in_size = p->next_packet_size; /* we measure the change of total_out */ uint32_t out_size = zs->total_out; - uint32_t expected_size = used * qemu_target_page_size(); + uint32_t expected_size = p->pages->num * qemu_target_page_size(); uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; int ret; int i; @@ -263,17 +260,16 @@ static int zlib_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) zs->avail_in = in_size; zs->next_in = z->zbuff; - for (i = 0; i < used; i++) { - struct iovec *iov = &p->pages->iov[i]; + for (i = 0; i < p->pages->num; i++) { int flush = Z_NO_FLUSH; unsigned long start = zs->total_out; - if (i == used - 1) { + if (i == p->pages->num - 1) { flush = Z_SYNC_FLUSH; } - zs->avail_out = iov->iov_len; - zs->next_out = iov->iov_base; + zs->avail_out = page_size; + zs->next_out = p->pages->block->host + p->pages->offset[i]; /* * Welcome to inflate semantics @@ -286,8 +282,8 @@ static int zlib_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) do { ret = inflate(zs, flush); } while (ret == Z_OK && zs->avail_in - && (zs->total_out - start) < iov->iov_len); - if (ret == Z_OK && (zs->total_out - start) < iov->iov_len) { + && (zs->total_out - start) < page_size); + if (ret == Z_OK && (zs->total_out - start) < page_size) { error_setg(errp, "multifd %d: inflate generated too few output", p->id); return -1; diff --git a/migration/multifd-zstd.c b/migration/multifd-zstd.c index 693bddf8c9..2d5b61106c 100644 --- a/migration/multifd-zstd.c +++ b/migration/multifd-zstd.c @@ -13,6 +13,7 @@ #include "qemu/osdep.h" #include #include "qemu/rcu.h" +#include "exec/ramblock.h" #include "exec/target_page.h" #include "qapi/error.h" #include "migration.h" @@ -47,7 +48,6 @@ struct zstd_data { */ static int zstd_send_setup(MultiFDSendParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zstd_data *z = g_new0(struct zstd_data, 1); int res; @@ -67,9 +67,8 @@ static int zstd_send_setup(MultiFDSendParams *p, Error **errp) p->id, ZSTD_getErrorName(res)); return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { ZSTD_freeCStream(z->zcs); @@ -86,6 +85,7 @@ static int zstd_send_setup(MultiFDSendParams *p, Error **errp) * Close the channel and return memory. * * @p: Params for the channel that we are using + * @errp: pointer to an error */ static void zstd_send_cleanup(MultiFDSendParams *p, Error **errp) { @@ -108,12 +108,12 @@ static void zstd_send_cleanup(MultiFDSendParams *p, Error **errp) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used + * @errp: pointer to an error */ -static int zstd_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) +static int zstd_send_prepare(MultiFDSendParams *p, Error **errp) { - struct iovec *iov = p->pages->iov; struct zstd_data *z = p->data; + size_t page_size = qemu_target_page_size(); int ret; uint32_t i; @@ -121,14 +121,14 @@ static int zstd_send_prepare(MultiFDSendParams *p, uint32_t used, Error **errp) z->out.size = z->zbuff_len; z->out.pos = 0; - for (i = 0; i < used; i++) { + for (i = 0; i < p->pages->num; i++) { ZSTD_EndDirective flush = ZSTD_e_continue; - if (i == used - 1) { + if (i == p->pages->num - 1) { flush = ZSTD_e_flush; } - z->in.src = iov[i].iov_base; - z->in.size = iov[i].iov_len; + z->in.src = p->pages->block->host + p->pages->offset[i]; + z->in.size = page_size; z->in.pos = 0; /* @@ -191,7 +191,6 @@ static int zstd_send_write(MultiFDSendParams *p, uint32_t used, Error **errp) */ static int zstd_recv_setup(MultiFDRecvParams *p, Error **errp) { - uint32_t page_count = MULTIFD_PACKET_SIZE / qemu_target_page_size(); struct zstd_data *z = g_new0(struct zstd_data, 1); int ret; @@ -212,10 +211,8 @@ static int zstd_recv_setup(MultiFDRecvParams *p, Error **errp) return -1; } - /* We will never have more than page_count pages */ - z->zbuff_len = page_count * qemu_target_page_size(); - /* We know compression "could" use more space */ - z->zbuff_len *= 2; + /* To be safe, we reserve twice the size of the packet */ + z->zbuff_len = MULTIFD_PACKET_SIZE * 2; z->zbuff = g_try_malloc(z->zbuff_len); if (!z->zbuff) { ZSTD_freeDStream(z->zds); @@ -254,14 +251,14 @@ static void zstd_recv_cleanup(MultiFDRecvParams *p) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int zstd_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) +static int zstd_recv_pages(MultiFDRecvParams *p, Error **errp) { uint32_t in_size = p->next_packet_size; uint32_t out_size = 0; - uint32_t expected_size = used * qemu_target_page_size(); + size_t page_size = qemu_target_page_size(); + uint32_t expected_size = p->pages->num * page_size; uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; struct zstd_data *z = p->data; int ret; @@ -282,11 +279,9 @@ static int zstd_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) z->in.size = in_size; z->in.pos = 0; - for (i = 0; i < used; i++) { - struct iovec *iov = &p->pages->iov[i]; - - z->out.dst = iov->iov_base; - z->out.size = iov->iov_len; + for (i = 0; i < p->pages->num; i++) { + z->out.dst = p->pages->block->host + p->pages->offset[i]; + z->out.size = page_size; z->out.pos = 0; /* @@ -300,8 +295,8 @@ static int zstd_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) do { ret = ZSTD_decompressStream(z->zds, &z->out, &z->in); } while (ret > 0 && (z->in.size - z->in.pos > 0) - && (z->out.pos < iov->iov_len)); - if (ret > 0 && (z->out.pos < iov->iov_len)) { + && (z->out.pos < page_size)); + if (ret > 0 && (z->out.pos < page_size)) { error_setg(errp, "multifd %d: decompressStream buffer too small", p->id); return -1; diff --git a/migration/multifd.c b/migration/multifd.c index 7c9deb1921..3242f688e5 100644 --- a/migration/multifd.c +++ b/migration/multifd.c @@ -66,6 +66,7 @@ static int nocomp_send_setup(MultiFDSendParams *p, Error **errp) * For no compression this function does nothing. * * @p: Params for the channel that we are using + * @errp: pointer to an error */ static void nocomp_send_cleanup(MultiFDSendParams *p, Error **errp) { @@ -81,13 +82,11 @@ static void nocomp_send_cleanup(MultiFDSendParams *p, Error **errp) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int nocomp_send_prepare(MultiFDSendParams *p, uint32_t used, - Error **errp) +static int nocomp_send_prepare(MultiFDSendParams *p, Error **errp) { - p->next_packet_size = used * qemu_target_page_size(); + p->next_packet_size = p->pages->num * qemu_target_page_size(); p->flags |= MULTIFD_FLAG_NOCOMP; return 0; } @@ -142,10 +141,9 @@ static void nocomp_recv_cleanup(MultiFDRecvParams *p) * Returns 0 for success or -1 for error * * @p: Params for the channel that we are using - * @used: number of pages used * @errp: pointer to an error */ -static int nocomp_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) +static int nocomp_recv_pages(MultiFDRecvParams *p, Error **errp) { uint32_t flags = p->flags & MULTIFD_FLAG_COMPRESSION_MASK; @@ -154,7 +152,7 @@ static int nocomp_recv_pages(MultiFDRecvParams *p, uint32_t used, Error **errp) p->id, flags, MULTIFD_FLAG_NOCOMP); return -1; } - return qio_channel_readv_all(p->c, p->pages->iov, used, errp); + return qio_channel_readv_all(p->c, p->pages->iov, p->pages->num, errp); } static MultiFDMethods multifd_nocomp_ops = { @@ -252,7 +250,7 @@ static MultiFDPages_t *multifd_pages_init(size_t size) static void multifd_pages_clear(MultiFDPages_t *pages) { - pages->used = 0; + pages->num = 0; pages->allocated = 0; pages->packet_num = 0; pages->block = NULL; @@ -270,7 +268,7 @@ static void multifd_send_fill_packet(MultiFDSendParams *p) packet->flags = cpu_to_be32(p->flags); packet->pages_alloc = cpu_to_be32(p->pages->allocated); - packet->pages_used = cpu_to_be32(p->pages->used); + packet->pages_used = cpu_to_be32(p->pages->num); packet->next_packet_size = cpu_to_be32(p->next_packet_size); packet->packet_num = cpu_to_be64(p->packet_num); @@ -278,7 +276,7 @@ static void multifd_send_fill_packet(MultiFDSendParams *p) strncpy(packet->ramblock, p->pages->block->idstr, 256); } - for (i = 0; i < p->pages->used; i++) { + for (i = 0; i < p->pages->num; i++) { /* there are architectures where ram_addr_t is 32 bit */ uint64_t temp = p->pages->offset[i]; @@ -289,7 +287,8 @@ static void multifd_send_fill_packet(MultiFDSendParams *p) static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) { MultiFDPacket_t *packet = p->packet; - uint32_t pages_max = MULTIFD_PACKET_SIZE / qemu_target_page_size(); + size_t page_size = qemu_target_page_size(); + uint32_t pages_max = MULTIFD_PACKET_SIZE / page_size; RAMBlock *block; int i; @@ -331,18 +330,18 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) p->pages = multifd_pages_init(packet->pages_alloc); } - p->pages->used = be32_to_cpu(packet->pages_used); - if (p->pages->used > packet->pages_alloc) { + p->pages->num = be32_to_cpu(packet->pages_used); + if (p->pages->num > packet->pages_alloc) { error_setg(errp, "multifd: received packet " "with %d pages and expected maximum pages are %d", - p->pages->used, packet->pages_alloc) ; + p->pages->num, packet->pages_alloc) ; return -1; } p->next_packet_size = be32_to_cpu(packet->next_packet_size); p->packet_num = be64_to_cpu(packet->packet_num); - if (p->pages->used == 0) { + if (p->pages->num == 0) { return 0; } @@ -355,17 +354,19 @@ static int multifd_recv_unfill_packet(MultiFDRecvParams *p, Error **errp) return -1; } - for (i = 0; i < p->pages->used; i++) { + p->pages->block = block; + for (i = 0; i < p->pages->num; i++) { uint64_t offset = be64_to_cpu(packet->offset[i]); - if (offset > (block->used_length - qemu_target_page_size())) { + if (offset > (block->used_length - page_size)) { error_setg(errp, "multifd: offset too long %" PRIu64 " (max " RAM_ADDR_FMT ")", offset, block->used_length); return -1; } + p->pages->offset[i] = offset; p->pages->iov[i].iov_base = block->host + offset; - p->pages->iov[i].iov_len = qemu_target_page_size(); + p->pages->iov[i].iov_len = page_size; } return 0; @@ -442,13 +443,13 @@ static int multifd_send_pages(QEMUFile *f) } qemu_mutex_unlock(&p->mutex); } - assert(!p->pages->used); + assert(!p->pages->num); assert(!p->pages->block); p->packet_num = multifd_send_state->packet_num++; multifd_send_state->pages = p->pages; p->pages = pages; - transferred = ((uint64_t) pages->used) * qemu_target_page_size() + transferred = ((uint64_t) pages->num) * qemu_target_page_size() + p->packet_len; qemu_file_update_transfer(f, transferred); ram_counters.multifd_bytes += transferred; @@ -468,12 +469,12 @@ int multifd_queue_page(QEMUFile *f, RAMBlock *block, ram_addr_t offset) } if (pages->block == block) { - pages->offset[pages->used] = offset; - pages->iov[pages->used].iov_base = block->host + offset; - pages->iov[pages->used].iov_len = qemu_target_page_size(); - pages->used++; + pages->offset[pages->num] = offset; + pages->iov[pages->num].iov_base = block->host + offset; + pages->iov[pages->num].iov_len = qemu_target_page_size(); + pages->num++; - if (pages->used < pages->allocated) { + if (pages->num < pages->allocated) { return 1; } } @@ -523,6 +524,9 @@ static void multifd_send_terminate_threads(Error *err) qemu_mutex_lock(&p->mutex); p->quit = true; qemu_sem_post(&p->sem); + if (p->c) { + qio_channel_shutdown(p->c, QIO_CHANNEL_SHUTDOWN_BOTH, NULL); + } qemu_mutex_unlock(&p->mutex); } } @@ -585,7 +589,7 @@ void multifd_send_sync_main(QEMUFile *f) if (!migrate_use_multifd()) { return; } - if (multifd_send_state->pages->used) { + if (multifd_send_state->pages->num) { if (multifd_send_pages(f) < 0) { error_report("%s: multifd_send_pages fail", __func__); return; @@ -627,7 +631,6 @@ static void *multifd_send_thread(void *opaque) MultiFDSendParams *p = opaque; Error *local_err = NULL; int ret = 0; - uint32_t flags = 0; trace_multifd_send_thread_start(p->id); rcu_register_thread(); @@ -648,13 +651,12 @@ static void *multifd_send_thread(void *opaque) qemu_mutex_lock(&p->mutex); if (p->pending_job) { - uint32_t used = p->pages->used; + uint32_t used = p->pages->num; uint64_t packet_num = p->packet_num; - flags = p->flags; + uint32_t flags = p->flags; if (used) { - ret = multifd_send_state->ops->send_prepare(p, used, - &local_err); + ret = multifd_send_state->ops->send_prepare(p, &local_err); if (ret != 0) { qemu_mutex_unlock(&p->mutex); break; @@ -664,7 +666,7 @@ static void *multifd_send_thread(void *opaque) p->flags = 0; p->num_packets++; p->num_pages += used; - p->pages->used = 0; + p->pages->num = 0; p->pages->block = NULL; qemu_mutex_unlock(&p->mutex); @@ -1090,7 +1092,7 @@ static void *multifd_recv_thread(void *opaque) break; } - used = p->pages->used; + used = p->pages->num; flags = p->flags; /* recv methods don't know how to handle the SYNC flag */ p->flags &= ~MULTIFD_FLAG_SYNC; @@ -1101,7 +1103,7 @@ static void *multifd_recv_thread(void *opaque) qemu_mutex_unlock(&p->mutex); if (used) { - ret = multifd_recv_state->ops->recv_pages(p, used, &local_err); + ret = multifd_recv_state->ops->recv_pages(p, &local_err); if (ret != 0) { break; } diff --git a/migration/multifd.h b/migration/multifd.h index 15c50ca0b2..e57adc783b 100644 --- a/migration/multifd.h +++ b/migration/multifd.h @@ -55,7 +55,7 @@ typedef struct { typedef struct { /* number of used pages */ - uint32_t used; + uint32_t num; /* number of allocated pages */ uint32_t allocated; /* global number of generated multifd packets */ @@ -159,7 +159,7 @@ typedef struct { /* Cleanup for sending side */ void (*send_cleanup)(MultiFDSendParams *p, Error **errp); /* Prepare the send packet */ - int (*send_prepare)(MultiFDSendParams *p, uint32_t used, Error **errp); + int (*send_prepare)(MultiFDSendParams *p, Error **errp); /* Write the send packet */ int (*send_write)(MultiFDSendParams *p, uint32_t used, Error **errp); /* Setup for receiving side */ @@ -167,7 +167,7 @@ typedef struct { /* Cleanup for receiving side */ void (*recv_cleanup)(MultiFDRecvParams *p); /* Read all pages */ - int (*recv_pages)(MultiFDRecvParams *p, uint32_t used, Error **errp); + int (*recv_pages)(MultiFDRecvParams *p, Error **errp); } MultiFDMethods; void multifd_register_ops(int method, MultiFDMethods *ops); diff --git a/migration/ram.c b/migration/ram.c index 863035d235..57efa67f20 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -81,11 +81,6 @@ /* 0x80 is reserved in migration.h start with 0x100 next */ #define RAM_SAVE_FLAG_COMPRESS_PAGE 0x100 -static inline bool is_zero_range(uint8_t *p, uint64_t size) -{ - return buffer_is_zero(p, size); -} - XBZRLECacheStats xbzrle_counters; /* struct contains XBZRLE cache and a static page @@ -1180,7 +1175,7 @@ static int save_zero_page_to_file(RAMState *rs, QEMUFile *file, uint8_t *p = block->host + offset; int len = 0; - if (is_zero_range(p, TARGET_PAGE_SIZE)) { + if (buffer_is_zero(p, TARGET_PAGE_SIZE)) { len += save_page_header(rs, file, block, offset | RAM_SAVE_FLAG_ZERO); qemu_put_byte(file, 0); len += 1; @@ -3367,7 +3362,7 @@ static inline void *colo_cache_from_block_offset(RAMBlock *block, */ void ram_handle_compressed(void *host, uint8_t ch, uint64_t size) { - if (ch != 0 || !is_zero_range(host, size)) { + if (ch != 0 || !buffer_is_zero(host, size)) { memset(host, ch, size); } } @@ -3918,7 +3913,6 @@ void colo_flush_ram_cache(void) unsigned long offset = 0; memory_global_dirty_log_sync(); - qemu_mutex_lock(&ram_state->bitmap_mutex); WITH_RCU_READ_LOCK_GUARD() { RAMBLOCK_FOREACH_NOT_IGNORED(block) { ramblock_sync_dirty_bitmap(ram_state, block); @@ -3954,7 +3948,6 @@ void colo_flush_ram_cache(void) } } trace_colo_flush_ram_cache_end(); - qemu_mutex_unlock(&ram_state->bitmap_mutex); } /** diff --git a/migration/savevm.c b/migration/savevm.c index d59e976d50..0bef031acb 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -1685,6 +1685,7 @@ static int loadvm_postcopy_handle_advise(MigrationIncomingState *mis, { PostcopyState ps = postcopy_state_set(POSTCOPY_INCOMING_ADVISE); uint64_t remote_pagesize_summary, local_pagesize_summary, remote_tps; + size_t page_size = qemu_target_page_size(); Error *local_err = NULL; trace_loadvm_postcopy_handle_advise(); @@ -1741,13 +1742,13 @@ static int loadvm_postcopy_handle_advise(MigrationIncomingState *mis, } remote_tps = qemu_get_be64(mis->from_src_file); - if (remote_tps != qemu_target_page_size()) { + if (remote_tps != page_size) { /* * Again, some differences could be dealt with, but for now keep it * simple. */ error_report("Postcopy needs matching target page sizes (s=%d d=%zd)", - (int)remote_tps, qemu_target_page_size()); + (int)remote_tps, page_size); return -1; } diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c index 9c91bf93e9..2669156b28 100644 --- a/monitor/hmp-cmds.c +++ b/monitor/hmp-cmds.c @@ -1810,6 +1810,7 @@ void hmp_info_memory_devices(Monitor *mon, const QDict *qdict) se->id ? se->id : ""); monitor_printf(mon, " memaddr: 0x%" PRIx64 "\n", se->memaddr); monitor_printf(mon, " size: %" PRIu64 "\n", se->size); + monitor_printf(mon, " node: %" PRId64 "\n", se->node); monitor_printf(mon, " memdev: %s\n", se->memdev); break; default: diff --git a/pc-bios/README b/pc-bios/README index db39d757b0..c51ae58824 100644 --- a/pc-bios/README +++ b/pc-bios/README @@ -14,7 +14,7 @@ - SLOF (Slimline Open Firmware) is a free IEEE 1275 Open Firmware implementation for certain IBM POWER hardware. The sources are at https://github.com/aik/SLOF, and the image currently in qemu is - built from git tag qemu-slof-20210711. + built from git tag qemu-slof-20211112. - VOF (Virtual Open Firmware) is a minimalistic firmware to work with -machine pseries,x-vof=on. When enabled, the firmware acts as a slim shim and diff --git a/pc-bios/meson.build b/pc-bios/meson.build index b40ff3f2bd..1812a4084f 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -15,7 +15,7 @@ if unpack_edk2_blobs roms += custom_target(f, build_by_default: have_system, output: f, - input: '@0@.bz2'.format(f), + input: files('@0@.bz2'.format(f)), capture: true, install: get_option('install_blobs'), install_dir: qemu_datadir, diff --git a/pc-bios/slof.bin b/pc-bios/slof.bin index 855521e650..046ca63709 100644 Binary files a/pc-bios/slof.bin and b/pc-bios/slof.bin differ diff --git a/qapi/machine.json b/qapi/machine.json index 067e3f5378..edeab6084b 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -867,7 +867,7 @@ # # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to -# @die-id: die number within node/board the CPU belongs to (Since 4.1) +# @die-id: die number within socket the CPU belongs to (since 4.1) # @core-id: core number within die the CPU belongs to # @thread-id: thread number within core the CPU belongs to # @@ -1207,12 +1207,15 @@ # # @memdev: memory backend linked with device # +# @node: the numa node +# # Since: 6.2 ## { 'struct': 'SgxEPCDeviceInfo', 'data': { '*id': 'str', 'memaddr': 'size', 'size': 'size', + 'node': 'int', 'memdev': 'str' } } @@ -1285,10 +1288,15 @@ # # @memdev: memory backend linked with device # +# @node: the numa node +# # Since: 6.2 ## { 'struct': 'SgxEPC', - 'data': { 'memdev': 'str' } } + 'data': { 'memdev': 'str', + 'node': 'int' + } +} ## # @SgxEPCProperties: diff --git a/qapi/misc-target.json b/qapi/misc-target.json index 5aa2b95b7d..1022aa0184 100644 --- a/qapi/misc-target.json +++ b/qapi/misc-target.json @@ -337,6 +337,21 @@ 'if': 'TARGET_ARM' } +## +# @SGXEPCSection: +# +# Information about intel SGX EPC section info +# +# @node: the numa node +# +# @size: the size of epc section +# +# Since: 6.2 +## +{ 'struct': 'SGXEPCSection', + 'data': { 'node': 'int', + 'size': 'uint64'}} + ## # @SGXInfo: # @@ -350,7 +365,7 @@ # # @flc: true if FLC is supported # -# @section-size: The EPC section size for guest +# @sections: The EPC sections info for guest # # Since: 6.2 ## @@ -359,7 +374,7 @@ 'sgx1': 'bool', 'sgx2': 'bool', 'flc': 'bool', - 'section-size': 'uint64'}, + 'sections': ['SGXEPCSection']}, 'if': 'TARGET_I386' } ## diff --git a/qemu-keymap.c b/qemu-keymap.c index 536e8f2385..4095b654a6 100644 --- a/qemu-keymap.c +++ b/qemu-keymap.c @@ -187,6 +187,7 @@ int main(int argc, char *argv[]) } fprintf(outfile, + "# SPDX-License-Identifier: GPL-2.0-or-later\n" "#\n" "# generated by qemu-keymap\n" "# model : %s\n" diff --git a/qemu-options.hx b/qemu-options.hx index ae2c6dbbfc..489b58e151 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -127,11 +127,11 @@ SRST ERST DEF("M", HAS_ARG, QEMU_OPTION_M, - " sgx-epc.0.memdev=memid\n", + " sgx-epc.0.memdev=memid,sgx-epc.0.node=numaid\n", QEMU_ARCH_ALL) SRST -``sgx-epc.0.memdev=@var{memid}`` +``sgx-epc.0.memdev=@var{memid},sgx-epc.0.node=@var{numaid}`` Define an SGX EPC section. ERST diff --git a/roms/SLOF b/roms/SLOF index dd0dcaa1c1..a6906b024c 160000 --- a/roms/SLOF +++ b/roms/SLOF @@ -1 +1 @@ -Subproject commit dd0dcaa1c1085c159ddab709c7f274b3917be8bd +Subproject commit a6906b024c6cca5a86496f51eb4bfee3a0c36148 diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index cb8eff233e..5caa739db4 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2850,6 +2850,11 @@ sub process { WARN("consider using g_path_get_$1() in preference to g_strdup($1())\n" . $herecurr); } +# enforce g_memdup2() over g_memdup() + if ($line =~ /\bg_memdup\s*\(/) { + ERROR("use g_memdup2() instead of unsafe g_memdup()\n" . $herecurr); + } + # recommend qemu_strto* over strto* for numeric conversions if ($line =~ /\b(strto[^kd].*?)\s*\(/) { ERROR("consider using qemu_$1 in preference to $1\n" . $herecurr); diff --git a/scripts/entitlement.sh b/scripts/entitlement.sh index e2c956a3ac..0f412949ec 100755 --- a/scripts/entitlement.sh +++ b/scripts/entitlement.sh @@ -15,7 +15,7 @@ ENTITLEMENT="$4" if $in_place; then trap 'rm "$DST.tmp"' exit - cp -af "$SRC" "$DST.tmp" + cp -pPf "$SRC" "$DST.tmp" SRC="$DST.tmp" else cd "$MESON_INSTALL_DESTDIR_PREFIX" diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 7a17ff4218..ae8f18edc2 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -53,6 +53,7 @@ meson_options_help() { printf "%s\n" ' libiscsi libiscsi userspace initiator' printf "%s\n" ' libnfs libnfs block device driver' printf "%s\n" ' libpmem libpmem support' + printf "%s\n" ' libssh ssh block device support' printf "%s\n" ' libudev Use libudev to enumerate host devices' printf "%s\n" ' libusb libusb support for USB passthrough' printf "%s\n" ' libxml2 libxml2 support for Parallels image format' @@ -177,6 +178,8 @@ _meson_option_parse() { --disable-libnfs) printf "%s" -Dlibnfs=disabled ;; --enable-libpmem) printf "%s" -Dlibpmem=enabled ;; --disable-libpmem) printf "%s" -Dlibpmem=disabled ;; + --enable-libssh) printf "%s" -Dlibssh=enabled ;; + --disable-libssh) printf "%s" -Dlibssh=disabled ;; --enable-libudev) printf "%s" -Dlibudev=enabled ;; --disable-libudev) printf "%s" -Dlibudev=disabled ;; --enable-libusb) printf "%s" -Dlibusb=enabled ;; diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2983e36dd3..32f3caec23 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -220,6 +220,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + target_ulong pc; int n; /* @@ -231,6 +232,28 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc = is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { if (bp_wp_matches(cpu, n, false)) { return true; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 134da0d0ae..ca1de47511 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -77,8 +77,13 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) tmp = ldl_p(mem_buf); - /* Mask out low bit of PC to workaround gdb bugs. This will probably - cause problems if we ever implement the Jazelle DBX extensions. */ + /* + * Mask out low bits of PC to workaround gdb bugs. + * This avoids an assert in thumb_tr_translate_insn, because it is + * architecturally impossible to misalign the pc. + * This will probably cause problems if we ever implement the + * Jazelle DBX extensions. + */ if (n == 15) { tmp &= ~1; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 9b317899a6..db837d53bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4519,18 +4519,18 @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, uint64_t exponent; uint64_t length; - num = extract64(value, 39, 4); + num = extract64(value, 39, 5); scale = extract64(value, 44, 2); page_size_granule = extract64(value, 46, 2); - page_shift = page_size_granule * 2 + 12; - if (page_size_granule == 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); return 0; } + page_shift = (page_size_granule - 1) * 2 + 12; + exponent = (5 * scale) + 1; length = (num + 1) << (exponent + page_shift); diff --git a/target/arm/helper.h b/target/arm/helper.h index 448a86edfd..b463d9343b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) diff --git a/target/arm/machine.c b/target/arm/machine.c index c74d8c3f4b..135d2420b5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -794,6 +794,16 @@ static int cpu_post_load(void *opaque, int version_id) return -1; } } + + /* + * Misaligned thumb pc is architecturally impossible. + * We have an assert in thumb_tr_translate_insn to verify this. + * Fail an incoming migrate to avoid this assert. + */ + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { + return -1; + } + if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index f30f4130a2..8cde8e7243 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -282,4 +282,9 @@ static inline uint32_t syn_illegalstate(void) return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; } +static inline uint32_t syn_pcalignment(void) +{ + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 12a934e924..b79004e0cc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/helper-proto.h" static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -49,25 +50,11 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, return syn; } -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *fi) +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, + int target_el, int mmu_idx, uint32_t *ret_fsc) { - CPUARMState *env = &cpu->env; - int target_el; - bool same_el; - uint32_t syn, exc, fsr, fsc; ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); - - target_el = exception_target_el(env); - if (fi->stage2) { - target_el = 2; - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; - if (arm_is_secure_below_el3(env) && fi->s1ns) { - env->cp15.hpfar_el2 |= HPFAR_NS; - } - } - same_el = (arm_current_el(env) == target_el); + uint32_t fsr, fsc; if (target_el == 2 || arm_el_is_aa64(env, target_el) || arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { @@ -88,6 +75,31 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, fsc = 0x3f; } + *ret_fsc = fsc; + return fsr; +} + +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) +{ + CPUARMState *env = &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc, fsr, fsc; + + target_el = exception_target_el(env); + if (fi->stage2) { + target_el = 2; + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi->s1ns) { + env->cp15.hpfar_el2 |= HPFAR_NS; + } + } + same_el = (arm_current_el(env) == target_el); + + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + if (access_type == MMU_INST_FETCH) { syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc = EXCP_PREFETCH_ABORT; @@ -123,6 +135,23 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; + int target_el = exception_target_el(env); + int mmu_idx = cpu_mmu_index(env, true); + uint32_t fsc; + + env->exception.vaddress = pc; + + /* + * Note that the fsc is not applicable to this exception, + * since any syndrome is pcalignment not insn_abort. + */ + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); +} + #if !defined(CONFIG_USER_ONLY) /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8014f44cc1..33c7805b8f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14786,8 +14786,10 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *s = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint64_t pc = s->base.pc_next; uint32_t insn; + /* Singlestep exceptions have the highest priority. */ if (s->ss_active && !s->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -14802,13 +14804,28 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) assert(s->base.num_insns == 1); gen_swstep_exception(s, 0, 0); s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = pc + 4; return; } - s->pc_curr = s->base.pc_next; - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code. + * This should only be possible after an indirect branch, at the + * start of the TB. + */ + assert(s->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + s->base.is_jmp = DISAS_NORETURN; + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + s->pc_curr = pc; + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); s->insn = insn; - s->base.pc_next += 4; + s->base.pc_next = pc + 4; s->fp_access_checked = false; s->sve_access_checked = false; diff --git a/target/arm/translate.c b/target/arm/translate.c index 9cf7e649e5..55c994acba 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9544,7 +9544,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_pre_translate_insn(DisasContext *dc) +static bool arm_check_kernelpage(DisasContext *dc) { #ifdef CONFIG_USER_ONLY /* Intercept jump to the magic kernel page. */ @@ -9556,7 +9556,11 @@ static bool arm_pre_translate_insn(DisasContext *dc) return true; } #endif + return false; +} +static bool arm_check_ss_active(DisasContext *dc) +{ if (dc->ss_active && !dc->pstate_ss) { /* Singlestep state is Active-pending. * If we're in this state at the start of a TB then either @@ -9590,17 +9594,38 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; unsigned int insn; - if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 4; + /* Singlestep exceptions have the highest priority. */ + if (arm_check_ss_active(dc)) { + dc->base.pc_next = pc + 4; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + if (pc & 3) { + /* + * PC alignment fault. This has priority over the instruction abort + * that we would receive from a translation fault via arm_ldl_code + * (or the execution of the kernelpage entrypoint). This should only + * be possible after an indirect branch, at the start of the TB. + */ + assert(dc->base.num_insns == 1); + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + dc->base.is_jmp = DISAS_NORETURN; + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); + return; + } + + if (arm_check_kernelpage(dc)) { + dc->base.pc_next = pc + 4; + return; + } + + dc->pc_curr = pc; + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); dc->insn = insn; - dc->base.pc_next += 4; + dc->base.pc_next = pc + 4; disas_arm_insn(dc, insn); arm_post_translate_insn(dc); @@ -9659,25 +9684,28 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; + uint32_t pc = dc->base.pc_next; uint32_t insn; bool is_16bit; - if (arm_pre_translate_insn(dc)) { - dc->base.pc_next += 2; + /* Misaligned thumb PC is architecturally impossible. */ + assert((dc->base.pc_next & 1) == 0); + + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { + dc->base.pc_next = pc + 2; return; } - dc->pc_curr = dc->base.pc_next; - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); + dc->pc_curr = pc; + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); - dc->base.pc_next += 2; + pc += 2; if (!is_16bit) { - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, - dc->sctlr_b); - + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); insn = insn << 16 | insn2; - dc->base.pc_next += 2; + pc += 2; } + dc->base.pc_next = pc; dc->insn = insn; if (dc->pstate_il) { diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index de121d950f..58a0d3870b 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -23,7 +23,6 @@ typedef struct CPUHexagonState CPUHexagonState; #include "fpu/softfloat-types.h" -#include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 5a698bde19..13f8e30c2a 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1406,7 +1406,7 @@ static int hyperv_fill_cpuids(CPUState *cs, c->edx = cpu->hyperv_limits[2]; if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { - __u32 function; + uint32_t function; /* Create zeroed 0x40000006..0x40000009 leaves */ for (function = HV_CPUID_IMPLEMENT_LIMITS + 1; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a95a13a94e..79d770e148 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3539,9 +3539,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, case 0x171: /* shift xmm, im */ case 0x172: case 0x173: - if (b1 >= 2) { - goto unknown_op; - } val = x86_ldub_code(env, s); if (is_xmm) { tcg_gen_movi_tl(s->T0, val); @@ -3560,6 +3557,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, offsetof(CPUX86State, mmx_t0.MMX_L(1))); op1_offset = offsetof(CPUX86State,mmx_t0); } + assert(b1 < 2); sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1]; if (!sse_fn_epp) { @@ -3790,10 +3788,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = modrm & 7; reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; - if (b1 >= 2) { - goto unknown_op; - } + assert(b1 < 2); sse_fn_epp = sse_op_table6[b].op[b1]; if (!sse_fn_epp) { goto unknown_op; @@ -4220,10 +4216,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, rm = modrm & 7; reg = ((modrm >> 3) & 7) | REX_R(s); mod = (modrm >> 6) & 3; - if (b1 >= 2) { - goto unknown_op; - } + assert(b1 < 2); sse_fn_eppi = sse_op_table7[b].op[b1]; if (!sse_fn_eppi) { goto unknown_op; diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c index 4baa111713..c9fcb6119f 100644 --- a/target/ppc/cpu-models.c +++ b/target/ppc/cpu-models.c @@ -67,40 +67,6 @@ POWERPC_DEF_SVR(_name, _desc, _pvr, POWERPC_SVR_NONE, _type) /* Embedded PowerPC */ - /* PowerPC 401 family */ - POWERPC_DEF("401", CPU_POWERPC_401, 401, - "Generic PowerPC 401") - /* PowerPC 401 cores */ - POWERPC_DEF("401a1", CPU_POWERPC_401A1, 401, - "PowerPC 401A1") - POWERPC_DEF("401b2", CPU_POWERPC_401B2, 401x2, - "PowerPC 401B2") - POWERPC_DEF("401c2", CPU_POWERPC_401C2, 401x2, - "PowerPC 401C2") - POWERPC_DEF("401d2", CPU_POWERPC_401D2, 401x2, - "PowerPC 401D2") - POWERPC_DEF("401e2", CPU_POWERPC_401E2, 401x2, - "PowerPC 401E2") - POWERPC_DEF("401f2", CPU_POWERPC_401F2, 401x2, - "PowerPC 401F2") - /* XXX: to be checked */ - POWERPC_DEF("401g2", CPU_POWERPC_401G2, 401x2, - "PowerPC 401G2") - /* PowerPC 401 microcontrollers */ - POWERPC_DEF("iop480", CPU_POWERPC_IOP480, IOP480, - "IOP480 (401 microcontroller)") - POWERPC_DEF("cobra", CPU_POWERPC_COBRA, 401, - "IBM Processor for Network Resources") - /* PowerPC 403 family */ - /* PowerPC 403 microcontrollers */ - POWERPC_DEF("403ga", CPU_POWERPC_403GA, 403, - "PowerPC 403 GA") - POWERPC_DEF("403gb", CPU_POWERPC_403GB, 403, - "PowerPC 403 GB") - POWERPC_DEF("403gc", CPU_POWERPC_403GC, 403, - "PowerPC 403 GC") - POWERPC_DEF("403gcx", CPU_POWERPC_403GCX, 403GCX, - "PowerPC 403 GCX") /* PowerPC 405 family */ /* PowerPC 405 cores */ POWERPC_DEF("405d2", CPU_POWERPC_405D2, 405, diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 0952592759..bf1dc7e5ca 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -38,27 +38,8 @@ extern PowerPCCPUAlias ppc_cpu_aliases[]; /*****************************************************************************/ /* PVR definitions for most known PowerPC */ enum { - /* PowerPC 401 family */ - /* Generic PowerPC 401 */ -#define CPU_POWERPC_401 CPU_POWERPC_401G2 - /* PowerPC 401 cores */ - CPU_POWERPC_401A1 = 0x00210000, - CPU_POWERPC_401B2 = 0x00220000, - CPU_POWERPC_401C2 = 0x00230000, - CPU_POWERPC_401D2 = 0x00240000, - CPU_POWERPC_401E2 = 0x00250000, - CPU_POWERPC_401F2 = 0x00260000, - CPU_POWERPC_401G2 = 0x00270000, - /* PowerPC 401 microcontrolers */ -#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2 /* IBM Processor for Network Resources */ CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */ - /* PowerPC 403 family */ - /* PowerPC 403 microcontrollers */ - CPU_POWERPC_403GA = 0x00200011, - CPU_POWERPC_403GB = 0x00200100, - CPU_POWERPC_403GC = 0x00200200, - CPU_POWERPC_403GCX = 0x00201400, /* PowerPC 405 family */ /* PowerPC 405 cores */ CPU_POWERPC_405D2 = 0x20010000, diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 5800fa324e..99a6b509af 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -45,12 +45,14 @@ enum powerpc_mmu_t { POWERPC_MMU_32B = 0x00000001, /* PowerPC 6xx MMU with software TLB */ POWERPC_MMU_SOFT_6xx = 0x00000002, - /* PowerPC 74xx MMU with software TLB */ + /* + * PowerPC 74xx MMU with software TLB (this has been + * disabled, see git history for more information. + * keywords: tlbld tlbli TLBMISS PTEHI PTELO) + */ POWERPC_MMU_SOFT_74xx = 0x00000003, /* PowerPC 4xx MMU with software TLB */ POWERPC_MMU_SOFT_4xx = 0x00000004, - /* PowerPC 4xx MMU with software TLB and zones protections */ - POWERPC_MMU_SOFT_4xx_Z = 0x00000005, /* PowerPC MMU in real mode only */ POWERPC_MMU_REAL = 0x00000006, /* Freescale MPC8xx MMU model */ @@ -94,8 +96,6 @@ enum powerpc_excp_t { POWERPC_EXCP_602, /* PowerPC 603 exception model */ POWERPC_EXCP_603, - /* PowerPC 603e exception model */ - POWERPC_EXCP_603E, /* PowerPC G2 exception model */ POWERPC_EXCP_G2, /* PowerPC 604 exception model */ @@ -147,8 +147,6 @@ enum powerpc_input_t { PPC_FLAGS_INPUT_POWER7, /* PowerPC POWER9 bus */ PPC_FLAGS_INPUT_POWER9, - /* PowerPC 401 bus */ - PPC_FLAGS_INPUT_401, /* Freescale RCPU bus */ PPC_FLAGS_INPUT_RCPU, }; diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index f933d9f2bd..d7b42bae52 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -112,7 +112,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env) void ppc_store_fpscr(CPUPPCState *env, target_ulong val) { - val &= ~(FP_VX | FP_FEX); + val &= FPSCR_MTFS_MASK; if (val & FPSCR_IX) { val |= FP_VX; } diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index e946da5f3a..fc66c3561d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -296,6 +296,16 @@ typedef struct ppc_v3_pate_t { uint64_t dw1; } ppc_v3_pate_t; +/* PMU related structs and defines */ +#define PMU_COUNTERS_NUM 6 +typedef enum { + PMU_EVENT_INVALID = 0, + PMU_EVENT_INACTIVE, + PMU_EVENT_CYCLES, + PMU_EVENT_INSTRUCTIONS, + PMU_EVENT_INSN_RUN_LATCH, +} PMUEventType; + /*****************************************************************************/ /* Machine state register bits definition */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */ @@ -351,6 +361,11 @@ typedef struct ppc_v3_pate_t { #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ #define MMCR0_PMCC0 PPC_BIT(44) /* PMC Control bit 0 */ #define MMCR0_PMCC1 PPC_BIT(45) /* PMC Control bit 1 */ +#define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ +#define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ +#define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ @@ -363,6 +378,33 @@ typedef struct ppc_v3_pate_t { #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \ MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0) +#define MMCR1_EVT_SIZE 8 +/* extract64() does a right shift before extracting */ +#define MMCR1_PMC1SEL_START 32 +#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC2SEL_START 40 +#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC3SEL_START 48 +#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC4SEL_START 56 +#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) + +/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ +#define CTRL_RUN PPC_BIT(63) + +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) @@ -630,6 +672,7 @@ enum { HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */ HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */ + HFLAGS_INSN_CNT = 17, /* PMU instruction count enabled */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ @@ -759,6 +802,10 @@ enum { FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ FP_VXSQRT | FP_VXCVI) +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */ +#define FPSCR_MTFS_MASK (~(MAKE_64BIT_MASK(36, 28) | PPC_BIT(28) | \ + FP_FEX | FP_VX | PPC_BIT(52))) + /*****************************************************************************/ /* Vector status and control register */ #define VSCR_NJ 16 /* Vector non-java */ @@ -1191,6 +1238,18 @@ struct CPUPPCState { uint32_t tm_vscr; uint64_t tm_dscr; uint64_t tm_tar; + + /* + * Timers used to fire performance monitor alerts + * when counting cycles. + */ + QEMUTimer *pmu_cyc_overflow_timers[PMU_COUNTERS_NUM]; + + /* + * PMU base time value used by the PMU to calculate + * running cycles. + */ + uint64_t pmu_base_time; }; #define SET_FIT_PERIOD(a_, b_, c_, d_) \ @@ -2138,8 +2197,6 @@ enum { PPC_SEGMENT = 0x0000020000000000ULL, /* PowerPC 6xx TLB management instructions */ PPC_6xx_TLB = 0x0000040000000000ULL, - /* PowerPC 74xx TLB management instructions */ - PPC_74xx_TLB = 0x0000080000000000ULL, /* PowerPC 40x TLB management instructions */ PPC_40x_TLB = 0x0000100000000000ULL, /* segment register access instructions for PowerPC 64 "bridge" */ @@ -2196,7 +2253,7 @@ enum { | PPC_CACHE_DCBZ \ | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ - | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ + | PPC_40x_TLB | PPC_SEGMENT_64B \ | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6695985e9b..06ef15cd9e 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -45,6 +45,7 @@ #include "helper_regs.h" #include "internal.h" #include "spr_tcg.h" +#include "power8-pmu.h" /* #define PPC_DEBUG_SPR */ /* #define USE_APPLE_GDB */ @@ -945,31 +946,6 @@ static void register_l3_ctrl(CPUPPCState *env) 0x00000000); } -static void register_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) -{ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = nb_tlbs; - env->nb_ways = nb_ways; - env->id_tlbs = 1; - env->tlb_type = TLB_6XX; - /* XXX : not implemented */ - spr_register(env, SPR_PTEHI, "PTEHI", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_PTELO, "PTELO", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_TLBMISS, "TLBMISS", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -#endif -} - static void register_usprg3_sprs(CPUPPCState *env) { spr_register(env, SPR_USPRG3, "USPRG3", @@ -1578,169 +1554,6 @@ static void register_405_sprs(CPUPPCState *env) register_usprgh_sprs(env); } -/* SPR shared between PowerPC 401 & 403 implementations */ -static void register_401_403_sprs(CPUPPCState *env) -{ - /* Time base */ - spr_register(env, SPR_403_VTBL, "TBL", - &spr_read_tbl, SPR_NOACCESS, - &spr_read_tbl, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_403_TBL, "TBL", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbl, - 0x00000000); - spr_register(env, SPR_403_VTBU, "TBU", - &spr_read_tbu, SPR_NOACCESS, - &spr_read_tbu, SPR_NOACCESS, - 0x00000000); - spr_register(env, SPR_403_TBU, "TBU", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_tbu, - 0x00000000); - /* Debug */ - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_403_CDBCR, "CDBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 401 implementation */ -static void register_401_sprs(CPUPPCState *env) -{ - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Storage control */ - /* XXX: TODO: not implemented */ - spr_register(env, SPR_405_SLER, "SLER", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_sler, - 0x00000000); - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void register_401x2_sprs(CPUPPCState *env) -{ - register_401_sprs(env); - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC 403 implementation */ -static void register_403_sprs(CPUPPCState *env) -{ - /* Debug interface */ - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBCR0, "DBCR0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_40x_dbcr0, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DBSR, "DBSR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_clear, - /* Last reset was system reset */ - 0x00000300); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC1, "DAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_DAC2, "DAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC1, "IAC1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_40x_IAC2, "IAC2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -static void register_403_real_sprs(CPUPPCState *env) -{ - spr_register(env, SPR_403_PBL1, "PBL1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBU1, "PBU1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBL2, "PBL2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); - spr_register(env, SPR_403_PBU2, "PBU2", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_403_pbr, &spr_write_403_pbr, - 0x00000000); -} - -static void register_403_mmu_sprs(CPUPPCState *env) -{ - /* MMU */ - spr_register(env, SPR_40x_PID, "PID", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register(env, SPR_40x_ZPR, "ZPR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} - -/* SPR specific to PowerPC compression coprocessor extension */ -static void register_compress_sprs(CPUPPCState *env) -{ - /* XXX : not implemented */ - spr_register(env, SPR_401_SKR, "SKR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); -} static void register_5xx_8xx_sprs(CPUPPCState *env) { @@ -2128,26 +1941,6 @@ static void register_8xx_sprs(CPUPPCState *env) /*****************************************************************************/ /* Exception vectors models */ -static void init_excp_4xx_real(CPUPPCState *env) -{ -#if !defined(CONFIG_USER_ONLY) - env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; - env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; - env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; - env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; - env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; - env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; - env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; - env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; - env->ivor_mask = 0x0000FFF0UL; - env->ivpr_mask = 0xFFFF0000UL; - /* Hardware reset vector */ - env->hreset_vector = 0xFFFFFFFCUL; -#endif -} - static void init_excp_4xx_softmmu(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -2180,7 +1973,7 @@ static void init_excp_MPC5xx(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; @@ -2207,7 +2000,7 @@ static void init_excp_MPC8xx(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; - env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; + env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; @@ -2273,8 +2066,14 @@ static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; + /* + * These two are the same IVOR as POWERPC_EXCP_VPU and + * POWERPC_EXCP_VPUA. We deal with that when dispatching at + * powerpc_excp(). + */ env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; + env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; env->ivor_mask = 0x0000FFF7UL; env->ivpr_mask = ivpr_mask; @@ -2537,9 +2336,6 @@ static void init_excp_7450(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; - env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; - env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; - env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; @@ -2690,335 +2486,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env) \ static void glue(glue(ppc_, _name), _cpu_family_class_init) -static void init_proc_401(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401_sprs(env); - init_excp_4xx_real(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401"; - pcc->init_proc = init_proc_401; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_WRTEE | PPC_DCR | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_401x2(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401x2_sprs(env); - register_compress_sprs(env); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401x2"; - pcc->init_proc = init_proc_401x2; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_401x3(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401_sprs(env); - register_401x2_sprs(env); - register_compress_sprs(env); - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(12, 16, 20, 24); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 401x3"; - pcc->init_proc = init_proc_401x3; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DWE) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_IOP480(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_401x2_sprs(env); - register_compress_sprs(env); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "IOP480"; - pcc->init_proc = init_proc_IOP480; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | PPC_CACHE_DCBA | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << 20) | - (1ull << MSR_KEY) | - (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_DE) | - (1ull << MSR_IR) | - (1ull << MSR_DR) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_403(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_403_sprs(env); - register_403_real_sprs(env); - init_excp_4xx_real(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(403)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 403"; - pcc->init_proc = init_proc_403; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_PE) | - (1ull << MSR_PX) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_REAL; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | - POWERPC_FLAG_BUS_CLK; -} - -static void init_proc_403GCX(CPUPPCState *env) -{ - register_40x_sprs(env); - register_401_403_sprs(env); - register_403_sprs(env); - register_403_real_sprs(env); - register_403_mmu_sprs(env); - /* Bus access control */ - /* not emulated, as QEMU never does speculative access */ - spr_register(env, SPR_40x_SGR, "SGR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0xFFFFFFFF); - /* not emulated, as QEMU do not emulate caches */ - spr_register(env, SPR_40x_DCWR, "DCWR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ -#if !defined(CONFIG_USER_ONLY) - env->nb_tlb = 64; - env->nb_ways = 1; - env->id_tlbs = 0; - env->tlb_type = TLB_EMB; -#endif - init_excp_4xx_softmmu(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc40x_irq_init(env_archcpu(env)); - - SET_FIT_PERIOD(8, 12, 16, 20); - SET_WDT_PERIOD(16, 20, 24, 28); -} - -POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); - - dc->desc = "PowerPC 403 GCX"; - pcc->init_proc = init_proc_403GCX; - pcc->check_pow = check_pow_nocheck; - pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | - PPC_DCR | PPC_WRTEE | - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | - PPC_CACHE_DCBZ | - PPC_MEM_SYNC | PPC_MEM_EIEIO | - PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | - PPC_4xx_COMMON | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | - (1ull << MSR_CE) | - (1ull << MSR_ILE) | - (1ull << MSR_EE) | - (1ull << MSR_PR) | - (1ull << MSR_ME) | - (1ull << MSR_PE) | - (1ull << MSR_PX) | - (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; - pcc->excp_model = POWERPC_EXCP_40x; - pcc->bus_model = PPC_FLAGS_INPUT_401; - pcc->bfd_mach = bfd_mach_ppc_403; - pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | - POWERPC_FLAG_BUS_CLK; -} - static void init_proc_405(CPUPPCState *env) { /* Time base */ @@ -4607,6 +4074,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) (1ull << MSR_IR) | (1ull << MSR_DR); pcc->mmu_model = POWERPC_MMU_601; + pcc->excp_model = POWERPC_EXCP_601; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_601; pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; @@ -4749,41 +4217,13 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data) POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; } -static void init_proc_603E(CPUPPCState *env) -{ - register_ne_601_sprs(env); - register_sdr1_sprs(env); - register_603_sprs(env); - /* Time base */ - register_tbl(env); - /* hardware implementation registers */ - /* XXX : not implemented */ - spr_register(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* XXX : not implemented */ - spr_register(env, SPR_HID1, "HID1", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - /* Memory management */ - register_low_BATs(env); - register_6xx_7xx_soft_tlb(env, 64, 2); - init_excp_603(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; - /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(env_archcpu(env)); -} - POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); dc->desc = "PowerPC 603e"; - pcc->init_proc = init_proc_603E; + pcc->init_proc = init_proc_603; pcc->check_pow = check_pow_hid0; pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | @@ -4809,7 +4249,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) (1ull << MSR_RI) | (1ull << MSR_LE); pcc->mmu_model = POWERPC_MMU_SOFT_6xx; - pcc->excp_model = POWERPC_EXCP_603E; + pcc->excp_model = POWERPC_EXCP_603; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_ec603e; pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | @@ -5932,7 +5372,6 @@ static void init_proc_7440(CPUPPCState *env) 0x00000000); /* Memory management */ register_low_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -5956,7 +5395,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -5976,7 +5415,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6067,7 +5506,6 @@ static void init_proc_7450(CPUPPCState *env) 0x00000000); /* Memory management */ register_low_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6091,7 +5529,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6111,7 +5549,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6205,7 +5643,6 @@ static void init_proc_7445(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6229,7 +5666,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6249,7 +5686,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6345,7 +5782,6 @@ static void init_proc_7455(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6369,7 +5805,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6389,7 +5825,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6509,7 +5945,6 @@ static void init_proc_7457(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6533,7 +5968,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->msr_mask = (1ull << MSR_VR) | @@ -6553,7 +5988,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - pcc->mmu_model = POWERPC_MMU_SOFT_74xx; + pcc->mmu_model = POWERPC_MMU_32B; pcc->excp_model = POWERPC_EXCP_74xx; pcc->bus_model = PPC_FLAGS_INPUT_6xx; pcc->bfd_mach = bfd_mach_ppc_7400; @@ -6648,7 +6083,6 @@ static void init_proc_e600(CPUPPCState *env) /* Memory management */ register_low_BATs(env); register_high_BATs(env); - register_74xx_soft_tlb(env, 128, 2); init_excp_7450(env); env->dcache_line_size = 32; env->icache_line_size = 32; @@ -6672,7 +6106,7 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) PPC_CACHE_DCBA | PPC_CACHE_DCBZ | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | - PPC_MEM_TLBIA | PPC_74xx_TLB | + PPC_MEM_TLBIA | PPC_SEGMENT | PPC_EXTERN | PPC_ALTIVEC; pcc->insns_flags2 = PPC_NONE; @@ -6748,7 +6182,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *env) { spr_register(env, SPR_CTRL, "SPR_CTRL", SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, &spr_write_generic, + SPR_NOACCESS, &spr_write_CTRL, 0x00000000); spr_register(env, SPR_UCTRL, "SPR_UCTRL", &spr_read_ureg, SPR_NOACCESS, @@ -6820,11 +6254,11 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) { spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - KVM_REG_PPC_MMCR0, 0x00000000); + &spr_read_generic, &spr_write_MMCR0, + KVM_REG_PPC_MMCR0, 0x80000000); spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_MMCR1, KVM_REG_PPC_MMCR1, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", SPR_NOACCESS, SPR_NOACCESS, @@ -6832,27 +6266,27 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState *env) KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC1, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC2, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC3, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC4, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC5, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_PMC, &spr_write_PMC, KVM_REG_PPC_PMC6, 0x00000000); spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, @@ -6869,7 +6303,7 @@ static void register_book3s_pmu_user_sprs(CPUPPCState *env) spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, &spr_read_ureg, &spr_write_ureg, - 0x00000000); + 0x80000000); spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, &spr_write_ureg, @@ -7377,6 +6811,20 @@ static void register_power9_mmu_sprs(CPUPPCState *env) #endif } +/* + * Initialize PMU counter overflow timers for Power8 and + * newer Power chips when using TCG. + */ +static void init_tcg_pmu_power8(CPUPPCState *env) +{ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + /* Init PMU overflow timers */ + if (!kvm_enabled()) { + cpu_ppc_pmu_init(env); + } +#endif +} + static void init_proc_book3s_common(CPUPPCState *env) { register_ne_601_sprs(env); @@ -7694,6 +7142,9 @@ static void init_proc_POWER8(CPUPPCState *env) register_sdr1_sprs(env); register_book3s_207_dbg_sprs(env); + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_rmor_sprs(env); @@ -7888,6 +7339,9 @@ static void init_proc_POWER9(CPUPPCState *env) init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_amr_sprs(env); @@ -8104,6 +7558,9 @@ static void init_proc_POWER10(CPUPPCState *env) init_proc_book3s_common(env); register_book3s_207_dbg_sprs(env); + /* Common TCG PMU */ + init_tcg_pmu_power8(env); + /* POWER8 Specific Registers */ register_book3s_ids_sprs(env); register_amr_sprs(env); @@ -9247,7 +8704,6 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) case POWERPC_MMU_32B: case POWERPC_MMU_601: case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: #if defined(TARGET_PPC64) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 17607adbe4..f90e616aac 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -344,6 +344,16 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) excp = POWERPC_EXCP_PROGRAM; } +#ifdef TARGET_PPC64 + /* + * SPEU and VPU share the same IVOR but they exist in different + * processors. SPEU is e500v1/2 only and VPU is e6500 only. + */ + if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) { + excp = POWERPC_EXCP_SPEU; + } +#endif + switch (excp) { case POWERPC_EXCP_NONE: /* Should never happen */ @@ -454,15 +464,13 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ + /* Get rS/rD and rA from faulting opcode */ /* - * Get rS/rD and rA from faulting opcode. - * Note: We will only invoke ALIGN for atomic operations, - * so all instructions are X-form. + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. */ - { - uint32_t insn = cpu_ldl_code(env, env->nip); - env->spr[SPR_DSISR] |= (insn & 0x03FF0000) >> 16; - } + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { @@ -569,7 +577,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) cpu_abort(cs, "Debug exception triggered on unsupported model\n"); } break; - case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ + case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */ env->spr[SPR_BOOKE_ESR] = ESR_SPV; break; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ @@ -672,7 +680,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) switch (excp_model) { case POWERPC_EXCP_602: case POWERPC_EXCP_603: - case POWERPC_EXCP_603E: case POWERPC_EXCP_G2: /* Swap temporary saved registers with GPRs */ if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { @@ -714,35 +721,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Set way using a LRU mechanism */ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; break; - case POWERPC_EXCP_74xx: -#if defined(DEBUG_SOFTWARE_TLB) - if (qemu_log_enabled()) { - const char *es; - target_ulong *miss, *cmp; - int en; - - if (excp == POWERPC_EXCP_IFTLB) { - es = "I"; - en = 'I'; - miss = &env->spr[SPR_TLBMISS]; - cmp = &env->spr[SPR_PTEHI]; - } else { - if (excp == POWERPC_EXCP_DLTLB) { - es = "DL"; - } else { - es = "DS"; - } - en = 'D'; - miss = &env->spr[SPR_TLBMISS]; - cmp = &env->spr[SPR_PTEHI]; - } - qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " - TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, - env->error_code); - } -#endif - msr |= env->error_code; /* key bit */ - break; default: cpu_abort(cs, "Invalid TLB miss exception\n"); break; @@ -1250,6 +1228,37 @@ void helper_hrfid(CPUPPCState *env) } #endif +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void helper_rfebb(CPUPPCState *env, target_ulong s) +{ + target_ulong msr = env->msr; + + /* + * Handling of BESCR bits 32:33 according to PowerISA v3.1: + * + * "If BESCR 32:33 != 0b00 the instruction is treated as if + * the instruction form were invalid." + */ + if (env->spr[SPR_BESCR] & BESCR_INVALID) { + raise_exception_err(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } + + env->nip = env->spr[SPR_EBBRR]; + + /* Switching to 32-bit ? Crop the nip */ + if (!msr_is_64bit(env, msr)) { + env->nip = (uint32_t)env->spr[SPR_EBBRR]; + } + + if (s) { + env->spr[SPR_BESCR] |= BESCR_GE; + } else { + env->spr[SPR_BESCR] &= ~BESCR_GE; + } +} +#endif + /*****************************************************************************/ /* Embedded PowerPC specific helpers */ void helper_40x_rfci(CPUPPCState *env) @@ -1461,10 +1470,14 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { CPUPPCState *env = cs->env_ptr; + uint32_t insn; + + /* Restore state and reload the insn we executed, for filling in DSISR. */ + cpu_restore_state(cs, retaddr, true); + insn = cpu_ldl_code(env, env->nip); switch (env->mmu_model) { case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: env->spr[SPR_40x_DEAR] = vaddr; break; case POWERPC_MMU_BOOKE: @@ -1477,8 +1490,8 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, } cs->exception_index = POWERPC_EXCP_ALIGN; - env->error_code = 0; - cpu_loop_exit_restore(cs, retaddr); + env->error_code = insn & 0x03FF0000; + cpu_loop_exit(cs); } #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c4896cecc8..700c79156b 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -414,6 +414,54 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles) ppc_store_fpscr(env, val); } +void helper_fpscr_check_status(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong fpscr = env->fpscr; + int error = 0; + + if ((fpscr & FP_OX) && (fpscr & FP_OE)) { + error = POWERPC_EXCP_FP_OX; + } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { + error = POWERPC_EXCP_FP_UX; + } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { + error = POWERPC_EXCP_FP_XX; + } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { + error = POWERPC_EXCP_FP_ZX; + } else if (fpscr & FP_VE) { + if (fpscr & FP_VXSOFT) { + error = POWERPC_EXCP_FP_VXSOFT; + } else if (fpscr & FP_VXSNAN) { + error = POWERPC_EXCP_FP_VXSNAN; + } else if (fpscr & FP_VXISI) { + error = POWERPC_EXCP_FP_VXISI; + } else if (fpscr & FP_VXIDI) { + error = POWERPC_EXCP_FP_VXIDI; + } else if (fpscr & FP_VXZDZ) { + error = POWERPC_EXCP_FP_VXZDZ; + } else if (fpscr & FP_VXIMZ) { + error = POWERPC_EXCP_FP_VXIMZ; + } else if (fpscr & FP_VXVC) { + error = POWERPC_EXCP_FP_VXVC; + } else if (fpscr & FP_VXSQRT) { + error = POWERPC_EXCP_FP_VXSQRT; + } else if (fpscr & FP_VXCVI) { + error = POWERPC_EXCP_FP_VXCVI; + } else { + return; + } + } else { + return; + } + cs->exception_index = POWERPC_EXCP_PROGRAM; + env->error_code = error | POWERPC_EXCP_FP; + /* Deferred floating-point exception after target FPSCR update */ + if (fp_exceptions_enabled(env)) { + raise_exception_err_ra(env, cs->exception_index, + env->error_code, GETPC()); + } +} + static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { CPUState *cs = env_cpu(env); @@ -450,13 +498,12 @@ void helper_reset_fpstatus(CPUPPCState *env) set_float_exception_flags(0, &env->fp_status); } -static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc, - uintptr_t retaddr, int classes) +static void float_invalid_op_addsub(CPUPPCState *env, int flags, + bool set_fpcc, uintptr_t retaddr) { - if ((classes & ~is_neg) == is_inf) { - /* Magnitude subtraction of infinities */ + if (flags & float_flag_invalid_isi) { float_invalid_op_vxisi(env, set_fpcc, retaddr); - } else if (classes & is_snan) { + } else if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -465,39 +512,58 @@ static void float_invalid_op_addsub(CPUPPCState *env, bool set_fpcc, float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_add(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); } return ret; } +/* fadds - fadds. */ +float64 helper_fadds(CPUPPCState *env, float64 arg1, float64 arg2) +{ + float64 ret = float64r32_add(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); + } + return ret; +} + /* fsub - fsub. */ float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_sub(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); } return ret; } -static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc, - uintptr_t retaddr, int classes) +/* fsubs - fsubs. */ +float64 helper_fsubs(CPUPPCState *env, float64 arg1, float64 arg2) { - if ((classes & (is_zero | is_inf)) == (is_zero | is_inf)) { - /* Multiplication of zero by infinity */ + float64 ret = float64r32_sub(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_addsub(env, flags, 1, GETPC()); + } + return ret; +} + +static void float_invalid_op_mul(CPUPPCState *env, int flags, + bool set_fprc, uintptr_t retaddr) +{ + if (flags & float_flag_invalid_imz) { float_invalid_op_vximz(env, set_fprc, retaddr); - } else if (classes & is_snan) { + } else if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -506,28 +572,35 @@ static void float_invalid_op_mul(CPUPPCState *env, bool set_fprc, float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_mul(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - float_invalid_op_mul(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_mul(env, flags, 1, GETPC()); } return ret; } -static void float_invalid_op_div(CPUPPCState *env, bool set_fprc, - uintptr_t retaddr, int classes) +/* fmuls - fmuls. */ +float64 helper_fmuls(CPUPPCState *env, float64 arg1, float64 arg2) { - classes &= ~is_neg; - if (classes == is_inf) { - /* Division of infinity by infinity */ + float64 ret = float64r32_mul(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_mul(env, flags, 1, GETPC()); + } + return ret; +} + +static void float_invalid_op_div(CPUPPCState *env, int flags, + bool set_fprc, uintptr_t retaddr) +{ + if (flags & float_flag_invalid_idi) { float_invalid_op_vxidi(env, set_fprc, retaddr); - } else if (classes == is_zero) { - /* Division of zero by zero */ + } else if (flags & float_flag_invalid_zdz) { float_invalid_op_vxzdz(env, set_fprc, retaddr); - } else if (classes & is_snan) { + } else if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, retaddr); } } @@ -536,43 +609,57 @@ static void float_invalid_op_div(CPUPPCState *env, bool set_fprc, float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2) { float64 ret = float64_div(arg1, arg2, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - float_invalid_op_div(env, 1, GETPC(), - float64_classify(arg1) | - float64_classify(arg2)); - } - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, GETPC()); - } + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_div(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); } return ret; } -static void float_invalid_cvt(CPUPPCState *env, bool set_fprc, - uintptr_t retaddr, int class1) +/* fdivs - fdivs. */ +float64 helper_fdivs(CPUPPCState *env, float64 arg1, float64 arg2) { - float_invalid_op_vxcvi(env, set_fprc, retaddr); - if (class1 & is_snan) { - float_invalid_op_vxsnan(env, retaddr); + float64 ret = float64r32_div(arg1, arg2, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_div(env, flags, 1, GETPC()); } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + } + + return ret; +} + +static uint64_t float_invalid_cvt(CPUPPCState *env, int flags, + uint64_t ret, uint64_t ret_nan, + bool set_fprc, uintptr_t retaddr) +{ + /* + * VXCVI is different from most in that it sets two exception bits, + * VXCVI and VXSNAN for an SNaN input. + */ + if (flags & float_flag_invalid_snan) { + env->fpscr |= FP_VXSNAN; + } + float_invalid_op_vxcvi(env, set_fprc, retaddr); + + return flags & float_flag_invalid_cvti ? ret : ret_nan; } #define FPU_FCTI(op, cvt, nanval) \ uint64_t helper_##op(CPUPPCState *env, float64 arg) \ { \ uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \ - int status = get_float_exception_flags(&env->fp_status); \ - \ - if (unlikely(status)) { \ - if (status & float_flag_invalid) { \ - float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \ - ret = nanval; \ - } \ - do_float_check_status(env, GETPC()); \ + int flags = get_float_exception_flags(&env->fp_status); \ + if (unlikely(flags & float_flag_invalid)) { \ + ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \ } \ return ret; \ } @@ -606,32 +693,26 @@ FPU_FCFI(fcfids, int64_to_float32, 1) FPU_FCFI(fcfidu, uint64_to_float64, 0) FPU_FCFI(fcfidus, uint64_to_float32, 1) -static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg, - int rounding_mode) +static uint64_t do_fri(CPUPPCState *env, uint64_t arg, + FloatRoundMode rounding_mode) { - CPU_DoubleU farg; FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status); + int flags; - farg.ll = arg; + set_float_rounding_mode(rounding_mode, &env->fp_status); + arg = float64_round_to_int(arg, &env->fp_status); + set_float_rounding_mode(old_rounding_mode, &env->fp_status); - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN round */ + flags = get_float_exception_flags(&env->fp_status); + if (flags & float_flag_invalid_snan) { float_invalid_op_vxsnan(env, GETPC()); - farg.ll = arg | 0x0008000000000000ULL; - } else { - int inexact = get_float_exception_flags(&env->fp_status) & - float_flag_inexact; - set_float_rounding_mode(rounding_mode, &env->fp_status); - farg.ll = float64_round_to_int(farg.d, &env->fp_status); - set_float_rounding_mode(old_rounding_mode, &env->fp_status); - - /* fri* does not set FPSCR[XX] */ - if (!inexact) { - env->fp_status.float_exception_flags &= ~float_flag_inexact; - } } + + /* fri* does not set FPSCR[XX] */ + set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status); do_float_check_status(env, GETPC()); - return farg.ll; + + return arg; } uint64_t helper_frin(CPUPPCState *env, uint64_t arg) @@ -654,57 +735,48 @@ uint64_t helper_frim(CPUPPCState *env, uint64_t arg) return do_fri(env, arg, float_round_down); } -#define FPU_MADDSUB_UPDATE(NAME, TP) \ -static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \ - unsigned int madd_flags, uintptr_t retaddr) \ -{ \ - if (TP##_is_signaling_nan(arg1, &env->fp_status) || \ - TP##_is_signaling_nan(arg2, &env->fp_status) || \ - TP##_is_signaling_nan(arg3, &env->fp_status)) { \ - /* sNaN operation */ \ - float_invalid_op_vxsnan(env, retaddr); \ - } \ - if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \ - (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \ - /* Multiplication of zero by infinity */ \ - float_invalid_op_vximz(env, 1, retaddr); \ - } \ - if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \ - TP##_is_infinity(arg3)) { \ - uint8_t aSign, bSign, cSign; \ - \ - aSign = TP##_is_neg(arg1); \ - bSign = TP##_is_neg(arg2); \ - cSign = TP##_is_neg(arg3); \ - if (madd_flags & float_muladd_negate_c) { \ - cSign ^= 1; \ - } \ - if (aSign ^ bSign ^ cSign) { \ - float_invalid_op_vxisi(env, 1, retaddr); \ - } \ - } \ +static void float_invalid_op_madd(CPUPPCState *env, int flags, + bool set_fpcc, uintptr_t retaddr) +{ + if (flags & float_flag_invalid_imz) { + float_invalid_op_vximz(env, set_fpcc, retaddr); + } else { + float_invalid_op_addsub(env, flags, set_fpcc, retaddr); + } } -FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32) -FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64) -#define FPU_FMADD(op, madd_flags) \ -uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ - uint64_t arg2, uint64_t arg3) \ -{ \ - uint32_t flags; \ - float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \ - &env->fp_status); \ - flags = get_float_exception_flags(&env->fp_status); \ - if (flags) { \ - if (flags & float_flag_invalid) { \ - float64_maddsub_update_excp(env, arg1, arg2, arg3, \ - madd_flags, GETPC()); \ - } \ - do_float_check_status(env, GETPC()); \ - } \ - return ret; \ +static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b, + float64 c, int madd_flags, uintptr_t retaddr) +{ + float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_madd(env, flags, 1, retaddr); + } + return ret; } +static uint64_t do_fmadds(CPUPPCState *env, float64 a, float64 b, + float64 c, int madd_flags, uintptr_t retaddr) +{ + float64 ret = float64r32_muladd(a, b, c, madd_flags, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_madd(env, flags, 1, retaddr); + } + return ret; +} + +#define FPU_FMADD(op, madd_flags) \ + uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \ + uint64_t arg2, uint64_t arg3) \ + { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); } \ + uint64_t helper_##op##s(CPUPPCState *env, uint64_t arg1, \ + uint64_t arg2, uint64_t arg3) \ + { return do_fmadds(env, arg1, arg2, arg3, madd_flags, GETPC()); } + #define MADD_FLGS 0 #define MSUB_FLGS float_muladd_negate_c #define NMADD_FLGS float_muladd_negate_result @@ -716,62 +788,71 @@ FPU_FMADD(fmsub, MSUB_FLGS) FPU_FMADD(fnmsub, NMSUB_FLGS) /* frsp - frsp. */ +static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr) +{ + float32 f32 = float64_to_float32(arg, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, retaddr); + } + return helper_todouble(f32); +} + uint64_t helper_frsp(CPUPPCState *env, uint64_t arg) { - CPU_DoubleU farg; - float32 f32; + return do_frsp(env, arg, GETPC()); +} - farg.ll = arg; - - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - float_invalid_op_vxsnan(env, GETPC()); +static void float_invalid_op_sqrt(CPUPPCState *env, int flags, + bool set_fpcc, uintptr_t retaddr) +{ + if (unlikely(flags & float_flag_invalid_sqrt)) { + float_invalid_op_vxsqrt(env, set_fpcc, retaddr); + } else if (unlikely(flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, retaddr); } - f32 = float64_to_float32(farg.d, &env->fp_status); - farg.d = float32_to_float64(f32, &env->fp_status); - - return farg.ll; } /* fsqrt - fsqrt. */ float64 helper_fsqrt(CPUPPCState *env, float64 arg) { float64 ret = float64_sqrt(arg, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status & float_flag_invalid)) { - if (unlikely(float64_is_any_nan(arg))) { - if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) { - /* sNaN square root */ - float_invalid_op_vxsnan(env, GETPC()); - } - } else { - /* Square root of a negative nonzero number */ - float_invalid_op_vxsqrt(env, 1, GETPC()); - } + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); } return ret; } +/* fsqrts - fsqrts. */ +float64 helper_fsqrts(CPUPPCState *env, float64 arg) +{ + float64 ret = float64r32_sqrt(arg, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); + } + return ret; +} + /* fre - fre. */ float64 helper_fre(CPUPPCState *env, float64 arg) { /* "Estimate" the reciprocal with actual division. */ float64 ret = float64_div(float64_one, arg, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - if (float64_is_signaling_nan(arg, &env->fp_status)) { - /* sNaN reciprocal */ - float_invalid_op_vxsnan(env, GETPC()); - } - } - if (status & float_flag_divbyzero) { - float_zero_divide_excp(env, GETPC()); - /* For FPSCR.ZE == 0, the result is 1/2. */ - ret = float64_set_sign(float64_half, float64_is_neg(arg)); - } + if (unlikely(flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE == 0, the result is 1/2. */ + ret = float64_set_sign(float64_half, float64_is_neg(arg)); } return ret; @@ -780,20 +861,20 @@ float64 helper_fre(CPUPPCState *env, float64 arg) /* fres - fres. */ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) { - CPU_DoubleU farg; - float32 f32; + /* "Estimate" the reciprocal with actual division. */ + float64 ret = float64r32_div(float64_one, arg, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - farg.ll = arg; - - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal */ + if (unlikely(flags & float_flag_invalid_snan)) { float_invalid_op_vxsnan(env, GETPC()); } - farg.d = float64_div(float64_one, farg.d, &env->fp_status); - f32 = float64_to_float32(farg.d, &env->fp_status); - farg.d = float32_to_float64(f32, &env->fp_status); + if (unlikely(flags & float_flag_divbyzero)) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE == 0, the result is 1/2. */ + ret = float64_set_sign(float64_half, float64_is_neg(arg)); + } - return farg.ll; + return ret; } /* frsqrte - frsqrte. */ @@ -802,22 +883,33 @@ float64 helper_frsqrte(CPUPPCState *env, float64 arg) /* "Estimate" the reciprocal with actual division. */ float64 rets = float64_sqrt(arg, &env->fp_status); float64 retd = float64_div(float64_one, rets, &env->fp_status); - int status = get_float_exception_flags(&env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); - if (unlikely(status)) { - if (status & float_flag_invalid) { - if (float64_is_signaling_nan(arg, &env->fp_status)) { - /* sNaN reciprocal */ - float_invalid_op_vxsnan(env, GETPC()); - } else { - /* Square root of a negative nonzero number */ - float_invalid_op_vxsqrt(env, 1, GETPC()); - } - } - if (status & float_flag_divbyzero) { - /* Reciprocal of (square root of) zero. */ - float_zero_divide_excp(env, GETPC()); - } + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + /* Reciprocal of (square root of) zero. */ + float_zero_divide_excp(env, GETPC()); + } + + return retd; +} + +/* frsqrtes - frsqrtes. */ +float64 helper_frsqrtes(CPUPPCState *env, float64 arg) +{ + /* "Estimate" the reciprocal with actual division. */ + float64 rets = float64_sqrt(arg, &env->fp_status); + float64 retd = float64r32_div(float64_one, rets, &env->fp_status); + int flags = get_float_exception_flags(&env->fp_status); + + if (unlikely(flags & float_flag_invalid)) { + float_invalid_op_sqrt(env, flags, 1, GETPC()); + } + if (unlikely(flags & float_flag_divbyzero)) { + /* Reciprocal of (square root of) zero. */ + float_zero_divide_excp(env, GETPC()); } return retd; @@ -1616,13 +1708,12 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_addsub(env, sfprf, GETPC(), \ - tp##_classify(xa->fld) | \ - tp##_classify(xb->fld)); \ + float_invalid_op_addsub(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1660,9 +1751,7 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); @@ -1695,13 +1784,12 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_mul(env, sfprf, GETPC(), \ - tp##_classify(xa->fld) | \ - tp##_classify(xb->fld)); \ + float_invalid_op_mul(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1735,9 +1823,7 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_mul(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); @@ -1769,16 +1855,15 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - float_invalid_op_div(env, sfprf, GETPC(), \ - tp##_classify(xa->fld) | \ - tp##_classify(xb->fld)); \ + float_invalid_op_div(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \ float_zero_divide_excp(env, GETPC()); \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1812,9 +1897,7 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_div(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC()); } if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { float_zero_divide_excp(env, GETPC()); @@ -1848,7 +1931,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1888,15 +1971,12 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \ - float_invalid_op_vxsqrt(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_sqrt(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -1935,17 +2015,12 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.fld = tp##_sqrt(xb->fld, &tstat); \ t.fld = tp##_div(tp##_one, t.fld, &tstat); \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ - \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \ - float_invalid_op_vxsqrt(env, sfprf, GETPC()); \ - } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \ - float_invalid_op_vxsnan(env, GETPC()); \ - } \ + float_invalid_op_sqrt(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ - \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -2111,12 +2186,12 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \ \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \ - tp##_maddsub_update_excp(env, xa->fld, b->fld, \ - c->fld, maddflgs, GETPC()); \ + float_invalid_op_madd(env, tstat.float_exception_flags, \ + sfprf, GETPC()); \ } \ \ if (r2sp) { \ - t.fld = helper_frsp(env, t.fld); \ + t.fld = do_frsp(env, t.fld, GETPC()); \ } \ \ if (sfprf) { \ @@ -2420,7 +2495,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i)) VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i)) #define VSX_MAX_MINC(name, max) \ -void helper_##name(CPUPPCState *env, uint32_t opcode, \ +void helper_##name(CPUPPCState *env, \ ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = *xt; \ @@ -2455,7 +2530,7 @@ VSX_MAX_MINC(xsmaxcdp, 1); VSX_MAX_MINC(xsmincdp, 0); #define VSX_MAX_MINJ(name, max) \ -void helper_##name(CPUPPCState *env, uint32_t opcode, \ +void helper_##name(CPUPPCState *env, \ ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = *xt; \ @@ -2676,18 +2751,14 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1) VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0) VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0) -/* - * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be - * added to this later. - */ -void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode, - ppc_vsr_t *xt, ppc_vsr_t *xb) +void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt, + ppc_vsr_t *xb) { ppc_vsr_t t = { }; float_status tstat; tstat = env->fp_status; - if (unlikely(Rc(opcode) != 0)) { + if (ro != 0) { tstat.float_rounding_mode = float_round_to_odd; } @@ -2773,8 +2844,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \ flags = env->fp_status.float_exception_flags; \ if (unlikely(flags & float_flag_invalid)) { \ - float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \ - t.tfld = rnan; \ + t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\ } \ all_flags |= flags; \ } \ @@ -2816,11 +2886,12 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ ppc_vsr_t *xt, ppc_vsr_t *xb) \ { \ ppc_vsr_t t = { }; \ + int flags; \ \ t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \ - if (env->fp_status.float_exception_flags & float_flag_invalid) { \ - float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \ - t.tfld = rnan; \ + flags = get_float_exception_flags(&env->fp_status); \ + if (flags & float_flag_invalid) { \ + t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \ } \ \ *xt = t; \ @@ -2855,7 +2926,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \ for (i = 0; i < nels; i++) { \ t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \ if (r2sp) { \ - t.tfld = helper_frsp(env, t.tfld); \ + t.tfld = do_frsp(env, t.tfld, GETPC()); \ } \ if (sfprf) { \ helper_compute_fprf_float64(env, t.tfld); \ @@ -2980,7 +3051,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb) { helper_reset_fpstatus(env); - uint64_t xt = helper_frsp(env, xb); + uint64_t xt = do_frsp(env, xb, GETPC()); helper_compute_fprf_float64(env, xt); do_float_check_status(env, GETPC()); @@ -3088,26 +3159,25 @@ void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) { uint32_t dcmx, sign, exp; uint32_t cc, match = 0, not_sp = 0; + float64 arg = xb->VsrD(0); + float64 arg_sp; dcmx = DCMX(opcode); - exp = (xb->VsrD(0) >> 52) & 0x7FF; + exp = (arg >> 52) & 0x7FF; + sign = float64_is_neg(arg); - sign = float64_is_neg(xb->VsrD(0)); - if (float64_is_any_nan(xb->VsrD(0))) { + if (float64_is_any_nan(arg)) { match = extract32(dcmx, 6, 1); - } else if (float64_is_infinity(xb->VsrD(0))) { + } else if (float64_is_infinity(arg)) { match = extract32(dcmx, 4 + !sign, 1); - } else if (float64_is_zero(xb->VsrD(0))) { + } else if (float64_is_zero(arg)) { match = extract32(dcmx, 2 + !sign, 1); - } else if (float64_is_zero_or_denormal(xb->VsrD(0)) || - (exp > 0 && exp < 0x381)) { + } else if (float64_is_zero_or_denormal(arg) || (exp > 0 && exp < 0x381)) { match = extract32(dcmx, 0 + !sign, 1); } - not_sp = !float64_eq(xb->VsrD(0), - float32_to_float64( - float64_to_float32(xb->VsrD(0), &env->fp_status), - &env->fp_status), &env->fp_status); + arg_sp = helper_todouble(helper_tosingle(arg)); + not_sp = arg != arg_sp; cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT; env->fpscr &= ~FP_FPCC; @@ -3156,11 +3226,8 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode, t.f128 = float128_round_to_int(xb->f128, &tstat); env->fp_status.float_exception_flags |= tstat.float_exception_flags; - if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb->f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - t.f128 = float128_snan_to_qnan(t.f128); - } + if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); } if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) { @@ -3214,11 +3281,9 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode, t.f128 = floatx80_to_float128(round_res, &tstat); env->fp_status.float_exception_flags |= tstat.float_exception_flags; - if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb->f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - t.f128 = float128_snan_to_qnan(t.f128); - } + if (unlikely(tstat.float_exception_flags & float_flag_invalid_snan)) { + float_invalid_op_vxsnan(env, GETPC()); + t.f128 = float128_snan_to_qnan(t.f128); } helper_compute_fprf_float128(env, t.f128); @@ -3244,15 +3309,7 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - if (float128_is_signaling_nan(xb->f128, &tstat)) { - float_invalid_op_vxsnan(env, GETPC()); - t.f128 = float128_snan_to_qnan(xb->f128); - } else if (float128_is_quiet_nan(xb->f128, &tstat)) { - t.f128 = xb->f128; - } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128)) { - float_invalid_op_vxsqrt(env, 1, GETPC()); - t.f128 = float128_default_nan(&env->fp_status); - } + float_invalid_op_sqrt(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); @@ -3278,9 +3335,7 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode, env->fp_status.float_exception_flags |= tstat.float_exception_flags; if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { - float_invalid_op_addsub(env, 1, GETPC(), - float128_classify(xa->f128) | - float128_classify(xb->f128)); + float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC()); } helper_compute_fprf_float128(env, t.f128); diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 627811cefc..fb6cac38b4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,8 +18,14 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_mmcr0, void, env, tl) +DEF_HELPER_2(store_mmcr1, void, env, tl) +DEF_HELPER_3(store_pmc, void, env, i32, i64) +DEF_HELPER_2(read_pmc, tl, env, i32) +DEF_HELPER_2(insns_inc, void, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) @@ -63,6 +69,7 @@ DEF_HELPER_FLAGS_1(cntlzw32, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_1(float_check_status, void, env) +DEF_HELPER_1(fpscr_check_status, void, env) DEF_HELPER_1(reset_fpstatus, void, env) DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) @@ -93,17 +100,27 @@ DEF_HELPER_2(frip, i64, env, i64) DEF_HELPER_2(frim, i64, env, i64) DEF_HELPER_3(fadd, f64, env, f64, f64) +DEF_HELPER_3(fadds, f64, env, f64, f64) DEF_HELPER_3(fsub, f64, env, f64, f64) +DEF_HELPER_3(fsubs, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64) +DEF_HELPER_3(fmuls, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64) +DEF_HELPER_3(fdivs, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fmsub, i64, env, i64, i64, i64) DEF_HELPER_4(fnmadd, i64, env, i64, i64, i64) DEF_HELPER_4(fnmsub, i64, env, i64, i64, i64) +DEF_HELPER_4(fmadds, i64, env, i64, i64, i64) +DEF_HELPER_4(fmsubs, i64, env, i64, i64, i64) +DEF_HELPER_4(fnmadds, i64, env, i64, i64, i64) +DEF_HELPER_4(fnmsubs, i64, env, i64, i64, i64) DEF_HELPER_2(fsqrt, f64, env, f64) +DEF_HELPER_2(fsqrts, f64, env, f64) DEF_HELPER_2(fre, i64, env, i64) DEF_HELPER_2(fres, i64, env, i64) DEF_HELPER_2(frsqrte, i64, env, i64) +DEF_HELPER_2(frsqrtes, i64, env, i64) DEF_HELPER_4(fsel, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ftdiv, TCG_CALL_NO_RWG_SE, i32, i64, i64) @@ -392,15 +409,15 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr) DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr) DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr) -DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr) -DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr) +DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr) +DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr) DEF_HELPER_3(xscvdphp, void, env, vsr, vsr) DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr) DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr) DEF_HELPER_2(xscvdpspn, i64, env, i64) -DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr) +DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr) DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr) DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr) DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr) @@ -614,8 +631,6 @@ DEF_HELPER_2(booke_set_eplc, void, env, tl) DEF_HELPER_2(booke_set_epsc, void, env, tl) DEF_HELPER_2(6xx_tlbd, void, env, tl) DEF_HELPER_2(6xx_tlbi, void, env, tl) -DEF_HELPER_2(74xx_tlbd, void, env, tl) -DEF_HELPER_2(74xx_tlbi, void, env, tl) DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 99562edd57..b847928842 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "helper_regs.h" +#include "power8-pmu.h" /* Swap temporary saved registers with GPRs */ void hreg_swap_gpr_tgpr(CPUPPCState *env) @@ -121,6 +122,12 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) hflags |= 1 << HFLAGS_HV; } +#if defined(TARGET_PPC64) + if (pmu_insn_cnt_enabled(env)) { + hflags |= 1 << HFLAGS_INSN_CNT; + } +#endif + /* * This is our encoding for server processors. The architecture * specifies that there is no such thing as userspace with diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e135b8aba4..2a9c91a423 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -40,6 +40,10 @@ %ds_rtp 22:4 !function=times_2 @DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si +&DX_b vrt b +%dx_b 6:10 16:5 0:1 +@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b + &DX rt d %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d @@ -56,6 +60,9 @@ &VX_uim4 vrt uim vrb @VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4 +&VX_tb vrt vrb +@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X @@ -123,10 +130,14 @@ &X_vrt_frbp vrt frbp @X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp +%xx_xt 0:1 21:5 +%xx_xb 1:1 11:5 +%xx_xa 2:1 16:5 &XX2 xt xb uim:uint8_t -%xx2_xt 0:1 21:5 -%xx2_xb 1:1 11:5 -@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb +@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb + +&XX3 xt xa xb +@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb &Z22_bf_fra bf fra dm @Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra @@ -408,6 +419,27 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN +## Vector Mask Manipulation Instructions + +MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb +MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb +MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb +MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb +MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb +MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b + +VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb +VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb +VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb +VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb +VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb + +VEXTRACTBM 000100 ..... 01000 ..... 11001000010 @VX_tb +VEXTRACTHM 000100 ..... 01001 ..... 11001000010 @VX_tb +VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb +VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb +VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb + # VSX Load/Store Instructions LXV 111101 ..... ..... ............ . 001 @DQ_TSX @@ -427,3 +459,19 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2 ## VSX Vector Load Special Value Instruction LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5 + +## VSX Comparison Instructions + +XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3 +XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3 +XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3 +XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3 + +## VSX Binary Floating-Point Convert Instructions + +XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc + +### rfebb +&XL_s s:uint8_t +@XL_s ......-------------- s:1 .......... - &XL_s +RFEBB 010011-------------- . 0010010010 - @XL_s diff --git a/target/ppc/meson.build b/target/ppc/meson.build index b85f295703..a49a8911e0 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -51,6 +51,7 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-book3s-v3.c', 'mmu-hash64.c', 'mmu-radix64.c', + 'power8-pmu.c', )) target_arch += {'ppc': ppc_ss} diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 754509e556..4e278365ca 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -1147,7 +1147,6 @@ void dump_mmu(CPUPPCState *env) mmubooke206_dump_mmu(env); break; case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: mmu6xx_dump_mmu(env); break; #if defined(TARGET_PPC64) @@ -1174,53 +1173,23 @@ void dump_mmu(CPUPPCState *env) static int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, MMUAccessType access_type) { - int in_plb, ret; - ctx->raddr = eaddr; ctx->prot = PAGE_READ | PAGE_EXEC; - ret = 0; + switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: case POWERPC_MMU_SOFT_4xx: case POWERPC_MMU_REAL: case POWERPC_MMU_BOOKE: ctx->prot |= PAGE_WRITE; break; - case POWERPC_MMU_SOFT_4xx_Z: - if (unlikely(msr_pe != 0)) { - /* - * 403 family add some particular protections, using - * PBL/PBU registers for accesses with no translation. - */ - in_plb = - /* Check PLB validity */ - (env->pb[0] < env->pb[1] && - /* and address in plb area */ - eaddr >= env->pb[0] && eaddr < env->pb[1]) || - (env->pb[2] < env->pb[3] && - eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; - if (in_plb ^ msr_px) { - /* Access in protected area */ - if (access_type == MMU_DATA_STORE) { - /* Access is not allowed */ - ret = -2; - } - } else { - /* Read-write access is allowed */ - ctx->prot |= PAGE_WRITE; - } - } - break; - default: /* Caller's checks mean we should never get here for other models */ - abort(); - return -1; + g_assert_not_reached(); } - return ret; + return 0; } int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, @@ -1234,7 +1203,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: if (real_mode) { ret = check_physical(env, ctx, eaddr, access_type); } else { @@ -1250,7 +1218,6 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx, break; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: if (real_mode) { ret = check_physical(env, ctx, eaddr, access_type); } else { @@ -1383,11 +1350,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, env->spr[SPR_IMISS] = eaddr; env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; goto tlb_miss; - case POWERPC_MMU_SOFT_74xx: - cs->exception_index = POWERPC_EXCP_IFTLB; - goto tlb_miss_74xx; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_ITLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = eaddr; @@ -1454,21 +1417,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, env->spr[SPR_HASH2] = ppc_hash32_hpt_base(cpu) + get_pteg_offset32(cpu, ctx.hash[1]); break; - case POWERPC_MMU_SOFT_74xx: - if (access_type == MMU_DATA_STORE) { - cs->exception_index = POWERPC_EXCP_DSTLB; - } else { - cs->exception_index = POWERPC_EXCP_DLTLB; - } - tlb_miss_74xx: - /* Implement LRU algorithm */ - env->error_code = ctx.key << 19; - env->spr[SPR_TLBMISS] = (eaddr & ~((target_ulong)0x3)) | - ((env->last_way + 1) & (env->nb_ways - 1)); - env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; - break; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: cs->exception_index = POWERPC_EXCP_DTLB; env->error_code = 0; env->spr[SPR_40x_DEAR] = eaddr; @@ -1501,8 +1450,7 @@ static bool ppc_jumbo_xlate(PowerPCCPU *cpu, vaddr eaddr, /* Access rights violation */ cs->exception_index = POWERPC_EXCP_DSI; env->error_code = 0; - if (env->mmu_model == POWERPC_MMU_SOFT_4xx - || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) { + if (env->mmu_model == POWERPC_MMU_SOFT_4xx) { env->spr[SPR_40x_DEAR] = eaddr; if (access_type == MMU_DATA_STORE) { env->spr[SPR_40x_ESR] |= 0x00800000; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e0c4950dda..2ec3d203a0 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -385,11 +385,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: ppc6xx_tlb_invalidate_all(env); break; case POWERPC_MMU_SOFT_4xx: - case POWERPC_MMU_SOFT_4xx_Z: ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: @@ -434,7 +432,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: - case POWERPC_MMU_SOFT_74xx: ppc6xx_tlb_invalidate_virt(env, addr, 0); if (env->id_tlbs == 1) { ppc6xx_tlb_invalidate_virt(env, addr, 1); @@ -571,35 +568,6 @@ void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN) do_6xx_tlb(env, EPN, 1); } -/* PowerPC 74xx software TLB load instructions helpers */ -static void do_74xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code) -{ - target_ulong RPN, CMP, EPN; - int way; - - RPN = env->spr[SPR_PTELO]; - CMP = env->spr[SPR_PTEHI]; - EPN = env->spr[SPR_TLBMISS] & ~0x3; - way = env->spr[SPR_TLBMISS] & 0x3; - (void)EPN; /* avoid a compiler warning */ - LOG_SWTLB("%s: EPN " TARGET_FMT_lx " " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx - " PTE1 " TARGET_FMT_lx " way %d\n", __func__, new_EPN, EPN, CMP, - RPN, way); - /* Store this TLB */ - ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK), - way, is_code, CMP, RPN); -} - -void helper_74xx_tlbd(CPUPPCState *env, target_ulong EPN) -{ - do_74xx_tlb(env, EPN, 0); -} - -void helper_74xx_tlbi(CPUPPCState *env, target_ulong EPN) -{ - do_74xx_tlb(env, EPN, 1); -} - /*****************************************************************************/ /* PowerPC 601 specific instructions (POWER bridge) */ diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index 7391851238..2bab6cece7 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -104,6 +104,23 @@ void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) tcg_temp_free(t0); } +static void write_MMCR0_common(DisasContext *ctx, TCGv val) +{ + /* + * helper_store_mmcr0 will make clock based operations that + * will cause 'bad icount read' errors if we do not execute + * gen_icount_io_start() beforehand. + */ + gen_icount_io_start(ctx); + gen_helper_store_mmcr0(cpu_env, val); + + /* + * End the translation block because MMCR0 writes can change + * ctx->pmu_insn_cnt. + */ + ctx->base.is_jmp = DISAS_EXIT_UPDATE; +} + void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) { TCGv masked_gprn; @@ -119,7 +136,7 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) */ masked_gprn = masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0, MMCR0_UREG_MASK); - gen_store_spr(SPR_POWER_MMCR0, masked_gprn); + write_MMCR0_common(ctx, masked_gprn); tcg_temp_free(masked_gprn); } @@ -170,13 +187,23 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn) tcg_temp_free(masked_gprn); } +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) +{ + TCGv_i32 t_sprn = tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); + + tcg_temp_free_i32(t_sprn); +} + void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) { if (!spr_groupA_read_allowed(ctx)) { return; } - spr_read_ureg(ctx, gprn, sprn); + spr_read_PMC(ctx, gprn, sprn + 0x10); } void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) @@ -195,13 +222,23 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn) spr_read_PMC14_ureg(ctx, gprn, sprn); } +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + TCGv_i32 t_sprn = tcg_const_i32(sprn); + + gen_icount_io_start(ctx); + gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + + tcg_temp_free_i32(t_sprn); +} + void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) { if (!spr_groupA_write_allowed(ctx)) { return; } - spr_write_ureg(ctx, sprn, gprn); + spr_write_PMC(ctx, sprn + 0x10, gprn); } void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) @@ -219,6 +256,17 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) /* The remaining steps are similar to PMCs 1-4 userspace write */ spr_write_PMC14_ureg(ctx, sprn, gprn); } + +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + write_MMCR0_common(ctx, cpu_gpr[gprn]); +} + +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) +{ + gen_icount_io_start(ctx); + gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]); +} #else void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) { @@ -259,4 +307,19 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn) { spr_noaccess(ctx, gprn, sprn); } + +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} + +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} + +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c new file mode 100644 index 0000000000..08d1902cd5 --- /dev/null +++ b/target/ppc/power8-pmu.c @@ -0,0 +1,350 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include "power8-pmu.h" +#include "cpu.h" +#include "helper_regs.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" +#include "hw/ppc/ppc.h" + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +#define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL + +static bool pmc_is_inactive(CPUPPCState *env, int sprn) +{ + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { + return true; + } + + if (sprn < SPR_POWER_PMC5) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_FC14; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_FC56; +} + +static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) +{ + if (sprn == SPR_POWER_PMC1) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; +} + +/* + * For PMCs 1-4, IBM POWER chips has support for an implementation + * dependent event, 0x1E, that enables cycle counting. The Linux kernel + * makes extensive use of 0x1E, so let's also support it. + * + * Likewise, event 0x2 is an implementation-dependent event that IBM + * POWER chips implement (at least since POWER8) that is equivalent to + * PM_INST_CMPL. Let's support this event on PMCs 1-4 as well. + */ +static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) +{ + uint8_t mmcr1_evt_extr[] = { MMCR1_PMC1EVT_EXTR, MMCR1_PMC2EVT_EXTR, + MMCR1_PMC3EVT_EXTR, MMCR1_PMC4EVT_EXTR }; + PMUEventType evt_type = PMU_EVENT_INVALID; + uint8_t pmcsel; + int i; + + if (pmc_is_inactive(env, sprn)) { + return PMU_EVENT_INACTIVE; + } + + if (sprn == SPR_POWER_PMC5) { + return PMU_EVENT_INSTRUCTIONS; + } + + if (sprn == SPR_POWER_PMC6) { + return PMU_EVENT_CYCLES; + } + + i = sprn - SPR_POWER_PMC1; + pmcsel = extract64(env->spr[SPR_POWER_MMCR1], mmcr1_evt_extr[i], + MMCR1_EVT_SIZE); + + switch (pmcsel) { + case 0x2: + evt_type = PMU_EVENT_INSTRUCTIONS; + break; + case 0x1E: + evt_type = PMU_EVENT_CYCLES; + break; + case 0xF0: + /* + * PMC1SEL = 0xF0 is the architected PowerISA v3.1 + * event that counts cycles using PMC1. + */ + if (sprn == SPR_POWER_PMC1) { + evt_type = PMU_EVENT_CYCLES; + } + break; + case 0xFA: + /* + * PMC4SEL = 0xFA is the "instructions completed + * with run latch set" event. + */ + if (sprn == SPR_POWER_PMC4) { + evt_type = PMU_EVENT_INSN_RUN_LATCH; + } + break; + case 0xFE: + /* + * PMC1SEL = 0xFE is the architected PowerISA v3.1 + * event to sample instructions using PMC1. + */ + if (sprn == SPR_POWER_PMC1) { + evt_type = PMU_EVENT_INSTRUCTIONS; + } + break; + default: + break; + } + + return evt_type; +} + +bool pmu_insn_cnt_enabled(CPUPPCState *env) +{ + int sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { + if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS || + pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) { + return true; + } + } + + return false; +} + +static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered = false; + int sprn; + + /* PMC6 never counts instructions */ + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { + PMUEventType evt_type = pmc_get_event(env, sprn); + bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS || + evt_type == PMU_EVENT_INSN_RUN_LATCH; + + if (pmc_is_inactive(env, sprn) || !insn_event) { + continue; + } + + if (evt_type == PMU_EVENT_INSTRUCTIONS) { + env->spr[sprn] += num_insns; + } + + if (evt_type == PMU_EVENT_INSN_RUN_LATCH && + env->spr[SPR_CTRL] & CTRL_RUN) { + env->spr[sprn] += num_insns; + } + + if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && + pmc_has_overflow_enabled(env, sprn)) { + + overflow_triggered = true; + + /* + * The real PMU will always trigger a counter overflow with + * PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to + * do that since we're counting block of instructions at + * the end of each translation block, and we're probably + * passing this value at this point. + * + * Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed + * counter to simulate what the real hardware would do. + */ + env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL; + } + } + + return overflow_triggered; +} + +static void pmu_update_cycles(CPUPPCState *env) +{ + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t time_delta = now - env->pmu_base_time; + int sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES) { + continue; + } + + /* + * The pseries and powernv clock runs at 1Ghz, meaning + * that 1 nanosec equals 1 cycle. + */ + env->spr[sprn] += time_delta; + } + + /* Update base_time for future calculations */ + env->pmu_base_time = now; +} + +/* + * Helper function to retrieve the cycle overflow timer of the + * 'sprn' counter. + */ +static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn) +{ + return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1]; +} + +static void pmc_update_overflow_timer(CPUPPCState *env, int sprn) +{ + QEMUTimer *pmc_overflow_timer = get_cyc_overflow_timer(env, sprn); + int64_t timeout; + + /* + * PMC5 does not have an overflow timer and this pointer + * will be NULL. + */ + if (!pmc_overflow_timer) { + return; + } + + if (pmc_get_event(env, sprn) != PMU_EVENT_CYCLES || + !pmc_has_overflow_enabled(env, sprn)) { + /* Overflow timer is not needed for this counter */ + timer_del(pmc_overflow_timer); + return; + } + + if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL) { + timeout = 0; + } else { + timeout = PMC_COUNTER_NEGATIVE_VAL - env->spr[sprn]; + } + + /* + * Use timer_mod_anticipate() because an overflow timer might + * be already running for this PMC. + */ + timer_mod_anticipate(pmc_overflow_timer, env->pmu_base_time + timeout); +} + +static void pmu_update_overflow_timers(CPUPPCState *env) +{ + int sprn; + + /* + * Scroll through all PMCs and start counter overflow timers for + * PM_CYC events, if needed. + */ + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + pmc_update_overflow_timer(env, sprn); + } +} + +void helper_store_mmcr0(CPUPPCState *env, target_ulong value) +{ + pmu_update_cycles(env); + + env->spr[SPR_POWER_MMCR0] = value; + + /* MMCR0 writes can change HFLAGS_PMCCCLEAR and HFLAGS_INSN_CNT */ + hreg_compute_hflags(env); + + /* Update cycle overflow timers with the current MMCR0 state */ + pmu_update_overflow_timers(env); +} + +void helper_store_mmcr1(CPUPPCState *env, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[SPR_POWER_MMCR1] = value; + + /* MMCR1 writes can change HFLAGS_INSN_CNT */ + hreg_compute_hflags(env); +} + +target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) +{ + pmu_update_cycles(env); + + return env->spr[sprn]; +} + +void helper_store_pmc(CPUPPCState *env, uint32_t sprn, uint64_t value) +{ + pmu_update_cycles(env); + + env->spr[sprn] = value; + + pmc_update_overflow_timer(env, sprn); +} + +static void fire_PMC_interrupt(PowerPCCPU *cpu) +{ + CPUPPCState *env = &cpu->env; + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { + return; + } + + /* PMC interrupt not implemented yet */ + return; +} + +/* This helper assumes that the PMC is running. */ +void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered; + PowerPCCPU *cpu; + + overflow_triggered = pmu_increment_insns(env, num_insns); + + if (overflow_triggered) { + cpu = env_archcpu(env); + fire_PMC_interrupt(cpu); + } +} + +static void cpu_ppc_pmu_timer_cb(void *opaque) +{ + PowerPCCPU *cpu = opaque; + + fire_PMC_interrupt(cpu); +} + +void cpu_ppc_pmu_init(CPUPPCState *env) +{ + PowerPCCPU *cpu = env_archcpu(env); + int i, sprn; + + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + if (sprn == SPR_POWER_PMC5) { + continue; + } + + i = sprn - SPR_POWER_PMC1; + + env->pmu_cyc_overflow_timers[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, + &cpu_ppc_pmu_timer_cb, + cpu); + } +} +#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h new file mode 100644 index 0000000000..3ee4b4cda5 --- /dev/null +++ b/target/ppc/power8-pmu.h @@ -0,0 +1,26 @@ +/* + * PMU emulation helpers for TCG IBM POWER chips + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef POWER8_PMU +#define POWER8_PMU + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +void cpu_ppc_pmu_init(CPUPPCState *env); +bool pmu_insn_cnt_enabled(CPUPPCState *env); + +#endif diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index 520f1ef233..f98d97c0ba 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -25,6 +25,10 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn); void spr_read_generic(DisasContext *ctx, int gprn, int sprn); void spr_write_generic(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); +void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); void spr_write_xer(DisasContext *ctx, int sprn, int gprn); void spr_read_lr(DisasContext *ctx, int gprn, int sprn); @@ -34,6 +38,7 @@ void spr_write_ctr(DisasContext *ctx, int sprn, int gprn); void spr_read_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn); +void spr_read_PMC(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn); void spr_read_tbl(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9960df6e18..114456148c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -177,6 +177,7 @@ struct DisasContext { bool hr; bool mmcr0_pmcc0; bool mmcr0_pmcc1; + bool pmu_insn_cnt; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -402,6 +403,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn) spr_store_dump_spr(sprn); } +void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) +{ + spr_write_generic(ctx, sprn, gprn); + + /* + * SPR_CTRL writes must force a new translation block, + * allowing the PMU to calculate the run latch events with + * more accuracy. + */ + ctx->base.is_jmp = DISAS_EXIT_UPDATE; +} + #if !defined(CONFIG_USER_ONLY) void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) { @@ -4170,6 +4183,49 @@ static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) #endif } +#if defined(TARGET_PPC64) +static void pmu_count_insns(DisasContext *ctx) +{ + /* + * Do not bother calling the helper if the PMU isn't counting + * instructions. + */ + if (!ctx->pmu_insn_cnt) { + return; + } + + #if !defined(CONFIG_USER_ONLY) + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +#else + /* + * User mode can read (but not write) PMC5 and start/stop + * the PMU via MMCR0_FC. In this case just increment + * PMC5 with base.num_insns. + */ + TCGv t0 = tcg_temp_new(); + + gen_load_spr(t0, SPR_POWER_PMC5); + tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); + gen_store_spr(SPR_POWER_PMC5, t0); + + tcg_temp_free(t0); +#endif /* #if !defined(CONFIG_USER_ONLY) */ +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif /* #if defined(TARGET_PPC64) */ + static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -4180,6 +4236,14 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx) if (unlikely(ctx->singlestep_enabled)) { gen_debug_exception(ctx); } else { + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); } } @@ -4191,6 +4255,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) dest = (uint32_t) dest; } if (use_goto_tb(ctx, dest)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_nip, dest & ~3); tcg_gen_exit_tb(ctx->base.tb, n); @@ -6252,30 +6317,6 @@ static void gen_tlbli_6xx(DisasContext *ctx) #endif /* defined(CONFIG_USER_ONLY) */ } -/* 74xx TLB management */ - -/* tlbld */ -static void gen_tlbld_74xx(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - -/* tlbli */ -static void gen_tlbli_74xx(DisasContext *ctx) -{ -#if defined(CONFIG_USER_ONLY) - GEN_PRIV; -#else - CHK_SV; - gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); -#endif /* defined(CONFIG_USER_ONLY) */ -} - /* POWER instructions not in PowerPC 601 */ /* clf */ @@ -7420,6 +7461,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) #include "translate/spe-impl.c.inc" +#include "translate/branch-impl.c.inc" + /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) { @@ -7735,8 +7778,6 @@ GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), -GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), -GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), @@ -8458,6 +8499,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->hr = (hflags >> HFLAGS_HR) & 1; ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; + ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { @@ -8564,6 +8606,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) switch (is_jmp) { case DISAS_TOO_MANY: if (use_goto_tb(ctx, nip)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(0); gen_update_nip(ctx, nip); tcg_gen_exit_tb(ctx->base.tb, 0); @@ -8574,6 +8617,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_CHAIN: + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); break; @@ -8581,6 +8632,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_EXIT: + pmu_count_insns(ctx); tcg_gen_exit_tb(NULL, 0); break; diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc new file mode 100644 index 0000000000..29cfa11854 --- /dev/null +++ b/target/ppc/translate/branch-impl.c.inc @@ -0,0 +1,33 @@ +/* + * Power ISA decode for branch instructions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + + gen_icount_io_start(ctx); + gen_update_cfar(ctx, ctx->cia); + gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + + ctx->base.is_jmp = DISAS_CHAIN; + + return true; +} +#else +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + gen_invalid(ctx); + return true; +} +#endif diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index c9e05201d9..2baae5988f 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -31,7 +31,7 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx) #endif /*** Floating-Point arithmetic ***/ -#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ +#define _GEN_FLOAT_ACB(name, op1, op2, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ TCGv_i64 t0; \ @@ -50,10 +50,7 @@ static void gen_f##name(DisasContext *ctx) \ get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \ get_fpr(t2, rB(ctx->opcode)); \ - gen_helper_f##op(t3, cpu_env, t0, t1, t2); \ - if (isfloat) { \ - gen_helper_frsp(t3, cpu_env, t3); \ - } \ + gen_helper_f##name(t3, cpu_env, t0, t1, t2); \ set_fpr(rD(ctx->opcode), t3); \ if (set_fprf) { \ gen_compute_fprf_float64(t3); \ @@ -68,10 +65,10 @@ static void gen_f##name(DisasContext *ctx) \ } #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ -_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ -_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); +_GEN_FLOAT_ACB(name, 0x3F, op2, set_fprf, type); \ +_GEN_FLOAT_ACB(name##s, 0x3B, op2, set_fprf, type); -#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +#define _GEN_FLOAT_AB(name, op1, op2, inval, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ TCGv_i64 t0; \ @@ -87,10 +84,7 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t1, rB(ctx->opcode)); \ - gen_helper_f##op(t2, cpu_env, t0, t1); \ - if (isfloat) { \ - gen_helper_frsp(t2, cpu_env, t2); \ - } \ + gen_helper_f##name(t2, cpu_env, t0, t1); \ set_fpr(rD(ctx->opcode), t2); \ if (set_fprf) { \ gen_compute_fprf_float64(t2); \ @@ -103,10 +97,10 @@ static void gen_f##name(DisasContext *ctx) \ tcg_temp_free_i64(t2); \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ -_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); +_GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); \ +_GEN_FLOAT_AB(name##s, 0x3B, op2, inval, set_fprf, type); -#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ +#define _GEN_FLOAT_AC(name, op1, op2, inval, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ { \ TCGv_i64 t0; \ @@ -122,10 +116,7 @@ static void gen_f##name(DisasContext *ctx) \ gen_reset_fpstatus(); \ get_fpr(t0, rA(ctx->opcode)); \ get_fpr(t1, rC(ctx->opcode)); \ - gen_helper_f##op(t2, cpu_env, t0, t1); \ - if (isfloat) { \ - gen_helper_frsp(t2, cpu_env, t2); \ - } \ + gen_helper_f##name(t2, cpu_env, t0, t1); \ set_fpr(rD(ctx->opcode), t2); \ if (set_fprf) { \ gen_compute_fprf_float64(t2); \ @@ -138,8 +129,8 @@ static void gen_f##name(DisasContext *ctx) \ tcg_temp_free_i64(t2); \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ -_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ -_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); +_GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); \ +_GEN_FLOAT_AC(name##s, 0x3B, op2, inval, set_fprf, type); #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ static void gen_f##name(DisasContext *ctx) \ @@ -157,8 +148,9 @@ static void gen_f##name(DisasContext *ctx) \ gen_helper_f##name(t1, cpu_env, t0); \ set_fpr(rD(ctx->opcode), t1); \ if (set_fprf) { \ - gen_compute_fprf_float64(t1); \ + gen_helper_compute_fprf_float64(cpu_env, t1); \ } \ + gen_helper_float_check_status(cpu_env); \ if (unlikely(Rc(ctx->opcode) != 0)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ @@ -220,8 +212,7 @@ static void gen_frsqrtes(DisasContext *ctx) t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); get_fpr(t0, rB(ctx->opcode)); - gen_helper_frsqrte(t1, cpu_env, t0); - gen_helper_frsp(t1, cpu_env, t1); + gen_helper_frsqrtes(t1, cpu_env, t0); set_fpr(rD(ctx->opcode), t1); gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { @@ -232,7 +223,7 @@ static void gen_frsqrtes(DisasContext *ctx) } /* fsel */ -_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); +_GEN_FLOAT_ACB(sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL); /* fsub - fsubs */ GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); /* Optional: */ @@ -272,8 +263,7 @@ static void gen_fsqrts(DisasContext *ctx) t1 = tcg_temp_new_i64(); gen_reset_fpstatus(); get_fpr(t0, rB(ctx->opcode)); - gen_helper_fsqrt(t1, cpu_env, t0); - gen_helper_frsp(t1, cpu_env, t1); + gen_helper_fsqrts(t1, cpu_env, t0); set_fpr(rD(ctx->opcode), t1); gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) != 0)) { @@ -769,7 +759,6 @@ static void gen_mtfsb1(DisasContext *ctx) return; } crb = 31 - crbD(ctx->opcode); - gen_reset_fpstatus(); /* XXX: we pretend we can only do IEEE floating-point computations */ if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { TCGv_i32 t0; @@ -782,7 +771,7 @@ static void gen_mtfsb1(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); } /* mtfsf */ @@ -803,7 +792,6 @@ static void gen_mtfsf(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } - gen_reset_fpstatus(); if (l) { t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); } else { @@ -818,7 +806,7 @@ static void gen_mtfsf(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); tcg_temp_free_i64(t1); } @@ -840,7 +828,6 @@ static void gen_mtfsfi(DisasContext *ctx) return; } sh = (8 * w) + 7 - bf; - gen_reset_fpstatus(); t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); t1 = tcg_const_i32(1 << sh); gen_helper_store_fpscr(cpu_env, t0, t1); @@ -851,7 +838,7 @@ static void gen_mtfsfi(DisasContext *ctx) tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_float_check_status(cpu_env); + gen_helper_fpscr_check_status(cpu_env); } static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 8eb8d3a067..d5e02fd7f2 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1491,6 +1491,237 @@ static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a) return true; } +static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb), + (8 << vece) - 1, 16, 16); + + return true; +} + +TRANS(VEXPANDBM, do_vexpand, MO_8) +TRANS(VEXPANDHM, do_vexpand, MO_16) +TRANS(VEXPANDWM, do_vexpand, MO_32) +TRANS(VEXPANDDM, do_vexpand, MO_64) + +static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + get_avr64(tmp, a->vrb, true); + tcg_gen_sari_i64(tmp, tmp, 63); + set_avr64(a->vrt, tmp, false); + set_avr64(a->vrt, tmp, true); + + tcg_temp_free_i64(tmp); + return true; +} + +static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece, + mask = dup_const(vece, 1 << (elem_width - 1)); + uint64_t i, j; + TCGv_i64 lo, hi, t0, t1; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = tcg_temp_new_i64(); + lo = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + get_avr64(lo, a->vrb, false); + get_avr64(hi, a->vrb, true); + + tcg_gen_andi_i64(lo, lo, mask); + tcg_gen_andi_i64(hi, hi, mask); + + /* + * Gather the most significant bit of each element in the highest element + * element. E.g. for bytes: + * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX + * & dup(1 << (elem_width - 1)) + * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000 + * << 32 - 4 + * 0000e0000000f0000000g0000000h00000000000000000000000000000000000 + * | + * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000 + * << 16 - 2 + * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000 + * | + * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000 + * << 8 - 1 + * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000 + * | + * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000 + */ + for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) { + tcg_gen_shli_i64(t0, hi, j - i); + tcg_gen_shli_i64(t1, lo, j - i); + tcg_gen_or_i64(hi, hi, t0); + tcg_gen_or_i64(lo, lo, t1); + } + + tcg_gen_shri_i64(hi, hi, 64 - elem_count_half); + tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half); + tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo); + + tcg_temp_free_i64(hi); + tcg_temp_free_i64(lo); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + return true; +} + +TRANS(VEXTRACTBM, do_vextractm, MO_8) +TRANS(VEXTRACTHM, do_vextractm, MO_16) +TRANS(VEXTRACTWM, do_vextractm, MO_32) +TRANS(VEXTRACTDM, do_vextractm, MO_64) + +static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + get_avr64(tmp, a->vrb, true); + tcg_gen_shri_i64(tmp, tmp, 63); + tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp); + + tcg_temp_free_i64(tmp); + + return true; +} + +static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece; + uint64_t c; + int i, j; + TCGv_i64 hi, lo, t0, t1; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = tcg_temp_new_i64(); + lo = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]); + tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half); + tcg_gen_extract_i64(lo, t0, 0, elem_count_half); + + /* + * Spread the bits into their respective elements. + * E.g. for bytes: + * 00000000000000000000000000000000000000000000000000000000abcdefgh + * << 32 - 4 + * 0000000000000000000000000000abcdefgh0000000000000000000000000000 + * | + * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh + * << 16 - 2 + * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000 + * | + * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh + * << 8 - 1 + * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000 + * | + * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh + * & dup(1) + * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h + * * 0xff + * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh + */ + for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) { + tcg_gen_shli_i64(t0, hi, j - i); + tcg_gen_shli_i64(t1, lo, j - i); + tcg_gen_or_i64(hi, hi, t0); + tcg_gen_or_i64(lo, lo, t1); + } + + c = dup_const(vece, 1); + tcg_gen_andi_i64(hi, hi, c); + tcg_gen_andi_i64(lo, lo, c); + + c = MAKE_64BIT_MASK(0, elem_width); + tcg_gen_muli_i64(hi, hi, c); + tcg_gen_muli_i64(lo, lo, c); + + set_avr64(a->vrt, lo, false); + set_avr64(a->vrt, hi, true); + + tcg_temp_free_i64(hi); + tcg_temp_free_i64(lo); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + return true; +} + +TRANS(MTVSRBM, do_mtvsrm, MO_8) +TRANS(MTVSRHM, do_mtvsrm, MO_16) +TRANS(MTVSRWM, do_mtvsrm, MO_32) +TRANS(MTVSRDM, do_mtvsrm, MO_64) + +static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]); + tcg_gen_sextract_i64(tmp, tmp, 0, 1); + set_avr64(a->vrt, tmp, false); + set_avr64(a->vrt, tmp, true); + + tcg_temp_free_i64(tmp); + + return true; +} + +static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a) +{ + const uint64_t mask = dup_const(MO_8, 1); + uint64_t hi, lo; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = extract16(a->b, 8, 8); + lo = extract16(a->b, 0, 8); + + for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) { + hi |= hi << (j - i); + lo |= lo << (j - i); + } + + hi = (hi & mask) * 0xFF; + lo = (lo & mask) * 0xFF; + + set_avr64(a->vrt, tcg_constant_i64(hi), true); + set_avr64(a->vrt, tcg_constant_i64(lo), false); + + return true; +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \ diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index c0e38060b4..c08185e857 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -904,21 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX) -static void gen_xscvqpdp(DisasContext *ctx) +static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a) { - TCGv_i32 opc; + TCGv_i32 ro; TCGv_ptr xt, xb; - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } - opc = tcg_const_i32(ctx->opcode); - xt = gen_vsr_ptr(xT(ctx->opcode)); - xb = gen_vsr_ptr(xB(ctx->opcode)); - gen_helper_xscvqpdp(cpu_env, opc, xt, xb); - tcg_temp_free_i32(opc); + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + ro = tcg_const_i32(a->rc); + + xt = gen_avr_ptr(a->rt); + xb = gen_avr_ptr(a->rb); + gen_helper_XSCVQPDP(cpu_env, ro, xt, xb); + tcg_temp_free_i32(ro); tcg_temp_free_ptr(xt); tcg_temp_free_ptr(xb); + + return true; } #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ @@ -1098,10 +1101,6 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX) -GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300) -GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300) GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300) @@ -2185,6 +2184,32 @@ TRANS(XXBLENDVH, do_xxblendv, MO_16) TRANS(XXBLENDVW, do_xxblendv, MO_32) TRANS(XXBLENDVD, do_xxblendv, MO_64) +static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a, + void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr)) +{ + TCGv_ptr xt, xa, xb; + + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + REQUIRE_VSX(ctx); + + xt = gen_vsr_ptr(a->xt); + xa = gen_vsr_ptr(a->xa); + xb = gen_vsr_ptr(a->xb); + + helper(cpu_env, xt, xa, xb); + + tcg_temp_free_ptr(xt); + tcg_temp_free_ptr(xa); + tcg_temp_free_ptr(xb); + + return true; +} + +TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp) +TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp) +TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp) +TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index 152d1e5c3b..c974324c4c 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -133,7 +133,6 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001), GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001), GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001), GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001), -GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0), GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001), GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001), GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001), @@ -207,10 +206,6 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001), GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001), GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), -GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300), -GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300), -GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300), -GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300), GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300), GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..6ef3314bce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -523,7 +523,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) ext |= RVH; } if (cpu->cfg.ext_v) { - int vext_version = VEXT_VERSION_0_07_1; + int vext_version = VEXT_VERSION_1_00_0; ext |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, @@ -548,8 +548,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { - vext_version = VEXT_VERSION_0_07_1; + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; } else { error_setg(errp, "Unsupported vector spec version '%s'", @@ -558,7 +558,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } else { qemu_log("vector version is not specified, " - "use the default value v0.7.1\n"); + "use the default value v1.0\n"); } set_vext_version(env, vext_version); } @@ -626,25 +626,27 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), + DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), - - /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), - DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), - DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), - DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), - DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), - DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + + /* These are experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), @@ -673,6 +675,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) if (strcmp(xmlname, "riscv-csr.xml") == 0) { return cpu->dyn_csr_xml; + } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { + return cpu->dyn_vreg_xml; } return NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0760c0af93..dc10f27093 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,7 +81,7 @@ enum { #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 -#define VEXT_VERSION_0_07_1 0x00000701 +#define VEXT_VERSION_1_00_0 0x00010000 enum { TRANSLATE_SUCCESS, @@ -100,12 +100,14 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" #endif -#define RV_VLEN_MAX 256 +#define RV_VLEN_MAX 1024 -FIELD(VTYPE, VLMUL, 0, 2) -FIELD(VTYPE, VSEW, 2, 3) -FIELD(VTYPE, VEDIV, 5, 2) -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9) +FIELD(VTYPE, VLMUL, 0, 3) +FIELD(VTYPE, VSEW, 3, 3) +FIELD(VTYPE, VTA, 6, 1) +FIELD(VTYPE, VMA, 7, 1) +FIELD(VTYPE, VEDIV, 8, 2) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) struct CPURISCVState { @@ -289,6 +291,7 @@ struct RISCVCPU { CPURISCVState env; char *dyn_csr_xml; + char *dyn_vreg_xml; /* Configuration Settings */ struct { @@ -312,6 +315,8 @@ struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_zfh; + bool ext_zfhmin; char *priv_spec; char *user_spec; @@ -350,6 +355,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); @@ -393,23 +399,27 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1) -FIELD(TB_FLAGS, LMUL, 4, 2) +FIELD(TB_FLAGS, LMUL, 3, 3) FIELD(TB_FLAGS, SEW, 6, 3) -FIELD(TB_FLAGS, VILL, 9, 1) +/* Skip MSTATUS_VS (0x600) bits */ +FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) +FIELD(TB_FLAGS, VILL, 12, 1) +/* Skip MSTATUS_FS (0x6000) bits */ /* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 10, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) +FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) +FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 13, 2) +FIELD(TB_FLAGS, XL, 20, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_ENABLED, 22, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -421,18 +431,27 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif /* - * A simplification for VLMAX - * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * = (VLEN << LMUL) / (8 << SEW) - * = (VLEN << LMUL) >> (SEW + 3) - * = VLEN >> (SEW + 3 - LMUL) + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + * + * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) + * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 + * => VLMAX = vlen >> (1 + 3 - (-3)) + * = 256 >> 7 + * = 2 */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { - uint8_t sew, lmul; - - sew = FIELD_EX64(vtype, VTYPE, VSEW); - lmul = FIELD_EX64(vtype, VTYPE, VLMUL); + uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); + int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); return cpu->cfg.vlen >> (sew + 3 - lmul); } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77..1e31f4d35f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -60,8 +60,16 @@ #define CSR_VSTART 0x008 #define CSR_VXSAT 0x009 #define CSR_VXRM 0x00a +#define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + +/* VCSR fields */ +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) /* User Timers and Counters */ #define CSR_CYCLE 0xc00 @@ -375,6 +383,7 @@ #define MSTATUS_UBE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 @@ -408,6 +417,7 @@ typedef enum { #define SSTATUS_UPIE 0x00000010 #define SSTATUS_SPIE 0x00000020 #define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 #define SSTATUS_FS 0x00006000 #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9eeed38c7e..10f3baba53 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,12 +75,22 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *cs_base = 0; if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to true + * only when maxsz >= 8 bytes. + */ uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz = vlmax << sew; + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && + (maxsz >= 8); flags = FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags = FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); @@ -90,12 +100,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY flags |= TB_FLAGS_MSTATUS_FS; + flags |= TB_FLAGS_MSTATUS_VS; #else flags |= cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { flags |= env->mstatus & MSTATUS_FS; } + if (riscv_cpu_vector_enabled(env)) { + flags |= env->mstatus & MSTATUS_VS; + } + if (riscv_has_ext(env, RVH)) { if (env->priv == PRV_M || (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || @@ -106,6 +121,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, get_field(env->mstatus_hs, MSTATUS_FS)); + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, + get_field(env->mstatus_hs, MSTATUS_VS)); } if (riscv_has_ext(env, RVJ)) { int priv = flags & TB_FLAGS_PRIV_MMU_MASK; @@ -189,11 +207,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { + return false; + } + return true; + } + + return false; +} + void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL; + MSTATUS64_UXL | MSTATUS_VS; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..146447eac5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -38,10 +38,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - /* loose check condition for fcsr in vector extension */ - if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) { - return RISCV_EXCP_NONE; - } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } @@ -52,6 +48,11 @@ static RISCVException fs(CPURISCVState *env, int csrno) static RISCVException vs(CPURISCVState *env, int csrno) { if (env->misa_ext & RVV) { +#if !defined(CONFIG_USER_ONLY) + if (!env->debugger && !riscv_cpu_vector_enabled(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } +#endif return RISCV_EXCP_NONE; } return RISCV_EXCP_ILLEGAL_INST; @@ -261,10 +262,6 @@ static RISCVException read_fcsr(CPURISCVState *env, int csrno, { *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); - if (vs(env, csrno) >= 0) { - *val |= (env->vxrm << FSR_VXRM_SHIFT) - | (env->vxsat << FSR_VXSAT_SHIFT); - } return RISCV_EXCP_NONE; } @@ -275,10 +272,6 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, env->mstatus |= MSTATUS_FS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; - if (vs(env, csrno) >= 0) { - env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT; - env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; - } riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); return RISCV_EXCP_NONE; } @@ -297,6 +290,12 @@ static RISCVException read_vl(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = env_archcpu(env)->cfg.vlen >> 3; + return RISCV_EXCP_NONE; +} + static RISCVException read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) { @@ -307,6 +306,9 @@ static RISCVException read_vxrm(CPURISCVState *env, int csrno, static RISCVException write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vxrm = val; return RISCV_EXCP_NONE; } @@ -321,6 +323,9 @@ static RISCVException read_vxsat(CPURISCVState *env, int csrno, static RISCVException write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vxsat = val; return RISCV_EXCP_NONE; } @@ -335,7 +340,30 @@ static RISCVException read_vstart(CPURISCVState *env, int csrno, static RISCVException write_vstart(CPURISCVState *env, int csrno, target_ulong val) { - env->vstart = val; +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif + /* + * The vstart CSR is defined to have only enough writable bits + * to hold the largest element index, i.e. lg2(VLEN) bits. + */ + env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen)); + return RISCV_EXCP_NONE; +} + +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT); + return RISCV_EXCP_NONE; +} + +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif + env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT; + env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT; return RISCV_EXCP_NONE; } @@ -453,7 +481,7 @@ static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_MXR; + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP; static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; @@ -492,6 +520,7 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno, static uint64_t add_status_sd(RISCVMXL xl, uint64_t status) { if ((status & MSTATUS_FS) == MSTATUS_FS || + (status & MSTATUS_VS) == MSTATUS_VS || (status & MSTATUS_XS) == MSTATUS_XS) { switch (xl) { case MXL_RV32: @@ -535,7 +564,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS_VS; if (riscv_cpu_mxl(env) != MXL_RV32) { /* @@ -632,7 +661,7 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ if ((val & RVD) && !(val & RVF)) { @@ -1818,8 +1847,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart }, [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat }, [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm }, + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr }, [CSR_VL] = { "vl", vs, read_vl }, [CSR_VTYPE] = { "vtype", vs, read_vtype }, + [CSR_VLENB] = { "vlenb", vs, read_vlenb }, /* User Timers and Counters */ [CSR_CYCLE] = { "cycle", ctr, read_instret }, [CSR_INSTRET] = { "instret", ctr, read_instret }, diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index d62f470900..4a5982d594 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) { int softrm; - if (rm == 7) { + if (rm == RISCV_FRM_DYN) { rm = env->frm; } switch (rm) { - case 0: + case RISCV_FRM_RNE: softrm = float_round_nearest_even; break; - case 1: + case RISCV_FRM_RTZ: softrm = float_round_to_zero; break; - case 2: + case RISCV_FRM_RDN: softrm = float_round_down; break; - case 3: + case RISCV_FRM_RUP: softrm = float_round_up; break; - case 4: + case RISCV_FRM_RMM: softrm = float_round_ties_away; break; default: @@ -81,6 +81,20 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +void helper_set_rod_rounding_mode(CPURISCVState *env) +{ + set_float_rounding_mode(float_round_to_odd, &env->fp_status); +} + +static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, + uint64_t rs3, int flags) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + float16 frs3 = check_nanbox_h(rs3); + return nanbox_h(float16_muladd(frs1, frs2, frs3, flags, &env->fp_status)); +} + static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { @@ -102,6 +116,12 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status); } +uint64_t helper_fmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, 0); +} + uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { @@ -115,6 +135,12 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, &env->fp_status); } +uint64_t helper_fmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_c); +} + uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { @@ -128,6 +154,12 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, &env->fp_status); } +uint64_t helper_fnmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_product); +} + uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, uint64_t frs3) { @@ -142,6 +174,13 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, float_muladd_negate_product, &env->fp_status); } +uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return do_fmadd_h(env, frs1, frs2, frs3, + float_muladd_negate_c | float_muladd_negate_product); +} + uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { float32 frs1 = check_nanbox_s(rs1); @@ -374,3 +413,149 @@ target_ulong helper_fclass_d(uint64_t frs1) { return fclass_d(frs1); } + +uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_add(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fsub_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_sub(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fmul_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_mul(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fdiv_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(float16_div(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? + float16_minnum(frs1, frs2, &env->fp_status) : + float16_minimum_number(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? + float16_maxnum(frs1, frs2, &env->fp_status) : + float16_maximum_number(frs1, frs2, &env->fp_status)); +} + +uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return nanbox_h(float16_sqrt(frs1, &env->fp_status)); +} + +target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return float16_le(frs1, frs2, &env->fp_status); +} + +target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return float16_lt(frs1, frs2, &env->fp_status); +} + +target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) +{ + float16 frs1 = check_nanbox_h(rs1); + float16 frs2 = check_nanbox_h(rs2); + return float16_eq_quiet(frs1, frs2, &env->fp_status); +} + +target_ulong helper_fclass_h(uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return fclass_h(frs1); +} + +target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_int32(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return (int32_t)float16_to_uint32(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_int64(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_uint64(frs1, &env->fp_status); +} + +uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(int32_to_float16((int32_t)rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_wu(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(uint32_to_float16((uint32_t)rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_l(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(int64_to_float16(rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_ulong rs1) +{ + return nanbox_h(uint64_to_float16(rs1, &env->fp_status)); +} + +uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1) +{ + float32 frs1 = check_nanbox_s(rs1); + return nanbox_h(float32_to_float16(frs1, true, &env->fp_status)); +} + +uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return nanbox_s(float16_to_float32(frs1, true, &env->fp_status)); +} + +uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1) +{ + return nanbox_h(float64_to_float16(rs1, true, &env->fp_status)); +} + +uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1) +{ + float16 frs1 = check_nanbox_h(rs1); + return float16_to_float64(frs1, true, &env->fp_status); +} diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 23429179e2..881ab33392 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -20,6 +20,32 @@ #include "exec/gdbstub.h" #include "cpu.h" +struct TypeSize { + const char *gdb_type; + const char *id; + int size; + const char suffix; +}; + +static const struct TypeSize vec_lanes[] = { + /* quads */ + { "uint128", "quads", 128, 'q' }, + /* 64 bit */ + { "uint64", "longs", 64, 'l' }, + /* 32 bit */ + { "uint32", "words", 32, 'w' }, + /* 16 bit */ + { "uint16", "shorts", 16, 's' }, + /* + * TODO: currently there is no reliable way of telling + * if the remote gdb actually understands ieee_half so + * we don't expose it in the target description for now. + * { "ieee_half", 16, 'h', 'f' }, + */ + /* bytes */ + { "uint8", "bytes", 8, 'b' }, +}; + int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +/* + * Convert register index number passed by GDB to the correspond + * vector CSR number. Vector CSRs are defined after vector registers + * in dynamic generated riscv-vector.xml, thus the starting register index + * of vector CSRs is 32. + * Return 0 if register index number is out of range. + */ +static int riscv_gdb_vector_csrno(int num_regs) +{ + /* + * The order of vector CSRs in the switch case + * should match with the order defined in csr_ops[]. + */ + switch (num_regs) { + case 32: + return CSR_VSTART; + case 33: + return CSR_VXSAT; + case 34: + return CSR_VXRM; + case 35: + return CSR_VCSR; + case 36: + return CSR_VL; + case 37: + return CSR_VTYPE; + case 38: + return CSR_VLENB; + default: + /* Unknown register. */ + return 0; + } +} + +static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + int cnt = 0; + for (i = 0; i < vlenb; i += 8) { + cnt += gdb_get_reg64(buf, + env->vreg[(n * vlenb + i) / 8]); + } + return cnt; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = 0; + int result = riscv_csrrw_debug(env, csrno, &val, 0, 0); + + if (result == 0) { + return gdb_get_regl(buf, val); + } + + return 0; +} + +static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + if (n < 32) { + int i; + for (i = 0; i < vlenb; i += 8) { + env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i); + } + return vlenb; + } + + int csrno = riscv_gdb_vector_csrno(n); + + if (!csrno) { + return 0; + } + + target_ulong val = ldtul_p(mem_buf); + int result = riscv_csrrw_debug(env, csrno, NULL, val, -1); + + if (result == 0) { + return sizeof(target_ulong); + } + + return 0; +} + static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) { if (n < CSR_TABLE_SIZE) { @@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) return CSR_TABLE_SIZE; } +static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + GString *s = g_string_new(NULL); + g_autoptr(GString) ts = g_string_new(""); + int reg_width = cpu->cfg.vlen; + int num_regs = 0; + int i; + + g_string_printf(s, ""); + g_string_append_printf(s, ""); + g_string_append_printf(s, ""); + + /* First define types and totals in a whole VL */ + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + int count = reg_width / vec_lanes[i].size; + g_string_printf(ts, "%s", vec_lanes[i].id); + g_string_append_printf(s, + "", + ts->str, vec_lanes[i].gdb_type, count); + } + + /* Define unions */ + g_string_append_printf(s, ""); + for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) { + g_string_append_printf(s, "", + vec_lanes[i].suffix, + vec_lanes[i].id); + } + g_string_append(s, ""); + + /* Define vector registers */ + for (i = 0; i < 32; i++) { + g_string_append_printf(s, + "", + i, reg_width, base_reg++); + num_regs++; + } + + /* Define vector CSRs */ + const char *vector_csrs[7] = { + "vstart", "vxsat", "vxrm", "vcsr", + "vl", "vtype", "vlenb" + }; + + for (i = 0; i < 7; i++) { + g_string_append_printf(s, + "", + vector_csrs[i], TARGET_LONG_BITS, base_reg++); + num_regs++; + } + + g_string_append_printf(s, ""); + + cpu->dyn_vreg_xml = g_string_free(s, false); + return num_regs; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 36, "riscv-32bit-fpu.xml", 0); } + if (env->misa_ext & RVV) { + gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, + ricsv_gen_dynamic_vector_xml(cs, + cs->gdb_num_regs), + "riscv-vector.xml", 0); + } #if defined(TARGET_RISCV32) gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, 1, "riscv-32bit-virtual.xml", 0); diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c7a5376227..c15497e4a1 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,16 +3,21 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) /* Floating Point - Single Precision */ DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) @@ -62,6 +67,31 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl) +/* Floating Point - Half Precision */ +DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmul_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_3(fle_h, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(flt_h, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(feq_h, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_d_h, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_h_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_w_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_wu_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_l_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_h, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_1(fclass_h, TCG_CALL_NO_RWG_SE, tl, i64) + /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) DEF_HELPER_3(csrw, void, env, int, tl) @@ -83,195 +113,89 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) /* Vector functions */ DEF_HELPER_3(vsetvl, tl, env, tl, tl) -DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32) -DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32) -DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) -DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) -DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlm_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vsm_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32) +DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32) + +DEF_HELPER_4(vl1re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl1re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl1re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl1re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl2re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl4re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re8_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re16_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re32_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vl8re64_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs2r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs4r_v, void, ptr, tl, env, i32) +DEF_HELPER_4(vs8r_v, void, ptr, tl, env, i32) DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) @@ -430,18 +354,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) @@ -727,18 +651,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) @@ -749,28 +689,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) - DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) @@ -788,18 +706,18 @@ DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclip_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclipu_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) @@ -925,6 +843,14 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32) + DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) @@ -987,12 +913,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) -DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) @@ -1019,23 +939,27 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) @@ -1092,16 +1016,16 @@ DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmandn_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmorn_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vcpop_m, tl, ptr, ptr, env, i32) -DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32) DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32) @@ -1134,10 +1058,21 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32) + DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrgatherei16_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32) @@ -1147,3 +1082,22 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32) + +DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2f251dac1b..8617307b29 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -49,7 +49,6 @@ &atomic aq rl rs2 rs1 rd &rmrr vm rd rs1 rs2 &rmr vm rd rs2 -&rwdvm vm wd rd rs1 rs2 &r2nfvm vm rd rs1 nf &rnfvm vm rd rs1 rs2 nf @@ -79,8 +78,8 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd -@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd -@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd +@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -296,60 +295,69 @@ hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2 hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s # *** Vector loads and stores are encoded within LOADFP/STORE-FP *** -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm -vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm -vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm -vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm -vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm -vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm -vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm -vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm -vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm -vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm -vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm -vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm -vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm -vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm -vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm +# Vector unit-stride load/store insns. +vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm +vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm +vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm +vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm +vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm +vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm +vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm +vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm -vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm -vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm -vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm -vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm -vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm -vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm -vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm -vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm -vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm -vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm -vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm +# Vector unit-stride mask load/store insns. +vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2 +vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2 + +# Vector strided insns. +vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm +vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm +vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm +vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm +vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm +vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm +vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm +vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm + +# Vector ordered-indexed and unordered-indexed load insns. +vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm +vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm +vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm +vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm -vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm -vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm -vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm -vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm -vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm -vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm -vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm # Vector ordered-indexed and unordered-indexed store insns. -vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm -vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm -vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm -vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm +vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm +vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm +vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm +vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm -#*** Vector AMO operations are encoded under the standard AMO major opcode *** -vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm -vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm +# Vector unit-stride fault-only-first load insns. +vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm +vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm +vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm +vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm + +# Vector whole register insns +vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2 +vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2 +vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2 +vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2 +vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2 +vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2 +vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2 +vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2 +vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2 +vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2 +vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2 +vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2 +vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2 +vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2 +vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2 +vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2 +vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2 +vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2 +vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2 +vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2 # *** new major opcode OP-V *** vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm @@ -375,16 +383,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm -vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1 -vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1 -vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1 -vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1 -vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1 +vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1 +vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1 +vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1 +vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm +vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm +vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm +vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1 +vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1 +vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm +vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm @@ -403,12 +411,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm -vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm -vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm -vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm -vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm -vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm -vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm +vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm +vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm +vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm +vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm +vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm +vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm @@ -471,9 +479,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm -vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm -vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm -vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm +vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 @@ -490,32 +498,28 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm -vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm -vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm -vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm -vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm -vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm +vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm +vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm +vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm +vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm +vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm +vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm +vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm +vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm -vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm -vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm -vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm -vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm -vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm -vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm -vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm -vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm -vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm -vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm -vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm +vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm +vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm +vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm +vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm +vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm +vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm @@ -560,7 +564,9 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm -vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm +vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm +vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm +vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm @@ -571,6 +577,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm +vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm @@ -581,25 +589,34 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm -vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm -vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm -vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm +vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 -vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm -vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm -vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm -vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm -vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm -vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm -vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm -vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm -vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm -vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm -vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm -vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm -vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm -vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm + +vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm +vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm +vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm +vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm +vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm +vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm + +vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm +vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm +vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm +vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm +vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm +vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm +vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm + +vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm +vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm +vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm +vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm +vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm +vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm +vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm +vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm + vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm @@ -618,23 +635,23 @@ vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r -vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r +vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r -vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r +vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm -vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm -vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm -vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 +vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm +vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm +vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm +vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd +vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm @@ -642,24 +659,27 @@ vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm +vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd -vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm +# Vector Integer Extension +vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm +vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm +vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm +vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm +vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm +vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm + +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 +vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r -#*** Vector AMO operations (in addition to Zvamo) *** -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm - # *** RV32 Zba Standard Extension *** sh1add 0010000 .......... 010 ..... 0110011 @r sh2add 0010000 .......... 100 ..... 0110011 @r @@ -726,3 +746,41 @@ binv 0110100 .......... 001 ..... 0110011 @r binvi 01101. ........... 001 ..... 0010011 @sh bset 0010100 .......... 001 ..... 0110011 @r bseti 00101. ........... 001 ..... 0010011 @sh + +# *** RV32 Zfh Extension *** +flh ............ ..... 001 ..... 0000111 @i +fsh ....... ..... ..... 001 ..... 0100111 @s +fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm +fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm +fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm +fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm +fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm +fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm +fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm +fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm +fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm +fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r +fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r +fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r +fmin_h 0010110 ..... ..... 000 ..... 1010011 @r +fmax_h 0010110 ..... ..... 001 ..... 1010011 @r +fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm +fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm +fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm +fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm +fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm +fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm +fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2 +feq_h 1010010 ..... ..... 010 ..... 1010011 @r +flt_h 1010010 ..... ..... 001 ..... 1010011 @r +fle_h 1010010 ..... ..... 000 ..... 1010011 @r +fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2 +fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm +fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm +fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2 + +# *** RV64 Zfh Extension (in addition to RV32 Zfh) *** +fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm +fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm +fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm +fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 17ee3babef..5e3f7fdb77 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1,5 +1,4 @@ /* - * RISC-V translation routines for the RVV Standard Extension. * * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. * @@ -19,59 +18,187 @@ #include "tcg/tcg-gvec-desc.h" #include "internals.h" -static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) +static inline bool is_overlapped(const int8_t astart, int8_t asize, + const int8_t bstart, int8_t bsize) { - TCGv s1, s2, dst; + const int8_t aend = astart + asize; + const int8_t bend = bstart + bsize; - if (!has_ext(ctx, RVV)) { + return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize; +} + +static bool require_rvv(DisasContext *s) +{ + return s->mstatus_vs != 0; +} + +static bool require_rvf(DisasContext *s) +{ + if (s->mstatus_fs == 0) { return false; } - s2 = get_gpr(ctx, a->rs2, EXT_ZERO); - dst = dest_gpr(ctx, a->rd); + switch (s->sew) { + case MO_16: + case MO_32: + return has_ext(s, RVF); + case MO_64: + return has_ext(s, RVD); + default: + return false; + } +} - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 == 0) { +static bool require_scale_rvf(DisasContext *s) +{ + if (s->mstatus_fs == 0) { + return false; + } + + switch (s->sew) { + case MO_8: + case MO_16: + return has_ext(s, RVF); + case MO_32: + return has_ext(s, RVD); + default: + return false; + } +} + +/* Destination vector register group cannot overlap source mask register. */ +static bool require_vm(int vm, int vd) +{ + return (vm != 0 || vd != 0); +} + +static bool require_nf(int vd, int nf, int lmul) +{ + int size = nf << MAX(lmul, 0); + return size <= 8 && vd + size <= 32; +} + +/* + * Vector register should aligned with the passed-in LMUL (EMUL). + * If LMUL < 0, i.e. fractional LMUL, any vector register is allowed. + */ +static bool require_align(const int8_t val, const int8_t lmul) +{ + return lmul <= 0 || extract32(val, 0, lmul) == 0; +} + +/* + * A destination vector register group can overlap a source vector + * register group only if one of the following holds: + * 1. The destination EEW equals the source EEW. + * 2. The destination EEW is smaller than the source EEW and the overlap + * is in the lowest-numbered part of the source register group. + * 3. The destination EEW is greater than the source EEW, the source EMUL + * is at least 1, and the overlap is in the highest-numbered part of + * the destination register group. + * (Section 5.2) + * + * This function returns true if one of the following holds: + * * Destination vector register group does not overlap a source vector + * register group. + * * Rule 3 met. + * For rule 1, overlap is allowed so this function doesn't need to be called. + * For rule 2, (vd == vs). Caller has to check whether: (vd != vs) before + * calling this function. + */ +static bool require_noover(const int8_t dst, const int8_t dst_lmul, + const int8_t src, const int8_t src_lmul) +{ + int8_t dst_size = dst_lmul <= 0 ? 1 : 1 << dst_lmul; + int8_t src_size = src_lmul <= 0 ? 1 : 1 << src_lmul; + + /* Destination EEW is greater than the source EEW, check rule 3. */ + if (dst_size > src_size) { + if (dst < src && + src_lmul >= 0 && + is_overlapped(dst, dst_size, src, src_size) && + !is_overlapped(dst, dst_size, src + src_size, src_size)) { + return true; + } + } + + return !is_overlapped(dst, dst_size, src, src_size); +} + +static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) +{ + TCGv s1, dst; + + if (!require_rvv(s) || !has_ext(s, RVV)) { + return false; + } + + dst = dest_gpr(s, rd); + + if (rd == 0 && rs1 == 0) { + s1 = tcg_temp_new(); + tcg_gen_mov_tl(s1, cpu_vl); + } else if (rs1 == 0) { /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ s1 = tcg_constant_tl(RV_VLEN_MAX); } else { - s1 = get_gpr(ctx, a->rs1, EXT_ZERO); + s1 = get_gpr(s, rs1, EXT_ZERO); } - gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); - tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); + gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_set_gpr(s, rd, dst); + mark_vs_dirty(s); + + tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); - ctx->base.is_jmp = DISAS_NORETURN; + s->base.is_jmp = DISAS_NORETURN; + + if (rd == 0 && rs1 == 0) { + tcg_temp_free(s1); + } + return true; } -static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) +static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) { - TCGv s1, s2, dst; + TCGv dst; - if (!has_ext(ctx, RVV)) { + if (!require_rvv(s) || !has_ext(s, RVV)) { return false; } - s2 = tcg_constant_tl(a->zimm); - dst = dest_gpr(ctx, a->rd); + dst = dest_gpr(s, rd); - /* Using x0 as the rs1 register specifier, encodes an infinite AVL */ - if (a->rs1 == 0) { - /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ - s1 = tcg_constant_tl(RV_VLEN_MAX); - } else { - s1 = get_gpr(ctx, a->rs1, EXT_ZERO); - } gen_helper_vsetvl(dst, cpu_env, s1, s2); - gen_set_gpr(ctx, a->rd, dst); + gen_set_gpr(s, rd, dst); + mark_vs_dirty(s); + tcg_gen_movi_tl(cpu_pc, s->pc_succ_insn); + tcg_gen_lookup_and_goto_ptr(); + s->base.is_jmp = DISAS_NORETURN; - gen_goto_tb(ctx, 0, ctx->pc_succ_insn); - ctx->base.is_jmp = DISAS_NORETURN; return true; } +static bool trans_vsetvl(DisasContext *s, arg_vsetvl *a) +{ + TCGv s2 = get_gpr(s, a->rs2, EXT_ZERO); + return do_vsetvl(s, a->rd, a->rs1, s2); +} + +static bool trans_vsetvli(DisasContext *s, arg_vsetvli *a) +{ + TCGv s2 = tcg_constant_tl(a->zimm); + return do_vsetvl(s, a->rd, a->rs1, s2); +} + +static bool trans_vsetivli(DisasContext *s, arg_vsetivli *a) +{ + TCGv s1 = tcg_const_tl(a->rs1); + TCGv s2 = tcg_const_tl(a->zimm); + return do_vsetivli(s, a->rd, s1, s2); +} + /* vector register offset from env */ static uint32_t vreg_ofs(DisasContext *s, int reg) { @@ -80,6 +207,350 @@ static uint32_t vreg_ofs(DisasContext *s, int reg) /* check functions */ +/* + * Vector unit-stride, strided, unit-stride segment, strided segment + * store check function. + * + * Rules to be checked here: + * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3) + * 2. Destination vector register number is multiples of EMUL. + * (Section 3.4.2, 7.3) + * 3. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8) + * 4. Vector register numbers accessed by the segment load or store + * cannot increment past 31. (Section 7.8) + */ +static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew) +{ + int8_t emul = eew - s->sew + s->lmul; + return (emul >= -3 && emul <= 3) && + require_align(vd, emul) && + require_nf(vd, nf, emul); +} + +/* + * Vector unit-stride, strided, unit-stride segment, strided segment + * load check function. + * + * Rules to be checked here: + * 1. All rules applies to store instructions are applies + * to load instructions. + * 2. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_check_load(DisasContext *s, int vd, int nf, int vm, + uint8_t eew) +{ + return vext_check_store(s, vd, nf, eew) && require_vm(vm, vd); +} + +/* + * Vector indexed, indexed segment store check function. + * + * Rules to be checked here: + * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3) + * 2. Index vector register number is multiples of EMUL. + * (Section 3.4.2, 7.3) + * 3. Destination vector register number is multiples of LMUL. + * (Section 3.4.2, 7.3) + * 4. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8) + * 5. Vector register numbers accessed by the segment load or store + * cannot increment past 31. (Section 7.8) + */ +static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, + uint8_t eew) +{ + int8_t emul = eew - s->sew + s->lmul; + return (emul >= -3 && emul <= 3) && + require_align(vs2, emul) && + require_align(vd, s->lmul) && + require_nf(vd, nf, s->lmul); +} + +/* + * Vector indexed, indexed segment load check function. + * + * Rules to be checked here: + * 1. All rules applies to store instructions are applies + * to load instructions. + * 2. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 3. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + * 4. Destination vector register groups cannot overlap + * the source vector register (vs2) group for + * indexed segment load instructions. (Section 7.8.3) + */ +static bool vext_check_ld_index(DisasContext *s, int vd, int vs2, + int nf, int vm, uint8_t eew) +{ + int8_t seg_vd; + int8_t emul = eew - s->sew + s->lmul; + bool ret = vext_check_st_index(s, vd, vs2, nf, eew) && + require_vm(vm, vd); + + /* Each segment register group has to follow overlap rules. */ + for (int i = 0; i < nf; ++i) { + seg_vd = vd + (1 << MAX(s->lmul, 0)) * i; + + if (eew > s->sew) { + if (seg_vd != vs2) { + ret &= require_noover(seg_vd, s->lmul, vs2, emul); + } + } else if (eew < s->sew) { + ret &= require_noover(seg_vd, s->lmul, vs2, emul); + } + + /* + * Destination vector register groups cannot overlap + * the source vector register (vs2) group for + * indexed segment load instructions. + */ + if (nf > 1) { + ret &= !is_overlapped(seg_vd, 1 << MAX(s->lmul, 0), + vs2, 1 << MAX(emul, 0)); + } + } + return ret; +} + +static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) +{ + return require_vm(vm, vd) && + require_align(vd, s->lmul) && + require_align(vs, s->lmul); +} + +/* + * Check function for vector instruction with format: + * single-width result and single-width sources (SEW = SEW op SEW) + * + * Rules to be checked here: + * 1. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 2. Destination vector register number is multiples of LMUL. + * (Section 3.4.2) + * 3. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.4.2) + */ +static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_ss(s, vd, vs2, vm) && + require_align(vs1, s->lmul); +} + +static bool vext_check_ms(DisasContext *s, int vd, int vs) +{ + bool ret = require_align(vs, s->lmul); + if (vd != vs) { + ret &= require_noover(vd, 0, vs, s->lmul); + } + return ret; +} + +/* + * Check function for maskable vector instruction with format: + * single-width result and single-width sources (SEW = SEW op SEW) + * + * Rules to be checked here: + * 1. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.4.2) + * 2. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) + * 3. The destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0), + * unless the destination vector register is being written + * with a mask value (e.g., comparisons) or the scalar result + * of a reduction. (Section 5.3) + */ +static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) +{ + bool ret = vext_check_ms(s, vd, vs2) && + require_align(vs1, s->lmul); + if (vd != vs1) { + ret &= require_noover(vd, 0, vs1, s->lmul); + } + return ret; +} + +/* + * Common check function for vector widening instructions + * of double-width result (2*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * => LMUL < 8. + * => SEW < 64. + * 2. Double-width SEW cannot greater than ELEN. + * 3. Destination vector register number is multiples of 2 * LMUL. + * (Section 3.4.2) + * 4. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_wide_check_common(DisasContext *s, int vd, int vm) +{ + return (s->lmul <= 2) && + (s->sew < MO_64) && + ((s->sew + 1) <= (s->elen >> 4)) && + require_align(vd, s->lmul + 1) && + require_vm(vm, vd); +} + +/* + * Common check function for vector narrowing instructions + * of single-width result (SEW) and double-width source (2*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers (Section 5.2): + * => LMUL < 8. + * => SEW < 64. + * 2. Double-width SEW cannot greater than ELEN. + * 3. Source vector register number is multiples of 2 * LMUL. + * (Section 3.4.2) + * 4. Destination vector register number is multiples of LMUL. + * (Section 3.4.2) + * 5. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + */ +static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2, + int vm) +{ + return (s->lmul <= 2) && + (s->sew < MO_64) && + ((s->sew + 1) <= (s->elen >> 4)) && + require_align(vs2, s->lmul + 1) && + require_align(vd, s->lmul) && + require_vm(vm, vd); +} + +static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm) +{ + return vext_wide_check_common(s, vd, vm) && + require_align(vs, s->lmul) && + require_noover(vd, s->lmul + 1, vs, s->lmul); +} + +static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) +{ + return vext_wide_check_common(s, vd, vm) && + require_align(vs, s->lmul + 1); +} + +/* + * Check function for vector instruction with format: + * double-width result and single-width sources (2*SEW = SEW op SEW) + * + * Rules to be checked here: + * 1. All rules in defined in widen common rules are applied. + * 2. Source (vs2, vs1) vector register number are multiples of LMUL. + * (Section 3.4.2) + * 3. Destination vector register cannot overlap a source vector + * register (vs2, vs1) group. + * (Section 5.2) + */ +static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_ds(s, vd, vs2, vm) && + require_align(vs1, s->lmul) && + require_noover(vd, s->lmul + 1, vs1, s->lmul); +} + +/* + * Check function for vector instruction with format: + * double-width result and double-width source1 and single-width + * source2 (2*SEW = 2*SEW op SEW) + * + * Rules to be checked here: + * 1. All rules in defined in widen common rules are applied. + * 2. Source 1 (vs2) vector register number is multiples of 2 * LMUL. + * (Section 3.4.2) + * 3. Source 2 (vs1) vector register number is multiples of LMUL. + * (Section 3.4.2) + * 4. Destination vector register cannot overlap a source vector + * register (vs1) group. + * (Section 5.2) + */ +static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_ds(s, vd, vs1, vm) && + require_align(vs2, s->lmul + 1); +} + +static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) +{ + bool ret = vext_narrow_check_common(s, vd, vs, vm); + if (vd != vs) { + ret &= require_noover(vd, s->lmul, vs, s->lmul + 1); + } + return ret; +} + +/* + * Check function for vector instruction with format: + * single-width result and double-width source 1 and single-width + * source 2 (SEW = 2*SEW op SEW) + * + * Rules to be checked here: + * 1. All rules in defined in narrow common rules are applied. + * 2. Destination vector register cannot overlap a source vector + * register (vs2) group. + * (Section 5.2) + * 3. Source 2 (vs1) vector register number is multiples of LMUL. + * (Section 3.4.2) + */ +static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm) +{ + return vext_check_sd(s, vd, vs2, vm) && + require_align(vs1, s->lmul); +} + +/* + * Check function for vector reduction instructions. + * + * Rules to be checked here: + * 1. Source 1 (vs2) vector register number is multiples of LMUL. + * (Section 3.4.2) + */ +static bool vext_check_reduction(DisasContext *s, int vs2) +{ + return require_align(vs2, s->lmul) && (s->vstart == 0); +} + +/* + * Check function for vector slide instructions. + * + * Rules to be checked here: + * 1. Source 1 (vs2) vector register number is multiples of LMUL. + * (Section 3.4.2) + * 2. Destination vector register number is multiples of LMUL. + * (Section 3.4.2) + * 3. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 5.3) + * 4. The destination vector register group for vslideup, vslide1up, + * vfslide1up, cannot overlap the source vector register (vs2) group. + * (Section 5.2, 16.3.1, 16.3.3) + */ +static bool vext_check_slide(DisasContext *s, int vd, int vs2, + int vm, bool is_over) +{ + bool ret = require_align(vs2, s->lmul) && + require_align(vd, s->lmul) && + require_vm(vm, vd); + if (is_over) { + ret &= (vd != vs2); + } + return ret; +} + /* * In cpu_get_tb_cpu_state(), set VILL if RVV was not present. * So RVV is also be checked in this function. @@ -89,62 +560,20 @@ static bool vext_check_isa_ill(DisasContext *s) return !s->vill; } -/* - * There are two rules check here. - * - * 1. Vector register numbers are multiples of LMUL. (Section 3.2) - * - * 2. For all widening instructions, the destination LMUL value must also be - * a supported LMUL value. (Section 11.2) - */ -static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen) -{ - /* - * The destination vector register group results are arranged as if both - * SEW and LMUL were at twice their current settings. (Section 11.2). - */ - int legal = widen ? 2 << s->lmul : 1 << s->lmul; - - return !((s->lmul == 0x3 && widen) || (reg % legal)); -} - -/* - * There are two rules check here. - * - * 1. The destination vector register group for a masked vector instruction can - * only overlap the source mask register (v0) when LMUL=1. (Section 5.3) - * - * 2. In widen instructions and some other insturctions, like vslideup.vx, - * there is no need to check whether LMUL=1. - */ -static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm, - bool force) -{ - return (vm != 0 || vd != 0) || (!force && (s->lmul == 0)); -} - -/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */ -static bool vext_check_nf(DisasContext *s, uint32_t nf) -{ - return (1 << s->lmul) * nf <= 8; -} - -/* - * The destination vector register group cannot overlap a source vector register - * group of a different element width. (Section 11.2) - */ -static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen) -{ - return ((rd >= rs + slen) || (rs >= rd + dlen)); -} /* common translation macro */ -#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\ -{ \ - if (CHECK(s, a)) { \ - return OP(s, a, SEQ); \ - } \ - return false; \ +#define GEN_VEXT_TRANS(NAME, EEW, ARGTYPE, OP, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \ +{ \ + if (CHECK(s, a, EEW)) { \ + return OP(s, a, EEW); \ + } \ + return false; \ +} + +static uint8_t vext_get_emul(DisasContext *s, uint8_t eew) +{ + int8_t emul = eew - s->sew + s->lmul; + return emul < 0 ? 0 : emul; } /* @@ -154,7 +583,8 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, TCGv_env, TCGv_i32); static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s) + gen_helper_ldst_us *fn, DisasContext *s, + bool is_store) { TCGv_ptr dest, mask; TCGv base; @@ -168,8 +598,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, base = get_gpr(s, rs1, EXT_NONE); /* - * As simd_desc supports at most 256 bytes, and in this implementation, - * the max vector group length is 2048 bytes. So split it into two parts. + * As simd_desc supports at most 2048 bytes, and in this implementation, + * the max vector group length is 4096 bytes. So split it into two parts. * * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. @@ -183,123 +613,133 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } -static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][7][4] = { + static gen_helper_ldst_us * const fns[2][4] = { /* masked unit stride load */ - { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask, - gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask }, - { NULL, gen_helper_vlh_v_h_mask, - gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask }, - { NULL, NULL, - gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask }, - { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask, - gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask }, - { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask, - gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask }, - { NULL, gen_helper_vlhu_v_h_mask, - gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask }, - { NULL, NULL, - gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } }, + { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask, + gen_helper_vle32_v_mask, gen_helper_vle64_v_mask }, /* unmasked unit stride load */ - { { gen_helper_vlb_v_b, gen_helper_vlb_v_h, - gen_helper_vlb_v_w, gen_helper_vlb_v_d }, - { NULL, gen_helper_vlh_v_h, - gen_helper_vlh_v_w, gen_helper_vlh_v_d }, - { NULL, NULL, - gen_helper_vlw_v_w, gen_helper_vlw_v_d }, - { gen_helper_vle_v_b, gen_helper_vle_v_h, - gen_helper_vle_v_w, gen_helper_vle_v_d }, - { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h, - gen_helper_vlbu_v_w, gen_helper_vlbu_v_d }, - { NULL, gen_helper_vlhu_v_h, - gen_helper_vlhu_v_w, gen_helper_vlhu_v_d }, - { NULL, NULL, - gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } } + { gen_helper_vle8_v, gen_helper_vle16_v, + gen_helper_vle32_v, gen_helper_vle64_v } }; - fn = fns[a->vm][seq][s->sew]; + fn = fns[a->vm][eew]; if (fn == NULL) { return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + /* + * Vector load/store instructions have the EEW encoded + * directly in the instructions. The maximum vector size is + * calculated with EMUL rather than LMUL. + */ + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } -static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) +static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_load(s, a->rd, a->nf, a->vm, eew); } -GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check) -GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle8_v, MO_8, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle16_v, MO_16, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle32_v, MO_32, r2nfvm, ld_us_op, ld_us_check) +GEN_VEXT_TRANS(vle64_v, MO_64, r2nfvm, ld_us_op, ld_us_check) -static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[2][4][4] = { - /* masked unit stride load and store */ - { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask, - gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask }, - { NULL, gen_helper_vsh_v_h_mask, - gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask }, - { NULL, NULL, - gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask }, - { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask, - gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } }, + static gen_helper_ldst_us * const fns[2][4] = { + /* masked unit stride store */ + { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask, + gen_helper_vse32_v_mask, gen_helper_vse64_v_mask }, /* unmasked unit stride store */ - { { gen_helper_vsb_v_b, gen_helper_vsb_v_h, - gen_helper_vsb_v_w, gen_helper_vsb_v_d }, - { NULL, gen_helper_vsh_v_h, - gen_helper_vsh_v_w, gen_helper_vsh_v_d }, - { NULL, NULL, - gen_helper_vsw_v_w, gen_helper_vsw_v_d }, - { gen_helper_vse_v_b, gen_helper_vse_v_h, - gen_helper_vse_v_w, gen_helper_vse_v_d } } + { gen_helper_vse8_v, gen_helper_vse16_v, + gen_helper_vse32_v, gen_helper_vse64_v } }; - fn = fns[a->vm][seq][s->sew]; + fn = fns[a->vm][eew]; if (fn == NULL) { return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } -static bool st_us_check(DisasContext *s, arg_r2nfvm* a) +static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_store(s, a->rd, a->nf, eew); } -GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check) -GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse8_v, MO_8, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check) +GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check) + +/* + *** unit stride mask load and store + */ +static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn = gen_helper_vlm_v; + + /* EMUL = 1, NFIELDS = 1 */ + data = FIELD_DP32(data, VDATA, LMUL, 0); + data = FIELD_DP32(data, VDATA, NF, 1); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); +} + +static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew) +{ + /* EMUL = 1, NFIELDS = 1 */ + return require_rvv(s) && vext_check_isa_ill(s); +} + +static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew) +{ + uint32_t data = 0; + gen_helper_ldst_us *fn = gen_helper_vsm_v; + + /* EMUL = 1, NFIELDS = 1 */ + data = FIELD_DP32(data, VDATA, LMUL, 0); + data = FIELD_DP32(data, VDATA, NF, 1); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); +} + +static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew) +{ + /* EMUL = 1, NFIELDS = 1 */ + return require_rvv(s) && vext_check_isa_ill(s); +} + +GEN_VEXT_TRANS(vlm_v, MO_8, vlm_v, ld_us_mask_op, ld_us_mask_check) +GEN_VEXT_TRANS(vsm_v, MO_8, vsm_v, st_us_mask_op, st_us_mask_check) /* *** stride load and store @@ -309,7 +749,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask; TCGv base, stride; @@ -331,98 +771,81 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } -static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[7][4] = { - { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h, - gen_helper_vlsb_v_w, gen_helper_vlsb_v_d }, - { NULL, gen_helper_vlsh_v_h, - gen_helper_vlsh_v_w, gen_helper_vlsh_v_d }, - { NULL, NULL, - gen_helper_vlsw_v_w, gen_helper_vlsw_v_d }, - { gen_helper_vlse_v_b, gen_helper_vlse_v_h, - gen_helper_vlse_v_w, gen_helper_vlse_v_d }, - { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h, - gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d }, - { NULL, gen_helper_vlshu_v_h, - gen_helper_vlshu_v_w, gen_helper_vlshu_v_d }, - { NULL, NULL, - gen_helper_vlswu_v_w, gen_helper_vlswu_v_d }, + static gen_helper_ldst_stride * const fns[4] = { + gen_helper_vlse8_v, gen_helper_vlse16_v, + gen_helper_vlse32_v, gen_helper_vlse64_v }; - fn = fns[seq][s->sew]; + fn = fns[eew]; if (fn == NULL) { return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } -static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) +static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_load(s, a->rd, a->nf, a->vm, eew); } -GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check) -GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse8_v, MO_8, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse16_v, MO_16, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse32_v, MO_32, rnfvm, ld_stride_op, ld_stride_check) +GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check) -static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_stride *fn; - static gen_helper_ldst_stride * const fns[4][4] = { + static gen_helper_ldst_stride * const fns[4] = { /* masked stride store */ - { gen_helper_vssb_v_b, gen_helper_vssb_v_h, - gen_helper_vssb_v_w, gen_helper_vssb_v_d }, - { NULL, gen_helper_vssh_v_h, - gen_helper_vssh_v_w, gen_helper_vssh_v_d }, - { NULL, NULL, - gen_helper_vssw_v_w, gen_helper_vssw_v_d }, - { gen_helper_vsse_v_b, gen_helper_vsse_v_h, - gen_helper_vsse_v_w, gen_helper_vsse_v_d } + gen_helper_vsse8_v, gen_helper_vsse16_v, + gen_helper_vsse32_v, gen_helper_vsse64_v }; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - fn = fns[seq][s->sew]; + fn = fns[eew]; if (fn == NULL) { return false; } - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } -static bool st_stride_check(DisasContext *s, arg_rnfvm* a) +static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_store(s, a->rd, a->nf, eew); } -GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check) -GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse8_v, MO_8, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse16_v, MO_16, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse32_v, MO_32, rnfvm, st_stride_op, st_stride_check) +GEN_VEXT_TRANS(vsse64_v, MO_64, rnfvm, st_stride_op, st_stride_check) /* *** index load and store @@ -432,7 +855,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t data, gen_helper_ldst_index *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask, index; TCGv base; @@ -456,107 +879,118 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } -static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_ldst_index *fn; - static gen_helper_ldst_index * const fns[7][4] = { - { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h, - gen_helper_vlxb_v_w, gen_helper_vlxb_v_d }, - { NULL, gen_helper_vlxh_v_h, - gen_helper_vlxh_v_w, gen_helper_vlxh_v_d }, - { NULL, NULL, - gen_helper_vlxw_v_w, gen_helper_vlxw_v_d }, - { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h, - gen_helper_vlxe_v_w, gen_helper_vlxe_v_d }, - { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h, - gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d }, - { NULL, gen_helper_vlxhu_v_h, - gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d }, - { NULL, NULL, - gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d }, - }; - - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} - -/* - * For vector indexed segment loads, the destination vector register - * groups cannot overlap the source vector register group (specified by - * `vs2`), else an illegal instruction exception is raised. - */ -static bool ld_index_check(DisasContext *s, arg_rnfvm* a) -{ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf) && - ((a->nf == 1) || - vext_check_overlap_group(a->rd, a->nf << s->lmul, - a->rs2, 1 << s->lmul))); -} - -GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check) -GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check) - -static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) +static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_index *fn; static gen_helper_ldst_index * const fns[4][4] = { - { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h, - gen_helper_vsxb_v_w, gen_helper_vsxb_v_d }, - { NULL, gen_helper_vsxh_v_h, - gen_helper_vsxh_v_w, gen_helper_vsxh_v_d }, - { NULL, NULL, - gen_helper_vsxw_v_w, gen_helper_vsxw_v_d }, - { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h, - gen_helper_vsxe_v_w, gen_helper_vsxe_v_d } + /* + * offset vector register group EEW = 8, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v, + gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v }, + /* + * offset vector register group EEW = 16, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v, + gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v }, + /* + * offset vector register group EEW = 32, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v, + gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v }, + /* + * offset vector register group EEW = 64, + * data vector register group EEW = SEW + */ + { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v, + gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v } }; - fn = fns[seq][s->sew]; - if (fn == NULL) { - return false; - } + fn = fns[eew][s->sew]; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + uint8_t emul = vext_get_emul(s, s->sew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } -static bool st_index_check(DisasContext *s, arg_rnfvm* a) +static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew); } -GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check) -GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vlxei8_v, MO_8, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei16_v, MO_16, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei32_v, MO_32, rnfvm, ld_index_op, ld_index_check) +GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check) + +static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) +{ + uint32_t data = 0; + gen_helper_ldst_index *fn; + static gen_helper_ldst_index * const fns[4][4] = { + /* + * offset vector register group EEW = 8, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v, + gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v }, + /* + * offset vector register group EEW = 16, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v, + gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v }, + /* + * offset vector register group EEW = 32, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v, + gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v }, + /* + * offset vector register group EEW = 64, + * data vector register group EEW = SEW + */ + { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v, + gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v } + }; + + fn = fns[eew][s->sew]; + + uint8_t emul = vext_get_emul(s, s->sew); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, emul); + data = FIELD_DP32(data, VDATA, NF, a->nf); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); +} + +static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_st_index(s, a->rd, a->rs2, a->nf, eew); +} + +GEN_VEXT_TRANS(vsxei8_v, MO_8, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei16_v, MO_16, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei32_v, MO_32, rnfvm, st_index_op, st_index_check) +GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check) /* *** unit stride fault-only-first load @@ -583,203 +1017,125 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + mark_vs_dirty(s); gen_set_label(over); return true; } -static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) { uint32_t data = 0; gen_helper_ldst_us *fn; - static gen_helper_ldst_us * const fns[7][4] = { - { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h, - gen_helper_vlbff_v_w, gen_helper_vlbff_v_d }, - { NULL, gen_helper_vlhff_v_h, - gen_helper_vlhff_v_w, gen_helper_vlhff_v_d }, - { NULL, NULL, - gen_helper_vlwff_v_w, gen_helper_vlwff_v_d }, - { gen_helper_vleff_v_b, gen_helper_vleff_v_h, - gen_helper_vleff_v_w, gen_helper_vleff_v_d }, - { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h, - gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d }, - { NULL, gen_helper_vlhuff_v_h, - gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d }, - { NULL, NULL, - gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d } + static gen_helper_ldst_us * const fns[4] = { + gen_helper_vle8ff_v, gen_helper_vle16ff_v, + gen_helper_vle32ff_v, gen_helper_vle64ff_v }; - fn = fns[seq][s->sew]; + fn = fns[eew]; if (fn == NULL) { return false; } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + uint8_t emul = vext_get_emul(s, eew); data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); return ldff_trans(a->rd, a->rs1, data, fn, s); } -GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) -GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle8ff_v, MO_8, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check) /* - *** vector atomic operation + * load and store whole register instructions */ -typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr, - TCGv_env, TCGv_i32); +typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); -static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, - uint32_t data, gen_helper_amo *fn, DisasContext *s) +static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, + gen_helper_ldst_whole *fn, DisasContext *s, + bool is_store) { - TCGv_ptr dest, mask, index; + TCGv_ptr dest; TCGv base; TCGv_i32 desc; - TCGLabel *over = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - + uint32_t data = FIELD_DP32(0, VDATA, NF, nf); dest = tcg_temp_new_ptr(); - mask = tcg_temp_new_ptr(); - index = tcg_temp_new_ptr(); - base = get_gpr(s, rs1, EXT_NONE); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); + base = get_gpr(s, rs1, EXT_NONE); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - fn(dest, mask, base, index, cpu_env, desc); + fn(dest, base, cpu_env, desc); tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(index); - gen_set_label(over); + + if (!is_store) { + mark_vs_dirty(s); + } + return true; } -static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq) -{ - uint32_t data = 0; - gen_helper_amo *fn; - static gen_helper_amo *const fnsw[9] = { - /* no atomic operation */ - gen_helper_vamoswapw_v_w, - gen_helper_vamoaddw_v_w, - gen_helper_vamoxorw_v_w, - gen_helper_vamoandw_v_w, - gen_helper_vamoorw_v_w, - gen_helper_vamominw_v_w, - gen_helper_vamomaxw_v_w, - gen_helper_vamominuw_v_w, - gen_helper_vamomaxuw_v_w - }; - static gen_helper_amo *const fnsd[18] = { - gen_helper_vamoswapw_v_d, - gen_helper_vamoaddw_v_d, - gen_helper_vamoxorw_v_d, - gen_helper_vamoandw_v_d, - gen_helper_vamoorw_v_d, - gen_helper_vamominw_v_d, - gen_helper_vamomaxw_v_d, - gen_helper_vamominuw_v_d, - gen_helper_vamomaxuw_v_d, - gen_helper_vamoswapd_v_d, - gen_helper_vamoaddd_v_d, - gen_helper_vamoxord_v_d, - gen_helper_vamoandd_v_d, - gen_helper_vamoord_v_d, - gen_helper_vamomind_v_d, - gen_helper_vamomaxd_v_d, - gen_helper_vamominud_v_d, - gen_helper_vamomaxud_v_d - }; - - if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp = DISAS_NORETURN; - return true; - } - - switch (s->sew) { - case 0 ... 2: - assert(seq < ARRAY_SIZE(fnsw)); - fn = fnsw[seq]; - break; - case 3: - /* XLEN check done in amo_check(). */ - assert(seq < ARRAY_SIZE(fnsd)); - fn = fnsd[seq]; - break; - default: - g_assert_not_reached(); - } - - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); - data = FIELD_DP32(data, VDATA, VM, a->vm); - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); - data = FIELD_DP32(data, VDATA, WD, a->wd); - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s); -} /* - * There are two rules check here. - * - * 1. SEW must be at least as wide as the AMO memory element size. - * - * 2. If SEW is greater than XLEN, an illegal instruction exception is raised. + * load and store whole register instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 7.9) */ -static bool amo_check(DisasContext *s, arg_rwdvm* a) -{ - return (!s->vill && has_ext(s, RVA) && - (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((1 << s->sew) <= sizeof(target_ulong)) && - ((1 << s->sew) >= 4)); +#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \ + return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \ + s, IS_STORE); \ + } \ + return false; \ } -static bool amo_check64(DisasContext *s, arg_rwdvm* a) -{ - REQUIRE_64BIT(s); - return amo_check(s, a); -} +GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false) +GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false) +GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false) +GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, false) +GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false) +GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false) +GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false) -GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check) -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64) -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64) +GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true) +GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true) +GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true) +GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale = s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} static bool opivv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, @@ -803,13 +1159,13 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, } else { uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -847,7 +1203,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, src2 = tcg_temp_new_ptr(); src1 = get_gpr(s, rs1, EXT_NONE); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); @@ -861,16 +1216,16 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } static bool opivx_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); } typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, @@ -892,6 +1247,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, src1, MAXSZ(s), MAXSZ(s)); tcg_temp_free_i64(src1); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -970,8 +1326,32 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs, GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs) +typedef enum { + IMM_ZX, /* Zero-extended */ + IMM_SX, /* Sign-extended */ + IMM_TRUNC_SEW, /* Truncate to log(SEW) bits */ + IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */ +} imm_mode_t; + +static int64_t extract_imm(DisasContext *s, uint32_t imm, imm_mode_t imm_mode) +{ + switch (imm_mode) { + case IMM_ZX: + return extract64(imm, 0, 5); + case IMM_SX: + return sextract64(imm, 0, 5); + case IMM_TRUNC_SEW: + return extract64(imm, 0, s->sew + 3); + case IMM_TRUNC_2SEW: + return extract64(imm, 0, s->sew + 4); + default: + g_assert_not_reached(); + } +} + static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, - gen_helper_opivx *fn, DisasContext *s, int zx) + gen_helper_opivx *fn, DisasContext *s, + imm_mode_t imm_mode) { TCGv_ptr dest, src2, mask; TCGv src1; @@ -984,12 +1364,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, dest = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr(); - if (zx) { - src1 = tcg_constant_tl(imm); - } else { - src1 = tcg_constant_tl(sextract64(imm, 0, 5)); - } - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + src1 = tcg_constant_tl(extract_imm(s, imm, imm_mode)); + data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); @@ -1003,6 +1379,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1012,28 +1389,23 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, - gen_helper_opivx *fn, int zx) + gen_helper_opivx *fn, imm_mode_t imm_mode) { if (!opivx_check(s, a)) { return false; } if (a->vm && s->vl_eq_vlmax) { - if (zx) { - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } else { - gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), - sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); - } - } else { - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), + extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); + mark_vs_dirty(s); + return true; } - return true; + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode); } /* OPIVI with GVEC IR */ -#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \ +#define GEN_OPIVI_GVEC_TRANS(NAME, IMM_MODE, OPIVX, SUF) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ static gen_helper_opivx * const fns[4] = { \ @@ -1041,10 +1413,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ - fns[s->sew], ZX); \ + fns[s->sew], IMM_MODE); \ } -GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi) +GEN_OPIVI_GVEC_TRANS(vadd_vi, IMM_SX, vadd_vx, addi) static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, int64_t c, uint32_t oprsz, uint32_t maxsz) @@ -1053,23 +1425,16 @@ static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz); } -GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) +GEN_OPIVI_GVEC_TRANS(vrsub_vi, IMM_SX, vrsub_vx, rsubi) /* Vector Widening Integer Add/Subtract */ /* OPIVV with WIDEN */ static bool opivv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, @@ -1081,7 +1446,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), @@ -1089,6 +1453,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1114,13 +1479,9 @@ GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check) /* OPIVX with WIDEN */ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ds(s, a->rd, a->rs2, a->vm); } static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, @@ -1151,14 +1512,9 @@ GEN_OPIVX_WIDEN_TRANS(vwsub_vx) /* WIDEN OPIVV with WIDEN */ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, @@ -1169,13 +1525,13 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1201,11 +1557,9 @@ GEN_OPIWV_WIDEN_TRANS(vwsub_wv) /* WIDEN OPIVX with WIDEN */ static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_dd(s, a->rd, a->rs2, a->vm); } static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a, @@ -1247,7 +1601,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1255,6 +1608,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1263,15 +1617,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.3) + * destination vector register is v0 and LMUL > 1. (Section 11.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((a->rd != 0) || (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd != 0) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check) @@ -1283,11 +1636,9 @@ GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check) */ static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2); } GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check) @@ -1295,10 +1646,10 @@ GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check) static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - ((a->rd != 0) || (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd != 0) && + vext_check_ss(s, a->rd, a->rs2, a->vm); } /* OPIVX without GVEC IR */ @@ -1321,16 +1672,16 @@ GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check) static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ms(s, a->rd, a->rs2); } GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check) GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check) /* OPIVI without GVEC IR */ -#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \ +#define GEN_OPIVI_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ if (CHECK(s, a)) { \ @@ -1339,13 +1690,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ + fns[s->sew], s, IMM_MODE); \ } \ return false; \ } -GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check) +GEN_OPIVI_TRANS(vadc_vim, IMM_SX, vadc_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmadc_vim, IMM_SX, vmadc_vxm, opivx_vmadc_check) /* Vector Bitwise Logical Instructions */ GEN_OPIVV_GVEC_TRANS(vand_vv, and) @@ -1354,9 +1705,9 @@ GEN_OPIVV_GVEC_TRANS(vxor_vv, xor) GEN_OPIVX_GVEC_TRANS(vand_vx, ands) GEN_OPIVX_GVEC_TRANS(vor_vx, ors) GEN_OPIVX_GVEC_TRANS(vxor_vx, xors) -GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi) -GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori) -GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori) +GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi) +GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx, ori) +GEN_OPIVI_GVEC_TRANS(vxor_vi, IMM_SX, vxor_vx, xori) /* Vector Single-Width Bit Shift Instructions */ GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv) @@ -1383,6 +1734,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, src1, MAXSZ(s), MAXSZ(s)); tcg_temp_free_i32(src1); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1403,28 +1755,23 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls) GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs) GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars) -GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli) -GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri) -GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari) +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli) +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ -static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sds(s, a->rd, a->rs1, a->rs2, a->vm); } /* OPIVV with NARROW */ -#define GEN_OPIVV_NARROW_TRANS(NAME) \ +#define GEN_OPIWV_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivv_narrow_check(s, a)) { \ + if (opiwv_narrow_check(s, a)) { \ uint32_t data = 0; \ static gen_helper_gvec_4_ptr * const fns[3] = { \ gen_helper_##NAME##_b, \ @@ -1434,7 +1781,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1442,30 +1788,27 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ return false; \ } -GEN_OPIVV_NARROW_TRANS(vnsra_vv) -GEN_OPIVV_NARROW_TRANS(vnsrl_vv) +GEN_OPIWV_NARROW_TRANS(vnsra_wv) +GEN_OPIWV_NARROW_TRANS(vnsrl_wv) -static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sd(s, a->rd, a->rs2, a->vm); } /* OPIVX with NARROW */ -#define GEN_OPIVX_NARROW_TRANS(NAME) \ +#define GEN_OPIWX_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] = { \ gen_helper_##NAME##_b, \ gen_helper_##NAME##_h, \ @@ -1476,27 +1819,27 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ return false; \ } -GEN_OPIVX_NARROW_TRANS(vnsra_vx) -GEN_OPIVX_NARROW_TRANS(vnsrl_vx) +GEN_OPIWX_NARROW_TRANS(vnsra_wx) +GEN_OPIWX_NARROW_TRANS(vnsrl_wx) -/* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \ +/* OPIWI with NARROW */ +#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] = { \ gen_helper_##OPIVX##_b, \ gen_helper_##OPIVX##_h, \ gen_helper_##OPIVX##_w, \ }; \ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \ - fns[s->sew], s, ZX); \ + fns[s->sew], s, IMM_MODE); \ } \ return false; \ } -GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) +GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx) +GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx) /* Vector Integer Comparison Instructions */ /* @@ -1506,13 +1849,11 @@ GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx) */ static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2); } + GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check) GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check) GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check) @@ -1522,10 +1863,9 @@ GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check) static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul == 0))); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ms(s, a->rd, a->rs2); } GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check) @@ -1537,12 +1877,12 @@ GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check) GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check) GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check) -GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsleu_vi, IMM_SX, vmsleu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgtu_vi, IMM_SX, vmsgtu_vx, opivx_cmp_check) +GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check) /* Vector Integer Min/Max Instructions */ GEN_OPIVV_GVEC_TRANS(vminu_vv, umin) @@ -1604,10 +1944,10 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.v has rs2 = 0 and vm = 1 */ + vext_check_sss(s, a->rd, a->rs1, 0, 1)) { if (s->vl_eq_vlmax) { tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), @@ -1626,6 +1966,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) fns[s->sew]); gen_set_label(over); } + mark_vs_dirty(s); return true; } return false; @@ -1634,9 +1975,10 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32); static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.x has rs2 = 0 and vm = 1 */ + vext_check_ss(s, a->rd, 0, 1)) { TCGv s1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -1665,6 +2007,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) tcg_temp_free_i64(s1_i64); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1673,13 +2016,15 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false)) { - + if (require_rvv(s) && + vext_check_isa_ill(s) && + /* vmv.v.i has rs2 = 0 and vm = 1 */ + vext_check_ss(s, a->rd, 0, 1)) { int64_t simm = sextract64(a->rs1, 0, 5); if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); + mark_vs_dirty(s); } else { TCGv_i32 desc; TCGv_i64 s1; @@ -1699,6 +2044,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) fns[s->sew](dest, s1, cpu_env, desc); tcg_temp_free_ptr(dest); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -1708,7 +2054,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) -GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmerge_vim, IMM_SX, vmerge_vxm, opivx_vadc_check) /* *** Vector Fixed-Point Arithmetic Instructions @@ -1723,48 +2069,69 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check) GEN_OPIVX_TRANS(vsadd_vx, opivx_check) GEN_OPIVX_TRANS(vssubu_vx, opivx_check) GEN_OPIVX_TRANS(vssub_vx, opivx_check) -GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check) -GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check) +GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check) +GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check) /* Vector Single-Width Averaging Add and Subtract */ GEN_OPIVV_TRANS(vaadd_vv, opivv_check) +GEN_OPIVV_TRANS(vaaddu_vv, opivv_check) GEN_OPIVV_TRANS(vasub_vv, opivv_check) +GEN_OPIVV_TRANS(vasubu_vv, opivv_check) GEN_OPIVX_TRANS(vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vaaddu_vx, opivx_check) GEN_OPIVX_TRANS(vasub_vx, opivx_check) -GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) +GEN_OPIVX_TRANS(vasubu_vx, opivx_check) /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ GEN_OPIVV_TRANS(vsmul_vv, opivv_check) GEN_OPIVX_TRANS(vsmul_vx, opivx_check) -/* Vector Widening Saturating Scaled Multiply-Add */ -GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check) -GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx) - /* Vector Single-Width Scaling Shift Instructions */ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) GEN_OPIVV_TRANS(vssra_vv, opivv_check) GEN_OPIVX_TRANS(vssrl_vx, opivx_check) GEN_OPIVX_TRANS(vssra_vx, opivx_check) -GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check) -GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check) +GEN_OPIVI_TRANS(vssrl_vi, IMM_TRUNC_SEW, vssrl_vx, opivx_check) +GEN_OPIVI_TRANS(vssra_vi, IMM_TRUNC_SEW, vssra_vx, opivx_check) /* Vector Narrowing Fixed-Point Clip Instructions */ -GEN_OPIVV_NARROW_TRANS(vnclipu_vv) -GEN_OPIVV_NARROW_TRANS(vnclip_vv) -GEN_OPIVX_NARROW_TRANS(vnclipu_vx) -GEN_OPIVX_NARROW_TRANS(vnclip_vx) -GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx) -GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) +GEN_OPIWV_NARROW_TRANS(vnclipu_wv) +GEN_OPIWV_NARROW_TRANS(vnclip_wv) +GEN_OPIWX_NARROW_TRANS(vnclipu_wx) +GEN_OPIWX_NARROW_TRANS(vnclip_wx) +GEN_OPIWI_NARROW_TRANS(vnclipu_wi, IMM_ZX, vnclipu_wx) +GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx) /* *** Vector Float Point Arithmetic Instructions */ + +/* + * As RVF-only cpus always have values NaN-boxed to 64-bits, + * RVF and RVD can be treated equally. + * We don't have to deal with the cases of: SEW > FLEN. + * + * If SEW < FLEN, check whether input fp register is a valid + * NaN-boxed value, in which case the least-significant SEW bits + * of the f regsiter are used, else the canonical NaN value is used. + */ +static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in) +{ + switch (s->sew) { + case 1: + gen_check_nanbox_h(out, in); + break; + case 2: + gen_check_nanbox_s(out, in); + break; + case 3: + tcg_gen_mov_i64(out, in); + break; + default: + g_assert_not_reached(); + } +} + /* Vector Single-Width Floating-Point Add/Subtract Instructions */ /* @@ -1773,12 +2140,10 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx) */ static bool opfvv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } /* OPFVV without GVEC IR */ @@ -1793,10 +2158,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1804,6 +2168,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1820,6 +2185,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, { TCGv_ptr dest, src2, mask; TCGv_i32 desc; + TCGv_i64 t1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -1833,26 +2199,31 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + /* NaN-box f[rs1] */ + t1 = tcg_temp_new_i64(); + do_nanbox(s, t1, cpu_fpr[rs1]); + + fn(dest, mask, t1, src2, cpu_env, desc); tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + tcg_temp_free_i64(t1); + mark_vs_dirty(s); gen_set_label(over); return true; } -static bool opfvf_check(DisasContext *s, arg_rmrr *a) -{ /* * If the current SEW does not correspond to a supported IEEE floating-point * type, an illegal instruction exception is raised */ - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0)); +static bool opfvf_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); } /* OPFVF without GVEC IR */ @@ -1866,8 +2237,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_w, \ gen_helper_##NAME##_d, \ }; \ - gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -1883,16 +2253,10 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) /* Vector Widening Floating-Point Add/Subtract Instructions */ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } /* OPFVV with WIDEN */ @@ -1905,10 +2269,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1916,6 +2279,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1927,13 +2291,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_ds(s, a->rd, a->rs2, a->vm); } /* OPFVF with WIDEN */ @@ -1945,8 +2306,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -1960,14 +2320,10 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - vext_check_reg(s, a->rs1, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } /* WIDEN OPFVV with WIDEN */ @@ -1980,10 +2336,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ @@ -1991,6 +2346,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2002,11 +2358,10 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, true) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_dd(s, a->rd, a->rs2, a->vm); } /* WIDEN OPFVF with WIDEN */ @@ -2018,8 +2373,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2078,41 +2432,54 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) */ static bool opfv_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + /* OPFV instructions ignore vs1 check */ + vext_check_ss(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data = 0; \ - static gen_helper_gvec_3_ptr * const fns[3] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ - data = FIELD_DP32(data, VDATA, VM, a->vm); \ - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, \ - s->vlen / 8, s->vlen / 8, data, \ - fns[s->sew - 1]); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ +static bool do_opfv(DisasContext *s, arg_rmr *a, + gen_helper_gvec_3_ptr *fn, + bool (*checkfn)(DisasContext *, arg_rmr *), + int rm) +{ + if (checkfn(s, a)) { + if (rm != RISCV_FRM_DYN) { + gen_set_rm(s, RISCV_FRM_DYN); + } + + uint32_t data = 0; + TCGLabel *over = gen_new_label(); + gen_set_rm(s, rm); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), cpu_env, + s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); + gen_set_label(over); + return true; + } + return false; } -GEN_OPFV_TRANS(vfsqrt_v, opfv_check) +#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d \ + }; \ + return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \ +} + +GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point MIN/MAX Instructions */ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) @@ -2131,28 +2498,23 @@ GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) /* Vector Floating-Point Compare Instructions */ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - vext_check_reg(s, a->rs1, false) && - (s->sew != 0) && - ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) && - vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) || - (s->lmul == 0))); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_mss(s, a->rd, a->rs1, a->rs2); } GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check) static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rs2, false) && - (s->sew != 0) && - (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) || - (s->lmul == 0))); + return require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + vext_check_ms(s, a->rd, a->rs2); } GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) @@ -2161,23 +2523,31 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check) /* Vector Floating-Point Classify Instruction */ -GEN_OPFV_TRANS(vfclass_v, opfv_check) +GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN) /* Vector Floating-Point Merge Instruction */ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - (s->sew != 0)) { + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul)) { + gen_set_rm(s, RISCV_FRM_DYN); + + TCGv_i64 t1; if (s->vl_eq_vlmax) { + t1 = tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), - MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); + MAXSZ(s), MAXSZ(s), t1); + mark_vs_dirty(s); } else { TCGv_ptr dest; TCGv_i32 desc; @@ -2190,24 +2560,45 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + t1 = tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + dest = tcg_temp_new_ptr(); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); + + fns[s->sew - 1](dest, t1, cpu_env, desc); tcg_temp_free_ptr(dest); + mark_vs_dirty(s); gen_set_label(over); } + tcg_temp_free_i64(t1); return true; } return false; } /* Single-Width Floating-Point/Integer Type-Convert Instructions */ -GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) -GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) +#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + gen_helper_##HELPER##_d \ + }; \ + return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \ +} + +GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN) +GEN_OPFV_CVT_TRANS(vfcvt_x_f_v, vfcvt_x_f_v, RISCV_FRM_DYN) +GEN_OPFV_CVT_TRANS(vfcvt_f_xu_v, vfcvt_f_xu_v, RISCV_FRM_DYN) +GEN_OPFV_CVT_TRANS(vfcvt_f_x_v, vfcvt_f_x_v, RISCV_FRM_DYN) +/* Reuse the helper functions from vfcvt.xu.f.v and vfcvt.x.f.v */ +GEN_OPFV_CVT_TRANS(vfcvt_rtz_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_RTZ) +GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v, RISCV_FRM_RTZ) /* Widening Floating-Point/Integer Type-Convert Instructions */ @@ -2217,46 +2608,87 @@ GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) */ static bool opfv_widen_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, true) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2, - 1 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && + vext_check_isa_ill(s) && + vext_check_ds(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_WIDEN_TRANS(NAME) \ +#define GEN_OPFV_WIDEN_TRANS(NAME, HELPER, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_widen_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ return false; \ } -GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) +GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, vfwcvt_x_f_v, RISCV_FRM_DYN) +GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, vfwcvt_f_f_v, RISCV_FRM_DYN) +/* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */ +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_RTZ) +GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, vfwcvt_x_f_v, RISCV_FRM_RTZ) + +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + require_scale_rvf(s) && + vext_check_isa_ill(s) && + /* OPFV widening instructions ignore vs1 check */ + vext_check_ds(s, a->rd, a->rs2, a->vm); +} + +#define GEN_OPFXV_WIDEN_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfxv_widen_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, RISCV_FRM_DYN); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->vlen / 8, s->vlen / 8, data, \ + fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v) +GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) /* Narrowing Floating-Point/Integer Type-Convert Instructions */ @@ -2266,46 +2698,94 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v) */ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, false) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, true) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, - 2 << s->lmul) && - (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0)); + return require_rvv(s) && + require_rvf(s) && + (s->sew != MO_64) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sd(s, a->rd, a->rs2, a->vm); } -#define GEN_OPFV_NARROW_TRANS(NAME) \ +#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_narrow_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ return false; \ } -GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN) +/* Reuse the helper function from vfncvt.f.f.w */ +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD) + +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + require_scale_rvf(s) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sd(s, a->rd, a->rs2, a->vm); +} + +#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opxfv_narrow_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##HELPER##_b, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, FRM); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->vlen / 8, s->vlen / 8, data, \ + fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN) +GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN) +/* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */ +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ) +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ) /* *** Vector Reduction Operations @@ -2313,7 +2793,9 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) /* Vector Single-Width Integer Reduction Instructions */ static bool reduction_check(DisasContext *s, arg_rmrr *a) { - return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_reduction(s, a->rs2); } GEN_OPIVV_TRANS(vredsum_vs, reduction_check) @@ -2326,16 +2808,35 @@ GEN_OPIVV_TRANS(vredor_vs, reduction_check) GEN_OPIVV_TRANS(vredxor_vs, reduction_check) /* Vector Widening Integer Reduction Instructions */ -GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check) -GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) +static bool reduction_widen_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_check(s, a) && (s->sew < MO_64) && + ((s->sew + 1) <= (s->elen >> 4)); +} + +GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check) /* Vector Single-Width Floating-Point Reduction Instructions */ -GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) -GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) -GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) +static bool freduction_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_check(s, a) && + require_rvf(s); +} + +GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) +GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) +GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) /* Vector Widening Floating-Point Reduction Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) +static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) +{ + return reduction_widen_check(s, a) && + require_scale_rvf(s) && + (s->sew != MO_8); +} + +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) /* *** Vector Mask Operations @@ -2345,18 +2846,19 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) #define GEN_MM_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_r *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s)) { \ uint32_t data = 0; \ gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2365,22 +2867,23 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ GEN_MM_TRANS(vmand_mm) GEN_MM_TRANS(vmnand_mm) -GEN_MM_TRANS(vmandnot_mm) +GEN_MM_TRANS(vmandn_mm) GEN_MM_TRANS(vmxor_mm) GEN_MM_TRANS(vmor_mm) GEN_MM_TRANS(vmnor_mm) -GEN_MM_TRANS(vmornot_mm) +GEN_MM_TRANS(vmorn_mm) GEN_MM_TRANS(vmxnor_mm) -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +/* Vector count population in mask vcpop */ +static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + s->vstart == 0) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -2392,25 +2895,27 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + return true; } return false; } /* vmfirst find-first-set mask bit */ -static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) +static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + s->vstart == 0) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; uint32_t data = 0; - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); @@ -2422,7 +2927,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); + gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); @@ -2438,19 +2943,23 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s) && \ + require_vm(a->vm, a->rd) && \ + (a->rd != a->rs2) && \ + (s->vstart == 0)) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, s->vlen / 8, s->vlen / 8, \ data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2461,18 +2970,25 @@ GEN_M_TRANS(vmsbf_m) GEN_M_TRANS(vmsif_m) GEN_M_TRANS(vmsof_m) -/* Vector Iota Instruction */ +/* + * Vector Iota Instruction + * + * 1. The destination register cannot overlap the source register. + * 2. If masked, cannot overlap the mask register ('v0'). + * 3. An illegal instruction exception is raised if vstart is non-zero. + */ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && - (a->vm != 0 || a->rd != 0)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && + require_vm(a->vm, a->rd) && + require_align(a->rd, s->lmul) && + (s->vstart == 0)) { uint32_t data = 0; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_3_ptr * const fns[4] = { @@ -2482,6 +2998,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2491,14 +3008,14 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) /* Vector Element Index Instruction */ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) { - if (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_overlap_mask(s, a->rd, a->vm, false)) { + if (require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_vm(a->vm, a->rd)) { uint32_t data = 0; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); static gen_helper_gvec_2_ptr * const fns[4] = { @@ -2508,6 +3025,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2518,20 +3036,30 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) *** Vector Permutation Instructions */ -/* Integer Extract Instruction */ - static void load_element(TCGv_i64 dest, TCGv_ptr base, - int ofs, int sew) + int ofs, int sew, bool sign) { switch (sew) { case MO_8: - tcg_gen_ld8u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld8u_i64(dest, base, ofs); + } else { + tcg_gen_ld8s_i64(dest, base, ofs); + } break; case MO_16: - tcg_gen_ld16u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld16u_i64(dest, base, ofs); + } else { + tcg_gen_ld16s_i64(dest, base, ofs); + } break; case MO_32: - tcg_gen_ld32u_i64(dest, base, ofs); + if (!sign) { + tcg_gen_ld32u_i64(dest, base, ofs); + } else { + tcg_gen_ld32s_i64(dest, base, ofs); + } break; case MO_64: tcg_gen_ld_i64(dest, base, ofs); @@ -2586,7 +3114,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, /* Perform the load. */ load_element(dest, base, - vreg_ofs(s, vreg), s->sew); + vreg_ofs(s, vreg), s->sew, false); tcg_temp_free_ptr(base); tcg_temp_free_i32(ofs); @@ -2602,30 +3130,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest, } static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, - int vreg, int idx) + int vreg, int idx, bool sign) { - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew); -} - -static bool trans_vext_x_v(DisasContext *s, arg_r *a) -{ - TCGv_i64 tmp = tcg_temp_new_i64(); - TCGv dest = dest_gpr(s, a->rd); - - if (a->rs1 == 0) { - /* Special case vmv.x.s rd, vs2. */ - vec_element_loadi(s, tmp, a->rs2, 0); - } else { - /* This instruction ignores LMUL and vector register groups */ - int vlmax = s->vlen >> (3 + s->sew); - vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax); - } - - tcg_gen_trunc_i64_tl(dest, tmp); - gen_set_gpr(s, a->rd, dest); - - tcg_temp_free_i64(tmp); - return true; + load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); } /* Integer Scalar Move Instruction */ @@ -2662,26 +3169,55 @@ static void vec_element_storei(DisasContext *s, int vreg, store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); } +/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */ +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) +{ + if (require_rvv(s) && + vext_check_isa_ill(s)) { + TCGv_i64 t1; + TCGv dest; + + t1 = tcg_temp_new_i64(); + dest = tcg_temp_new(); + /* + * load vreg and sign-extend to 64 bits, + * then truncate to XLEN bits before storing to gpr. + */ + vec_element_loadi(s, t1, a->rs2, 0, true); + tcg_gen_trunc_i64_tl(dest, t1); + gen_set_gpr(s, a->rd, dest); + tcg_temp_free_i64(t1); + tcg_temp_free(dest); + + return true; + } + return false; +} + /* vmv.s.x vd, rs1 # vd[0] = rs1 */ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { /* This instruction ignores LMUL and vector register groups */ - int maxsz = s->vlen >> 3; TCGv_i64 t1; + TCGv s1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0); - if (a->rs1 == 0) { - goto done; - } + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); t1 = tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + + /* + * load gpr and sign-extend to 64 bits, + * then truncate to SEW bits when storing to vreg. + */ + s1 = get_gpr(s, a->rs1, EXT_NONE); + tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); - done: + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2691,14 +3227,21 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) /* Floating-Point Scalar Move Instructions */ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) { - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs != 0) && (s->sew != 0)) { - unsigned int len = 8 << s->sew; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { + gen_set_rm(s, RISCV_FRM_DYN); - vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); + unsigned int ofs = (8 << s->sew); + unsigned int len = 64 - ofs; + TCGv_i64 t_nan; + + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); + /* NaN-box f[rd] as necessary for SEW */ + if (len) { + t_nan = tcg_constant_i64(UINT64_MAX); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + t_nan, ofs, len); } mark_fs_dirty(s); @@ -2710,27 +3253,26 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) { - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { - TCGv_i64 t1; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { + gen_set_rm(s, RISCV_FRM_DYN); + /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax = s->vlen >> 3; - - /* if vl == 0, skip vector register write back */ + TCGv_i64 t1; TCGLabel *over = gen_new_label(); + + /* if vl == 0 or vstart >= vl, skip vector register write back */ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ + /* NaN-box f[rs1] */ t1 = tcg_temp_new_i64(); - if (s->sew == MO_64 && !has_ext(s, RVD)) { - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); - } else { - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); - } + do_nanbox(s, t1, cpu_fpr[a->rs1]); + vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2740,41 +3282,82 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) /* Vector Slide Instructions */ static bool slideup_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_slide(s, a->rd, a->rs2, a->vm, true); } GEN_OPIVX_TRANS(vslideup_vx, slideup_check) GEN_OPIVX_TRANS(vslide1up_vx, slideup_check) -GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check) +GEN_OPIVI_TRANS(vslideup_vi, IMM_ZX, vslideup_vx, slideup_check) -GEN_OPIVX_TRANS(vslidedown_vx, opivx_check) -GEN_OPIVX_TRANS(vslide1down_vx, opivx_check) -GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check) +static bool slidedown_check(DisasContext *s, arg_rmrr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_slide(s, a->rd, a->rs2, a->vm, false); +} + +GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check) +GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check) +GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check) + +/* Vector Floating-Point Slide Instructions */ +static bool fslideup_check(DisasContext *s, arg_rmrr *a) +{ + return slideup_check(s, a) && + require_rvf(s); +} + +static bool fslidedown_check(DisasContext *s, arg_rmrr *a) +{ + return slidedown_check(s, a) && + require_rvf(s); +} + +GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check) +GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check) /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs1, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2) && (a->rd != a->rs1)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs1, s->lmul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2 && a->rd != a->rs1) && + require_vm(a->vm, a->rd); +} + +static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a) +{ + int8_t emul = MO_16 - s->sew + s->lmul; + return require_rvv(s) && + vext_check_isa_ill(s) && + (emul >= -3 && emul <= 3) && + require_align(a->rd, s->lmul) && + require_align(a->rs1, emul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2 && a->rd != a->rs1) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), + a->rs1, 1 << MAX(emul, 0)) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), + a->rs2, 1 << MAX(s->lmul, 0)) && + require_vm(a->vm, a->rd); } GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check) +GEN_OPIVV_TRANS(vrgatherei16_vv, vrgatherei16_vv_check) static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a) { - return (vext_check_isa_ill(s) && - vext_check_overlap_mask(s, a->rd, a->vm, true) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - (a->rd != a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2) && + require_vm(a->vm, a->rd); } /* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ @@ -2785,11 +3368,12 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) } if (a->vm && s->vl_eq_vlmax) { - int vlmax = s->vlen / s->mlen; + int scale = s->lmul - (s->sew + 3); + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale; TCGv_i64 dest = tcg_temp_new_i64(); if (a->rs1 == 0) { - vec_element_loadi(s, dest, a->rs2, 0); + vec_element_loadi(s, dest, a->rs2, 0, false); } else { vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax); } @@ -2797,6 +3381,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), dest); tcg_temp_free_i64(dest); + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] = { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2815,32 +3400,43 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) } if (a->vm && s->vl_eq_vlmax) { - if (a->rs1 >= s->vlen / s->mlen) { - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), + int scale = s->lmul - (s->sew + 3); + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale; + if (a->rs1 >= vlmax) { + tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); } else { tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd), endian_ofs(s, a->rs2, a->rs1), MAXSZ(s), MAXSZ(s)); } + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] = { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d }; - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1); + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], + s, IMM_ZX); } return true; } -/* Vector Compress Instruction */ +/* + * Vector Compress Instruction + * + * The destination vector register group cannot overlap the + * source vector register group or the source mask register. + */ static bool vcompress_vm_check(DisasContext *s, arg_r *a) { - return (vext_check_isa_ill(s) && - vext_check_reg(s, a->rd, false) && - vext_check_reg(s, a->rs2, false) && - vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && - (a->rd != a->rs2)); + return require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + (a->rd != a->rs2) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) && + (s->vstart == 0); } static bool trans_vcompress_vm(DisasContext *s, arg_r *a) @@ -2854,14 +3450,133 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } return false; } + +/* + * Whole Vector Register Move Instructions ignore vtype and vl setting. + * Thus, we don't need to check vill bit. (Section 16.6) + */ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (require_rvv(s) && \ + QEMU_IS_ALIGNED(a->rd, LEN) && \ + QEMU_IS_ALIGNED(a->rs2, LEN)) { \ + uint32_t maxsz = (s->vlen >> 3) * LEN; \ + if (s->vstart == 0) { \ + /* EEW = 8 */ \ + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ + vreg_ofs(s, a->rs2), maxsz, maxsz); \ + mark_vs_dirty(s); \ + } else { \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ + \ + static gen_helper_gvec_2_ptr * const fns[4] = { \ + gen_helper_vmv1r_v, gen_helper_vmv2r_v, \ + gen_helper_vmv4r_v, gen_helper_vmv8r_v, \ + }; \ + tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ + cpu_env, maxsz, maxsz, 0, fns[SEQ]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + } \ + return true; \ + } \ + return false; \ +} + +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3) + +static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div) +{ + uint8_t from = (s->sew + 3) - div; + bool ret = require_rvv(s) && + (from >= 3 && from <= 8) && + (a->rd != a->rs2) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul - div) && + require_vm(a->vm, a->rd) && + require_noover(a->rd, s->lmul, a->rs2, s->lmul - div); + return ret; +} + +static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq) +{ + uint32_t data = 0; + gen_helper_gvec_3_ptr *fn; + TCGLabel *over = gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + + static gen_helper_gvec_3_ptr * const fns[6][4] = { + { + NULL, gen_helper_vzext_vf2_h, + gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d + }, + { + NULL, NULL, + gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d, + }, + { + NULL, NULL, + NULL, gen_helper_vzext_vf8_d + }, + { + NULL, gen_helper_vsext_vf2_h, + gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d + }, + { + NULL, NULL, + gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d, + }, + { + NULL, NULL, + NULL, gen_helper_vsext_vf8_d + } + }; + + fn = fns[seq][s->sew]; + if (fn == NULL) { + return false; + } + + data = FIELD_DP32(data, VDATA, VM, a->vm); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), cpu_env, + s->vlen / 8, s->vlen / 8, data, fn); + + mark_vs_dirty(s); + gen_set_label(over); + return true; +} + +/* Vector Integer Extension */ +#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (int_ext_check(s, a, DIV)) { \ + return int_ext_op(s, a, SEQ); \ + } \ + return false; \ +} + +GEN_INT_EXT_TRANS(vzext_vf2, 1, 0) +GEN_INT_EXT_TRANS(vzext_vf4, 2, 1) +GEN_INT_EXT_TRANS(vzext_vf8, 3, 2) +GEN_INT_EXT_TRANS(vsext_vf2, 1, 3) +GEN_INT_EXT_TRANS(vsext_vf4, 2, 4) +GEN_INT_EXT_TRANS(vsext_vf8, 3, 5) diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc new file mode 100644 index 0000000000..5a7cac8958 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -0,0 +1,537 @@ +/* + * RISC-V translation routines for the RV64Zfh Standard Extension. + * + * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_ZFH(ctx) do { \ + if (!ctx->ext_zfh) { \ + return false; \ + } \ +} while (0) + +#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ + if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \ + return false; \ + } \ +} while (0) + +static bool trans_flh(DisasContext *ctx, arg_flh *a) +{ + TCGv_i64 dest; + TCGv t0; + + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + + t0 = get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp = temp_new(ctx); + tcg_gen_addi_tl(temp, t0, a->imm); + t0 = temp; + } + + dest = cpu_fpr[a->rd]; + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW); + gen_nanbox_h(dest, dest); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsh(DisasContext *ctx, arg_fsh *a) +{ + TCGv t0; + + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + + t0 = get_gpr(ctx, a->rs1, EXT_NONE); + if (a->imm) { + TCGv temp = tcg_temp_new(); + tcg_gen_addi_tl(temp, t0, a->imm); + t0 = temp; + } + + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW); + + return true; +} + +static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsub_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fnmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmadd_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fnmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fadd_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fsub_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fmul_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_h(cpu_fpr[a->rd], cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + if (a->rs1 == a->rs2) { /* FMOV */ + gen_check_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + } else { + TCGv_i64 rs1 = tcg_temp_new_i64(); + TCGv_i64 rs2 = tcg_temp_new_i64(); + + gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]); + gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]); + + /* This formulation retains the nanboxing of rs2. */ + tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 15); + tcg_temp_free_i64(rs1); + tcg_temp_free_i64(rs2); + } + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a) +{ + TCGv_i64 rs1, rs2, mask; + + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]); + + if (a->rs1 == a->rs2) { /* FNEG */ + tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(15, 1)); + } else { + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]); + + /* + * Replace bit 15 in rs1 with inverse in rs2. + * This formulation retains the nanboxing of rs1. + */ + mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1)); + tcg_gen_not_i64(rs2, rs2); + tcg_gen_andc_i64(rs2, rs2, mask); + tcg_gen_and_i64(rs1, mask, rs1); + tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(mask); + tcg_temp_free_i64(rs2); + } + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnjx_h *a) +{ + TCGv_i64 rs1, rs2; + + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + rs1 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + + if (a->rs1 == a->rs2) { /* FABS */ + tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(15, 1)); + } else { + rs2 = tcg_temp_new_i64(); + gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + /* + * Xor bit 15 in rs1 with that in rs2. + * This formulation retains the nanboxing of rs1. + */ + tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(15, 1)); + tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2); + + tcg_temp_free_i64(rs2); + } + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_helper_fmin_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + gen_helper_fmax_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], + cpu_fpr[a->rs2]); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + return true; +} + +static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + + return true; +} + +static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + return true; +} + +static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_EXT(ctx, RVD); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + + mark_fs_dirty(ctx); + + return true; +} + +static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_feq_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_flt_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_fle_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_helper_fclass_h(dest, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_w_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt_wu_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_wu_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_h_w *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_w(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_wu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + +#if defined(TARGET_RISCV64) + /* 16 bits -> 64 bits */ + tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]); +#else + /* 16 bits -> 32 bits */ + tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); + tcg_gen_ext16s_tl(dest, dest); +#endif + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a) +{ + REQUIRE_FPU; + REQUIRE_ZFH_OR_ZFHMIN(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO); + + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); + gen_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rd]); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcvt_l_h *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_l_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fcvt_lu_h *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv dest = dest_gpr(ctx, a->rd); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_lu_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcvt_h_l *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_l(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} + +static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fcvt_h_lu *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_FPU; + REQUIRE_ZFH(ctx); + + TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN); + + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_lu(cpu_fpr[a->rd], cpu_env, t0); + + mark_fs_dirty(ctx); + return true; +} diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b15ad394bb..065e8162a2 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -22,26 +22,30 @@ #include "hw/registerfields.h" /* share data between vector helpers and decode code */ -FIELD(VDATA, MLEN, 0, 8) -FIELD(VDATA, VM, 8, 1) -FIELD(VDATA, LMUL, 9, 2) -FIELD(VDATA, NF, 11, 4) -FIELD(VDATA, WD, 11, 1) +FIELD(VDATA, VM, 0, 1) +FIELD(VDATA, LMUL, 1, 3) +FIELD(VDATA, NF, 4, 4) +FIELD(VDATA, WD, 4, 1) /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); -#define SEW8 0 -#define SEW16 1 -#define SEW32 2 -#define SEW64 3 - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; #endif +enum { + RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ + RISCV_FRM_RTZ = 1, /* Round towards Zero */ + RISCV_FRM_RDN = 2, /* Round Down */ + RISCV_FRM_RUP = 3, /* Round Up */ + RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ + RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ + RISCV_FRM_ROD = 8, /* Round to Odd */ +}; + static inline uint64_t nanbox_s(float32 f) { return f | MAKE_64BIT_MASK(32, 32); @@ -58,4 +62,20 @@ static inline float32 check_nanbox_s(uint64_t f) } } +static inline uint64_t nanbox_h(float16 f) +{ + return f | MAKE_64BIT_MASK(16, 48); +} + +static inline float16 check_nanbox_h(uint64_t f) +{ + uint64_t mask = MAKE_64BIT_MASK(16, 48); + + if (likely((f & mask) == mask)) { + return (uint16_t)f; + } else { + return 0x7E00u; /* default qnan */ + } +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..5df6c0d800 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,9 +30,10 @@ #include "exec/log.h" #include "instmap.h" +#include "internals.h" /* global register indices */ -static TCGv cpu_gpr[32], cpu_pc, cpu_vl; +static TCGv cpu_gpr[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -62,7 +63,9 @@ typedef struct DisasContext { uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; + uint32_t mstatus_vs; uint32_t mstatus_hs_fs; + uint32_t mstatus_hs_vs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -73,13 +76,28 @@ typedef struct DisasContext { RISCVMXL ol; bool virt_enabled; bool ext_ifencei; + bool ext_zfh; + bool ext_zfhmin; bool hlsx; /* vector extension */ bool vill; - uint8_t lmul; + /* + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ + int8_t lmul; uint8_t sew; uint16_t vlen; - uint16_t mlen; + uint16_t elen; + target_ulong vstart; bool vl_eq_vlmax; uint8_t ntemp; CPUState *cs; @@ -134,6 +152,11 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); } +static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); +} + /* * A narrow n-bit operation, where n < FLEN, checks that input operands * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. @@ -142,6 +165,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) * * Here, the result is always nan-boxed, even the canonical nan. */ +static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) +{ + TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); + TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); + + tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); + tcg_temp_free_i64(t_max); + tcg_temp_free_i64(t_nan); +} + static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) { TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); @@ -331,12 +364,54 @@ static void mark_fs_dirty(DisasContext *ctx) static inline void mark_fs_dirty(DisasContext *ctx) { } #endif +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_vs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_vs_dirty(DisasContext *ctx) +{ + TCGv tmp; + + if (ctx->mstatus_vs != MSTATUS_VS) { + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_vs = MSTATUS_VS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); + } + + if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { + /* Remember the stage change for the rest of the TB. */ + ctx->mstatus_hs_vs = MSTATUS_VS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_temp_free(tmp); + } +} +#else +static inline void mark_vs_dirty(DisasContext *ctx) { } +#endif + static void gen_set_rm(DisasContext *ctx, int rm) { if (ctx->frm == rm) { return; } ctx->frm = rm; + + if (rm == RISCV_FRM_ROD) { + gen_helper_set_rod_rounding_mode(cpu_env); + return; + } + gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } @@ -574,6 +649,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvh.c.inc" #include "insn_trans/trans_rvv.c.inc" #include "insn_trans/trans_rvb.c.inc" +#include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" /* Include the auto-generated decoder for 16 bit insn */ @@ -613,6 +689,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver = env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { @@ -626,13 +703,17 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; + ctx->ext_zfh = cpu->cfg.ext_zfh; + ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; ctx->vlen = cpu->cfg.vlen; + ctx->elen = cpu->cfg.elen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); + ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); - ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); - ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); + ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); + ctx->vstart = env->vstart; ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs = cs; @@ -751,6 +832,8 @@ void riscv_translate_init(void) cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); + cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), + "vstart"); load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), "load_res"); load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..ad505ec9b2 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -17,6 +17,8 @@ */ #include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -31,12 +33,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, { int vlmax, vl; RISCVCPU *cpu = env_archcpu(env); + uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL); uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW); uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); bool vill = FIELD_EX64(s2, VTYPE, VILL); target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED); - if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { + if (lmul & 4) { + /* Fractional LMUL. */ + if (lmul == 4 || + cpu->cfg.elen >> (8 - lmul) < sew) { + vill = true; + } + } + + if ((sew > cpu->cfg.elen) + || vill + || (ediv != 0) + || (reserved != 0)) { /* only set vill bit. */ env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); env->vl = 0; @@ -81,35 +95,44 @@ static inline uint32_t vext_nf(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, NF); } -static inline uint32_t vext_mlen(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, MLEN); -} - static inline uint32_t vext_vm(uint32_t desc) { return FIELD_EX32(simd_data(desc), VDATA, VM); } -static inline uint32_t vext_lmul(uint32_t desc) +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) { - return FIELD_EX32(simd_data(desc), VDATA, LMUL); -} - -static uint32_t vext_wd(uint32_t desc) -{ - return (simd_data(desc) >> 11) & 0x1; + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); } /* - * Get vector group length in bytes. Its range is [64, 2048]. + * Get the maximum number of elements can be operated. * - * As simd_desc support at most 256, the max vlen is 512 bits. - * So vlen in bytes is encoded as maxsz. + * esz: log2 of element size in bytes. */ -static inline uint32_t vext_maxsz(uint32_t desc) +static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz) { - return simd_maxsz(desc) << vext_lmul(desc); + /* + * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits. + * so vlen in bytes (vlenb) is encoded as maxsz. + */ + uint32_t vlenb = simd_maxsz(desc); + + /* Return VLMAX */ + int scale = vext_lmul(desc) - esz; + return scale < 0 ? vlenb >> -scale : vlenb << scale; } /* @@ -139,108 +162,43 @@ static void probe_pages(CPURISCVState *env, target_ulong addr, } } -#ifdef HOST_WORDS_BIGENDIAN -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) +static inline void vext_set_elem_mask(void *v0, int index, + uint8_t value) { - /* - * Split the remaining range to two parts. - * The first part is in the last uint64_t unit. - * The second part start from the next uint64_t unit. - */ - int part1 = 0, part2 = tot - cnt; - if (cnt % 8) { - part1 = 8 - (cnt % 8); - part2 = tot - cnt - part1; - memset(QEMU_ALIGN_PTR_DOWN(tail, 8), 0, part1); - memset(QEMU_ALIGN_PTR_UP(tail, 8), 0, part2); - } else { - memset(tail, 0, part2); - } -} -#else -static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) -{ - memset(tail, 0, tot - cnt); -} -#endif - -static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int8_t *cur = ((int8_t *)vd + H1(idx)); - vext_clear(cur, cnt, tot); -} - -static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int16_t *cur = ((int16_t *)vd + H2(idx)); - vext_clear(cur, cnt, tot); -} - -static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int32_t *cur = ((int32_t *)vd + H4(idx)); - vext_clear(cur, cnt, tot); -} - -static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) -{ - int64_t *cur = (int64_t *)vd + idx; - vext_clear(cur, cnt, tot); -} - -static inline void vext_set_elem_mask(void *v0, int mlen, int index, - uint8_t value) -{ - int idx = (index * mlen) / 64; - int pos = (index * mlen) % 64; + int idx = index / 64; + int pos = index % 64; uint64_t old = ((uint64_t *)v0)[idx]; - ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value); + ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value); } -static inline int vext_elem_mask(void *v0, int mlen, int index) +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) { - int idx = (index * mlen) / 64; - int pos = (index * mlen) % 64; + int idx = index / 64; + int pos = index % 64; return (((uint64_t *)v0)[idx] >> pos) & 1; } /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); -typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot); -#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \ +#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ uint32_t idx, void *vd, uintptr_t retaddr)\ { \ - MTYPE data; \ ETYPE *cur = ((ETYPE *)vd + H(idx)); \ - data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ - *cur = data; \ + *cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ } \ -GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb) -GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb) -GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb) -GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw) -GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw) -GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl) -GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb) -GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw) -GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq) -GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub) -GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub) -GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub) -GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw) -GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw) -GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl) +GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static void NAME(CPURISCVState *env, abi_ptr addr, \ @@ -250,15 +208,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \ cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ } -GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb) -GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb) -GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb) -GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb) -GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw) -GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw) -GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw) -GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl) -GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl) GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) @@ -271,100 +220,57 @@ static void vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, - vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t mlen = vext_mlen(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); - /* probe every access*/ - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (i = env->vstart; i < env->vl; i++, env->vstart++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } - probe_pages(env, base + stride * i, nf * msz, ra, access_type); - } - /* do real access */ - for (i = 0; i < env->vl; i++) { + k = 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { - continue; - } while (k < nf) { - target_ulong addr = base + stride * i + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + target_ulong addr = base + stride * i + (k << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } - /* clear tail elements */ - if (clear_elem) { - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } - } + env->vstart = 0; } -#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq) +GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b) +GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h) +GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w) +GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d) -#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \ +#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ target_ulong stride, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vm = vext_vm(desc); \ vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ - NULL, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_STORE); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ } -GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b) -GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h) -GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w) -GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d) -GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h) -GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w) -GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d) -GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w) -GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d) -GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b) -GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h) -GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w) -GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) +GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) +GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h) +GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) +GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) /* *** unit-stride: access elements stored contiguously in memory @@ -373,31 +279,23 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) /* unmasked unit-stride load and store operation*/ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl, + uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); - /* probe every access */ - probe_pages(env, base, env->vl * nf * msz, ra, access_type); /* load bytes from guest memory */ - for (i = 0; i < env->vl; i++) { + for (i = env->vstart; i < evl; i++, env->vstart++) { k = 0; while (k < nf) { - target_ulong addr = base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + target_ulong addr = base + ((i * nf + k) << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } - /* clear tail elements */ - if (clear_elem) { - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } - } + env->vstart = 0; } /* @@ -405,76 +303,68 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, * stride = NF * sizeof (MTYPE) */ -#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } \ \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ - vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \ + vext_ldst_us(vd, base, env, desc, LOAD_FN, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq) +GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) +GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) +GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) +GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) -#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \ -void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - NULL, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_STORE); \ -} \ - \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\ +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ + vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ +} \ + \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_us(vd, base, env, desc, STORE_FN, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \ } -GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b) -GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h) -GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w) -GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d) -GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h) -GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w) -GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d) -GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w) -GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d) -GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b) -GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h) -GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w) -GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d) +GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) +GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) +GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) +GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) + +/* + *** unit stride mask load and store, EEW = 1 + */ +void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl = ceil(vl/8) */ + uint8_t evl = (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, lde_b, + 0, evl, GETPC(), MMU_DATA_LOAD); +} + +void HELPER(vsm_v)(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc) +{ + /* evl = ceil(vl/8) */ + uint8_t evl = (env->vl + 7) >> 3; + vext_ldst_us(vd, base, env, desc, ste_b, + 0, evl, GETPC(), MMU_DATA_STORE); +} /* *** index: access vector element from indexed memory @@ -489,108 +379,89 @@ static target_ulong NAME(target_ulong base, \ return (base + *((ETYPE *)vs2 + H(idx))); \ } -GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1) -GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2) -GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4) -GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8) +GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1) +GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2) +GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4) +GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8) static inline void vext_ldst_index(void *vd, void *v0, target_ulong base, void *vs2, CPURISCVState *env, uint32_t desc, vext_get_index_addr get_index_addr, vext_ldst_elem_fn *ldst_elem, - clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra, - MMUAccessType access_type) + uint32_t esz, uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t mlen = vext_mlen(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); - /* probe every access*/ - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { - continue; - } - probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, - access_type); - } /* load bytes from guest memory */ - for (i = 0; i < env->vl; i++) { - k = 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (i = env->vstart; i < env->vl; i++, env->vstart++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } + + k = 0; while (k < nf) { - abi_ptr addr = get_index_addr(base, i, vs2) + k * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } - /* clear tail elements */ - if (clear_elem) { - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } - } + env->vstart = 0; } -#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \ +#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC(), MMU_DATA_LOAD); \ + LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ } -GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb) -GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh) -GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl) -GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq) -GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh) -GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl) -GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq) -GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl) -GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq) -GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb) -GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh) -GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl) -GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq) -GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb) -GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh) -GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl) -GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq) -GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh) -GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl) -GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq) -GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl) -GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq) +GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b) +GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h) +GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w) +GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d) +GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b) +GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h) +GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w) +GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d) +GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b) +GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h) +GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w) +GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d) +GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b) +GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h) +GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w) +GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d) -#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\ +#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ - STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\ + STORE_FN, ctzl(sizeof(ETYPE)), \ GETPC(), MMU_DATA_STORE); \ } -GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b) -GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h) -GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w) -GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d) -GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h) -GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w) -GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d) -GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w) -GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d) -GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b) -GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h) -GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w) -GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d) +GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b) +GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h) +GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w) +GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d) +GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b) +GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h) +GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w) +GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d) +GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b) +GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h) +GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w) +GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d) +GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b) +GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h) +GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w) +GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) /* *** unit-stride fault-only-fisrt load instructions @@ -599,40 +470,38 @@ static inline void vext_ldff(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc, vext_ldst_elem_fn *ldst_elem, - clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra) + uint32_t esz, uintptr_t ra) { void *host; uint32_t i, k, vl = 0; - uint32_t mlen = vext_mlen(desc); uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz); target_ulong addr, offset, remain; /* probe every access*/ - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (i = env->vstart; i < env->vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } - addr = base + nf * i * msz; + addr = base + i * (nf << esz); if (i == 0) { - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD); } else { /* if it triggers an exception, no need to check watchpoint */ - remain = nf * msz; + remain = nf << esz; while (remain > 0) { offset = -(addr | TARGET_PAGE_MASK); host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + if (page_check_range(addr, nf << esz, PAGE_READ) < 0) { vl = i; goto ProbeSuccess; } #else - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); + probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD); #endif } else { vl = i; @@ -651,89 +520,39 @@ ProbeSuccess: if (vl != 0) { env->vl = vl; } - for (i = 0; i < env->vl; i++) { + for (i = env->vstart; i < env->vl; i++) { k = 0; - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } while (k < nf) { - target_ulong addr = base + (i * nf + k) * msz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + target_ulong addr = base + ((i * nf + k) << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } - /* clear tail elements */ - if (vl != 0) { - return; - } - for (k = 0; k < nf; k++) { - clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); - } + env->vstart = 0; } -#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \ - sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ +#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ + ctzl(sizeof(ETYPE)), GETPC()); \ } -GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb) -GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh) -GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl) -GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq) -GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh) -GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl) -GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq) -GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl) -GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq) -GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb) -GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh) -GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl) -GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq) -GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb) -GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh) -GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl) -GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq) -GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh) -GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl) -GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq) -GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl) -GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq) +GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b) +GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h) +GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w) +GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) -/* - *** Vector AMO Operations (Zvamo) - */ -typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, - uint32_t wd, uint32_t idx, CPURISCVState *env, - uintptr_t retaddr); - -/* no atomic opreation for vector atomic insructions */ #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) #define DO_XOR(N, M) (N ^ M) #define DO_OR(N, M) (N | M) #define DO_ADD(N, M) (N + M) -#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \ -static void \ -vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \ - uint32_t wd, uint32_t idx, \ - CPURISCVState *env, uintptr_t retaddr)\ -{ \ - typedef int##ESZ##_t ETYPE; \ - typedef int##MSZ##_t MTYPE; \ - typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \ - ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \ - MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \ - \ - cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \ - if (wd) { \ - *pe3 = a; \ - } \ -} - /* Signed min/max */ #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) @@ -742,103 +561,81 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \ #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) - -static inline void -vext_amo_noatomic(void *vs3, void *v0, target_ulong base, - void *vs2, CPURISCVState *env, uint32_t desc, - vext_get_index_addr get_index_addr, - vext_amo_noatomic_fn *noatomic_op, - clear_fn *clear_elem, - uint32_t esz, uint32_t msz, uintptr_t ra) +/* + *** load and store whole register instructions + */ +static void +vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra, + MMUAccessType access_type) { - uint32_t i; - target_long addr; - uint32_t wd = vext_wd(desc); - uint32_t vm = vext_vm(desc); - uint32_t mlen = vext_mlen(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t i, k, off, pos; + uint32_t nf = vext_nf(desc); + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3; + uint32_t max_elems = vlenb >> esz; - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { - continue; + k = env->vstart / max_elems; + off = env->vstart % max_elems; + + if (off) { + /* load/store rest of elements of current segment pointed by vstart */ + for (pos = off; pos < max_elems; pos++, env->vstart++) { + target_ulong addr = base + ((pos + k * max_elems) << esz); + ldst_elem(env, addr, pos + k * max_elems, vd, ra); } - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD); - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE); + k++; } - for (i = 0; i < env->vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { - continue; + + /* load/store elements for rest of segments */ + for (; k < nf; k++) { + for (i = 0; i < max_elems; i++, env->vstart++) { + target_ulong addr = base + ((i + k * max_elems) << esz); + ldst_elem(env, addr, i + k * max_elems, vd, ra); } - addr = get_index_addr(base, i, vs2); - noatomic_op(vs3, addr, wd, i, env, ra); } - clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); + + env->vstart = 0; } -#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \ -void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ -{ \ - vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \ - INDEX_FN, vext_##NAME##_noatomic_op, \ - CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ - GETPC()); \ +#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, LOAD_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), \ + MMU_DATA_LOAD); \ } -GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) -GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl) -GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl) -GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) +GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d) +GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b) +GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h) +GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w) +GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d) + +#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME)(void *vd, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_whole(vd, base, env, desc, STORE_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), \ + MMU_DATA_STORE); \ +} + +GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b) +GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b) +GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b) +GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) /* *** Vector Integer Arithmetic Instructions @@ -904,41 +701,39 @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivv2_fn *fn, clear_fn *clearfn) + opivv2_fn *fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; - for (i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i); } - clearfn(vd, vl, vl * dsz, vlmax * dsz); + env->vstart = 0; } /* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VV(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } -GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vadd_vv_b, 1, 1) +GEN_VEXT_VV(vadd_vv_h, 2, 2) +GEN_VEXT_VV(vadd_vv_w, 4, 4) +GEN_VEXT_VV(vadd_vv_d, 8, 8) +GEN_VEXT_VV(vsub_vv_b, 1, 1) +GEN_VEXT_VV(vsub_vv_h, 2, 2) +GEN_VEXT_VV(vsub_vv_w, 4, 4) +GEN_VEXT_VV(vsub_vv_d, 8, 8) typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); @@ -969,45 +764,43 @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivx2_fn fn, clear_fn *clearfn) + opivx2_fn fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; - for (i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i); } - clearfn(vd, vl, vl * dsz, vlmax * dsz); + env->vstart = 0; } /* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VX(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } -GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vadd_vx_b, 1, 1) +GEN_VEXT_VX(vadd_vx_h, 2, 2) +GEN_VEXT_VX(vadd_vx_w, 4, 4) +GEN_VEXT_VX(vadd_vx_d, 8, 8) +GEN_VEXT_VX(vsub_vx_b, 1, 1) +GEN_VEXT_VX(vsub_vx_h, 2, 2) +GEN_VEXT_VX(vsub_vx_w, 4, 4) +GEN_VEXT_VX(vsub_vx_d, 8, 8) +GEN_VEXT_VX(vrsub_vx_b, 1, 1) +GEN_VEXT_VX(vrsub_vx_h, 2, 2) +GEN_VEXT_VX(vrsub_vx_w, 4, 4) +GEN_VEXT_VX(vrsub_vx_d, 8, 8) void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc) { @@ -1086,30 +879,30 @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD) RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB) RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB) RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB) -GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq) -GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq) -GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh) -GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl) -GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq) +GEN_VEXT_VV(vwaddu_vv_b, 1, 2) +GEN_VEXT_VV(vwaddu_vv_h, 2, 4) +GEN_VEXT_VV(vwaddu_vv_w, 4, 8) +GEN_VEXT_VV(vwsubu_vv_b, 1, 2) +GEN_VEXT_VV(vwsubu_vv_h, 2, 4) +GEN_VEXT_VV(vwsubu_vv_w, 4, 8) +GEN_VEXT_VV(vwadd_vv_b, 1, 2) +GEN_VEXT_VV(vwadd_vv_h, 2, 4) +GEN_VEXT_VV(vwadd_vv_w, 4, 8) +GEN_VEXT_VV(vwsub_vv_b, 1, 2) +GEN_VEXT_VV(vwsub_vv_h, 2, 4) +GEN_VEXT_VV(vwsub_vv_w, 4, 8) +GEN_VEXT_VV(vwaddu_wv_b, 1, 2) +GEN_VEXT_VV(vwaddu_wv_h, 2, 4) +GEN_VEXT_VV(vwaddu_wv_w, 4, 8) +GEN_VEXT_VV(vwsubu_wv_b, 1, 2) +GEN_VEXT_VV(vwsubu_wv_h, 2, 4) +GEN_VEXT_VV(vwsubu_wv_w, 4, 8) +GEN_VEXT_VV(vwadd_wv_b, 1, 2) +GEN_VEXT_VV(vwadd_wv_h, 2, 4) +GEN_VEXT_VV(vwadd_wv_w, 4, 8) +GEN_VEXT_VV(vwsub_wv_b, 1, 2) +GEN_VEXT_VV(vwsub_wv_h, 2, 4) +GEN_VEXT_VV(vwsub_wv_w, 4, 8) RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD) RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD) @@ -1135,93 +928,87 @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD) RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB) RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB) RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB) -GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq) -GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq) -GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh) -GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl) -GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq) +GEN_VEXT_VX(vwaddu_vx_b, 1, 2) +GEN_VEXT_VX(vwaddu_vx_h, 2, 4) +GEN_VEXT_VX(vwaddu_vx_w, 4, 8) +GEN_VEXT_VX(vwsubu_vx_b, 1, 2) +GEN_VEXT_VX(vwsubu_vx_h, 2, 4) +GEN_VEXT_VX(vwsubu_vx_w, 4, 8) +GEN_VEXT_VX(vwadd_vx_b, 1, 2) +GEN_VEXT_VX(vwadd_vx_h, 2, 4) +GEN_VEXT_VX(vwadd_vx_w, 4, 8) +GEN_VEXT_VX(vwsub_vx_b, 1, 2) +GEN_VEXT_VX(vwsub_vx_h, 2, 4) +GEN_VEXT_VX(vwsub_vx_w, 4, 8) +GEN_VEXT_VX(vwaddu_wx_b, 1, 2) +GEN_VEXT_VX(vwaddu_wx_h, 2, 4) +GEN_VEXT_VX(vwaddu_wx_w, 4, 8) +GEN_VEXT_VX(vwsubu_wx_b, 1, 2) +GEN_VEXT_VX(vwsubu_wx_h, 2, 4) +GEN_VEXT_VX(vwsubu_wx_w, 4, 8) +GEN_VEXT_VX(vwadd_wx_b, 1, 2) +GEN_VEXT_VX(vwadd_wx_h, 2, 4) +GEN_VEXT_VX(vwadd_wx_w, 4, 8) +GEN_VEXT_VX(vwsub_wx_b, 1, 2) +GEN_VEXT_VX(vwsub_wx_h, 2, 4) +GEN_VEXT_VX(vwsub_wx_w, 4, 8) /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ #define DO_VADC(N, M, C) (N + M + C) #define DO_VSBC(N, M, C) (N - M - C) -#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \ +#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ + ETYPE carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb) -GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh) -GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl) -GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq) +GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC) +GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC) +GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC) +GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC) -GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb) -GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh) -GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl) -GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq) +GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC) +GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC) +GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC) +GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC) -#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \ +#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ + ETYPE carry = vext_elem_mask(v0, i); \ \ *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb) -GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh) -GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl) -GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq) +GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC) +GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC) +GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC) +GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC) -GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb) -GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh) -GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl) -GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq) +GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC) +GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC) +GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC) +GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC) #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \ (__typeof(N))(N + M) < N) @@ -1231,21 +1018,17 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ - \ - vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + ETYPE carry = !vm && vext_elem_mask(v0, i); \ + vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ + env->vstart = 0; \ } GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC) @@ -1262,21 +1045,17 @@ GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vm = vext_vm(desc); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - uint8_t carry = vext_elem_mask(v0, mlen, i); \ - \ - vext_set_elem_mask(vd, mlen, i, \ + ETYPE carry = !vm && vext_elem_mask(v0, i); \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ - } \ + env->vstart = 0; \ } GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC) @@ -1302,18 +1081,18 @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR) RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR) RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR) RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR) -GEN_VEXT_VV(vand_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vand_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vand_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vand_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vor_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vor_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vor_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vor_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vand_vv_b, 1, 1) +GEN_VEXT_VV(vand_vv_h, 2, 2) +GEN_VEXT_VV(vand_vv_w, 4, 4) +GEN_VEXT_VV(vand_vv_d, 8, 8) +GEN_VEXT_VV(vor_vv_b, 1, 1) +GEN_VEXT_VV(vor_vv_h, 2, 2) +GEN_VEXT_VV(vor_vv_w, 4, 4) +GEN_VEXT_VV(vor_vv_d, 8, 8) +GEN_VEXT_VV(vxor_vv_b, 1, 1) +GEN_VEXT_VV(vxor_vv_h, 2, 2) +GEN_VEXT_VV(vxor_vv_w, 4, 4) +GEN_VEXT_VV(vxor_vv_d, 8, 8) RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND) RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND) @@ -1327,111 +1106,105 @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR) RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR) RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR) RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR) -GEN_VEXT_VX(vand_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vand_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vand_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vand_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vor_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vor_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vor_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vor_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vand_vx_b, 1, 1) +GEN_VEXT_VX(vand_vx_h, 2, 2) +GEN_VEXT_VX(vand_vx_w, 4, 4) +GEN_VEXT_VX(vand_vx_d, 8, 8) +GEN_VEXT_VX(vor_vx_b, 1, 1) +GEN_VEXT_VX(vor_vx_h, 2, 2) +GEN_VEXT_VX(vor_vx_w, 4, 4) +GEN_VEXT_VX(vor_vx_d, 8, 8) +GEN_VEXT_VX(vxor_vx_b, 1, 1) +GEN_VEXT_VX(vxor_vx_h, 2, 2) +GEN_VEXT_VX(vxor_vx_w, 4, 4) +GEN_VEXT_VX(vxor_vx_d, 8, 8) /* Vector Single-Width Bit Shift Instructions */ #define DO_SLL(N, M) (N << (M)) #define DO_SRL(N, M) (N >> (M)) /* generate the helpers for shift instructions with two vector operators */ -#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \ +#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(TS1); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ TS1 s1 = *((TS1 *)vs1 + HS1(i)); \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb) -GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh) -GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl) -GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq) +GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7) +GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf) +GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f) +GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f) -GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f) /* generate the helpers for shift instructions with one vector and one scalar */ -#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t esz = sizeof(TD); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ - continue; \ - } \ - TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ - } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ + } \ + env->vstart = 0; \ } -GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb) -GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh) -GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl) -GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq) +GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7) +GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf) +GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f) +GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f) -GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb) -GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh) -GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl) -GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) +GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7) +GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f) /* Vector Narrowing Integer Right Shift Instructions */ -GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl) -GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) -GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl) -GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) -GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh) -GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) +GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) /* Vector Integer Comparison Instructions */ #define DO_MSEQ(N, M) (N == M) @@ -1444,23 +1217,19 @@ GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ) @@ -1497,23 +1266,19 @@ GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ - } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ) @@ -1573,22 +1338,22 @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX) RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX) RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX) RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX) -GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vminu_vv_b, 1, 1) +GEN_VEXT_VV(vminu_vv_h, 2, 2) +GEN_VEXT_VV(vminu_vv_w, 4, 4) +GEN_VEXT_VV(vminu_vv_d, 8, 8) +GEN_VEXT_VV(vmin_vv_b, 1, 1) +GEN_VEXT_VV(vmin_vv_h, 2, 2) +GEN_VEXT_VV(vmin_vv_w, 4, 4) +GEN_VEXT_VV(vmin_vv_d, 8, 8) +GEN_VEXT_VV(vmaxu_vv_b, 1, 1) +GEN_VEXT_VV(vmaxu_vv_h, 2, 2) +GEN_VEXT_VV(vmaxu_vv_w, 4, 4) +GEN_VEXT_VV(vmaxu_vv_d, 8, 8) +GEN_VEXT_VV(vmax_vv_b, 1, 1) +GEN_VEXT_VV(vmax_vv_h, 2, 2) +GEN_VEXT_VV(vmax_vv_w, 4, 4) +GEN_VEXT_VV(vmax_vv_d, 8, 8) RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN) RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN) @@ -1606,22 +1371,22 @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX) RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX) RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX) RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX) -GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vminu_vx_b, 1, 1) +GEN_VEXT_VX(vminu_vx_h, 2, 2) +GEN_VEXT_VX(vminu_vx_w, 4, 4) +GEN_VEXT_VX(vminu_vx_d, 8, 8) +GEN_VEXT_VX(vmin_vx_b, 1, 1) +GEN_VEXT_VX(vmin_vx_h, 2, 2) +GEN_VEXT_VX(vmin_vx_w, 4, 4) +GEN_VEXT_VX(vmin_vx_d, 8, 8) +GEN_VEXT_VX(vmaxu_vx_b, 1, 1) +GEN_VEXT_VX(vmaxu_vx_h, 2, 2) +GEN_VEXT_VX(vmaxu_vx_w, 4, 4) +GEN_VEXT_VX(vmaxu_vx_d, 8, 8) +GEN_VEXT_VX(vmax_vx_b, 1, 1) +GEN_VEXT_VX(vmax_vx_h, 2, 2) +GEN_VEXT_VX(vmax_vx_w, 4, 4) +GEN_VEXT_VX(vmax_vx_d, 8, 8) /* Vector Single-Width Integer Multiply Instructions */ #define DO_MUL(N, M) (N * M) @@ -1629,10 +1394,10 @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL) RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL) RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL) RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL) -GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmul_vv_b, 1, 1) +GEN_VEXT_VV(vmul_vv_h, 2, 2) +GEN_VEXT_VV(vmul_vv_w, 4, 4) +GEN_VEXT_VV(vmul_vv_d, 8, 8) static int8_t do_mulh_b(int8_t s2, int8_t s1) { @@ -1736,18 +1501,18 @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b) RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h) RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w) RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d) -GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmulh_vv_b, 1, 1) +GEN_VEXT_VV(vmulh_vv_h, 2, 2) +GEN_VEXT_VV(vmulh_vv_w, 4, 4) +GEN_VEXT_VV(vmulh_vv_d, 8, 8) +GEN_VEXT_VV(vmulhu_vv_b, 1, 1) +GEN_VEXT_VV(vmulhu_vv_h, 2, 2) +GEN_VEXT_VV(vmulhu_vv_w, 4, 4) +GEN_VEXT_VV(vmulhu_vv_d, 8, 8) +GEN_VEXT_VV(vmulhsu_vv_b, 1, 1) +GEN_VEXT_VV(vmulhsu_vv_h, 2, 2) +GEN_VEXT_VV(vmulhsu_vv_w, 4, 4) +GEN_VEXT_VV(vmulhsu_vv_d, 8, 8) RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL) RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL) @@ -1765,22 +1530,22 @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b) RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h) RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w) RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d) -GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmul_vx_b, 1, 1) +GEN_VEXT_VX(vmul_vx_h, 2, 2) +GEN_VEXT_VX(vmul_vx_w, 4, 4) +GEN_VEXT_VX(vmul_vx_d, 8, 8) +GEN_VEXT_VX(vmulh_vx_b, 1, 1) +GEN_VEXT_VX(vmulh_vx_h, 2, 2) +GEN_VEXT_VX(vmulh_vx_w, 4, 4) +GEN_VEXT_VX(vmulh_vx_d, 8, 8) +GEN_VEXT_VX(vmulhu_vx_b, 1, 1) +GEN_VEXT_VX(vmulhu_vx_h, 2, 2) +GEN_VEXT_VX(vmulhu_vx_w, 4, 4) +GEN_VEXT_VX(vmulhu_vx_d, 8, 8) +GEN_VEXT_VX(vmulhsu_vx_b, 1, 1) +GEN_VEXT_VX(vmulhsu_vx_h, 2, 2) +GEN_VEXT_VX(vmulhsu_vx_w, 4, 4) +GEN_VEXT_VX(vmulhsu_vx_d, 8, 8) /* Vector Integer Divide Instructions */ #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M) @@ -1806,22 +1571,22 @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM) RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM) RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM) RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM) -GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vdivu_vv_b, 1, 1) +GEN_VEXT_VV(vdivu_vv_h, 2, 2) +GEN_VEXT_VV(vdivu_vv_w, 4, 4) +GEN_VEXT_VV(vdivu_vv_d, 8, 8) +GEN_VEXT_VV(vdiv_vv_b, 1, 1) +GEN_VEXT_VV(vdiv_vv_h, 2, 2) +GEN_VEXT_VV(vdiv_vv_w, 4, 4) +GEN_VEXT_VV(vdiv_vv_d, 8, 8) +GEN_VEXT_VV(vremu_vv_b, 1, 1) +GEN_VEXT_VV(vremu_vv_h, 2, 2) +GEN_VEXT_VV(vremu_vv_w, 4, 4) +GEN_VEXT_VV(vremu_vv_d, 8, 8) +GEN_VEXT_VV(vrem_vv_b, 1, 1) +GEN_VEXT_VV(vrem_vv_h, 2, 2) +GEN_VEXT_VV(vrem_vv_w, 4, 4) +GEN_VEXT_VV(vrem_vv_d, 8, 8) RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU) RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU) @@ -1839,22 +1604,22 @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM) RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM) RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM) RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM) -GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vdivu_vx_b, 1, 1) +GEN_VEXT_VX(vdivu_vx_h, 2, 2) +GEN_VEXT_VX(vdivu_vx_w, 4, 4) +GEN_VEXT_VX(vdivu_vx_d, 8, 8) +GEN_VEXT_VX(vdiv_vx_b, 1, 1) +GEN_VEXT_VX(vdiv_vx_h, 2, 2) +GEN_VEXT_VX(vdiv_vx_w, 4, 4) +GEN_VEXT_VX(vdiv_vx_d, 8, 8) +GEN_VEXT_VX(vremu_vx_b, 1, 1) +GEN_VEXT_VX(vremu_vx_h, 2, 2) +GEN_VEXT_VX(vremu_vx_w, 4, 4) +GEN_VEXT_VX(vremu_vx_d, 8, 8) +GEN_VEXT_VX(vrem_vx_b, 1, 1) +GEN_VEXT_VX(vrem_vx_h, 2, 2) +GEN_VEXT_VX(vrem_vx_w, 4, 4) +GEN_VEXT_VX(vrem_vx_d, 8, 8) /* Vector Widening Integer Multiply Instructions */ RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL) @@ -1866,15 +1631,15 @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL) RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL) RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL) RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL) -GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmul_vv_b, 1, 2) +GEN_VEXT_VV(vwmul_vv_h, 2, 4) +GEN_VEXT_VV(vwmul_vv_w, 4, 8) +GEN_VEXT_VV(vwmulu_vv_b, 1, 2) +GEN_VEXT_VV(vwmulu_vv_h, 2, 4) +GEN_VEXT_VV(vwmulu_vv_w, 4, 8) +GEN_VEXT_VV(vwmulsu_vv_b, 1, 2) +GEN_VEXT_VV(vwmulsu_vv_h, 2, 4) +GEN_VEXT_VV(vwmulsu_vv_w, 4, 8) RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL) RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL) @@ -1885,15 +1650,15 @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL) RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL) RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL) RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL) -GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmul_vx_b, 1, 2) +GEN_VEXT_VX(vwmul_vx_h, 2, 4) +GEN_VEXT_VX(vwmul_vx_w, 4, 8) +GEN_VEXT_VX(vwmulu_vx_b, 1, 2) +GEN_VEXT_VX(vwmulu_vx_h, 2, 4) +GEN_VEXT_VX(vwmulu_vx_w, 4, 8) +GEN_VEXT_VX(vwmulsu_vx_b, 1, 2) +GEN_VEXT_VX(vwmulsu_vx_h, 2, 4) +GEN_VEXT_VX(vwmulsu_vx_w, 4, 8) /* Vector Single-Width Integer Multiply-Add Instructions */ #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ @@ -1925,22 +1690,22 @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB) RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB) RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB) RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB) -GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq) -GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb) -GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV(vmacc_vv_b, 1, 1) +GEN_VEXT_VV(vmacc_vv_h, 2, 2) +GEN_VEXT_VV(vmacc_vv_w, 4, 4) +GEN_VEXT_VV(vmacc_vv_d, 8, 8) +GEN_VEXT_VV(vnmsac_vv_b, 1, 1) +GEN_VEXT_VV(vnmsac_vv_h, 2, 2) +GEN_VEXT_VV(vnmsac_vv_w, 4, 4) +GEN_VEXT_VV(vnmsac_vv_d, 8, 8) +GEN_VEXT_VV(vmadd_vv_b, 1, 1) +GEN_VEXT_VV(vmadd_vv_h, 2, 2) +GEN_VEXT_VV(vmadd_vv_w, 4, 4) +GEN_VEXT_VV(vmadd_vv_d, 8, 8) +GEN_VEXT_VV(vnmsub_vv_b, 1, 1) +GEN_VEXT_VV(vnmsub_vv_h, 2, 2) +GEN_VEXT_VV(vnmsub_vv_w, 4, 4) +GEN_VEXT_VV(vnmsub_vv_d, 8, 8) #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ @@ -1966,22 +1731,22 @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB) RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB) RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB) RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB) -GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq) -GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb) -GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh) -GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl) -GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq) +GEN_VEXT_VX(vmacc_vx_b, 1, 1) +GEN_VEXT_VX(vmacc_vx_h, 2, 2) +GEN_VEXT_VX(vmacc_vx_w, 4, 4) +GEN_VEXT_VX(vmacc_vx_d, 8, 8) +GEN_VEXT_VX(vnmsac_vx_b, 1, 1) +GEN_VEXT_VX(vnmsac_vx_h, 2, 2) +GEN_VEXT_VX(vnmsac_vx_w, 4, 4) +GEN_VEXT_VX(vnmsac_vx_d, 8, 8) +GEN_VEXT_VX(vmadd_vx_b, 1, 1) +GEN_VEXT_VX(vmadd_vx_h, 2, 2) +GEN_VEXT_VX(vmadd_vx_w, 4, 4) +GEN_VEXT_VX(vmadd_vx_d, 8, 8) +GEN_VEXT_VX(vnmsub_vx_b, 1, 1) +GEN_VEXT_VX(vnmsub_vx_h, 2, 2) +GEN_VEXT_VX(vnmsub_vx_w, 4, 4) +GEN_VEXT_VX(vnmsub_vx_d, 8, 8) /* Vector Widening Integer Multiply-Add Instructions */ RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC) @@ -1993,15 +1758,15 @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC) RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC) RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC) RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC) -GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq) -GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmaccu_vv_b, 1, 2) +GEN_VEXT_VV(vwmaccu_vv_h, 2, 4) +GEN_VEXT_VV(vwmaccu_vv_w, 4, 8) +GEN_VEXT_VV(vwmacc_vv_b, 1, 2) +GEN_VEXT_VV(vwmacc_vv_h, 2, 4) +GEN_VEXT_VV(vwmacc_vv_w, 4, 8) +GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2) +GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4) +GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8) RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC) RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC) @@ -2015,106 +1780,96 @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC) RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC) RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC) RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC) -GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq) -GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh) -GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl) -GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmaccu_vx_b, 1, 2) +GEN_VEXT_VX(vwmaccu_vx_h, 2, 4) +GEN_VEXT_VX(vwmaccu_vx_w, 4, 8) +GEN_VEXT_VX(vwmacc_vx_b, 1, 2) +GEN_VEXT_VX(vwmacc_vx_h, 2, 4) +GEN_VEXT_VX(vwmacc_vx_w, 4, 8) +GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2) +GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4) +GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8) +GEN_VEXT_VX(vwmaccus_vx_b, 1, 2) +GEN_VEXT_VX(vwmaccus_vx_h, 2, 4) +GEN_VEXT_VX(vwmaccus_vx_w, 4, 8) /* Vector Integer Merge and Move Instructions */ -#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMV_VV(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ *((ETYPE *)vd + H(i)) = s1; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb) -GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2, clearh) -GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4, clearl) -GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8, clearq) +GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1) +GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2) +GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4) +GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8) -#define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMV_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \ uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ *((ETYPE *)vd + H(i)) = (ETYPE)s1; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb) -GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2, clearh) -GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4, clearl) -GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq) +GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1) +GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2) +GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4) +GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8) -#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \ + for (i = env->vstart; i < vl; i++) { \ + ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \ *((ETYPE *)vd + H(i)) = *(vt + H(i)); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb) -GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2, clearh) -GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4, clearl) -GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq) +GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1) +GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2) +GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4) +GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8) -#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \ + ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \ (ETYPE)(target_long)s1); \ *((ETYPE *)vd + H(i)) = d; \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb) -GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh) -GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl) -GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq) +GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) +GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2) +GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4) +GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8) /* *** Vector Fixed-Point Arithmetic Instructions @@ -2142,57 +1897,54 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \ static inline void vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm, + uint32_t vl, uint32_t vm, int vxrm, opivv2_rm_fn *fn) { - for (uint32_t i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (uint32_t i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, vs1, vs2, i, env, vxrm); } + env->vstart = 0; } static inline void vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivv2_rm_fn *fn, clear_fn *clearfn) + opivv2_rm_fn *fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; switch (env->vxrm) { case 0: /* rnu */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 0, fn); + env, vl, vm, 0, fn); break; case 1: /* rne */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 1, fn); + env, vl, vm, 1, fn); break; case 2: /* rdn */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 2, fn); + env, vl, vm, 2, fn); break; default: /* rod */ vext_vv_rm_1(vd, v0, vs1, vs2, - env, vl, vm, mlen, 3, fn); + env, vl, vm, 3, fn); break; } - - clearfn(vd, vl, vl * dsz, vlmax * dsz); } /* generate helpers for fixed point instructions with OPIVV format */ -#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) @@ -2242,10 +1994,10 @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8) RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16) RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32) RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64) -GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8) typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i, CPURISCVState *env, int vxrm); @@ -2262,67 +2014,64 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \ static inline void vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, - uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm, + uint32_t vl, uint32_t vm, int vxrm, opivx2_rm_fn *fn) { - for (uint32_t i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (uint32_t i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } fn(vd, s1, vs2, i, env, vxrm); } + env->vstart = 0; } static inline void vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t desc, uint32_t esz, uint32_t dsz, - opivx2_rm_fn *fn, clear_fn *clearfn) + opivx2_rm_fn *fn) { - uint32_t vlmax = vext_maxsz(desc) / esz; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; switch (env->vxrm) { case 0: /* rnu */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 0, fn); + env, vl, vm, 0, fn); break; case 1: /* rne */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 1, fn); + env, vl, vm, 1, fn); break; case 2: /* rdn */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 2, fn); + env, vl, vm, 2, fn); break; default: /* rod */ vext_vx_rm_1(vd, v0, s1, vs2, - env, vl, vm, mlen, 3, fn); + env, vl, vm, 3, fn); break; } - - clearfn(vd, vl, vl * dsz, vlmax * dsz); } /* generate helpers for fixed point instructions with OPIVX format */ -#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ - do_##NAME, CLEAR_FN); \ + do_##NAME); \ } RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8) RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16) RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32) RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64) -GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8) static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { @@ -2368,19 +2117,19 @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8) RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16) RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32) RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64) -GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1) +GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2) +GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4) +GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8) RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16) RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32) RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64) -GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1) +GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2) +GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4) +GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8) static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) { @@ -2429,19 +2178,19 @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8) RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16) RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32) RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64) -GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8) RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16) RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32) RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64) -GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8) static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { @@ -2487,19 +2236,19 @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8) RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16) RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32) RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64) -GEN_VEXT_VV_RM(vssub_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssub_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssub_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssub_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssub_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8) RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16) RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32) RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64) -GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssub_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssub_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssub_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssub_vx_d, 8, 8) /* Vector Single-Width Averaging Add and Subtract */ static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) @@ -2551,19 +2300,56 @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32) RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32) RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32) RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64) -GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1) +GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2) +GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4) +GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32) RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32) RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32) RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64) -GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1) +GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2) +GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4) +GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8) + +static inline uint32_t aaddu32(CPURISCVState *env, int vxrm, + uint32_t a, uint32_t b) +{ + uint64_t res = (uint64_t)a + b; + uint8_t round = get_round(vxrm, res, 1); + + return (res >> 1) + round; +} + +static inline uint64_t aaddu64(CPURISCVState *env, int vxrm, + uint64_t a, uint64_t b) +{ + uint64_t res = a + b; + uint8_t round = get_round(vxrm, res, 1); + uint64_t over = (uint64_t)(res < a) << 63; + + return ((res >> 1) | over) + round; +} + +RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32) +RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64) +GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8) + +RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32) +RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64) +GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8) static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) { @@ -2587,19 +2373,56 @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32) RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32) RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32) RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64) -GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vasub_vv_b, 1, 1) +GEN_VEXT_VV_RM(vasub_vv_h, 2, 2) +GEN_VEXT_VV_RM(vasub_vv_w, 4, 4) +GEN_VEXT_VV_RM(vasub_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32) RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32) RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32) RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64) -GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vasub_vx_b, 1, 1) +GEN_VEXT_VX_RM(vasub_vx_h, 2, 2) +GEN_VEXT_VX_RM(vasub_vx_w, 4, 4) +GEN_VEXT_VX_RM(vasub_vx_d, 8, 8) + +static inline uint32_t asubu32(CPURISCVState *env, int vxrm, + uint32_t a, uint32_t b) +{ + int64_t res = (int64_t)a - b; + uint8_t round = get_round(vxrm, res, 1); + + return (res >> 1) + round; +} + +static inline uint64_t asubu64(CPURISCVState *env, int vxrm, + uint64_t a, uint64_t b) +{ + uint64_t res = (uint64_t)a - b; + uint8_t round = get_round(vxrm, res, 1); + uint64_t over = (uint64_t)(res > a) << 63; + + return ((res >> 1) | over) + round; +} + +RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32) +RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64) +GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1) +GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2) +GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4) +GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8) + +RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32) +RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64) +GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1) +GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2) +GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4) +GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8) /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) @@ -2694,224 +2517,19 @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) -GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1) +GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2) +GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4) +GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) -GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq) - -/* Vector Widening Saturating Scaled Multiply-Add */ -static inline uint16_t -vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b, - uint16_t c) -{ - uint8_t round; - uint16_t res = (uint16_t)a * b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return saddu16(env, vxrm, c, res); -} - -static inline uint32_t -vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b, - uint32_t c) -{ - uint8_t round; - uint32_t res = (uint32_t)a * b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return saddu32(env, vxrm, c, res); -} - -static inline uint64_t -vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b, - uint64_t c) -{ - uint8_t round; - uint64_t res = (uint64_t)a * b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return saddu64(env, vxrm, c, res); -} - -#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static inline void \ -do_##NAME(void *vd, void *vs1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ -{ \ - TX1 s1 = *((T1 *)vs1 + HS1(i)); \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - TD d = *((TD *)vd + HD(i)); \ - *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \ -} - -RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8) -RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16) -RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32) -GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq) - -#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static inline void \ -do_##NAME(void *vd, target_long s1, void *vs2, int i, \ - CPURISCVState *env, int vxrm) \ -{ \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - TD d = *((TD *)vd + HD(i)); \ - *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \ -} - -RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8) -RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16) -RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32) -GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq) - -static inline int16_t -vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c) -{ - uint8_t round; - int16_t res = (int16_t)a * b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return sadd16(env, vxrm, c, res); -} - -static inline int32_t -vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c) -{ - uint8_t round; - int32_t res = (int32_t)a * b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return sadd32(env, vxrm, c, res); - -} - -static inline int64_t -vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c) -{ - uint8_t round; - int64_t res = (int64_t)a * b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return sadd64(env, vxrm, c, res); -} - -RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8) -RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16) -RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32) -GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq) -RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8) -RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16) -RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32) -GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq) - -static inline int16_t -vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c) -{ - uint8_t round; - int16_t res = a * (int16_t)b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return ssub16(env, vxrm, c, res); -} - -static inline int32_t -vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c) -{ - uint8_t round; - int32_t res = a * (int32_t)b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return ssub32(env, vxrm, c, res); -} - -static inline int64_t -vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c) -{ - uint8_t round; - int64_t res = a * (int64_t)b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return ssub64(env, vxrm, c, res); -} - -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8) -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16) -RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32) -GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh) -GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl) -GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16) -RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32) -GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq) - -static inline int16_t -vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c) -{ - uint8_t round; - int16_t res = (int16_t)a * b; - - round = get_round(vxrm, res, 4); - res = (res >> 4) + round; - return ssub16(env, vxrm, c, res); -} - -static inline int32_t -vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c) -{ - uint8_t round; - int32_t res = (int32_t)a * b; - - round = get_round(vxrm, res, 8); - res = (res >> 8) + round; - return ssub32(env, vxrm, c, res); -} - -static inline int64_t -vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c) -{ - uint8_t round; - int64_t res = (int64_t)a * b; - - round = get_round(vxrm, res, 16); - res = (res >> 16) + round; - return ssub64(env, vxrm, c, res); -} - -RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8) -RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16) -RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32) -GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh) -GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl) -GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq) +GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1) +GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2) +GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4) +GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8) /* Vector Single-Width Scaling Shift Instructions */ static inline uint8_t @@ -2958,19 +2576,19 @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8) RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16) RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32) RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64) -GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8) RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16) RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32) RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64) -GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8) static inline int8_t vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) @@ -3017,19 +2635,19 @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8) RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16) RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32) RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64) -GEN_VEXT_VV_RM(vssra_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vssra_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vssra_vv_w, 4, 4, clearl) -GEN_VEXT_VV_RM(vssra_vv_d, 8, 8, clearq) +GEN_VEXT_VV_RM(vssra_vv_b, 1, 1) +GEN_VEXT_VV_RM(vssra_vv_h, 2, 2) +GEN_VEXT_VV_RM(vssra_vv_w, 4, 4) +GEN_VEXT_VV_RM(vssra_vv_d, 8, 8) RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8) RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16) RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32) RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64) -GEN_VEXT_VX_RM(vssra_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vssra_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vssra_vx_w, 4, 4, clearl) -GEN_VEXT_VX_RM(vssra_vx_d, 8, 8, clearq) +GEN_VEXT_VX_RM(vssra_vx_b, 1, 1) +GEN_VEXT_VX_RM(vssra_vx_h, 2, 2) +GEN_VEXT_VX_RM(vssra_vx_w, 4, 4) +GEN_VEXT_VX_RM(vssra_vx_d, 8, 8) /* Vector Narrowing Fixed-Point Clip Instructions */ static inline int8_t @@ -3089,19 +2707,19 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b) } } -RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8) -RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16) -RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32) -GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl) +RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8) +RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16) +RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32) +GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1) +GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2) +GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4) -RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8) -RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16) -RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32) -GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl) +RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8) +RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16) +RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32) +GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1) +GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2) +GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4) static inline uint8_t vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b) @@ -3139,7 +2757,7 @@ static inline uint32_t vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) { uint8_t round, shift = b & 0x3f; - int64_t res; + uint64_t res; round = get_round(vxrm, a, shift); res = (a >> shift) + round; @@ -3151,19 +2769,19 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) } } -RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) -RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) -RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) -GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb) -GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh) -GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl) +RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) +RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) +RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) +GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1) +GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2) +GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4) -RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8) -RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16) -RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32) -GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb) -GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh) -GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl) +RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8) +RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16) +RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32) +GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1) +GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2) +GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4) /* *** Vector Float Point Arithmetic Instructions @@ -3178,32 +2796,30 @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \ } -#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs1, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + env->vstart = 0; \ } RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add) RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add) -GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8) #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ @@ -3213,45 +2829,43 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\ } -#define GEN_VEXT_VF(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_VF(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, s1, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + env->vstart = 0; \ } RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add) RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add) -GEN_VEXT_VF(vfadd_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfadd_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfadd_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfadd_vf_h, 2, 2) +GEN_VEXT_VF(vfadd_vf_w, 4, 4) +GEN_VEXT_VF(vfadd_vf_d, 8, 8) RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub) RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub) RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub) -GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8) RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub) RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub) RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub) -GEN_VEXT_VF(vfsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsub_vf_h, 2, 2) +GEN_VEXT_VF(vfsub_vf_w, 4, 4) +GEN_VEXT_VF(vfsub_vf_d, 8, 8) static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s) { @@ -3271,9 +2885,9 @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub) RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub) RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub) -GEN_VEXT_VF(vfrsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfrsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfrsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfrsub_vf_h, 2, 2) +GEN_VEXT_VF(vfrsub_vf_w, 4, 4) +GEN_VEXT_VF(vfrsub_vf_d, 8, 8) /* Vector Widening Floating-Point Add/Subtract Instructions */ static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s) @@ -3291,12 +2905,12 @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16) RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32) -GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8) RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16) RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32) -GEN_VEXT_VF(vfwadd_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwadd_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwadd_vf_h, 2, 4) +GEN_VEXT_VF(vfwadd_vf_w, 4, 8) static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s) { @@ -3313,12 +2927,12 @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16) RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32) -GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8) RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16) RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32) -GEN_VEXT_VF(vfwsub_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwsub_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwsub_vf_h, 2, 4) +GEN_VEXT_VF(vfwsub_vf_w, 4, 8) static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s) { @@ -3332,12 +2946,12 @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16) RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32) -GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8) RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16) RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32) -GEN_VEXT_VF(vfwadd_wf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwadd_wf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwadd_wf_h, 2, 4) +GEN_VEXT_VF(vfwadd_wf_w, 4, 8) static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s) { @@ -3351,39 +2965,39 @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s) RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16) RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32) -GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8) RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16) RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) -GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwsub_wf_h, 2, 4) +GEN_VEXT_VF(vfwsub_wf_w, 4, 8) /* Vector Single-Width Floating-Point Multiply/Divide Instructions */ RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) -GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8) RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) -GEN_VEXT_VF(vfmul_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmul_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmul_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmul_vf_h, 2, 2) +GEN_VEXT_VF(vfmul_vf_w, 4, 4) +GEN_VEXT_VF(vfmul_vf_d, 8, 8) RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div) RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div) RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div) -GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8) RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div) RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div) RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div) -GEN_VEXT_VF(vfdiv_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfdiv_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfdiv_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfdiv_vf_h, 2, 2) +GEN_VEXT_VF(vfdiv_vf_w, 4, 4) +GEN_VEXT_VF(vfdiv_vf_d, 8, 8) static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s) { @@ -3403,9 +3017,9 @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv) RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv) RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv) -GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfrdiv_vf_h, 2, 2) +GEN_VEXT_VF(vfrdiv_vf_w, 4, 4) +GEN_VEXT_VF(vfrdiv_vf_d, 8, 8) /* Vector Widening Floating-Point Multiply */ static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s) @@ -3422,12 +3036,12 @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s) } RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16) RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32) -GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8) RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16) RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32) -GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwmul_vf_h, 2, 4) +GEN_VEXT_VF(vfwmul_vf_w, 4, 8) /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ @@ -3458,9 +3072,9 @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16) RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32) RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64) -GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8) #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ @@ -3474,9 +3088,9 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16) RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32) RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64) -GEN_VEXT_VF(vfmacc_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmacc_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmacc_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmacc_vf_h, 2, 2) +GEN_VEXT_VF(vfmacc_vf_w, 4, 4) +GEN_VEXT_VF(vfmacc_vf_d, 8, 8) static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3499,15 +3113,15 @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32) RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64) -GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16) RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32) RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64) -GEN_VEXT_VF(vfnmacc_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmacc_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmacc_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmacc_vf_h, 2, 2) +GEN_VEXT_VF(vfnmacc_vf_w, 4, 4) +GEN_VEXT_VF(vfnmacc_vf_d, 8, 8) static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3527,15 +3141,15 @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16) RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32) RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64) -GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8) RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16) RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32) RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64) -GEN_VEXT_VF(vfmsac_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmsac_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmsac_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmsac_vf_h, 2, 2) +GEN_VEXT_VF(vfmsac_vf_w, 4, 4) +GEN_VEXT_VF(vfmsac_vf_d, 8, 8) static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3555,15 +3169,15 @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16) RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32) RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64) -GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16) RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32) RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64) -GEN_VEXT_VF(vfnmsac_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmsac_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmsac_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmsac_vf_h, 2, 2) +GEN_VEXT_VF(vfnmsac_vf_w, 4, 4) +GEN_VEXT_VF(vfnmsac_vf_d, 8, 8) static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3583,15 +3197,15 @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16) RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32) RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64) -GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8) RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16) RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32) RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64) -GEN_VEXT_VF(vfmadd_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmadd_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmadd_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmadd_vf_h, 2, 2) +GEN_VEXT_VF(vfmadd_vf_w, 4, 4) +GEN_VEXT_VF(vfmadd_vf_d, 8, 8) static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3614,15 +3228,15 @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32) RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64) -GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16) RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32) RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64) -GEN_VEXT_VF(vfnmadd_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmadd_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmadd_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmadd_vf_h, 2, 2) +GEN_VEXT_VF(vfnmadd_vf_w, 4, 4) +GEN_VEXT_VF(vfnmadd_vf_d, 8, 8) static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3642,15 +3256,15 @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16) RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32) RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64) -GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8) RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16) RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32) RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64) -GEN_VEXT_VF(vfmsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfmsub_vf_h, 2, 2) +GEN_VEXT_VF(vfmsub_vf_w, 4, 4) +GEN_VEXT_VF(vfmsub_vf_d, 8, 8) static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s) { @@ -3670,15 +3284,15 @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16) RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32) RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64) -GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8) RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16) RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32) RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64) -GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfnmsub_vf_h, 2, 2) +GEN_VEXT_VF(vfnmsub_vf_w, 4, 4) +GEN_VEXT_VF(vfnmsub_vf_d, 8, 8) /* Vector Widening Floating-Point Fused Multiply-Add Instructions */ static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) @@ -3695,12 +3309,12 @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16) RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32) -GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8) RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16) RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32) -GEN_VEXT_VF(vfwmacc_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwmacc_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwmacc_vf_h, 2, 4) +GEN_VEXT_VF(vfwmacc_vf_w, 4, 8) static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) { @@ -3718,12 +3332,12 @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32) -GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8) RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16) RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32) -GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4) +GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8) static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) { @@ -3741,12 +3355,12 @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32) -GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8) RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16) RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32) -GEN_VEXT_VF(vfwmsac_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwmsac_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwmsac_vf_h, 2, 4) +GEN_VEXT_VF(vfwmsac_vf_w, 4, 8) static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) { @@ -3764,12 +3378,12 @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32) -GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4, clearl) -GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8, clearq) +GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4) +GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8) RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16) RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) -GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4, clearl) -GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8, clearq) +GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4) +GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8) /* Vector Floating-Point Square-Root Instruction */ /* (TD, T2, TX2) */ @@ -3785,12 +3399,10 @@ static void do_##NAME(void *vd, void *vs2, int i, \ *((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \ } -#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ @@ -3798,48 +3410,421 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ if (vl == 0) { \ return; \ } \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i, env); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + env->vstart = 0; \ } RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt) RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) -GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2) +GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) +GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) + +/* + * Vector Floating-Point Reciprocal Square-Root Estimate Instruction + * + * Adapted from riscv-v-spec recip.c: + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c + */ +static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size) +{ + uint64_t sign = extract64(f, frac_size + exp_size, 1); + uint64_t exp = extract64(f, frac_size, exp_size); + uint64_t frac = extract64(f, 0, frac_size); + + const uint8_t lookup_table[] = { + 52, 51, 50, 48, 47, 46, 44, 43, + 42, 41, 40, 39, 38, 36, 35, 34, + 33, 32, 31, 30, 30, 29, 28, 27, + 26, 25, 24, 23, 23, 22, 21, 20, + 19, 19, 18, 17, 16, 16, 15, 14, + 14, 13, 12, 12, 11, 10, 10, 9, + 9, 8, 7, 7, 6, 6, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0, + 127, 125, 123, 121, 119, 118, 116, 114, + 113, 111, 109, 108, 106, 105, 103, 102, + 100, 99, 97, 96, 95, 93, 92, 91, + 90, 88, 87, 86, 85, 84, 83, 82, + 80, 79, 78, 77, 76, 75, 74, 73, + 72, 71, 70, 70, 69, 68, 67, 66, + 65, 64, 63, 63, 62, 61, 60, 59, + 59, 58, 57, 56, 56, 55, 54, 53 + }; + const int precision = 7; + + if (exp == 0 && frac != 0) { /* subnormal */ + /* Normalize the subnormal. */ + while (extract64(frac, frac_size - 1, 1) == 0) { + exp--; + frac <<= 1; + } + + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size); + } + + int idx = ((exp & 1) << (precision - 1)) | + (frac >> (frac_size - precision + 1)); + uint64_t out_frac = (uint64_t)(lookup_table[idx]) << + (frac_size - precision); + uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2; + + uint64_t val = 0; + val = deposit64(val, 0, frac_size, out_frac); + val = deposit64(val, frac_size, exp_size, out_exp); + val = deposit64(val, frac_size + exp_size, 1, sign); + return val; +} + +static float16 frsqrt7_h(float16 f, float_status *s) +{ + int exp_size = 5, frac_size = 10; + bool sign = float16_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float16_is_signaling_nan(f, s) || + (float16_is_infinity(f) && sign) || + (float16_is_normal(f) && sign) || + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float16_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float16_is_quiet_nan(f, s)) { + return float16_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float16_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float16_set_sign(float16_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float16_is_infinity(f) && !sign) { + return float16_set_sign(float16_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float16(val); +} + +static float32 frsqrt7_s(float32 f, float_status *s) +{ + int exp_size = 8, frac_size = 23; + bool sign = float32_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float32_is_signaling_nan(f, s) || + (float32_is_infinity(f) && sign) || + (float32_is_normal(f) && sign) || + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float32_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float32_is_quiet_nan(f, s)) { + return float32_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float32_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float32_set_sign(float32_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float32_is_infinity(f) && !sign) { + return float32_set_sign(float32_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float32(val); +} + +static float64 frsqrt7_d(float64 f, float_status *s) +{ + int exp_size = 11, frac_size = 52; + bool sign = float64_is_neg(f); + + /* + * frsqrt7(sNaN) = canonical NaN + * frsqrt7(-inf) = canonical NaN + * frsqrt7(-normal) = canonical NaN + * frsqrt7(-subnormal) = canonical NaN + */ + if (float64_is_signaling_nan(f, s) || + (float64_is_infinity(f) && sign) || + (float64_is_normal(f) && sign) || + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) { + s->float_exception_flags |= float_flag_invalid; + return float64_default_nan(s); + } + + /* frsqrt7(qNaN) = canonical NaN */ + if (float64_is_quiet_nan(f, s)) { + return float64_default_nan(s); + } + + /* frsqrt7(+-0) = +-inf */ + if (float64_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float64_set_sign(float64_infinity, sign); + } + + /* frsqrt7(+inf) = +0 */ + if (float64_is_infinity(f) && !sign) { + return float64_set_sign(float64_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val = frsqrt7(f, exp_size, frac_size); + return make_float64(val); +} + +RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h) +RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s) +RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d) +GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2) +GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4) +GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8) + +/* + * Vector Floating-Point Reciprocal Estimate Instruction + * + * Adapted from riscv-v-spec recip.c: + * https://github.com/riscv/riscv-v-spec/blob/master/recip.c + */ +static uint64_t frec7(uint64_t f, int exp_size, int frac_size, + float_status *s) +{ + uint64_t sign = extract64(f, frac_size + exp_size, 1); + uint64_t exp = extract64(f, frac_size, exp_size); + uint64_t frac = extract64(f, 0, frac_size); + + const uint8_t lookup_table[] = { + 127, 125, 123, 121, 119, 117, 116, 114, + 112, 110, 109, 107, 105, 104, 102, 100, + 99, 97, 96, 94, 93, 91, 90, 88, + 87, 85, 84, 83, 81, 80, 79, 77, + 76, 75, 74, 72, 71, 70, 69, 68, + 66, 65, 64, 63, 62, 61, 60, 59, + 58, 57, 56, 55, 54, 53, 52, 51, + 50, 49, 48, 47, 46, 45, 44, 43, + 42, 41, 40, 40, 39, 38, 37, 36, + 35, 35, 34, 33, 32, 31, 31, 30, + 29, 28, 28, 27, 26, 25, 25, 24, + 23, 23, 22, 21, 21, 20, 19, 19, + 18, 17, 17, 16, 15, 15, 14, 14, + 13, 12, 12, 11, 11, 10, 9, 9, + 8, 8, 7, 7, 6, 5, 5, 4, + 4, 3, 3, 2, 2, 1, 1, 0 + }; + const int precision = 7; + + if (exp == 0 && frac != 0) { /* subnormal */ + /* Normalize the subnormal. */ + while (extract64(frac, frac_size - 1, 1) == 0) { + exp--; + frac <<= 1; + } + + frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size); + + if (exp != 0 && exp != UINT64_MAX) { + /* + * Overflow to inf or max value of same sign, + * depending on sign and rounding mode. + */ + s->float_exception_flags |= (float_flag_inexact | + float_flag_overflow); + + if ((s->float_rounding_mode == float_round_to_zero) || + ((s->float_rounding_mode == float_round_down) && !sign) || + ((s->float_rounding_mode == float_round_up) && sign)) { + /* Return greatest/negative finite value. */ + return (sign << (exp_size + frac_size)) | + (MAKE_64BIT_MASK(frac_size, exp_size) - 1); + } else { + /* Return +-inf. */ + return (sign << (exp_size + frac_size)) | + MAKE_64BIT_MASK(frac_size, exp_size); + } + } + } + + int idx = frac >> (frac_size - precision); + uint64_t out_frac = (uint64_t)(lookup_table[idx]) << + (frac_size - precision); + uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp; + + if (out_exp == 0 || out_exp == UINT64_MAX) { + /* + * The result is subnormal, but don't raise the underflow exception, + * because there's no additional loss of precision. + */ + out_frac = (out_frac >> 1) | MAKE_64BIT_MASK(frac_size - 1, 1); + if (out_exp == UINT64_MAX) { + out_frac >>= 1; + out_exp = 0; + } + } + + uint64_t val = 0; + val = deposit64(val, 0, frac_size, out_frac); + val = deposit64(val, frac_size, exp_size, out_exp); + val = deposit64(val, frac_size + exp_size, 1, sign); + return val; +} + +static float16 frec7_h(float16 f, float_status *s) +{ + int exp_size = 5, frac_size = 10; + bool sign = float16_is_neg(f); + + /* frec7(+-inf) = +-0 */ + if (float16_is_infinity(f)) { + return float16_set_sign(float16_zero, sign); + } + + /* frec7(+-0) = +-inf */ + if (float16_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float16_set_sign(float16_infinity, sign); + } + + /* frec7(sNaN) = canonical NaN */ + if (float16_is_signaling_nan(f, s)) { + s->float_exception_flags |= float_flag_invalid; + return float16_default_nan(s); + } + + /* frec7(qNaN) = canonical NaN */ + if (float16_is_quiet_nan(f, s)) { + return float16_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val = frec7(f, exp_size, frac_size, s); + return make_float16(val); +} + +static float32 frec7_s(float32 f, float_status *s) +{ + int exp_size = 8, frac_size = 23; + bool sign = float32_is_neg(f); + + /* frec7(+-inf) = +-0 */ + if (float32_is_infinity(f)) { + return float32_set_sign(float32_zero, sign); + } + + /* frec7(+-0) = +-inf */ + if (float32_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float32_set_sign(float32_infinity, sign); + } + + /* frec7(sNaN) = canonical NaN */ + if (float32_is_signaling_nan(f, s)) { + s->float_exception_flags |= float_flag_invalid; + return float32_default_nan(s); + } + + /* frec7(qNaN) = canonical NaN */ + if (float32_is_quiet_nan(f, s)) { + return float32_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val = frec7(f, exp_size, frac_size, s); + return make_float32(val); +} + +static float64 frec7_d(float64 f, float_status *s) +{ + int exp_size = 11, frac_size = 52; + bool sign = float64_is_neg(f); + + /* frec7(+-inf) = +-0 */ + if (float64_is_infinity(f)) { + return float64_set_sign(float64_zero, sign); + } + + /* frec7(+-0) = +-inf */ + if (float64_is_zero(f)) { + s->float_exception_flags |= float_flag_divbyzero; + return float64_set_sign(float64_infinity, sign); + } + + /* frec7(sNaN) = canonical NaN */ + if (float64_is_signaling_nan(f, s)) { + s->float_exception_flags |= float_flag_invalid; + return float64_default_nan(s); + } + + /* frec7(qNaN) = canonical NaN */ + if (float64_is_quiet_nan(f, s)) { + return float64_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val = frec7(f, exp_size, frac_size, s); + return make_float64(val); +} + +RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h) +RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s) +RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d) +GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2) +GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4) +GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8) /* Vector Floating-Point MIN/MAX Instructions */ -RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) -RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) -RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) -GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq) -RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) -RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) -RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) -GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq) +RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) +RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) +RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number) +GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8) +RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number) +RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number) +RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number) +GEN_VEXT_VF(vfmin_vf_h, 2, 2) +GEN_VEXT_VF(vfmin_vf_w, 4, 4) +GEN_VEXT_VF(vfmin_vf_d, 8, 8) -RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) -RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) -RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) -GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq) -RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) -RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) -RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) -GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq) +RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number) +RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number) +RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number) +GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8) +RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number) +RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number) +RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number) +GEN_VEXT_VF(vfmax_vf_h, 2, 2) +GEN_VEXT_VF(vfmax_vf_w, 4, 4) +GEN_VEXT_VF(vfmax_vf_d, 8, 8) /* Vector Floating-Point Sign-Injection Instructions */ static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s) @@ -3860,15 +3845,15 @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16) RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32) RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64) -GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8) RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16) RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32) RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64) -GEN_VEXT_VF(vfsgnj_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsgnj_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsgnj_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsgnj_vf_h, 2, 2) +GEN_VEXT_VF(vfsgnj_vf_w, 4, 4) +GEN_VEXT_VF(vfsgnj_vf_d, 8, 8) static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s) { @@ -3888,15 +3873,15 @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16) RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32) RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64) -GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8) RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16) RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32) RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64) -GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2) +GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4) +GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8) static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s) { @@ -3916,39 +3901,35 @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s) RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16) RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32) RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64) -GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2, clearh) -GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4, clearl) -GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8, clearq) +GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2) +GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4) +GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8) RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16) RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32) RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64) -GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2, clearh) -GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl) -GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) +GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2) +GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4) +GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8) /* Vector Floating-Point Compare Instructions */ #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, s1, &env->fp_status)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ - } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) @@ -3959,23 +3940,19 @@ GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - vext_set_elem_mask(vd, mlen, i, \ + vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ - } \ + env->vstart = 0; \ } GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet) @@ -4068,13 +4045,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) -GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) -GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) -GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) -GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) - /* Vector Floating-Point Classify Instruction */ #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i) \ @@ -4083,23 +4053,21 @@ static void do_##NAME(void *vd, void *vs2, int i) \ *((TD *)vd + HD(i)) = OP(s2); \ } -#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \ +#define GEN_VEXT_V(NAME, ESZ, DSZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ do_##NAME(vd, vs2, i); \ } \ - CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ + env->vstart = 0; \ } target_ulong fclass_h(uint64_t frs1) @@ -4162,97 +4130,99 @@ target_ulong fclass_d(uint64_t frs1) RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h) RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s) RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) -GEN_VEXT_V(vfclass_v_h, 2, 2, clearh) -GEN_VEXT_V(vfclass_v_w, 4, 4, clearl) -GEN_VEXT_V(vfclass_v_d, 8, 8, clearq) +GEN_VEXT_V(vfclass_v_h, 2, 2) +GEN_VEXT_V(vfclass_v_w, 4, 4) +GEN_VEXT_V(vfclass_v_d, 8, 8) /* Vector Floating-Point Merge Instruction */ -#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VFMERGE_VF(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ *((ETYPE *)vd + H(i)) \ - = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \ + = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ - CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ + env->vstart = 0; \ } -GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh) -GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl) -GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq) +GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2) +GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4) +GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8) /* Single-Width Floating-Point/Integer Type-Convert Instructions */ /* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16) RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32) RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64) -GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8) /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */ RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16) RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32) RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64) -GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8) /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */ RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16) RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32) RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64) -GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8) /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */ RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16) RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32) RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64) -GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl) -GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq) +GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2) +GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4) +GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8) /* Widening Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define WOP_UU_B uint16_t, uint8_t, uint8_t #define WOP_UU_H uint32_t, uint16_t, uint16_t #define WOP_UU_W uint64_t, uint32_t, uint32_t /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/ RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32) RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64) -GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8) /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */ RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32) RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64) -GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8) /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */ +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8) /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ +RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) -GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8) /* - * vfwcvt.f.f.v vd, vs2, vm # + * vfwcvt.f.f.v vd, vs2, vm * Convert single-width float to double-width float. */ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) @@ -4262,36 +4232,41 @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16) RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64) -GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4, clearl) -GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq) +GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4) +GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8) /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define NOP_UU_B uint8_t, uint16_t, uint32_t #define NOP_UU_H uint16_t, uint32_t, uint32_t #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ -RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) -RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8) +RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16) +RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4) /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */ -RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) -RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) -GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8) +RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16) +RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32) +GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4) /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */ -RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4) /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ -RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4) /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */ static uint16_t vfncvtffv16(uint32_t a, float_status *s) @@ -4299,179 +4274,171 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s) return float32_to_float16(a, true, s); } -RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) -RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh) -GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl) +RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16) +RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4) /* *** Vector Reduction Operations */ /* Vector Single-Width Integer Reduction Instructions */ -#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ +#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \ TD s1 = *((TD *)vs1 + HD(0)); \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ s1 = OP(s1, (TD)s2); \ } \ *((TD *)vd + HD(0)) = s1; \ - CLEAR_FN(vd, 1, sizeof(TD), tot); \ + env->vstart = 0; \ } /* vd[0] = sum(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb) -GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh) -GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl) -GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq) +GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD) +GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD) +GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD) +GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD) /* vd[0] = maxu(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb) -GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh) -GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl) -GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq) +GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX) +GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX) /* vd[0] = max(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb) -GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh) -GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl) -GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq) +GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX) +GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX) +GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX) +GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX) /* vd[0] = minu(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb) -GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh) -GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl) -GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq) +GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN) +GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN) +GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN) +GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN) /* vd[0] = min(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb) -GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh) -GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl) -GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq) +GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN) +GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN) +GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN) +GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN) /* vd[0] = and(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb) -GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh) -GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl) -GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq) +GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND) +GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND) +GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND) +GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND) /* vd[0] = or(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb) -GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh) -GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl) -GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq) +GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR) +GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR) +GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR) +GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR) /* vd[0] = xor(vs1[0], vs2[*]) */ -GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb) -GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh) -GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl) -GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq) +GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR) +GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR) +GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR) +GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR) /* Vector Widening Integer Reduction Instructions */ /* signed sum reduction into double-width accumulator */ -GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh) -GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl) -GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq) +GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD) +GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD) +GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD) /* Unsigned sum reduction into double-width accumulator */ -GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh) -GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl) -GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq) +GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD) +GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD) +GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD) /* Vector Single-Width Floating-Point Reduction Instructions */ -#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\ +#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t i; \ - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \ TD s1 = *((TD *)vs1 + HD(0)); \ \ - for (i = 0; i < vl; i++) { \ + for (i = env->vstart; i < vl; i++) { \ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ s1 = OP(s1, (TD)s2, &env->fp_status); \ } \ *((TD *)vd + HD(0)) = s1; \ - CLEAR_FN(vd, 1, sizeof(TD), tot); \ + env->vstart = 0; \ } /* Unordered sum */ -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh) -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl) -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq) +GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) +GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) +GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) /* Maximum value */ -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh) -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl) -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq) +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_number) /* Minimum value */ -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh) -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl) -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq) +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_number) /* Vector Widening Floating-Point Reduction Instructions */ /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; uint32_t s1 = *((uint32_t *)vs1 + H4(0)); - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { uint16_t s2 = *((uint16_t *)vs2 + H2(i)); - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status), &env->fp_status); } *((uint32_t *)vd + H4(0)) = s1; - clearl(vd, 1, sizeof(uint32_t), tot); + env->vstart = 0; } void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc) { - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; uint32_t i; - uint32_t tot = env_archcpu(env)->cfg.vlen / 8; uint64_t s1 = *((uint64_t *)vs1); - for (i = 0; i < vl; i++) { + for (i = env->vstart; i < vl; i++) { uint32_t s2 = *((uint32_t *)vs2 + H4(i)); - if (!vm && !vext_elem_mask(v0, mlen, i)) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status), &env->fp_status); } *((uint64_t *)vd) = s1; - clearq(vd, 1, sizeof(uint64_t), tot); + env->vstart = 0; } /* @@ -4483,20 +4450,16 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vl = env->vl; \ uint32_t i; \ int a, b; \ \ - for (i = 0; i < vl; i++) { \ - a = vext_elem_mask(vs1, mlen, i); \ - b = vext_elem_mask(vs2, mlen, i); \ - vext_set_elem_mask(vd, mlen, i, OP(b, a)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, mlen, i, 0); \ + for (i = env->vstart; i < vl; i++) { \ + a = vext_elem_mask(vs1, i); \ + b = vext_elem_mask(vs2, i); \ + vext_set_elem_mask(vd, i, OP(b, a)); \ } \ + env->vstart = 0; \ } #define DO_NAND(N, M) (!(N & M)) @@ -4507,49 +4470,49 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ GEN_VEXT_MASK_VV(vmand_mm, DO_AND) GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND) -GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT) +GEN_VEXT_MASK_VV(vmandn_mm, DO_ANDNOT) GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR) GEN_VEXT_MASK_VV(vmor_mm, DO_OR) GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) -GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) +GEN_VEXT_MASK_VV(vmorn_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) -/* Vector mask population count vmpopc */ -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* Vector count population in mask vcpop */ +target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { target_ulong cnt = 0; - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; - for (i = 0; i < vl; i++) { - if (vm || vext_elem_mask(v0, mlen, i)) { - if (vext_elem_mask(vs2, mlen, i)) { + for (i = env->vstart; i < vl; i++) { + if (vm || vext_elem_mask(v0, i)) { + if (vext_elem_mask(vs2, i)) { cnt++; } } } + env->vstart = 0; return cnt; } -/* vmfirst find-first-set mask bit*/ -target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* vfirst find-first-set mask bit*/ +target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { - uint32_t mlen = vext_mlen(desc); uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; - for (i = 0; i < vl; i++) { - if (vm || vext_elem_mask(v0, mlen, i)) { - if (vext_elem_mask(vs2, mlen, i)) { + for (i = env->vstart; i < vl; i++) { + if (vm || vext_elem_mask(v0, i)) { + if (vext_elem_mask(vs2, i)) { return i; } } } + env->vstart = 0; return -1LL; } @@ -4562,40 +4525,36 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t mlen = vext_mlen(desc); - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; bool first_mask_bit = false; - for (i = 0; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, mlen, i)) { + for (i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { continue; } /* write a zero to all following active elements */ if (first_mask_bit) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); continue; } - if (vext_elem_mask(vs2, mlen, i)) { + if (vext_elem_mask(vs2, i)) { first_mask_bit = true; if (type == BEFORE_FIRST) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } else { - vext_set_elem_mask(vd, mlen, i, 1); + vext_set_elem_mask(vd, i, 1); } } else { if (type == ONLY_FIRST) { - vext_set_elem_mask(vd, mlen, i, 0); + vext_set_elem_mask(vd, i, 0); } else { - vext_set_elem_mask(vd, mlen, i, 1); + vext_set_elem_mask(vd, i, 1); } } } - for (; i < vlmax; i++) { - vext_set_elem_mask(vd, mlen, i, 0); - } + env->vstart = 0; } void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, @@ -4617,217 +4576,266 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, } /* Vector Iota Instruction */ -#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t sum = 0; \ int i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = sum; \ - if (vext_elem_mask(vs2, mlen, i)) { \ + if (vext_elem_mask(vs2, i)) { \ sum++; \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + env->vstart = 0; \ } -GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb) -GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh) -GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl) -GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq) +GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1) +GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2) +GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4) +GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8) /* Vector Element Index Instruction */ -#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VID_V(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ int i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = i; \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + env->vstart = 0; \ } -GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb) -GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh) -GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl) -GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) +GEN_VEXT_VID_V(vid_v_b, uint8_t, H1) +GEN_VEXT_VID_V(vid_v_h, uint16_t, H2) +GEN_VEXT_VID_V(vid_v_w, uint32_t, H4) +GEN_VEXT_VID_V(vid_v_d, uint64_t, H8) /* *** Vector Permutation Instructions */ /* Vector Slide Instructions */ -#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - target_ulong offset = s1, i; \ + target_ulong offset = s1, i_min, i; \ \ - for (i = offset; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + i_min = MAX(env->vstart, offset); \ + for (i = i_min; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ } /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */ -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8) -#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - target_ulong offset = s1, i; \ + target_ulong i_max, i; \ \ - for (i = 0; i < vl; ++i) { \ - target_ulong j = i + offset; \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ - continue; \ + i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \ + for (i = env->vstart; i < i_max; ++i) { \ + if (vm || vext_elem_mask(v0, i)) { \ + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \ } \ - *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + \ + for (i = i_max; i < vl; ++i) { \ + if (vm || vext_elem_mask(v0, i)) { \ + *((ETYPE *)vd + H(i)) = 0; \ + } \ + } \ + \ + env->vstart = 0; \ } /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */ -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) +GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) -#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ - continue; \ - } \ - if (i == 0) { \ - *((ETYPE *)vd + H(i)) = s1; \ - } else { \ - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ - } \ - } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +#define GEN_VEXT_VSLIE1UP(ESZ, H) \ +static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + typedef uint##ESZ##_t ETYPE; \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + if (i == 0) { \ + *((ETYPE *)vd + H(i)) = s1; \ + } else { \ + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ + } \ + } \ + env->vstart = 0; \ +} + +GEN_VEXT_VSLIE1UP(8, H1) +GEN_VEXT_VSLIE1UP(16, H2) +GEN_VEXT_VSLIE1UP(32, H4) +GEN_VEXT_VSLIE1UP(64, H8) + +#define GEN_VEXT_VSLIDE1UP_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \ } /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */ -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, 8) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, 16) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32) +GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64) -#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ - continue; \ - } \ - if (i == vl - 1) { \ - *((ETYPE *)vd + H(i)) = s1; \ - } else { \ - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ - } \ - } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +#define GEN_VEXT_VSLIDE1DOWN(ESZ, H) \ +static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + typedef uint##ESZ##_t ETYPE; \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + if (i == vl - 1) { \ + *((ETYPE *)vd + H(i)) = s1; \ + } else { \ + *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ + } \ + } \ + env->vstart = 0; \ +} + +GEN_VEXT_VSLIDE1DOWN(8, H1) +GEN_VEXT_VSLIDE1DOWN(16, H2) +GEN_VEXT_VSLIDE1DOWN(32, H4) +GEN_VEXT_VSLIDE1DOWN(64, H8) + +#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \ } /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */ -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, 8) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, 16) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, 32) +GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, 64) + +/* Vector Floating-Point Slide Instructions */ +#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \ +} + +/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */ +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, 16) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, 32) +GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, 64) + +#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \ +} + +/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */ +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, 16) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, 32) +GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64) /* Vector Register Gather Instruction */ -#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ - index = *((ETYPE *)vs1 + H(i)); \ + index = *((TS1 *)vs1 + HS1(i)); \ if (index >= vlmax) { \ - *((ETYPE *)vd + H(i)) = 0; \ + *((TS2 *)vd + HS2(i)) = 0; \ } else { \ - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ + *((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + env->vstart = 0; \ } /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */ -GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1, clearb) -GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2, clearh) -GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4, clearl) -GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq) +GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, uint8_t, H1, H1) +GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, uint16_t, H2, H2) +GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, uint32_t, H4, H4) +GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, uint64_t, H8, H8) -#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H, CLEAR_FN) \ +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_b, uint16_t, uint8_t, H2, H1) +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_h, uint16_t, uint16_t, H2, H2) +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_w, uint16_t, uint32_t, H2, H4) +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_d, uint16_t, uint64_t, H2, H8) + +#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint64_t index = s1; \ uint32_t i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ continue; \ } \ if (index >= vlmax) { \ @@ -4836,37 +4844,88 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ } \ } \ - CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + env->vstart = 0; \ } /* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ -GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb) -GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh) -GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl) -GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq) +GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1) +GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2) +GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4) +GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8) /* Vector Compress Instruction */ -#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \ +#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t mlen = vext_mlen(desc); \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ uint32_t vl = env->vl; \ uint32_t num = 0, i; \ \ - for (i = 0; i < vl; i++) { \ - if (!vext_elem_mask(vs1, mlen, i)) { \ + for (i = env->vstart; i < vl; i++) { \ + if (!vext_elem_mask(vs1, i)) { \ continue; \ } \ *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ num++; \ } \ - CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ + env->vstart = 0; \ } /* Compress into vd elements of vs2 where vs1 is enabled */ -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb) -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh) -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl) -GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) + +/* Vector Whole Register Move */ +#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \ +void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + /* EEW = 8 */ \ + uint32_t maxsz = simd_maxsz(desc); \ + uint32_t i = env->vstart; \ + \ + memcpy((uint8_t *)vd + H1(i), \ + (uint8_t *)vs2 + H1(i), \ + maxsz - env->vstart); \ + \ + env->vstart = 0; \ +} + +GEN_VEXT_VMV_WHOLE(vmv1r_v, 1) +GEN_VEXT_VMV_WHOLE(vmv2r_v, 2) +GEN_VEXT_VMV_WHOLE(vmv4r_v, 4) +GEN_VEXT_VMV_WHOLE(vmv8r_v, 8) + +/* Vector Integer Extension */ +#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vl = env->vl; \ + uint32_t vm = vext_vm(desc); \ + uint32_t i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \ + } \ + env->vstart = 0; \ +} + +GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1) +GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2) +GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4) +GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1) +GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2) +GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1) + +GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1) +GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2) +GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4) +GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1) +GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2) +GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 4ac71aec37..657db84ef0 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -20,7 +20,6 @@ #define RX_CPU_H #include "qemu/bitops.h" -#include "qemu-common.h" #include "hw/registerfields.h" #include "cpu-qom.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index ca3845d023..a75e559134 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -63,6 +63,8 @@ struct CPUS390XState { uint64_t etoken; /* etoken */ uint64_t etoken_extension; /* etoken extension */ + uint64_t diag318_info; + /* Fields up to this point are not cleared by initial CPU reset */ struct {} start_initial_reset_fields; @@ -118,8 +120,6 @@ struct CPUS390XState { uint16_t external_call_addr; DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); - uint64_t diag318_info; - #if !defined(CONFIG_USER_ONLY) uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ int tlb_fill_exc; /* exception number seen during tlb_fill */ diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 5b1fdb55c4..6acf14d5ec 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -1585,6 +1585,10 @@ void kvm_s390_set_diag318(CPUState *cs, uint64_t diag318_info) env->diag318_info = diag318_info; cs->kvm_run->s.regs.diag318 = diag318_info; cs->kvm_run->kvm_dirty_regs |= KVM_SYNC_DIAG318; + /* + * diag 318 info is zeroed during a clear reset and + * diag 308 IPL subcodes. + */ } } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 633b8a37ba..9d322cdba6 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2523,8 +2523,13 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2); return; case TCG_TYPE_V128: - /* regs 2; size 8; align 16 */ - tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2); + /* + * We have only 8-byte alignment for the stack per the ABI. + * Rather than dynamically re-align the stack, it's easier + * to simply not request alignment beyond that. So: + * regs 2; size 8; align 8 + */ + tcg_out_vldst(s, INSN_VLD1 | 0xad0, arg, arg1, arg2); return; default: g_assert_not_reached(); @@ -2543,8 +2548,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2); return; case TCG_TYPE_V128: - /* regs 2; size 8; align 16 */ - tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2); + /* See tcg_out_ld re alignment: regs 2; size 8; align 8 */ + tcg_out_vldst(s, INSN_VST1 | 0xad0, arg, arg1, arg2); return; default: g_assert_not_reached(); diff --git a/tcg/tcg.c b/tcg/tcg.c index 022aad58c2..ac989be5e6 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3071,7 +3071,13 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) g_assert_not_reached(); } - assert(align <= TCG_TARGET_STACK_ALIGN); + /* + * Assume the stack is sufficiently aligned. + * This affects e.g. ARM NEON, where we have 8 byte stack alignment + * and do not require 16 byte vector alignment. This seems slightly + * easier than fully parameterizing the above switch statement. + */ + align = MIN(TCG_TARGET_STACK_ALIGN, align); off = ROUND_UP(s->current_frame_offset, align); /* If we've exhausted the stack frame, restart with a smaller TB. */ diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot new file mode 100644 index 0000000000..1c3b4da5cb Binary files /dev/null and b/tests/data/acpi/q35/DSDT.viot differ diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot new file mode 100644 index 0000000000..9b179266cc Binary files /dev/null and b/tests/data/acpi/q35/VIOT.viot differ diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT new file mode 100644 index 0000000000..921f40d88c Binary files /dev/null and b/tests/data/acpi/virt/VIOT differ diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 258874167e..9a468e29eb 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1465,6 +1465,43 @@ static void test_acpi_virt_tcg(void) free_test_data(&data); } +static void test_acpi_q35_viot(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".viot", + }; + + /* + * To keep things interesting, two buses bypass the IOMMU. + * VIOT should only describes the other two buses. + */ + test_acpi_one("-machine default_bus_bypass_iommu=on " + "-device virtio-iommu-pci " + "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 " + "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on " + "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0", + &data); + free_test_data(&data); +} + +static void test_acpi_virt_viot(void) +{ + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57 " + "-device virtio-iommu-pci", &data); + free_test_data(&data); +} + static void test_oem_fields(test_data *data) { int i; @@ -1639,6 +1676,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); } + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); } else if (strcmp(arch, "aarch64") == 0) { if (has_tcg) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); @@ -1646,6 +1684,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); } } ret = g_test_run(); diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index 83828ba270..4d8e1343bd 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -285,7 +285,8 @@ int main(int argc, char *argv[]) g_test_init(&argc, &argv, NULL); for (i = 0; tests[i].arch != NULL; i++) { - if (strcmp(arch, tests[i].arch) == 0) { + if (g_str_equal(arch, tests[i].arch) && + qtest_has_machine(tests[i].machine)) { char *name = g_strdup_printf("boot-serial/%s", tests[i].machine); qtest_add_data_func(name, &tests[i], test_machine); g_free(name); diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index 5af944a5fb..c1fcac5c45 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -109,9 +109,11 @@ static void test_cdrom_param(gconstpointer data) static void add_cdrom_param_tests(const char **machines) { while (*machines) { - char *testname = g_strdup_printf("cdrom/param/%s", *machines); - qtest_add_data_func(testname, *machines, test_cdrom_param); - g_free(testname); + if (qtest_has_machine(*machines)) { + char *testname = g_strdup_printf("cdrom/param/%s", *machines); + qtest_add_data_func(testname, *machines, test_cdrom_param); + g_free(testname); + } machines++; } } diff --git a/tests/qtest/fuzz-lsi53c895a-test.c b/tests/qtest/fuzz-lsi53c895a-test.c new file mode 100644 index 0000000000..ba5d468970 --- /dev/null +++ b/tests/qtest/fuzz-lsi53c895a-test.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QTest fuzzer-generated testcase for LSI53C895A device + * + * Copyright (c) Red Hat + */ + +#include "qemu/osdep.h" +#include "libqos/libqtest.h" + +/* + * This used to trigger the assert in lsi_do_dma() + * https://bugs.launchpad.net/qemu/+bug/697510 + * https://bugs.launchpad.net/qemu/+bug/1905521 + * https://bugs.launchpad.net/qemu/+bug/1908515 + */ +static void test_lsi_do_dma_empty_queue(void) +{ + QTestState *s; + + s = qtest_init("-M q35 -nographic -monitor none -serial none " + "-drive if=none,id=drive0," + "file=null-co://,file.read-zeroes=on,format=raw " + "-device lsi53c895a,id=scsi0 " + "-device scsi-hd,drive=drive0," + "bus=scsi0.0,channel=0,scsi-id=0,lun=0"); + qtest_outl(s, 0xcf8, 0x80001814); + qtest_outl(s, 0xcfc, 0xe1068000); + qtest_outl(s, 0xcf8, 0x80001818); + qtest_outl(s, 0xcf8, 0x80001804); + qtest_outw(s, 0xcfc, 0x7); + qtest_outl(s, 0xcf8, 0x80002010); + + qtest_writeb(s, 0xe106802e, 0xff); /* Fill DSP bits 16-23 */ + qtest_writeb(s, 0xe106802f, 0xff); /* Fill DSP bits 24-31: trigger SCRIPT */ + + qtest_quit(s); +} + +int main(int argc, char **argv) +{ + const char *arch = qtest_get_arch(); + + g_test_init(&argc, &argv, NULL); + + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + qtest_add_func("fuzz/lsi53c895a/lsi_do_dma_empty_queue", + test_lsi_do_dma_empty_queue); + } + + return g_test_run(); +} diff --git a/tests/qtest/fuzz-megasas-test.c b/tests/qtest/fuzz-megasas-test.c index 940a76bf25..e1141c58a4 100644 --- a/tests/qtest/fuzz-megasas-test.c +++ b/tests/qtest/fuzz-megasas-test.c @@ -34,6 +34,34 @@ static void test_lp1878263_megasas_zero_iov_cnt(void) qtest_quit(s); } +/* + * Overflow SGL buffer. + * https://gitlab.com/qemu-project/qemu/-/issues/521 + */ +static void test_gitlab_issue521_megasas_sgl_ovf(void) +{ + QTestState *s = qtest_init("-display none -m 32M -machine q35 " + "-nodefaults -device megasas " + "-device scsi-cd,drive=null0 " + "-blockdev " + "driver=null-co,read-zeroes=on,node-name=null0"); + qtest_outl(s, 0xcf8, 0x80000818); + qtest_outl(s, 0xcfc, 0xc000); + qtest_outl(s, 0xcf8, 0x80000804); + qtest_outw(s, 0xcfc, 0x05); + qtest_bufwrite(s, 0x0, "\x01", 0x1); + qtest_bufwrite(s, 0x7, "\x01", 0x1); + qtest_bufwrite(s, 0x10, "\x02", 0x1); + qtest_bufwrite(s, 0x16, "\x01", 0x1); + qtest_bufwrite(s, 0x28, "\x01", 0x1); + qtest_bufwrite(s, 0x33, "\x01", 0x1); + qtest_outb(s, 0xc040, 0x0); + qtest_outb(s, 0xc040, 0x20); + qtest_outl(s, 0xc040, 0x20000000); + qtest_outb(s, 0xc040, 0x20); + qtest_quit(s); +} + int main(int argc, char **argv) { const char *arch = qtest_get_arch(); @@ -43,6 +71,8 @@ int main(int argc, char **argv) if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { qtest_add_func("fuzz/test_lp1878263_megasas_zero_iov_cnt", test_lp1878263_megasas_zero_iov_cnt); + qtest_add_func("fuzz/gitlab_issue521_megasas_sgl_ovf", + test_gitlab_issue521_megasas_sgl_ovf); } return g_test_run(); diff --git a/tests/qtest/ivshmem-test.c b/tests/qtest/ivshmem-test.c index dfa69424ed..fe94dd3b96 100644 --- a/tests/qtest/ivshmem-test.c +++ b/tests/qtest/ivshmem-test.c @@ -463,7 +463,6 @@ static gchar *mktempshm(int size, int *fd) int main(int argc, char **argv) { int ret, fd; - const char *arch = qtest_get_arch(); gchar dir[] = "/tmp/ivshmem-test.XXXXXX"; g_test_init(&argc, &argv, NULL); @@ -488,9 +487,7 @@ int main(int argc, char **argv) qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev); if (g_test_slow()) { qtest_add_func("/ivshmem/pair", test_ivshmem_pair); - if (strcmp(arch, "ppc64") != 0) { - qtest_add_func("/ivshmem/server", test_ivshmem_server); - } + qtest_add_func("/ivshmem/server", test_ivshmem_server); } out: diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index fba3e7a954..eaa2096512 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -639,8 +639,8 @@ void ahci_exec(AHCIQState *ahci, uint8_t port, AHCIOpts *opts; uint64_t buffer_in; - opts = g_memdup((opts_in == NULL ? &default_opts : opts_in), - sizeof(AHCIOpts)); + opts = g_memdup2((opts_in == NULL ? &default_opts : opts_in), + sizeof(AHCIOpts)); buffer_in = opts->buffer; @@ -860,7 +860,7 @@ AHCICommand *ahci_command_create(uint8_t command_name) g_assert(!props->ncq || props->lba48); /* Defaults and book-keeping */ - cmd->props = g_memdup(props, sizeof(AHCICommandProp)); + cmd->props = g_memdup2(props, sizeof(AHCICommandProp)); cmd->name = command_name; cmd->xbytes = props->size; cmd->prd_size = 4096; diff --git a/tests/qtest/libqos/libqtest.h b/tests/qtest/libqos/libqtest.h index 59e9271195..dff6b31cf0 100644 --- a/tests/qtest/libqos/libqtest.h +++ b/tests/qtest/libqos/libqtest.h @@ -710,6 +710,14 @@ QDict *qmp_fd(int fd, const char *fmt, ...) GCC_FMT_ATTR(2, 3); void qtest_cb_for_every_machine(void (*cb)(const char *machine), bool skip_old_versioned); +/** + * qtest_has_machine: + * @machine: The machine to look for + * + * Returns: true if the machine is available in the target binary. + */ +bool qtest_has_machine(const char *machine); + /** * qtest_qmp_device_add_qdict: * @qts: QTestState instance to operate on diff --git a/tests/qtest/libqos/meson.build b/tests/qtest/libqos/meson.build index 4af1f04787..e988d15791 100644 --- a/tests/qtest/libqos/meson.build +++ b/tests/qtest/libqos/meson.build @@ -41,6 +41,7 @@ libqos_srcs = files('../libqtest.c', 'virtio-rng.c', 'virtio-scsi.c', 'virtio-serial.c', + 'virtio-iommu.c', # qgraph machines: 'aarch64-xlnx-zcu102-machine.c', diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c index e1e96189c8..3a9076ae58 100644 --- a/tests/qtest/libqos/pci.c +++ b/tests/qtest/libqos/pci.c @@ -13,6 +13,8 @@ #include "qemu/osdep.h" #include "pci.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_regs.h" #include "qemu/host-utils.h" #include "qgraph.h" @@ -99,6 +101,123 @@ void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr) g_assert(!addr->device_id || device_id == addr->device_id); } +static uint8_t qpci_find_resource_reserve_capability(QPCIDevice *dev) +{ + uint16_t device_id; + uint8_t cap = 0; + + if (qpci_config_readw(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) { + return 0; + } + + device_id = qpci_config_readw(dev, PCI_DEVICE_ID); + + if (device_id != PCI_DEVICE_ID_REDHAT_PCIE_RP && + device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) { + return 0; + } + + do { + cap = qpci_find_capability(dev, PCI_CAP_ID_VNDR, cap); + } while (cap && + qpci_config_readb(dev, cap + REDHAT_PCI_CAP_TYPE_OFFSET) != + REDHAT_PCI_CAP_RESOURCE_RESERVE); + if (cap) { + uint8_t cap_len = qpci_config_readb(dev, cap + PCI_CAP_FLAGS); + if (cap_len < REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE) { + return 0; + } + } + return cap; +} + +static void qpci_secondary_buses_rec(QPCIBus *qbus, int bus, int *pci_bus) +{ + QPCIDevice *dev; + uint16_t class; + uint8_t pribus, secbus, subbus; + int index; + + for (index = 0; index < 32; index++) { + dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0)); + if (dev == NULL) { + continue; + } + class = qpci_config_readw(dev, PCI_CLASS_DEVICE); + if (class == PCI_CLASS_BRIDGE_PCI) { + qpci_config_writeb(dev, PCI_SECONDARY_BUS, 255); + qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 0); + } + g_free(dev); + } + + for (index = 0; index < 32; index++) { + dev = qpci_device_find(qbus, QPCI_DEVFN(bus + index, 0)); + if (dev == NULL) { + continue; + } + class = qpci_config_readw(dev, PCI_CLASS_DEVICE); + if (class != PCI_CLASS_BRIDGE_PCI) { + g_free(dev); + continue; + } + + pribus = qpci_config_readb(dev, PCI_PRIMARY_BUS); + if (pribus != bus) { + qpci_config_writeb(dev, PCI_PRIMARY_BUS, bus); + } + + secbus = qpci_config_readb(dev, PCI_SECONDARY_BUS); + (*pci_bus)++; + if (*pci_bus != secbus) { + secbus = *pci_bus; + qpci_config_writeb(dev, PCI_SECONDARY_BUS, secbus); + } + + subbus = qpci_config_readb(dev, PCI_SUBORDINATE_BUS); + qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, 255); + + qpci_secondary_buses_rec(qbus, secbus << 5, pci_bus); + + if (subbus != *pci_bus) { + uint8_t res_bus = *pci_bus; + uint8_t cap = qpci_find_resource_reserve_capability(dev); + + if (cap) { + uint32_t tmp_res_bus; + + tmp_res_bus = qpci_config_readl(dev, cap + + REDHAT_PCI_CAP_RES_RESERVE_BUS_RES); + if (tmp_res_bus != (uint32_t)-1) { + res_bus = tmp_res_bus & 0xFF; + if ((uint8_t)(res_bus + secbus) < secbus || + (uint8_t)(res_bus + secbus) < res_bus) { + res_bus = 0; + } + if (secbus + res_bus > *pci_bus) { + res_bus = secbus + res_bus; + } + } + } + subbus = res_bus; + *pci_bus = res_bus; + } + + qpci_config_writeb(dev, PCI_SUBORDINATE_BUS, subbus); + g_free(dev); + } +} + +int qpci_secondary_buses_init(QPCIBus *bus) +{ + int last_bus = 0; + + qpci_secondary_buses_rec(bus, 0, &last_bus); + + return last_bus; +} + + void qpci_device_enable(QPCIDevice *dev) { uint16_t cmd; diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h index ee64fdecbd..becb800f9e 100644 --- a/tests/qtest/libqos/pci.h +++ b/tests/qtest/libqos/pci.h @@ -81,6 +81,7 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, void *data); QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn); void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr); +int qpci_secondary_buses_init(QPCIBus *bus); bool qpci_has_buggy_msi(QPCIDevice *dev); bool qpci_check_buggy_msi(QPCIDevice *dev); diff --git a/tests/qtest/libqos/qgraph.c b/tests/qtest/libqos/qgraph.c index d1dc491930..109ff04e1e 100644 --- a/tests/qtest/libqos/qgraph.c +++ b/tests/qtest/libqos/qgraph.c @@ -93,7 +93,7 @@ static void add_edge(const char *source, const char *dest, edge->type = type; edge->dest = g_strdup(dest); edge->edge_name = g_strdup(opts->edge_name ?: dest); - edge->arg = g_memdup(opts->arg, opts->size_arg); + edge->arg = g_memdup2(opts->arg, opts->size_arg); edge->before_cmd_line = opts->before_cmd_line ? g_strconcat(" ", opts->before_cmd_line, NULL) : NULL; diff --git a/tests/qtest/libqos/virtio-iommu.c b/tests/qtest/libqos/virtio-iommu.c new file mode 100644 index 0000000000..18cba4ca36 --- /dev/null +++ b/tests/qtest/libqos/virtio-iommu.c @@ -0,0 +1,126 @@ +/* + * libqos driver virtio-iommu-pci framework + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at your + * option) any later version. See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "qemu/module.h" +#include "qgraph.h" +#include "virtio-iommu.h" +#include "hw/virtio/virtio-iommu.h" + +static QGuestAllocator *alloc; + +/* virtio-iommu-device */ +static void *qvirtio_iommu_get_driver(QVirtioIOMMU *v_iommu, + const char *interface) +{ + if (!g_strcmp0(interface, "virtio-iommu")) { + return v_iommu; + } + if (!g_strcmp0(interface, "virtio")) { + return v_iommu->vdev; + } + + fprintf(stderr, "%s not present in virtio-iommu-device\n", interface); + g_assert_not_reached(); +} + +static void virtio_iommu_cleanup(QVirtioIOMMU *interface) +{ + qvirtqueue_cleanup(interface->vdev->bus, interface->vq, alloc); +} + +static void virtio_iommu_setup(QVirtioIOMMU *interface) +{ + QVirtioDevice *vdev = interface->vdev; + uint64_t features; + + features = qvirtio_get_features(vdev); + features &= ~(QVIRTIO_F_BAD_FEATURE | + (1ull << VIRTIO_RING_F_INDIRECT_DESC) | + (1ull << VIRTIO_RING_F_EVENT_IDX) | + (1ull << VIRTIO_IOMMU_F_BYPASS)); + qvirtio_set_features(vdev, features); + interface->vq = qvirtqueue_setup(interface->vdev, alloc, 0); + qvirtio_set_driver_ok(interface->vdev); +} + +/* virtio-iommu-pci */ +static void *qvirtio_iommu_pci_get_driver(void *object, const char *interface) +{ + QVirtioIOMMUPCI *v_iommu = object; + if (!g_strcmp0(interface, "pci-device")) { + return v_iommu->pci_vdev.pdev; + } + return qvirtio_iommu_get_driver(&v_iommu->iommu, interface); +} + +static void qvirtio_iommu_pci_destructor(QOSGraphObject *obj) +{ + QVirtioIOMMUPCI *iommu_pci = (QVirtioIOMMUPCI *) obj; + QVirtioIOMMU *interface = &iommu_pci->iommu; + QOSGraphObject *pci_vobj = &iommu_pci->pci_vdev.obj; + + virtio_iommu_cleanup(interface); + qvirtio_pci_destructor(pci_vobj); +} + +static void qvirtio_iommu_pci_start_hw(QOSGraphObject *obj) +{ + QVirtioIOMMUPCI *iommu_pci = (QVirtioIOMMUPCI *) obj; + QVirtioIOMMU *interface = &iommu_pci->iommu; + QOSGraphObject *pci_vobj = &iommu_pci->pci_vdev.obj; + + qvirtio_pci_start_hw(pci_vobj); + virtio_iommu_setup(interface); +} + + +static void *virtio_iommu_pci_create(void *pci_bus, QGuestAllocator *t_alloc, + void *addr) +{ + QVirtioIOMMUPCI *virtio_rpci = g_new0(QVirtioIOMMUPCI, 1); + QVirtioIOMMU *interface = &virtio_rpci->iommu; + QOSGraphObject *obj = &virtio_rpci->pci_vdev.obj; + + virtio_pci_init(&virtio_rpci->pci_vdev, pci_bus, addr); + interface->vdev = &virtio_rpci->pci_vdev.vdev; + alloc = t_alloc; + + obj->get_driver = qvirtio_iommu_pci_get_driver; + obj->start_hw = qvirtio_iommu_pci_start_hw; + obj->destructor = qvirtio_iommu_pci_destructor; + + return obj; +} + +static void virtio_iommu_register_nodes(void) +{ + QPCIAddress addr = { + .devfn = QPCI_DEVFN(4, 0), + }; + + QOSGraphEdgeOptions opts = { + .extra_device_opts = "addr=04.0", + }; + + /* virtio-iommu-pci */ + add_qpci_address(&opts, &addr); + qos_node_create_driver("virtio-iommu-pci", virtio_iommu_pci_create); + qos_node_consumes("virtio-iommu-pci", "pci-bus", &opts); + qos_node_produces("virtio-iommu-pci", "pci-device"); + qos_node_produces("virtio-iommu-pci", "virtio"); + qos_node_produces("virtio-iommu-pci", "virtio-iommu"); +} + +libqos_init(virtio_iommu_register_nodes); diff --git a/tests/qtest/libqos/virtio-iommu.h b/tests/qtest/libqos/virtio-iommu.h new file mode 100644 index 0000000000..d753761958 --- /dev/null +++ b/tests/qtest/libqos/virtio-iommu.h @@ -0,0 +1,40 @@ +/* + * libqos driver virtio-iommu-pci framework + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at your + * option) any later version. See the COPYING file in the top-level directory. + * + */ + +#ifndef TESTS_LIBQOS_VIRTIO_IOMMU_H +#define TESTS_LIBQOS_VIRTIO_IOMMU_H + +#include "qgraph.h" +#include "virtio.h" +#include "virtio-pci.h" + +typedef struct QVirtioIOMMU QVirtioIOMMU; +typedef struct QVirtioIOMMUPCI QVirtioIOMMUPCI; +typedef struct QVirtioIOMMUDevice QVirtioIOMMUDevice; + +struct QVirtioIOMMU { + QVirtioDevice *vdev; + QVirtQueue *vq; +}; + +struct QVirtioIOMMUPCI { + QVirtioPCIDevice pci_vdev; + QVirtioIOMMU iommu; +}; + +struct QVirtioIOMMUDevice { + QOSGraphObject obj; + QVirtioIOMMU iommu; +}; + +#endif diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 25aeea385b..65ed949685 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1321,16 +1321,29 @@ static bool qtest_is_old_versioned_machine(const char *mname) return res; } -void qtest_cb_for_every_machine(void (*cb)(const char *machine), - bool skip_old_versioned) +struct MachInfo { + char *name; + char *alias; +}; + +/* + * Returns an array with pointers to the available machine names. + * The terminating entry has the name set to NULL. + */ +static struct MachInfo *qtest_get_machines(void) { + static struct MachInfo *machines; QDict *response, *minfo; QList *list; const QListEntry *p; QObject *qobj; QString *qstr; - const char *mname; QTestState *qts; + int idx; + + if (machines) { + return machines; + } qts = qtest_init("-machine none"); response = qtest_qmp(qts, "{ 'execute': 'query-machines' }"); @@ -1338,25 +1351,71 @@ void qtest_cb_for_every_machine(void (*cb)(const char *machine), list = qdict_get_qlist(response, "return"); g_assert(list); - for (p = qlist_first(list); p; p = qlist_next(p)) { + machines = g_new(struct MachInfo, qlist_size(list) + 1); + + for (p = qlist_first(list), idx = 0; p; p = qlist_next(p), idx++) { minfo = qobject_to(QDict, qlist_entry_obj(p)); g_assert(minfo); + qobj = qdict_get(minfo, "name"); g_assert(qobj); qstr = qobject_to(QString, qobj); g_assert(qstr); - mname = qstring_get_str(qstr); - /* Ignore machines that cannot be used for qtests */ - if (!strncmp("xenfv", mname, 5) || g_str_equal("xenpv", mname)) { - continue; - } - if (!skip_old_versioned || !qtest_is_old_versioned_machine(mname)) { - cb(mname); + machines[idx].name = g_strdup(qstring_get_str(qstr)); + + qobj = qdict_get(minfo, "alias"); + if (qobj) { /* The alias is optional */ + qstr = qobject_to(QString, qobj); + g_assert(qstr); + machines[idx].alias = g_strdup(qstring_get_str(qstr)); + } else { + machines[idx].alias = NULL; } } qtest_quit(qts); qobject_unref(response); + + memset(&machines[idx], 0, sizeof(struct MachInfo)); /* Terminating entry */ + return machines; +} + +void qtest_cb_for_every_machine(void (*cb)(const char *machine), + bool skip_old_versioned) +{ + struct MachInfo *machines; + int i; + + machines = qtest_get_machines(); + + for (i = 0; machines[i].name != NULL; i++) { + /* Ignore machines that cannot be used for qtests */ + if (!strncmp("xenfv", machines[i].name, 5) || + g_str_equal("xenpv", machines[i].name)) { + continue; + } + if (!skip_old_versioned || + !qtest_is_old_versioned_machine(machines[i].name)) { + cb(machines[i].name); + } + } +} + +bool qtest_has_machine(const char *machine) +{ + struct MachInfo *machines; + int i; + + machines = qtest_get_machines(); + + for (i = 0; machines[i].name != NULL; i++) { + if (g_str_equal(machine, machines[i].name) || + (machines[i].alias && g_str_equal(machine, machines[i].alias))) { + return true; + } + } + + return false; } /* diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c9d8458062..ebeac59b3f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -19,6 +19,7 @@ slow_qtests = { qtests_generic = \ (config_all_devices.has_key('CONFIG_MEGASAS_SCSI_PCI') ? ['fuzz-megasas-test'] : []) + \ + (config_all_devices.has_key('CONFIG_LSI_SCSI_PCI') ? ['fuzz-lsi53c895a-test'] : []) + \ (config_all_devices.has_key('CONFIG_VIRTIO_SCSI') ? ['fuzz-virtio-scsi-test'] : []) + \ (config_all_devices.has_key('CONFIG_SB16') ? ['fuzz-sb16-test'] : []) + \ (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \ @@ -68,6 +69,10 @@ qtests_i386 = \ (config_all_devices.has_key('CONFIG_RTL8139_PCI') ? ['rtl8139-test'] : []) + \ (config_all_devices.has_key('CONFIG_E1000E_PCI_EXPRESS') ? ['fuzz-e1000e-test'] : []) + \ (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \ + (config_all_devices.has_key('CONFIG_VIRTIO_NET') and \ + config_all_devices.has_key('CONFIG_Q35') and \ + config_all_devices.has_key('CONFIG_VIRTIO_PCI') and \ + slirp.found() ? ['virtio-net-failover'] : []) + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ qtests_pci + \ ['fdc-test', @@ -134,6 +139,7 @@ qtests_ppc = \ ['boot-order-test', 'prom-env-test', 'boot-serial-test'] \ qtests_ppc64 = \ + qtests_ppc + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['device-plug-test'] : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xscom-test'] : []) + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + \ @@ -183,11 +189,10 @@ qtests_aarch64 = \ (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ + (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'xlnx-can-test', - 'fuzz-xlnx-dp-test', 'migration-test'] qtests_s390x = \ @@ -230,6 +235,7 @@ qos_test_ss.add( 'virtio-rng-test.c', 'virtio-scsi-test.c', 'virtio-serial-test.c', + 'virtio-iommu-test.c', 'vmxnet3-test.c', ) if have_virtfs diff --git a/tests/qtest/prom-env-test.c b/tests/qtest/prom-env-test.c index f41d80154a..bdbb01d8e5 100644 --- a/tests/qtest/prom-env-test.c +++ b/tests/qtest/prom-env-test.c @@ -71,9 +71,11 @@ static void add_tests(const char *machines[]) char *name; for (i = 0; machines[i] != NULL; i++) { - name = g_strdup_printf("prom-env/%s", machines[i]); - qtest_add_data_func(name, machines[i], test_machine); - g_free(name); + if (qtest_has_machine(machines[i])) { + name = g_strdup_printf("prom-env/%s", machines[i]); + qtest_add_data_func(name, machines[i], test_machine); + g_free(name); + } } } diff --git a/tests/qtest/virtio-iommu-test.c b/tests/qtest/virtio-iommu-test.c new file mode 100644 index 0000000000..47e68388a0 --- /dev/null +++ b/tests/qtest/virtio-iommu-test.c @@ -0,0 +1,326 @@ +/* + * QTest testcase for VirtIO IOMMU + * + * Copyright (c) 2021 Red Hat, Inc. + * + * Authors: + * Eric Auger + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at your + * option) any later version. See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" +#include "qemu/module.h" +#include "libqos/qgraph.h" +#include "libqos/virtio-iommu.h" +#include "hw/virtio/virtio-iommu.h" + +#define PCI_SLOT_HP 0x06 +#define QVIRTIO_IOMMU_TIMEOUT_US (30 * 1000 * 1000) + +static QGuestAllocator *alloc; + +static void pci_config(void *obj, void *data, QGuestAllocator *t_alloc) +{ + QVirtioIOMMU *v_iommu = obj; + QVirtioDevice *dev = v_iommu->vdev; + uint64_t input_range_start = qvirtio_config_readq(dev, 8); + uint64_t input_range_end = qvirtio_config_readq(dev, 16); + uint32_t domain_range_start = qvirtio_config_readl(dev, 24); + uint32_t domain_range_end = qvirtio_config_readl(dev, 28); + + g_assert_cmpint(input_range_start, ==, 0); + g_assert_cmphex(input_range_end, ==, UINT64_MAX); + g_assert_cmpint(domain_range_start, ==, 0); + g_assert_cmpint(domain_range_end, ==, UINT32_MAX); +} + +static int read_tail_status(struct virtio_iommu_req_tail *buffer) +{ + int i; + + for (i = 0; i < 3; i++) { + g_assert_cmpint(buffer->reserved[i], ==, 0); + } + return buffer->status; +} + +/** + * send_attach_detach - Send an attach/detach command to the device + * @type: VIRTIO_IOMMU_T_ATTACH/VIRTIO_IOMMU_T_DETACH + * @domain: domain the endpoint is attached to + * @ep: endpoint + */ +static int send_attach_detach(QTestState *qts, QVirtioIOMMU *v_iommu, + uint8_t type, uint32_t domain, uint32_t ep) +{ + QVirtioDevice *dev = v_iommu->vdev; + QVirtQueue *vq = v_iommu->vq; + uint64_t ro_addr, wr_addr; + uint32_t free_head; + struct virtio_iommu_req_attach req = {}; /* same layout as detach */ + size_t ro_size = sizeof(req) - sizeof(struct virtio_iommu_req_tail); + size_t wr_size = sizeof(struct virtio_iommu_req_tail); + struct virtio_iommu_req_tail buffer; + int ret; + + req.head.type = type; + req.domain = cpu_to_le32(domain); + req.endpoint = cpu_to_le32(ep); + + ro_addr = guest_alloc(alloc, ro_size); + wr_addr = guest_alloc(alloc, wr_size); + + qtest_memwrite(qts, ro_addr, &req, ro_size); + free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); + qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); + qvirtqueue_kick(qts, dev, vq, free_head); + qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, + QVIRTIO_IOMMU_TIMEOUT_US); + qtest_memread(qts, wr_addr, &buffer, wr_size); + ret = read_tail_status(&buffer); + guest_free(alloc, ro_addr); + guest_free(alloc, wr_addr); + return ret; +} + +/** + * send_map - Send a map command to the device + * @domain: domain the new mapping is attached to + * @virt_start: iova start + * @virt_end: iova end + * @phys_start: base physical address + * @flags: mapping flags + */ +static int send_map(QTestState *qts, QVirtioIOMMU *v_iommu, + uint32_t domain, uint64_t virt_start, uint64_t virt_end, + uint64_t phys_start, uint32_t flags) +{ + QVirtioDevice *dev = v_iommu->vdev; + QVirtQueue *vq = v_iommu->vq; + uint64_t ro_addr, wr_addr; + uint32_t free_head; + struct virtio_iommu_req_map req; + size_t ro_size = sizeof(req) - sizeof(struct virtio_iommu_req_tail); + size_t wr_size = sizeof(struct virtio_iommu_req_tail); + struct virtio_iommu_req_tail buffer; + int ret; + + req.head.type = VIRTIO_IOMMU_T_MAP; + req.domain = cpu_to_le32(domain); + req.virt_start = cpu_to_le64(virt_start); + req.virt_end = cpu_to_le64(virt_end); + req.phys_start = cpu_to_le64(phys_start); + req.flags = cpu_to_le32(flags); + + ro_addr = guest_alloc(alloc, ro_size); + wr_addr = guest_alloc(alloc, wr_size); + + qtest_memwrite(qts, ro_addr, &req, ro_size); + free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); + qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); + qvirtqueue_kick(qts, dev, vq, free_head); + qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, + QVIRTIO_IOMMU_TIMEOUT_US); + qtest_memread(qts, wr_addr, &buffer, wr_size); + ret = read_tail_status(&buffer); + guest_free(alloc, ro_addr); + guest_free(alloc, wr_addr); + return ret; +} + +/** + * send_unmap - Send an unmap command to the device + * @domain: domain the new binding is attached to + * @virt_start: iova start + * @virt_end: iova end + */ +static int send_unmap(QTestState *qts, QVirtioIOMMU *v_iommu, + uint32_t domain, uint64_t virt_start, uint64_t virt_end) +{ + QVirtioDevice *dev = v_iommu->vdev; + QVirtQueue *vq = v_iommu->vq; + uint64_t ro_addr, wr_addr; + uint32_t free_head; + struct virtio_iommu_req_unmap req; + size_t ro_size = sizeof(req) - sizeof(struct virtio_iommu_req_tail); + size_t wr_size = sizeof(struct virtio_iommu_req_tail); + struct virtio_iommu_req_tail buffer; + int ret; + + req.head.type = VIRTIO_IOMMU_T_UNMAP; + req.domain = cpu_to_le32(domain); + req.virt_start = cpu_to_le64(virt_start); + req.virt_end = cpu_to_le64(virt_end); + + ro_addr = guest_alloc(alloc, ro_size); + wr_addr = guest_alloc(alloc, wr_size); + + qtest_memwrite(qts, ro_addr, &req, ro_size); + free_head = qvirtqueue_add(qts, vq, ro_addr, ro_size, false, true); + qvirtqueue_add(qts, vq, wr_addr, wr_size, true, false); + qvirtqueue_kick(qts, dev, vq, free_head); + qvirtio_wait_used_elem(qts, dev, vq, free_head, NULL, + QVIRTIO_IOMMU_TIMEOUT_US); + qtest_memread(qts, wr_addr, &buffer, wr_size); + ret = read_tail_status(&buffer); + guest_free(alloc, ro_addr); + guest_free(alloc, wr_addr); + return ret; +} + +static void test_attach_detach(void *obj, void *data, QGuestAllocator *t_alloc) +{ + QVirtioIOMMU *v_iommu = obj; + QTestState *qts = global_qtest; + int ret; + + alloc = t_alloc; + + /* type, domain, ep */ + + /* attach ep0 to domain 0 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 0, 0); + g_assert_cmpint(ret, ==, 0); + + /* attach a non existing device */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 0, 444); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + /* detach a non existing device (1) */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 0, 1); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + /* move ep0 from domain 0 to domain 1 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + + /* detach ep0 from domain 0 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 0, 0); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_INVAL); + + /* detach ep0 from domain 1 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 0x0, 0xFFF, 0xa1000, + VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 0x2000, 0x2FFF, 0xb1000, + VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_DETACH, 1, 0); + g_assert_cmpint(ret, ==, 0); +} + +/* Test map/unmap scenari documented in the spec */ +static void test_map_unmap(void *obj, void *data, QGuestAllocator *t_alloc) +{ + QVirtioIOMMU *v_iommu = obj; + QTestState *qts = global_qtest; + int ret; + + alloc = t_alloc; + + /* attach ep0 to domain 1 */ + ret = send_attach_detach(qts, v_iommu, VIRTIO_IOMMU_T_ATTACH, 1, 0); + g_assert_cmpint(ret, ==, 0); + + ret = send_map(qts, v_iommu, 0, 0, 0xFFF, 0xa1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + /* domain, virt start, virt end, phys start, flags */ + ret = send_map(qts, v_iommu, 1, 0x0, 0xFFF, 0xa1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + + /* send a new mapping overlapping the previous one */ + ret = send_map(qts, v_iommu, 1, 0, 0xFFFF, 0xb1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_INVAL); + + ret = send_unmap(qts, v_iommu, 4, 0x10, 0xFFF); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_NOENT); + + ret = send_unmap(qts, v_iommu, 1, 0x10, 0xFFF); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_RANGE); + + ret = send_unmap(qts, v_iommu, 1, 0, 0x1000); + g_assert_cmpint(ret, ==, 0); /* unmap everything */ + + /* Spec example sequence */ + + /* 1 */ + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, 0); /* doesn't unmap anything */ + + /* 2 */ + ret = send_map(qts, v_iommu, 1, 0, 9, 0xa1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 9); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,9] */ + + /* 3 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xb1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 5, 9, 0xb2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 9); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] and [5,9] */ + + /* 4 */ + ret = send_map(qts, v_iommu, 1, 0, 9, 0xc1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_RANGE); /* doesn't unmap anything */ + + ret = send_unmap(qts, v_iommu, 1, 0, 10); + g_assert_cmpint(ret, ==, 0); + + /* 5 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xd1000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 5, 9, 0xd2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] */ + + ret = send_unmap(qts, v_iommu, 1, 5, 9); + g_assert_cmpint(ret, ==, 0); + + /* 6 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xe2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 9); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] */ + + /* 7 */ + ret = send_map(qts, v_iommu, 1, 0, 4, 0xf2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 10, 14, 0xf3000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 14); + g_assert_cmpint(ret, ==, 0); /* unmaps [0,4] and [10,14] */ + + ret = send_map(qts, v_iommu, 1, 10, 14, 0xf3000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_map(qts, v_iommu, 1, 0, 4, 0xf2000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, 0); + ret = send_unmap(qts, v_iommu, 1, 0, 4); + g_assert_cmpint(ret, ==, 0); /* only unmaps [0,4] */ + ret = send_map(qts, v_iommu, 1, 10, 14, 0xf3000, VIRTIO_IOMMU_MAP_F_READ); + g_assert_cmpint(ret, ==, VIRTIO_IOMMU_S_INVAL); /* 10-14 still is mapped */ +} + +static void register_virtio_iommu_test(void) +{ + qos_add_test("config", "virtio-iommu", pci_config, NULL); + qos_add_test("attach_detach", "virtio-iommu", test_attach_detach, NULL); + qos_add_test("map_unmap", "virtio-iommu", test_map_unmap, NULL); +} + +libqos_init(register_virtio_iommu_test); diff --git a/tests/qtest/virtio-net-failover.c b/tests/qtest/virtio-net-failover.c new file mode 100644 index 0000000000..4b2ba8a106 --- /dev/null +++ b/tests/qtest/virtio-net-failover.c @@ -0,0 +1,1352 @@ +/* + * QTest testcase for virtio-net failover + * + * See docs/system/virtio-net-failover.rst + * + * Copyright (c) 2021 Red Hat, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "libqos/libqtest.h" +#include "libqos/pci.h" +#include "libqos/pci-pc.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qlist.h" +#include "qapi/qmp/qjson.h" +#include "libqos/malloc-pc.h" +#include "libqos/virtio-pci.h" +#include "hw/pci/pci.h" + +#define ACPI_PCIHP_ADDR_ICH9 0x0cc0 +#define PCI_EJ_BASE 0x0008 +#define PCI_SEL_BASE 0x0010 + +#define BASE_MACHINE "-M q35 -nodefaults " \ + "-device pcie-root-port,id=root0,addr=0x1,bus=pcie.0,chassis=1 " \ + "-device pcie-root-port,id=root1,addr=0x2,bus=pcie.0,chassis=2 " + +#define MAC_PRIMARY0 "52:54:00:11:11:11" +#define MAC_STANDBY0 "52:54:00:22:22:22" +#define MAC_PRIMARY1 "52:54:00:33:33:33" +#define MAC_STANDBY1 "52:54:00:44:44:44" + +static QGuestAllocator guest_malloc; +static QPCIBus *pcibus; + +static QTestState *machine_start(const char *args, int numbus) +{ + QTestState *qts; + QPCIDevice *dev; + int bus; + + qts = qtest_init(args); + + pc_alloc_init(&guest_malloc, qts, 0); + pcibus = qpci_new_pc(qts, &guest_malloc); + g_assert(qpci_secondary_buses_init(pcibus) == numbus); + + for (bus = 1; bus <= numbus; bus++) { + dev = qpci_device_find(pcibus, QPCI_DEVFN(bus, 0)); + g_assert_nonnull(dev); + + qpci_device_enable(dev); + qpci_iomap(dev, 4, NULL); + + g_free(dev); + } + + return qts; +} + +static void machine_stop(QTestState *qts) +{ + qpci_free_pc(pcibus); + alloc_destroy(&guest_malloc); + qtest_quit(qts); +} + +static void test_error_id(void) +{ + QTestState *qts; + QDict *resp; + QDict *err; + + qts = machine_start(BASE_MACHINE + "-device virtio-net,bus=root0,id=standby0,failover=on", + 2); + + resp = qtest_qmp(qts, "{'execute': 'device_add'," + "'arguments': {" + "'driver': 'virtio-net'," + "'bus': 'root1'," + "'failover_pair_id': 'standby0'" + "} }"); + g_assert(qdict_haskey(resp, "error")); + + err = qdict_get_qdict(resp, "error"); + g_assert(qdict_haskey(err, "desc")); + + g_assert_cmpstr(qdict_get_str(err, "desc"), ==, + "Device with failover_pair_id needs to have id"); + + qobject_unref(resp); + + machine_stop(qts); +} + +static void test_error_pcie(void) +{ + QTestState *qts; + QDict *resp; + QDict *err; + + qts = machine_start(BASE_MACHINE + "-device virtio-net,bus=root0,id=standby0,failover=on", + 2); + + resp = qtest_qmp(qts, "{'execute': 'device_add'," + "'arguments': {" + "'driver': 'virtio-net'," + "'id': 'primary0'," + "'bus': 'pcie.0'," + "'failover_pair_id': 'standby0'" + "} }"); + g_assert(qdict_haskey(resp, "error")); + + err = qdict_get_qdict(resp, "error"); + g_assert(qdict_haskey(err, "desc")); + + g_assert_cmpstr(qdict_get_str(err, "desc"), ==, + "Bus 'pcie.0' does not support hotplugging"); + + qobject_unref(resp); + + machine_stop(qts); +} + +static QDict *find_device(QDict *bus, const char *name) +{ + const QObject *obj; + QList *devices; + QList *list; + + devices = qdict_get_qlist(bus, "devices"); + if (devices == NULL) { + return NULL; + } + + list = qlist_copy(devices); + while ((obj = qlist_pop(list))) { + QDict *device; + + device = qobject_to(QDict, obj); + + if (qdict_haskey(device, "pci_bridge")) { + QDict *bridge; + QDict *bridge_device; + + bridge = qdict_get_qdict(device, "pci_bridge"); + + if (qdict_haskey(bridge, "devices")) { + bridge_device = find_device(bridge, name); + if (bridge_device) { + qobject_unref(device); + qobject_unref(list); + return bridge_device; + } + } + } + + if (!qdict_haskey(device, "qdev_id")) { + qobject_unref(device); + continue; + } + + if (strcmp(qdict_get_str(device, "qdev_id"), name) == 0) { + qobject_unref(list); + return device; + } + qobject_unref(device); + } + qobject_unref(list); + + return NULL; +} + +static QDict *get_bus(QTestState *qts, int num) +{ + QObject *obj; + QDict *resp; + QList *ret; + + resp = qtest_qmp(qts, "{ 'execute': 'query-pci' }"); + g_assert(qdict_haskey(resp, "return")); + + ret = qdict_get_qlist(resp, "return"); + g_assert_nonnull(ret); + + while ((obj = qlist_pop(ret))) { + QDict *bus; + + bus = qobject_to(QDict, obj); + if (!qdict_haskey(bus, "bus")) { + qobject_unref(bus); + continue; + } + if (qdict_get_int(bus, "bus") == num) { + qobject_unref(resp); + return bus; + } + qobject_ref(bus); + } + qobject_unref(resp); + + return NULL; +} + +static char *get_mac(QTestState *qts, const char *name) +{ + QDict *resp; + char *mac; + + resp = qtest_qmp(qts, "{ 'execute': 'qom-get', " + "'arguments': { " + "'path': %s, " + "'property': 'mac' } }", name); + + g_assert(qdict_haskey(resp, "return")); + + mac = g_strdup(qdict_get_str(resp, "return")); + + qobject_unref(resp); + + return mac; +} + +static void check_one_card(QTestState *qts, bool present, + const char *id, const char *mac) +{ + QDict *device; + QDict *bus; + char *addr; + + bus = get_bus(qts, 0); + device = find_device(bus, id); + if (present) { + char *path; + + g_assert_nonnull(device); + qobject_unref(device); + + path = g_strdup_printf("/machine/peripheral/%s", id); + addr = get_mac(qts, path); + g_free(path); + g_assert_cmpstr(mac, ==, addr); + g_free(addr); + } else { + g_assert_null(device); + } + + qobject_unref(bus); +} + +static void test_on(void) +{ + QTestState *qts; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0, + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + machine_stop(qts); +} + +static void test_on_mismatch(void) +{ + QTestState *qts; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby1,netdev=hs1,mac="MAC_PRIMARY0, + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + machine_stop(qts); +} + +static void test_off(void) +{ + QTestState *qts; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=off,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0, + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + machine_stop(qts); +} + +static QDict *get_failover_negociated_event(QTestState *qts) +{ + QDict *resp; + QDict *data; + + resp = qtest_qmp_eventwait_ref(qts, "FAILOVER_NEGOTIATED"); + g_assert(qdict_haskey(resp, "data")); + + data = qdict_get_qdict(resp, "data"); + g_assert(qdict_haskey(data, "device-id")); + qobject_ref(data); + qobject_unref(resp); + + return data; +} + +static QVirtioPCIDevice *start_virtio_net(QTestState *qts, int bus, int slot, + const char *id) +{ + QVirtioPCIDevice *dev; + uint64_t features; + QPCIAddress addr; + QDict *resp; + + addr.devfn = QPCI_DEVFN((bus << 5) + slot, 0); + dev = virtio_pci_new(pcibus, &addr); + g_assert_nonnull(dev); + qvirtio_pci_device_enable(dev); + qvirtio_start_device(&dev->vdev); + features = qvirtio_get_features(&dev->vdev); + features = features & ~(QVIRTIO_F_BAD_FEATURE | + (1ull << VIRTIO_RING_F_INDIRECT_DESC) | + (1ull << VIRTIO_RING_F_EVENT_IDX)); + qvirtio_set_features(&dev->vdev, features); + qvirtio_set_driver_ok(&dev->vdev); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, id); + qobject_unref(resp); + + return dev; +} + +static void test_enabled(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0" ", + 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_1(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-device virtio-net,bus=root0,id=standby0," + "failover=on,netdev=hs0,mac="MAC_STANDBY0" " + "-netdev user,id=hs1 ", 2); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_1_reverse(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-device virtio-net,bus=root1,id=primary0," + "failover_pair_id=standby0,netdev=hs1,mac="MAC_PRIMARY0" ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_2(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_hotplug_2_reverse(void) +{ + QTestState *qts; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_STANDBY0"'}"); + + /* + * XXX: sounds like a bug: + * The primary should be hidden until the virtio-net driver + * negotiates the VIRTIO_NET_F_STANDBY feature by start_virtio_net() + */ + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static QDict *migrate_status(QTestState *qts) +{ + QDict *resp, *ret; + + resp = qtest_qmp(qts, "{ 'execute': 'query-migrate' }"); + g_assert(qdict_haskey(resp, "return")); + + ret = qdict_get_qdict(resp, "return"); + g_assert(qdict_haskey(ret, "status")); + qobject_ref(ret); + qobject_unref(resp); + + return ret; +} + +static QDict *get_unplug_primary_event(QTestState *qts) +{ + QDict *resp; + QDict *data; + + resp = qtest_qmp_eventwait_ref(qts, "UNPLUG_PRIMARY"); + g_assert(qdict_haskey(resp, "data")); + + data = qdict_get_qdict(resp, "data"); + g_assert(qdict_haskey(data, "device-id")); + qobject_ref(data); + qobject_unref(resp); + + return data; +} + +static void test_migrate_out(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + /* wait the end of the migration setup phase */ + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "wait-unplug") == 0) { + qobject_unref(ret); + break; + } + + /* The migration must not start if the card is not ejected */ + g_assert_cmpstr(status, !=, "active"); + g_assert_cmpstr(status, !=, "completed"); + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + + qobject_unref(ret); + } + + if (g_test_slow()) { + /* check we stay in wait-unplug while the card is not ejected */ + for (int i = 0; i < 5; i++) { + sleep(1); + ret = migrate_status(qts); + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "wait-unplug"); + qobject_unref(ret); + } + } + + /* OS unplugs the cards, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "completed") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + qobject_unref(ret); + } + + qtest_qmp_eventwait(qts, "STOP"); + + /* + * in fact, the card is ejected from the point of view of kernel + * but not really from QEMU to be able to hotplug it back if + * migration fails. So we can't check that: + * check_one_card(qts, true, "standby0", MAC_STANDBY0); + * check_one_card(qts, false, "primary0", MAC_PRIMARY0); + */ + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static QDict *get_migration_event(QTestState *qts) +{ + QDict *resp; + QDict *data; + + resp = qtest_qmp_eventwait_ref(qts, "MIGRATION"); + g_assert(qdict_haskey(resp, "data")); + + data = qdict_get_qdict(resp, "data"); + g_assert(qdict_haskey(data, "status")); + qobject_ref(data); + qobject_unref(resp); + + return data; +} + +static void test_migrate_in(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat %s", (gchar *)opaque); + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-incoming defer ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate-incoming', 'arguments': %p}", + args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + resp = get_migration_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "status"), ==, "setup"); + qobject_unref(resp); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "standby0"); + qobject_unref(resp); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qtest_qmp_eventwait(qts, "RESUME"); + + ret = migrate_status(qts); + g_assert_cmpstr(qdict_get_str(ret, "status"), ==, "completed"); + qobject_unref(ret); + + machine_stop(qts); +} + +static void test_migrate_abort_wait_unplug(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate_cancel' }"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* migration has been cancelled while the unplug was in progress */ + + /* while the card is not ejected, we must be in "cancelling" state */ + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "cancelling"); + qobject_unref(ret); + + /* OS unplugs the cards, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "cancelled") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "active"); + qobject_unref(ret); + } + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_migrate_abort_active(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + /* OS unplugs the cards, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "wait-unplug") != 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + qobject_unref(ret); + } + + resp = qtest_qmp(qts, "{ 'execute': 'migrate_cancel' }"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "cancelled") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "active"); + qobject_unref(ret); + } + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_migrate_abort_timeout(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status; + int total; + QVirtioPCIDevice *vdev; + + qts = machine_start(BASE_MACHINE + "-netdev user,id=hs0 " + "-netdev user,id=hs1 ", + 2); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + vdev = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "primary0"); + qobject_unref(resp); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate_cancel' }"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* migration has been cancelled while the unplug was in progress */ + + /* while the card is not ejected, we must be in "cancelling" state */ + + total = 0; + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "cancelled") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, ==, "cancelling"); + g_assert(qdict_haskey(ret, "total-time")); + total = qdict_get_int(ret, "total-time"); + qobject_unref(ret); + } + + /* + * migration timeout in this case is 30 seconds + * check we exit on the timeout (ms) + */ + g_assert_cmpint(total, >, 30000); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + + qos_object_destroy((QOSGraphObject *)vdev); + machine_stop(qts); +} + +static void test_multi_out(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat > %s", (gchar *)opaque); + const gchar *status, *expected; + QVirtioPCIDevice *vdev0, *vdev1; + + qts = machine_start(BASE_MACHINE + "-device pcie-root-port,id=root2,addr=0x3,bus=pcie.0,chassis=3 " + "-device pcie-root-port,id=root3,addr=0x4,bus=pcie.0,chassis=4 " + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-netdev user,id=hs2 " + "-netdev user,id=hs3 ", + 4); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + vdev0 = start_virtio_net(qts, 1, 0, "standby0"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby1", + "{'bus': 'root2'," + "'failover': 'on'," + "'netdev': 'hs2'," + "'mac': '"MAC_STANDBY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary1", + "{'bus': 'root3'," + "'failover_pair_id': 'standby1'," + "'netdev': 'hs3'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + vdev1 = start_virtio_net(qts, 3, 0, "standby1"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, true, "primary1", MAC_PRIMARY1); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate', 'arguments': %p}", args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + /* the event is sent when QEMU asks the OS to unplug the card */ + resp = get_unplug_primary_event(qts); + if (strcmp(qdict_get_str(resp, "device-id"), "primary0") == 0) { + expected = "primary1"; + } else if (strcmp(qdict_get_str(resp, "device-id"), "primary1") == 0) { + expected = "primary0"; + } else { + g_assert_not_reached(); + } + qobject_unref(resp); + + resp = get_unplug_primary_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, expected); + qobject_unref(resp); + + /* wait the end of the migration setup phase */ + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "wait-unplug") == 0) { + qobject_unref(ret); + break; + } + + /* The migration must not start if the card is not ejected */ + g_assert_cmpstr(status, !=, "active"); + g_assert_cmpstr(status, !=, "completed"); + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + + qobject_unref(ret); + } + + /* OS unplugs primary1, but we must wait the second */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + ret = migrate_status(qts); + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "wait-unplug"); + qobject_unref(ret); + + if (g_test_slow()) { + /* check we stay in wait-unplug while the card is not ejected */ + for (int i = 0; i < 5; i++) { + sleep(1); + ret = migrate_status(qts); + status = qdict_get_str(ret, "status"); + g_assert_cmpstr(status, ==, "wait-unplug"); + qobject_unref(ret); + } + } + + /* OS unplugs primary0, QEMU can move from wait-unplug state */ + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_SEL_BASE, 2); + qtest_outl(qts, ACPI_PCIHP_ADDR_ICH9 + PCI_EJ_BASE, 1); + + while (true) { + ret = migrate_status(qts); + + status = qdict_get_str(ret, "status"); + if (strcmp(status, "completed") == 0) { + qobject_unref(ret); + break; + } + g_assert_cmpstr(status, !=, "failed"); + g_assert_cmpstr(status, !=, "cancelling"); + g_assert_cmpstr(status, !=, "cancelled"); + qobject_unref(ret); + } + + qtest_qmp_eventwait(qts, "STOP"); + + qos_object_destroy((QOSGraphObject *)vdev0); + qos_object_destroy((QOSGraphObject *)vdev1); + machine_stop(qts); +} + +static void test_multi_in(gconstpointer opaque) +{ + QTestState *qts; + QDict *resp, *args, *ret; + g_autofree gchar *uri = g_strdup_printf("exec: cat %s", (gchar *)opaque); + + qts = machine_start(BASE_MACHINE + "-device pcie-root-port,id=root2,addr=0x3,bus=pcie.0,chassis=3 " + "-device pcie-root-port,id=root3,addr=0x4,bus=pcie.0,chassis=4 " + "-netdev user,id=hs0 " + "-netdev user,id=hs1 " + "-netdev user,id=hs2 " + "-netdev user,id=hs3 " + "-incoming defer ", + 4); + + check_one_card(qts, false, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby0", + "{'bus': 'root0'," + "'failover': 'on'," + "'netdev': 'hs0'," + "'mac': '"MAC_STANDBY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary0", + "{'bus': 'root1'," + "'failover_pair_id': 'standby0'," + "'netdev': 'hs1'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY0"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, false, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "standby1", + "{'bus': 'root2'," + "'failover': 'on'," + "'netdev': 'hs2'," + "'mac': '"MAC_STANDBY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + qtest_qmp_device_add(qts, "virtio-net", "primary1", + "{'bus': 'root3'," + "'failover_pair_id': 'standby1'," + "'netdev': 'hs3'," + "'rombar': 0," + "'romfile': ''," + "'mac': '"MAC_PRIMARY1"'}"); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, false, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, false, "primary1", MAC_PRIMARY1); + + args = qdict_from_jsonf_nofail("{}"); + g_assert_nonnull(args); + qdict_put_str(args, "uri", uri); + + resp = qtest_qmp(qts, "{ 'execute': 'migrate-incoming', 'arguments': %p}", + args); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + + resp = get_migration_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "status"), ==, "setup"); + qobject_unref(resp); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "standby0"); + qobject_unref(resp); + + resp = get_failover_negociated_event(qts); + g_assert_cmpstr(qdict_get_str(resp, "device-id"), ==, "standby1"); + qobject_unref(resp); + + check_one_card(qts, true, "standby0", MAC_STANDBY0); + check_one_card(qts, true, "primary0", MAC_PRIMARY0); + check_one_card(qts, true, "standby1", MAC_STANDBY1); + check_one_card(qts, true, "primary1", MAC_PRIMARY1); + + qtest_qmp_eventwait(qts, "RESUME"); + + ret = migrate_status(qts); + g_assert_cmpstr(qdict_get_str(ret, "status"), ==, "completed"); + qobject_unref(ret); + + machine_stop(qts); +} + +int main(int argc, char **argv) +{ + const gchar *tmpdir = g_get_tmp_dir(); + gchar *tmpfile = g_strdup_printf("%s/failover_test_migrate-%u-%u", + tmpdir, getpid(), g_test_rand_int()); + int ret; + + g_test_init(&argc, &argv, NULL); + + qtest_add_func("failover-virtio-net/params/error/id", test_error_id); + qtest_add_func("failover-virtio-net/params/error/pcie", test_error_pcie); + qtest_add_func("failover-virtio-net/params/on", test_on); + qtest_add_func("failover-virtio-net/params/on_mismatch", + test_on_mismatch); + qtest_add_func("failover-virtio-net/params/off", test_off); + qtest_add_func("failover-virtio-net/params/enabled", test_enabled); + qtest_add_func("failover-virtio-net/hotplug_1", test_hotplug_1); + qtest_add_func("failover-virtio-net/hotplug_1_reverse", + test_hotplug_1_reverse); + qtest_add_func("failover-virtio-net/hotplug_2", test_hotplug_2); + qtest_add_func("failover-virtio-net/hotplug_2_reverse", + test_hotplug_2_reverse); + qtest_add_data_func("failover-virtio-net/migrate/out", tmpfile, + test_migrate_out); + qtest_add_data_func("failover-virtio-net/migrate/in", tmpfile, + test_migrate_in); + qtest_add_data_func("failover-virtio-net/migrate/abort/wait-unplug", + tmpfile, test_migrate_abort_wait_unplug); + qtest_add_data_func("failover-virtio-net/migrate/abort/active", tmpfile, + test_migrate_abort_active); + if (g_test_slow()) { + qtest_add_data_func("failover-virtio-net/migrate/abort/timeout", + tmpfile, test_migrate_abort_timeout); + } + qtest_add_data_func("failover-virtio-net/multi/out", + tmpfile, test_multi_out); + qtest_add_data_func("failover-virtio-net/multi/in", + tmpfile, test_multi_in); + + ret = g_test_run(); + + unlink(tmpfile); + g_free(tmpfile); + + return ret; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2c05c90d17..1d967901bd 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,8 +8,8 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# Float-convert Tests -AARCH64_TESTS=fcvt +# Base architecture tests +AARCH64_TESTS=fcvt pcalign-a64 fcvt: LDFLAGS+=-lm diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c new file mode 100644 index 0000000000..6b9277f919 --- /dev/null +++ b/tests/tcg/aarch64/pcalign-a64.c @@ -0,0 +1,37 @@ +/* Test PC misalignment exception */ + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 1\n\t" + "str %0, %1\n\t" + "br %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + abort(); +} diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 5ab59ed6ce..f509d823d4 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -29,6 +29,10 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# PC alignment test +ARM_TESTS += pcalign-a32 +pcalign-a32: CFLAGS+=-marm + ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) # Semihosting smoke test for linux-user diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c new file mode 100644 index 0000000000..3c9c8cc97b --- /dev/null +++ b/tests/tcg/arm/pcalign-a32.c @@ -0,0 +1,46 @@ +/* Test PC misalignment exception */ + +#ifdef __thumb__ +#error "This test must be compiled for ARM" +#endif + +#include +#include +#include +#include + +static void *expected; + +static void sigbus(int sig, siginfo_t *info, void *vuc) +{ + assert(info->si_code == BUS_ADRALN); + assert(info->si_addr == expected); + exit(EXIT_SUCCESS); +} + +int main() +{ + void *tmp; + + struct sigaction sa = { + .sa_sigaction = sigbus, + .sa_flags = SA_SIGINFO + }; + + if (sigaction(SIGBUS, &sa, NULL) < 0) { + perror("sigaction"); + return EXIT_FAILURE; + } + + asm volatile("adr %0, 1f + 2\n\t" + "str %0, %1\n\t" + "bx %0\n" + "1:" + : "=&r"(tmp), "=m"(expected)); + + /* + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns + * the address or not. If so, we can legitimately fall through. + */ + return EXIT_SUCCESS; +} diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 9b76f58258..9ef913df5b 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -64,7 +64,9 @@ fi : ${cross_cc_ppc="powerpc-linux-gnu-gcc"} : ${cross_cc_cflags_ppc="-m32"} : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"} -: ${cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"} +: ${cross_cc_cflags_ppc64="-m64 -mbig"} +: ${cross_cc_ppc64le="$cross_cc_ppc64"} +: ${cross_cc_cflags_ppc64le="-m64 -mlittle"} : ${cross_cc_riscv64="riscv64-linux-gnu-gcc"} : ${cross_cc_s390x="s390x-linux-gnu-gcc"} : ${cross_cc_sh4="sh4-linux-gnu-gcc"} diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target index 6ab7934fdf..8f4c7ac4ed 100644 --- a/tests/tcg/ppc64/Makefile.target +++ b/tests/tcg/ppc64/Makefile.target @@ -11,6 +11,7 @@ endif bcdsub: CFLAGS += -mpower8-vector PPC64_TESTS += byte_reverse +PPC64_TESTS += mtfsf ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),) run-byte_reverse: QEMU_OPTS+=-cpu POWER10 run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10 diff --git a/tests/tcg/ppc64le/Makefile.target b/tests/tcg/ppc64le/Makefile.target index ba2fde5ff1..e031f65adc 100644 --- a/tests/tcg/ppc64le/Makefile.target +++ b/tests/tcg/ppc64le/Makefile.target @@ -16,6 +16,7 @@ byte_reverse: CFLAGS += -mcpu=power10 run-byte_reverse: QEMU_OPTS+=-cpu POWER10 run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10 +PPC64LE_TESTS += mtfsf PPC64LE_TESTS += signal_save_restore_xer TESTS += $(PPC64LE_TESTS) diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c new file mode 100644 index 0000000000..b3d31f3637 --- /dev/null +++ b/tests/tcg/ppc64le/mtfsf.c @@ -0,0 +1,61 @@ +#include +#include +#include +#include + +#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ +#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ +#define FPSCR_FI 17 /* Floating-point fraction inexact */ + +#define FP_VE (1ull << FPSCR_VE) +#define FP_VXSOFT (1ull << FPSCR_VXSOFT) +#define FP_FI (1ull << FPSCR_FI) + +void sigfpe_handler(int sig, siginfo_t *si, void *ucontext) +{ + if (si->si_code == FPE_FLTINV) { + exit(0); + } + exit(1); +} + +int main(void) +{ + union { + double d; + long long ll; + } fpscr; + + struct sigaction sa = { + .sa_sigaction = sigfpe_handler, + .sa_flags = SA_SIGINFO + }; + + /* + * Enable the MSR bits F0 and F1 to enable exceptions. + * This shouldn't be needed in linux-user as these bits are enabled by + * default, but this allows to execute either in a VM or a real machine + * to compare the behaviors. + */ + prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE); + + /* First test if the FI bit is being set correctly */ + fpscr.ll = FP_FI; + __builtin_mtfsf(0b11111111, fpscr.d); + fpscr.d = __builtin_mffs(); + assert((fpscr.ll & FP_FI) != 0); + + /* Then test if the deferred exception is being called correctly */ + sigaction(SIGFPE, &sa, NULL); + + /* + * Although the VXSOFT exception has been chosen, based on test in a Power9 + * any combination of exception bit + its enabling bit should work. + * But if a different exception is chosen si_code check should + * change accordingly. + */ + fpscr.ll = FP_VE | FP_VXSOFT; + __builtin_mtfsf(0b11111111, fpscr.d); + + return 1; +} diff --git a/tests/unit/meson.build b/tests/unit/meson.build index acac3622ed..90acf5b0da 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -112,7 +112,7 @@ if have_block if nettle.found() or gcrypt.found() tests += {'test-crypto-pbkdf': [io]} endif - if 'CONFIG_EPOLL_CREATE1' in config_host + if config_host_data.get('CONFIG_EPOLL_CREATE1') tests += {'test-fdmon-epoll': [testblock]} endif endif