From 086a575f44911869081a79f3396a796e89f87d3a Mon Sep 17 00:00:00 2001
From: Alwin Berger <alwin.berger@tu-dortmund.de>
Date: Wed, 13 Sep 2023 14:05:24 +0200
Subject: [PATCH] add delay list to RefinedFreeRTOSSystemState

---
 fuzzers/FRET/src/systemstate/mod.rs       | 1 +
 fuzzers/FRET/src/systemstate/observers.rs | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/fuzzers/FRET/src/systemstate/mod.rs b/fuzzers/FRET/src/systemstate/mod.rs
index 7ea65715bc..7656334d85 100644
--- a/fuzzers/FRET/src/systemstate/mod.rs
+++ b/fuzzers/FRET/src/systemstate/mod.rs
@@ -102,6 +102,7 @@ pub struct RefinedFreeRTOSSystemState {
     input_counter: u32,
     pub current_task: RefinedTCB,
     ready_list_after: Vec<RefinedTCB>,
+    delay_list_after: Vec<RefinedTCB>,
 }
 impl PartialEq for RefinedFreeRTOSSystemState {
     fn eq(&self, other: &Self) -> bool {
diff --git a/fuzzers/FRET/src/systemstate/observers.rs b/fuzzers/FRET/src/systemstate/observers.rs
index 2c5c295828..12a4664616 100644
--- a/fuzzers/FRET/src/systemstate/observers.rs
+++ b/fuzzers/FRET/src/systemstate/observers.rs
@@ -120,11 +120,15 @@ for mut i in input.drain(..) {
         let mut tmp = tcb_list_to_vec_cached(j,&mut i.dumping_ground).iter().map(|x| RefinedTCB::from_tcb(x)).collect();
         collector.append(&mut tmp);
     }
+    let mut delay_list : Vec::<RefinedTCB> = tcb_list_to_vec_cached(i.delay_list, &mut i.dumping_ground).iter().map(|x| RefinedTCB::from_tcb(x)).collect();
+    // We don't care about the order
+    delay_list.sort_by(|a,b| a.task_name.cmp(&b.task_name));
     ret.push(RefinedFreeRTOSSystemState {
         current_task: RefinedTCB::from_tcb_owned(i.current_tcb),
         start_tick: start_tick,
         end_tick: i.qemu_tick,
         ready_list_after: collector,
+        delay_list_after: delay_list,
         input_counter: i.input_counter,//+IRQ_INPUT_BYTES_NUMBER,
         last_pc: i.last_pc,
     });